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1/*
2 * linux/arch/arm/mach-omap2/timer.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
17 *
18 * Some parts based off of TI's 24xx code:
19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 *
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29#include <linux/init.h>
30#include <linux/time.h>
31#include <linux/interrupt.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/clocksource.h>
37#include <linux/clockchips.h>
38#include <linux/slab.h>
39#include <linux/of.h>
40#include <linux/of_address.h>
41#include <linux/of_irq.h>
42#include <linux/platform_device.h>
43#include <linux/platform_data/dmtimer-omap.h>
44#include <linux/sched_clock.h>
45
46#include <asm/mach/time.h>
47
48#include "omap_hwmod.h"
49#include "omap_device.h"
50#include <plat/counter-32k.h>
51#include <clocksource/timer-ti-dm.h>
52
53#include "soc.h"
54#include "common.h"
55#include "control.h"
56#include "powerdomain.h"
57#include "omap-secure.h"
58
59#define REALTIME_COUNTER_BASE 0x48243200
60#define INCREMENTER_NUMERATOR_OFFSET 0x10
61#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
62#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
63
64/* Clockevent code */
65
66static struct omap_dm_timer clkev;
67static struct clock_event_device clockevent_gpt;
68
69/* Clockevent hwmod for am335x and am437x suspend */
70static struct omap_hwmod *clockevent_gpt_hwmod;
71
72/* Clockesource hwmod for am437x suspend */
73static struct omap_hwmod *clocksource_gpt_hwmod;
74
75#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
76static unsigned long arch_timer_freq;
77
78void set_cntfreq(void)
79{
80 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
81}
82#endif
83
84static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
85{
86 struct clock_event_device *evt = &clockevent_gpt;
87
88 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
89
90 evt->event_handler(evt);
91 return IRQ_HANDLED;
92}
93
94static struct irqaction omap2_gp_timer_irq = {
95 .name = "gp_timer",
96 .flags = IRQF_TIMER | IRQF_IRQPOLL,
97 .handler = omap2_gp_timer_interrupt,
98};
99
100static int omap2_gp_timer_set_next_event(unsigned long cycles,
101 struct clock_event_device *evt)
102{
103 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
104 0xffffffff - cycles, OMAP_TIMER_POSTED);
105
106 return 0;
107}
108
109static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
110{
111 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
112 return 0;
113}
114
115static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
116{
117 u32 period;
118
119 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
120
121 period = clkev.rate / HZ;
122 period -= 1;
123 /* Looks like we need to first set the load value separately */
124 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
125 OMAP_TIMER_POSTED);
126 __omap_dm_timer_load_start(&clkev,
127 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
128 0xffffffff - period, OMAP_TIMER_POSTED);
129 return 0;
130}
131
132static void omap_clkevt_idle(struct clock_event_device *unused)
133{
134 if (!clockevent_gpt_hwmod)
135 return;
136
137 omap_hwmod_idle(clockevent_gpt_hwmod);
138}
139
140static void omap_clkevt_unidle(struct clock_event_device *unused)
141{
142 if (!clockevent_gpt_hwmod)
143 return;
144
145 omap_hwmod_enable(clockevent_gpt_hwmod);
146 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
147}
148
149static struct clock_event_device clockevent_gpt = {
150 .features = CLOCK_EVT_FEAT_PERIODIC |
151 CLOCK_EVT_FEAT_ONESHOT,
152 .rating = 300,
153 .set_next_event = omap2_gp_timer_set_next_event,
154 .set_state_shutdown = omap2_gp_timer_shutdown,
155 .set_state_periodic = omap2_gp_timer_set_periodic,
156 .set_state_oneshot = omap2_gp_timer_shutdown,
157 .tick_resume = omap2_gp_timer_shutdown,
158};
159
160static const struct of_device_id omap_timer_match[] __initconst = {
161 { .compatible = "ti,omap2420-timer", },
162 { .compatible = "ti,omap3430-timer", },
163 { .compatible = "ti,omap4430-timer", },
164 { .compatible = "ti,omap5430-timer", },
165 { .compatible = "ti,dm814-timer", },
166 { .compatible = "ti,dm816-timer", },
167 { .compatible = "ti,am335x-timer", },
168 { .compatible = "ti,am335x-timer-1ms", },
169 { }
170};
171
172static int omap_timer_add_disabled_property(struct device_node *np)
173{
174 struct property *prop;
175
176 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
177 if (!prop)
178 return -ENOMEM;
179
180 prop->name = "status";
181 prop->value = "disabled";
182 prop->length = strlen(prop->value);
183
184 return of_add_property(np, prop);
185}
186
187static int omap_timer_update_dt(struct device_node *np)
188{
189 int error = 0;
190
191 if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
192 error = omap_timer_add_disabled_property(np);
193 if (error)
194 return error;
195 }
196
197 /* No parent interconnect target module configured? */
198 if (of_get_property(np, "ti,hwmods", NULL))
199 return error;
200
201 /* Tag parent interconnect target module disabled */
202 error = omap_timer_add_disabled_property(np->parent);
203 if (error)
204 return error;
205
206 return 0;
207}
208
209/**
210 * omap_get_timer_dt - get a timer using device-tree
211 * @match - device-tree match structure for matching a device type
212 * @property - optional timer property to match
213 *
214 * Helper function to get a timer during early boot using device-tree for use
215 * as kernel system timer. Optionally, the property argument can be used to
216 * select a timer with a specific property. Once a timer is found then mark
217 * the timer node in device-tree as disabled, to prevent the kernel from
218 * registering this timer as a platform device and so no one else can use it.
219 */
220static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
221 const char *property)
222{
223 struct device_node *np;
224 int error;
225
226 for_each_matching_node(np, match) {
227 if (!of_device_is_available(np))
228 continue;
229
230 if (property && !of_get_property(np, property, NULL))
231 continue;
232
233 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
234 of_get_property(np, "ti,timer-dsp", NULL) ||
235 of_get_property(np, "ti,timer-pwm", NULL) ||
236 of_get_property(np, "ti,timer-secure", NULL)))
237 continue;
238
239 error = omap_timer_update_dt(np);
240 WARN(error, "%s: Could not update dt: %i\n", __func__, error);
241
242 return np;
243 }
244
245 return NULL;
246}
247
248/**
249 * omap_dmtimer_init - initialisation function when device tree is used
250 *
251 * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
252 * cannot be used by the kernel as they are reserved. Therefore, to prevent the
253 * kernel registering these devices remove them dynamically from the device
254 * tree on boot.
255 */
256static void __init omap_dmtimer_init(void)
257{
258 struct device_node *np;
259
260 if (!cpu_is_omap34xx() && !soc_is_dra7xx())
261 return;
262
263 /* If we are a secure device, remove any secure timer nodes */
264 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
265 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
266 of_node_put(np);
267 }
268}
269
270/**
271 * omap_dm_timer_get_errata - get errata flags for a timer
272 *
273 * Get the timer errata flags that are specific to the OMAP device being used.
274 */
275static u32 __init omap_dm_timer_get_errata(void)
276{
277 if (cpu_is_omap24xx())
278 return 0;
279
280 return OMAP_TIMER_ERRATA_I103_I767;
281}
282
283static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
284 const char *fck_source,
285 const char *property,
286 const char **timer_name,
287 int posted)
288{
289 const char *oh_name = NULL;
290 struct device_node *np;
291 struct omap_hwmod *oh;
292 struct clk *src;
293 int r = 0;
294
295 np = omap_get_timer_dt(omap_timer_match, property);
296 if (!np)
297 return -ENODEV;
298
299 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
300 if (!oh_name) {
301 of_property_read_string_index(np->parent, "ti,hwmods", 0,
302 &oh_name);
303 if (!oh_name)
304 return -ENODEV;
305 }
306
307 timer->irq = irq_of_parse_and_map(np, 0);
308 if (!timer->irq)
309 return -ENXIO;
310
311 timer->io_base = of_iomap(np, 0);
312
313 timer->fclk = of_clk_get_by_name(np, "fck");
314
315 of_node_put(np);
316
317 oh = omap_hwmod_lookup(oh_name);
318 if (!oh)
319 return -ENODEV;
320
321 *timer_name = oh->name;
322
323 if (!timer->io_base)
324 return -ENXIO;
325
326 omap_hwmod_setup_one(oh_name);
327
328 /* After the dmtimer is using hwmod these clocks won't be needed */
329 if (IS_ERR_OR_NULL(timer->fclk))
330 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
331 if (IS_ERR(timer->fclk))
332 return PTR_ERR(timer->fclk);
333
334 src = clk_get(NULL, fck_source);
335 if (IS_ERR(src))
336 return PTR_ERR(src);
337
338 WARN(clk_set_parent(timer->fclk, src) < 0,
339 "Cannot set timer parent clock, no PLL clock driver?");
340
341 clk_put(src);
342
343 omap_hwmod_enable(oh);
344 __omap_dm_timer_init_regs(timer);
345
346 if (posted)
347 __omap_dm_timer_enable_posted(timer);
348
349 /* Check that the intended posted configuration matches the actual */
350 if (posted != timer->posted)
351 return -EINVAL;
352
353 timer->rate = clk_get_rate(timer->fclk);
354 timer->reserved = 1;
355
356 return r;
357}
358
359#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
360void tick_broadcast(const struct cpumask *mask)
361{
362}
363#endif
364
365static void __init omap2_gp_clockevent_init(int gptimer_id,
366 const char *fck_source,
367 const char *property)
368{
369 int res;
370
371 clkev.id = gptimer_id;
372 clkev.errata = omap_dm_timer_get_errata();
373
374 /*
375 * For clock-event timers we never read the timer counter and
376 * so we are not impacted by errata i103 and i767. Therefore,
377 * we can safely ignore this errata for clock-event timers.
378 */
379 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
380
381 res = omap_dm_timer_init_one(&clkev, fck_source, property,
382 &clockevent_gpt.name, OMAP_TIMER_POSTED);
383 BUG_ON(res);
384
385 omap2_gp_timer_irq.dev_id = &clkev;
386 setup_irq(clkev.irq, &omap2_gp_timer_irq);
387
388 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
389
390 clockevent_gpt.cpumask = cpu_possible_mask;
391 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
392 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
393 3, /* Timer internal resynch latency */
394 0xffffffff);
395
396 if (soc_is_am33xx() || soc_is_am43xx()) {
397 clockevent_gpt.suspend = omap_clkevt_idle;
398 clockevent_gpt.resume = omap_clkevt_unidle;
399
400 clockevent_gpt_hwmod =
401 omap_hwmod_lookup(clockevent_gpt.name);
402 }
403
404 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
405 clkev.rate);
406}
407
408/* Clocksource code */
409static struct omap_dm_timer clksrc;
410static bool use_gptimer_clksrc __initdata;
411
412/*
413 * clocksource
414 */
415static u64 clocksource_read_cycles(struct clocksource *cs)
416{
417 return (u64)__omap_dm_timer_read_counter(&clksrc,
418 OMAP_TIMER_NONPOSTED);
419}
420
421static struct clocksource clocksource_gpt = {
422 .rating = 300,
423 .read = clocksource_read_cycles,
424 .mask = CLOCKSOURCE_MASK(32),
425 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
426};
427
428static u64 notrace dmtimer_read_sched_clock(void)
429{
430 if (clksrc.reserved)
431 return __omap_dm_timer_read_counter(&clksrc,
432 OMAP_TIMER_NONPOSTED);
433
434 return 0;
435}
436
437static const struct of_device_id omap_counter_match[] __initconst = {
438 { .compatible = "ti,omap-counter32k", },
439 { }
440};
441
442/* Setup free-running counter for clocksource */
443static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
444{
445 int ret;
446 struct device_node *np = NULL;
447 struct omap_hwmod *oh;
448 const char *oh_name = "counter_32k";
449
450 /*
451 * See if the 32kHz counter is supported.
452 */
453 np = omap_get_timer_dt(omap_counter_match, NULL);
454 if (!np)
455 return -ENODEV;
456
457 of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
458 if (!oh_name) {
459 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
460 if (!oh_name)
461 return -ENODEV;
462 }
463
464 /*
465 * First check hwmod data is available for sync32k counter
466 */
467 oh = omap_hwmod_lookup(oh_name);
468 if (!oh || oh->slaves_cnt == 0)
469 return -ENODEV;
470
471 omap_hwmod_setup_one(oh_name);
472
473 ret = omap_hwmod_enable(oh);
474 if (ret) {
475 pr_warn("%s: failed to enable counter_32k module (%d)\n",
476 __func__, ret);
477 return ret;
478 }
479
480 return ret;
481}
482
483static unsigned int omap2_gptimer_clksrc_load;
484
485static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
486{
487 omap2_gptimer_clksrc_load =
488 __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
489
490 omap_hwmod_idle(clocksource_gpt_hwmod);
491}
492
493static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
494{
495 omap_hwmod_enable(clocksource_gpt_hwmod);
496
497 __omap_dm_timer_load_start(&clksrc,
498 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
499 omap2_gptimer_clksrc_load,
500 OMAP_TIMER_NONPOSTED);
501}
502
503static void __init omap2_gptimer_clocksource_init(int gptimer_id,
504 const char *fck_source,
505 const char *property)
506{
507 int res;
508
509 clksrc.id = gptimer_id;
510 clksrc.errata = omap_dm_timer_get_errata();
511
512 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
513 &clocksource_gpt.name,
514 OMAP_TIMER_NONPOSTED);
515
516 if (soc_is_am43xx()) {
517 clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
518 clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
519
520 clocksource_gpt_hwmod =
521 omap_hwmod_lookup(clocksource_gpt.name);
522 }
523
524 BUG_ON(res);
525
526 __omap_dm_timer_load_start(&clksrc,
527 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
528 OMAP_TIMER_NONPOSTED);
529 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
530
531 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
532 pr_err("Could not register clocksource %s\n",
533 clocksource_gpt.name);
534 else
535 pr_info("OMAP clocksource: %s at %lu Hz\n",
536 clocksource_gpt.name, clksrc.rate);
537}
538
539static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
540 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
541 const char *clksrc_prop, bool gptimer)
542{
543 omap_clk_init();
544 omap_dmtimer_init();
545 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
546
547 /* Enable the use of clocksource="gp_timer" kernel parameter */
548 if (use_gptimer_clksrc || gptimer)
549 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
550 clksrc_prop);
551 else
552 omap2_sync32k_clocksource_init();
553}
554
555void __init omap_init_time(void)
556{
557 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
558 2, "timer_sys_ck", NULL, false);
559
560 timer_probe();
561}
562
563#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
564void __init omap3_secure_sync32k_timer_init(void)
565{
566 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
567 2, "timer_sys_ck", NULL, false);
568
569 timer_probe();
570}
571#endif /* CONFIG_ARCH_OMAP3 */
572
573#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
574 defined(CONFIG_SOC_AM43XX)
575void __init omap3_gptimer_timer_init(void)
576{
577 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
578 1, "timer_sys_ck", "ti,timer-alwon", true);
579 if (of_have_populated_dt())
580 timer_probe();
581}
582#endif
583
584#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
585 defined(CONFIG_SOC_DRA7XX)
586static void __init omap4_sync32k_timer_init(void)
587{
588 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
589 2, "sys_clkin_ck", NULL, false);
590}
591
592void __init omap4_local_timer_init(void)
593{
594 omap4_sync32k_timer_init();
595 timer_probe();
596}
597#endif
598
599#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
600
601/*
602 * The realtime counter also called master counter, is a free-running
603 * counter, which is related to real time. It produces the count used
604 * by the CPU local timer peripherals in the MPU cluster. The timer counts
605 * at a rate of 6.144 MHz. Because the device operates on different clocks
606 * in different power modes, the master counter shifts operation between
607 * clocks, adjusting the increment per clock in hardware accordingly to
608 * maintain a constant count rate.
609 */
610static void __init realtime_counter_init(void)
611{
612#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
613 void __iomem *base;
614 static struct clk *sys_clk;
615 unsigned long rate;
616 unsigned int reg;
617 unsigned long long num, den;
618
619 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
620 if (!base) {
621 pr_err("%s: ioremap failed\n", __func__);
622 return;
623 }
624 sys_clk = clk_get(NULL, "sys_clkin");
625 if (IS_ERR(sys_clk)) {
626 pr_err("%s: failed to get system clock handle\n", __func__);
627 iounmap(base);
628 return;
629 }
630
631 rate = clk_get_rate(sys_clk);
632
633 if (soc_is_dra7xx()) {
634 /*
635 * Errata i856 says the 32.768KHz crystal does not start at
636 * power on, so the CPU falls back to an emulated 32KHz clock
637 * based on sysclk / 610 instead. This causes the master counter
638 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
639 * (OR sysclk * 75 / 244)
640 *
641 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
642 * Of course any board built without a populated 32.768KHz
643 * crystal would also need this fix even if the CPU is fixed
644 * later.
645 *
646 * Either case can be detected by using the two speedselect bits
647 * If they are not 0, then the 32.768KHz clock driving the
648 * coarse counter that corrects the fine counter every time it
649 * ticks is actually rate/610 rather than 32.768KHz and we
650 * should compensate to avoid the 570ppm (at 20MHz, much worse
651 * at other rates) too fast system time.
652 */
653 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
654 if (reg & DRA7_SPEEDSELECT_MASK) {
655 num = 75;
656 den = 244;
657 goto sysclk1_based;
658 }
659 }
660
661 /* Numerator/denumerator values refer TRM Realtime Counter section */
662 switch (rate) {
663 case 12000000:
664 num = 64;
665 den = 125;
666 break;
667 case 13000000:
668 num = 768;
669 den = 1625;
670 break;
671 case 19200000:
672 num = 8;
673 den = 25;
674 break;
675 case 20000000:
676 num = 192;
677 den = 625;
678 break;
679 case 26000000:
680 num = 384;
681 den = 1625;
682 break;
683 case 27000000:
684 num = 256;
685 den = 1125;
686 break;
687 case 38400000:
688 default:
689 /* Program it for 38.4 MHz */
690 num = 4;
691 den = 25;
692 break;
693 }
694
695sysclk1_based:
696 /* Program numerator and denumerator registers */
697 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
698 NUMERATOR_DENUMERATOR_MASK;
699 reg |= num;
700 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
701
702 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
703 NUMERATOR_DENUMERATOR_MASK;
704 reg |= den;
705 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
706
707 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
708 set_cntfreq();
709
710 iounmap(base);
711#endif
712}
713
714void __init omap5_realtime_timer_init(void)
715{
716 omap4_sync32k_timer_init();
717 realtime_counter_init();
718
719 timer_probe();
720}
721#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
722
723/**
724 * omap2_override_clocksource - clocksource override with user configuration
725 *
726 * Allows user to override default clocksource, using kernel parameter
727 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
728 *
729 * Note that, here we are using same standard kernel parameter "clocksource=",
730 * and not introducing any OMAP specific interface.
731 */
732static int __init omap2_override_clocksource(char *str)
733{
734 if (!str)
735 return 0;
736 /*
737 * For OMAP architecture, we only have two options
738 * - sync_32k (default)
739 * - gp_timer (sys_clk based)
740 */
741 if (!strcmp(str, "gp_timer"))
742 use_gptimer_clksrc = true;
743
744 return 0;
745}
746early_param("clocksource", omap2_override_clocksource);
1/*
2 * linux/arch/arm/mach-omap2/timer.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
17 *
18 * Some parts based off of TI's 24xx code:
19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 *
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29#include <linux/init.h>
30#include <linux/time.h>
31#include <linux/interrupt.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/clocksource.h>
37#include <linux/clockchips.h>
38#include <linux/slab.h>
39#include <linux/of.h>
40#include <linux/of_address.h>
41#include <linux/of_irq.h>
42#include <linux/platform_device.h>
43#include <linux/platform_data/dmtimer-omap.h>
44#include <linux/sched_clock.h>
45
46#include <asm/mach/time.h>
47#include <asm/smp_twd.h>
48
49#include "omap_hwmod.h"
50#include "omap_device.h"
51#include <plat/counter-32k.h>
52#include <plat/dmtimer.h>
53#include "omap-pm.h"
54
55#include "soc.h"
56#include "common.h"
57#include "control.h"
58#include "powerdomain.h"
59#include "omap-secure.h"
60
61#define REALTIME_COUNTER_BASE 0x48243200
62#define INCREMENTER_NUMERATOR_OFFSET 0x10
63#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
64#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
65
66/* Clockevent code */
67
68static struct omap_dm_timer clkev;
69static struct clock_event_device clockevent_gpt;
70
71#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
72static unsigned long arch_timer_freq;
73
74void set_cntfreq(void)
75{
76 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
77}
78#endif
79
80static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
81{
82 struct clock_event_device *evt = &clockevent_gpt;
83
84 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
85
86 evt->event_handler(evt);
87 return IRQ_HANDLED;
88}
89
90static struct irqaction omap2_gp_timer_irq = {
91 .name = "gp_timer",
92 .flags = IRQF_TIMER | IRQF_IRQPOLL,
93 .handler = omap2_gp_timer_interrupt,
94};
95
96static int omap2_gp_timer_set_next_event(unsigned long cycles,
97 struct clock_event_device *evt)
98{
99 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
100 0xffffffff - cycles, OMAP_TIMER_POSTED);
101
102 return 0;
103}
104
105static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
106{
107 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
108 return 0;
109}
110
111static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
112{
113 u32 period;
114
115 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
116
117 period = clkev.rate / HZ;
118 period -= 1;
119 /* Looks like we need to first set the load value separately */
120 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
121 OMAP_TIMER_POSTED);
122 __omap_dm_timer_load_start(&clkev,
123 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
124 0xffffffff - period, OMAP_TIMER_POSTED);
125 return 0;
126}
127
128static struct clock_event_device clockevent_gpt = {
129 .features = CLOCK_EVT_FEAT_PERIODIC |
130 CLOCK_EVT_FEAT_ONESHOT,
131 .rating = 300,
132 .set_next_event = omap2_gp_timer_set_next_event,
133 .set_state_shutdown = omap2_gp_timer_shutdown,
134 .set_state_periodic = omap2_gp_timer_set_periodic,
135 .set_state_oneshot = omap2_gp_timer_shutdown,
136 .tick_resume = omap2_gp_timer_shutdown,
137};
138
139static struct property device_disabled = {
140 .name = "status",
141 .length = sizeof("disabled"),
142 .value = "disabled",
143};
144
145static const struct of_device_id omap_timer_match[] __initconst = {
146 { .compatible = "ti,omap2420-timer", },
147 { .compatible = "ti,omap3430-timer", },
148 { .compatible = "ti,omap4430-timer", },
149 { .compatible = "ti,omap5430-timer", },
150 { .compatible = "ti,dm814-timer", },
151 { .compatible = "ti,dm816-timer", },
152 { .compatible = "ti,am335x-timer", },
153 { .compatible = "ti,am335x-timer-1ms", },
154 { }
155};
156
157/**
158 * omap_get_timer_dt - get a timer using device-tree
159 * @match - device-tree match structure for matching a device type
160 * @property - optional timer property to match
161 *
162 * Helper function to get a timer during early boot using device-tree for use
163 * as kernel system timer. Optionally, the property argument can be used to
164 * select a timer with a specific property. Once a timer is found then mark
165 * the timer node in device-tree as disabled, to prevent the kernel from
166 * registering this timer as a platform device and so no one else can use it.
167 */
168static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
169 const char *property)
170{
171 struct device_node *np;
172
173 for_each_matching_node(np, match) {
174 if (!of_device_is_available(np))
175 continue;
176
177 if (property && !of_get_property(np, property, NULL))
178 continue;
179
180 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
181 of_get_property(np, "ti,timer-dsp", NULL) ||
182 of_get_property(np, "ti,timer-pwm", NULL) ||
183 of_get_property(np, "ti,timer-secure", NULL)))
184 continue;
185
186 if (!of_device_is_compatible(np, "ti,omap-counter32k"))
187 of_add_property(np, &device_disabled);
188 return np;
189 }
190
191 return NULL;
192}
193
194/**
195 * omap_dmtimer_init - initialisation function when device tree is used
196 *
197 * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
198 * cannot be used by the kernel as they are reserved. Therefore, to prevent the
199 * kernel registering these devices remove them dynamically from the device
200 * tree on boot.
201 */
202static void __init omap_dmtimer_init(void)
203{
204 struct device_node *np;
205
206 if (!cpu_is_omap34xx() && !soc_is_dra7xx())
207 return;
208
209 /* If we are a secure device, remove any secure timer nodes */
210 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
211 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
212 of_node_put(np);
213 }
214}
215
216/**
217 * omap_dm_timer_get_errata - get errata flags for a timer
218 *
219 * Get the timer errata flags that are specific to the OMAP device being used.
220 */
221static u32 __init omap_dm_timer_get_errata(void)
222{
223 if (cpu_is_omap24xx())
224 return 0;
225
226 return OMAP_TIMER_ERRATA_I103_I767;
227}
228
229static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
230 const char *fck_source,
231 const char *property,
232 const char **timer_name,
233 int posted)
234{
235 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
236 const char *oh_name = NULL;
237 struct device_node *np;
238 struct omap_hwmod *oh;
239 struct resource irq, mem;
240 struct clk *src;
241 int r = 0;
242
243 if (of_have_populated_dt()) {
244 np = omap_get_timer_dt(omap_timer_match, property);
245 if (!np)
246 return -ENODEV;
247
248 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
249 if (!oh_name)
250 return -ENODEV;
251
252 timer->irq = irq_of_parse_and_map(np, 0);
253 if (!timer->irq)
254 return -ENXIO;
255
256 timer->io_base = of_iomap(np, 0);
257
258 of_node_put(np);
259 } else {
260 if (omap_dm_timer_reserve_systimer(timer->id))
261 return -ENODEV;
262
263 sprintf(name, "timer%d", timer->id);
264 oh_name = name;
265 }
266
267 oh = omap_hwmod_lookup(oh_name);
268 if (!oh)
269 return -ENODEV;
270
271 *timer_name = oh->name;
272
273 if (!of_have_populated_dt()) {
274 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
275 &irq);
276 if (r)
277 return -ENXIO;
278 timer->irq = irq.start;
279
280 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
281 &mem);
282 if (r)
283 return -ENXIO;
284
285 /* Static mapping, never released */
286 timer->io_base = ioremap(mem.start, mem.end - mem.start);
287 }
288
289 if (!timer->io_base)
290 return -ENXIO;
291
292 omap_hwmod_setup_one(oh_name);
293
294 /* After the dmtimer is using hwmod these clocks won't be needed */
295 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
296 if (IS_ERR(timer->fclk))
297 return PTR_ERR(timer->fclk);
298
299 src = clk_get(NULL, fck_source);
300 if (IS_ERR(src))
301 return PTR_ERR(src);
302
303 WARN(clk_set_parent(timer->fclk, src) < 0,
304 "Cannot set timer parent clock, no PLL clock driver?");
305
306 clk_put(src);
307
308 omap_hwmod_enable(oh);
309 __omap_dm_timer_init_regs(timer);
310
311 if (posted)
312 __omap_dm_timer_enable_posted(timer);
313
314 /* Check that the intended posted configuration matches the actual */
315 if (posted != timer->posted)
316 return -EINVAL;
317
318 timer->rate = clk_get_rate(timer->fclk);
319 timer->reserved = 1;
320
321 return r;
322}
323
324#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
325void tick_broadcast(const struct cpumask *mask)
326{
327}
328#endif
329
330static void __init omap2_gp_clockevent_init(int gptimer_id,
331 const char *fck_source,
332 const char *property)
333{
334 int res;
335
336 clkev.id = gptimer_id;
337 clkev.errata = omap_dm_timer_get_errata();
338
339 /*
340 * For clock-event timers we never read the timer counter and
341 * so we are not impacted by errata i103 and i767. Therefore,
342 * we can safely ignore this errata for clock-event timers.
343 */
344 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
345
346 res = omap_dm_timer_init_one(&clkev, fck_source, property,
347 &clockevent_gpt.name, OMAP_TIMER_POSTED);
348 BUG_ON(res);
349
350 omap2_gp_timer_irq.dev_id = &clkev;
351 setup_irq(clkev.irq, &omap2_gp_timer_irq);
352
353 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
354
355 clockevent_gpt.cpumask = cpu_possible_mask;
356 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
357 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
358 3, /* Timer internal resynch latency */
359 0xffffffff);
360
361 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
362 clkev.rate);
363}
364
365/* Clocksource code */
366static struct omap_dm_timer clksrc;
367static bool use_gptimer_clksrc __initdata;
368
369/*
370 * clocksource
371 */
372static u64 clocksource_read_cycles(struct clocksource *cs)
373{
374 return (u64)__omap_dm_timer_read_counter(&clksrc,
375 OMAP_TIMER_NONPOSTED);
376}
377
378static struct clocksource clocksource_gpt = {
379 .rating = 300,
380 .read = clocksource_read_cycles,
381 .mask = CLOCKSOURCE_MASK(32),
382 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
383};
384
385static u64 notrace dmtimer_read_sched_clock(void)
386{
387 if (clksrc.reserved)
388 return __omap_dm_timer_read_counter(&clksrc,
389 OMAP_TIMER_NONPOSTED);
390
391 return 0;
392}
393
394static const struct of_device_id omap_counter_match[] __initconst = {
395 { .compatible = "ti,omap-counter32k", },
396 { }
397};
398
399/* Setup free-running counter for clocksource */
400static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
401{
402 int ret;
403 struct device_node *np = NULL;
404 struct omap_hwmod *oh;
405 const char *oh_name = "counter_32k";
406
407 /*
408 * If device-tree is present, then search the DT blob
409 * to see if the 32kHz counter is supported.
410 */
411 if (of_have_populated_dt()) {
412 np = omap_get_timer_dt(omap_counter_match, NULL);
413 if (!np)
414 return -ENODEV;
415
416 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
417 if (!oh_name)
418 return -ENODEV;
419 }
420
421 /*
422 * First check hwmod data is available for sync32k counter
423 */
424 oh = omap_hwmod_lookup(oh_name);
425 if (!oh || oh->slaves_cnt == 0)
426 return -ENODEV;
427
428 omap_hwmod_setup_one(oh_name);
429
430 ret = omap_hwmod_enable(oh);
431 if (ret) {
432 pr_warn("%s: failed to enable counter_32k module (%d)\n",
433 __func__, ret);
434 return ret;
435 }
436
437 if (!of_have_populated_dt()) {
438 void __iomem *vbase;
439
440 vbase = omap_hwmod_get_mpu_rt_va(oh);
441
442 ret = omap_init_clocksource_32k(vbase);
443 if (ret) {
444 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
445 __func__, ret);
446 omap_hwmod_idle(oh);
447 }
448 }
449 return ret;
450}
451
452static void __init omap2_gptimer_clocksource_init(int gptimer_id,
453 const char *fck_source,
454 const char *property)
455{
456 int res;
457
458 clksrc.id = gptimer_id;
459 clksrc.errata = omap_dm_timer_get_errata();
460
461 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
462 &clocksource_gpt.name,
463 OMAP_TIMER_NONPOSTED);
464 BUG_ON(res);
465
466 __omap_dm_timer_load_start(&clksrc,
467 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
468 OMAP_TIMER_NONPOSTED);
469 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
470
471 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
472 pr_err("Could not register clocksource %s\n",
473 clocksource_gpt.name);
474 else
475 pr_info("OMAP clocksource: %s at %lu Hz\n",
476 clocksource_gpt.name, clksrc.rate);
477}
478
479static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
480 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
481 const char *clksrc_prop, bool gptimer)
482{
483 omap_clk_init();
484 omap_dmtimer_init();
485 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
486
487 /* Enable the use of clocksource="gp_timer" kernel parameter */
488 if (use_gptimer_clksrc || gptimer)
489 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
490 clksrc_prop);
491 else
492 omap2_sync32k_clocksource_init();
493}
494
495void __init omap_init_time(void)
496{
497 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
498 2, "timer_sys_ck", NULL, false);
499
500 clocksource_probe();
501}
502
503#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
504void __init omap3_secure_sync32k_timer_init(void)
505{
506 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
507 2, "timer_sys_ck", NULL, false);
508
509 clocksource_probe();
510}
511#endif /* CONFIG_ARCH_OMAP3 */
512
513#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
514 defined(CONFIG_SOC_AM43XX)
515void __init omap3_gptimer_timer_init(void)
516{
517 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
518 1, "timer_sys_ck", "ti,timer-alwon", true);
519 if (of_have_populated_dt())
520 clocksource_probe();
521}
522#endif
523
524#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
525 defined(CONFIG_SOC_DRA7XX)
526static void __init omap4_sync32k_timer_init(void)
527{
528 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
529 2, "sys_clkin_ck", NULL, false);
530}
531
532void __init omap4_local_timer_init(void)
533{
534 omap4_sync32k_timer_init();
535 clocksource_probe();
536}
537#endif
538
539#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
540
541/*
542 * The realtime counter also called master counter, is a free-running
543 * counter, which is related to real time. It produces the count used
544 * by the CPU local timer peripherals in the MPU cluster. The timer counts
545 * at a rate of 6.144 MHz. Because the device operates on different clocks
546 * in different power modes, the master counter shifts operation between
547 * clocks, adjusting the increment per clock in hardware accordingly to
548 * maintain a constant count rate.
549 */
550static void __init realtime_counter_init(void)
551{
552#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
553 void __iomem *base;
554 static struct clk *sys_clk;
555 unsigned long rate;
556 unsigned int reg;
557 unsigned long long num, den;
558
559 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
560 if (!base) {
561 pr_err("%s: ioremap failed\n", __func__);
562 return;
563 }
564 sys_clk = clk_get(NULL, "sys_clkin");
565 if (IS_ERR(sys_clk)) {
566 pr_err("%s: failed to get system clock handle\n", __func__);
567 iounmap(base);
568 return;
569 }
570
571 rate = clk_get_rate(sys_clk);
572
573 if (soc_is_dra7xx()) {
574 /*
575 * Errata i856 says the 32.768KHz crystal does not start at
576 * power on, so the CPU falls back to an emulated 32KHz clock
577 * based on sysclk / 610 instead. This causes the master counter
578 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
579 * (OR sysclk * 75 / 244)
580 *
581 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
582 * Of course any board built without a populated 32.768KHz
583 * crystal would also need this fix even if the CPU is fixed
584 * later.
585 *
586 * Either case can be detected by using the two speedselect bits
587 * If they are not 0, then the 32.768KHz clock driving the
588 * coarse counter that corrects the fine counter every time it
589 * ticks is actually rate/610 rather than 32.768KHz and we
590 * should compensate to avoid the 570ppm (at 20MHz, much worse
591 * at other rates) too fast system time.
592 */
593 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
594 if (reg & DRA7_SPEEDSELECT_MASK) {
595 num = 75;
596 den = 244;
597 goto sysclk1_based;
598 }
599 }
600
601 /* Numerator/denumerator values refer TRM Realtime Counter section */
602 switch (rate) {
603 case 12000000:
604 num = 64;
605 den = 125;
606 break;
607 case 13000000:
608 num = 768;
609 den = 1625;
610 break;
611 case 19200000:
612 num = 8;
613 den = 25;
614 break;
615 case 20000000:
616 num = 192;
617 den = 625;
618 break;
619 case 26000000:
620 num = 384;
621 den = 1625;
622 break;
623 case 27000000:
624 num = 256;
625 den = 1125;
626 break;
627 case 38400000:
628 default:
629 /* Program it for 38.4 MHz */
630 num = 4;
631 den = 25;
632 break;
633 }
634
635sysclk1_based:
636 /* Program numerator and denumerator registers */
637 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
638 NUMERATOR_DENUMERATOR_MASK;
639 reg |= num;
640 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
641
642 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
643 NUMERATOR_DENUMERATOR_MASK;
644 reg |= den;
645 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
646
647 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
648 set_cntfreq();
649
650 iounmap(base);
651#endif
652}
653
654void __init omap5_realtime_timer_init(void)
655{
656 omap4_sync32k_timer_init();
657 realtime_counter_init();
658
659 clocksource_probe();
660}
661#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
662
663/**
664 * omap_timer_init - build and register timer device with an
665 * associated timer hwmod
666 * @oh: timer hwmod pointer to be used to build timer device
667 * @user: parameter that can be passed from calling hwmod API
668 *
669 * Called by omap_hwmod_for_each_by_class to register each of the timer
670 * devices present in the system. The number of timer devices is known
671 * by parsing through the hwmod database for a given class name. At the
672 * end of function call memory is allocated for timer device and it is
673 * registered to the framework ready to be proved by the driver.
674 */
675static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
676{
677 int id;
678 int ret = 0;
679 char *name = "omap_timer";
680 struct dmtimer_platform_data *pdata;
681 struct platform_device *pdev;
682 struct omap_timer_capability_dev_attr *timer_dev_attr;
683
684 pr_debug("%s: %s\n", __func__, oh->name);
685
686 /* on secure device, do not register secure timer */
687 timer_dev_attr = oh->dev_attr;
688 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
689 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
690 return ret;
691
692 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
693 if (!pdata) {
694 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
695 return -ENOMEM;
696 }
697
698 /*
699 * Extract the IDs from name field in hwmod database
700 * and use the same for constructing ids' for the
701 * timer devices. In a way, we are avoiding usage of
702 * static variable witin the function to do the same.
703 * CAUTION: We have to be careful and make sure the
704 * name in hwmod database does not change in which case
705 * we might either make corresponding change here or
706 * switch back static variable mechanism.
707 */
708 sscanf(oh->name, "timer%2d", &id);
709
710 if (timer_dev_attr)
711 pdata->timer_capability = timer_dev_attr->timer_capability;
712
713 pdata->timer_errata = omap_dm_timer_get_errata();
714 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
715
716 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
717
718 if (IS_ERR(pdev)) {
719 pr_err("%s: Can't build omap_device for %s: %s.\n",
720 __func__, name, oh->name);
721 ret = -EINVAL;
722 }
723
724 kfree(pdata);
725
726 return ret;
727}
728
729/**
730 * omap2_dm_timer_init - top level regular device initialization
731 *
732 * Uses dedicated hwmod api to parse through hwmod database for
733 * given class name and then build and register the timer device.
734 */
735static int __init omap2_dm_timer_init(void)
736{
737 int ret;
738
739 /* If dtb is there, the devices will be created dynamically */
740 if (of_have_populated_dt())
741 return -ENODEV;
742
743 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
744 if (unlikely(ret)) {
745 pr_err("%s: device registration failed.\n", __func__);
746 return -EINVAL;
747 }
748
749 return 0;
750}
751omap_arch_initcall(omap2_dm_timer_init);
752
753/**
754 * omap2_override_clocksource - clocksource override with user configuration
755 *
756 * Allows user to override default clocksource, using kernel parameter
757 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
758 *
759 * Note that, here we are using same standard kernel parameter "clocksource=",
760 * and not introducing any OMAP specific interface.
761 */
762static int __init omap2_override_clocksource(char *str)
763{
764 if (!str)
765 return 0;
766 /*
767 * For OMAP architecture, we only have two options
768 * - sync_32k (default)
769 * - gp_timer (sys_clk based)
770 */
771 if (!strcmp(str, "gp_timer"))
772 use_gptimer_clksrc = true;
773
774 return 0;
775}
776early_param("clocksource", omap2_override_clocksource);