1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 2//
 3// Copyright 2013 Freescale Semiconductor, Inc.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 4
 
 5#include "vfxxx.dtsi"
 6#include <dt-bindings/interrupt-controller/arm-gic.h>
 7
 8/ {
 9	#address-cells = <1>;
10	#size-cells = <1>;
11	chosen { };
12	aliases { };
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		a5_cpu: cpu@0 {
19			compatible = "arm,cortex-a5";
20			device_type = "cpu";
21			reg = <0x0>;
22		};
23	};
24
25	soc {
26		aips-bus@40000000 {
27
28			intc: interrupt-controller@40003000 {
29				compatible = "arm,cortex-a9-gic";
30				#interrupt-cells = <3>;
31				interrupt-controller;
32				interrupt-parent = <&intc>;
33				reg = <0x40003000 0x1000>,
34				      <0x40002100 0x100>;
35			};
36
37			global_timer: timer@40002200 {
38				compatible = "arm,cortex-a9-global-timer";
39				reg = <0x40002200 0x20>;
40				interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
41				interrupt-parent = <&intc>;
42				clocks = <&clks VF610_CLK_PLATFORM_BUS>;
43			};
44		};
45
46		aips-bus@40080000 {
47			pmu@40089000 {
48				compatible = "arm,cortex-a5-pmu";
49				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
50				interrupt-affinity = <&a5_cpu>;
51				reg = <0x40089000 0x1000>;
52			};
53		};
54
55	};
56};
57
58&mscm_ir {
59	interrupt-parent = <&intc>;
60};
61
62&wdoga5 {
63	status = "okay";
64};

 1/*
 2 * Copyright 2013 Freescale Semiconductor, Inc.
 3 *
 4 * This file is dual-licensed: you can use it either under the terms
 5 * of the GPL or the X11 license, at your option. Note that this dual
 6 * licensing only applies to this file, and not this project as a
 7 * whole.
 8 *
 9 *  a) This file is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License
11 *     version 2 as published by the Free Software Foundation.
12 *
13 *     This file is distributed in the hope that it will be useful
14 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 *     GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 *  b) Permission is hereby granted, free of charge, to any person
21 *     obtaining a copy of this software and associated documentation
22 *     files (the "Software"), to deal in the Software without
23 *     restriction, including without limitation the rights to use
24 *     copy, modify, merge, publish, distribute, sublicense, and/or
25 *     sell copies of the Software, and to permit persons to whom the
26 *     Software is furnished to do so, subject to the following
27 *     conditions:
28 *
29 *     The above copyright notice and this permission notice shall be
30 *     included in all copies or substantial portions of the Software.
31 *
32 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 *     OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include "skeleton.dtsi"
43#include "vfxxx.dtsi"
44#include <dt-bindings/interrupt-controller/arm-gic.h>
45
46/ {
 
 
 
 
 
47	cpus {
48		#address-cells = <1>;
49		#size-cells = <0>;
50
51		a5_cpu: cpu@0 {
52			compatible = "arm,cortex-a5";
53			device_type = "cpu";
54			reg = <0x0>;
55		};
56	};
57
58	soc {
59		aips-bus@40000000 {
60
61			intc: interrupt-controller@40002000 {
62				compatible = "arm,cortex-a9-gic";
63				#interrupt-cells = <3>;
64				interrupt-controller;
65				interrupt-parent = <&intc>;
66				reg = <0x40003000 0x1000>,
67				      <0x40002100 0x100>;
68			};
69
70			global_timer: timer@40002200 {
71				compatible = "arm,cortex-a9-global-timer";
72				reg = <0x40002200 0x20>;
73				interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
74				interrupt-parent = <&intc>;
75				clocks = <&clks VF610_CLK_PLATFORM_BUS>;
76			};
77		};
78
79		aips-bus@40080000 {
80			pmu@40089000 {
81				compatible = "arm,cortex-a5-pmu";
82				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
83				interrupt-affinity = <&a5_cpu>;
84				reg = <0x40089000 0x1000>;
85			};
86		};
87
88	};
89};
90
91&mscm_ir {
92	interrupt-parent = <&intc>;
93};
94
95&wdoga5 {
96	status = "okay";
97};