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1/*
2 * Device Tree Source for UniPhier sLD3 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46/include/ "skeleton.dtsi"
47
48/ {
49 compatible = "socionext,uniphier-sld3";
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu@0 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a9";
58 reg = <0>;
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 };
62
63 cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a9";
66 reg = <1>;
67 enable-method = "psci";
68 next-level-cache = <&l2>;
69 };
70 };
71
72 psci {
73 compatible = "arm,psci-0.2";
74 method = "smc";
75 };
76
77 clocks {
78 refclk: ref {
79 #clock-cells = <0>;
80 compatible = "fixed-clock";
81 clock-frequency = <24576000>;
82 };
83
84 arm_timer_clk: arm_timer_clk {
85 #clock-cells = <0>;
86 compatible = "fixed-clock";
87 clock-frequency = <50000000>;
88 };
89 };
90
91 soc {
92 compatible = "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 interrupt-parent = <&intc>;
97
98 timer@20000200 {
99 compatible = "arm,cortex-a9-global-timer";
100 reg = <0x20000200 0x20>;
101 interrupts = <1 11 0x304>;
102 clocks = <&arm_timer_clk>;
103 };
104
105 timer@20000600 {
106 compatible = "arm,cortex-a9-twd-timer";
107 reg = <0x20000600 0x20>;
108 interrupts = <1 13 0x304>;
109 clocks = <&arm_timer_clk>;
110 };
111
112 intc: interrupt-controller@20001000 {
113 compatible = "arm,cortex-a9-gic";
114 #interrupt-cells = <3>;
115 interrupt-controller;
116 reg = <0x20001000 0x1000>,
117 <0x20000100 0x100>;
118 };
119
120 l2: l2-cache@500c0000 {
121 compatible = "socionext,uniphier-system-cache";
122 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
123 <0x506c0000 0x400>;
124 interrupts = <0 174 4>, <0 175 4>;
125 cache-unified;
126 cache-size = <(512 * 1024)>;
127 cache-sets = <256>;
128 cache-line-size = <128>;
129 cache-level = <2>;
130 };
131
132 serial0: serial@54006800 {
133 compatible = "socionext,uniphier-uart";
134 status = "disabled";
135 reg = <0x54006800 0x40>;
136 interrupts = <0 33 4>;
137 clocks = <&sys_clk 0>;
138 };
139
140 serial1: serial@54006900 {
141 compatible = "socionext,uniphier-uart";
142 status = "disabled";
143 reg = <0x54006900 0x40>;
144 interrupts = <0 35 4>;
145 clocks = <&sys_clk 0>;
146 };
147
148 serial2: serial@54006a00 {
149 compatible = "socionext,uniphier-uart";
150 status = "disabled";
151 reg = <0x54006a00 0x40>;
152 interrupts = <0 37 4>;
153 clocks = <&sys_clk 0>;
154 };
155
156 i2c0: i2c@58400000 {
157 compatible = "socionext,uniphier-i2c";
158 status = "disabled";
159 reg = <0x58400000 0x40>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupts = <0 41 1>;
163 clocks = <&sys_clk 1>;
164 clock-frequency = <100000>;
165 };
166
167 i2c1: i2c@58480000 {
168 compatible = "socionext,uniphier-i2c";
169 status = "disabled";
170 reg = <0x58480000 0x40>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 interrupts = <0 42 1>;
174 clocks = <&sys_clk 1>;
175 clock-frequency = <100000>;
176 };
177
178 i2c2: i2c@58500000 {
179 compatible = "socionext,uniphier-i2c";
180 status = "disabled";
181 reg = <0x58500000 0x40>;
182 #address-cells = <1>;
183 #size-cells = <0>;
184 interrupts = <0 43 1>;
185 clocks = <&sys_clk 1>;
186 clock-frequency = <100000>;
187 };
188
189 i2c3: i2c@58580000 {
190 compatible = "socionext,uniphier-i2c";
191 status = "disabled";
192 reg = <0x58580000 0x40>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 interrupts = <0 44 1>;
196 clocks = <&sys_clk 1>;
197 clock-frequency = <100000>;
198 };
199
200 /* chip-internal connection for DMD */
201 i2c4: i2c@58600000 {
202 compatible = "socionext,uniphier-i2c";
203 reg = <0x58600000 0x40>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 interrupts = <0 45 1>;
207 clocks = <&sys_clk 1>;
208 clock-frequency = <400000>;
209 };
210
211 system_bus: system-bus@58c00000 {
212 compatible = "socionext,uniphier-system-bus";
213 status = "disabled";
214 reg = <0x58c00000 0x400>;
215 #address-cells = <2>;
216 #size-cells = <1>;
217 };
218
219 smpctrl@59800000 {
220 compatible = "socionext,uniphier-smpctrl";
221 reg = <0x59801000 0x400>;
222 };
223
224 mioctrl@59810000 {
225 compatible = "socionext,uniphier-sld3-mioctrl",
226 "simple-mfd", "syscon";
227 reg = <0x59810000 0x800>;
228
229 mio_clk: clock {
230 compatible = "socionext,uniphier-sld3-mio-clock";
231 #clock-cells = <1>;
232 };
233
234 mio_rst: reset {
235 compatible = "socionext,uniphier-sld3-mio-reset";
236 #reset-cells = <1>;
237 };
238 };
239
240 usb0: usb@5a800100 {
241 compatible = "socionext,uniphier-ehci", "generic-ehci";
242 status = "disabled";
243 reg = <0x5a800100 0x100>;
244 interrupts = <0 80 4>;
245 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
246 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
247 <&mio_rst 12>;
248 };
249
250 usb1: usb@5a810100 {
251 compatible = "socionext,uniphier-ehci", "generic-ehci";
252 status = "disabled";
253 reg = <0x5a810100 0x100>;
254 interrupts = <0 81 4>;
255 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
256 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
257 <&mio_rst 13>;
258 };
259
260 usb2: usb@5a820100 {
261 compatible = "socionext,uniphier-ehci", "generic-ehci";
262 status = "disabled";
263 reg = <0x5a820100 0x100>;
264 interrupts = <0 82 4>;
265 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
266 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
267 <&mio_rst 14>;
268 };
269
270 usb3: usb@5a830100 {
271 compatible = "socionext,uniphier-ehci", "generic-ehci";
272 status = "disabled";
273 reg = <0x5a830100 0x100>;
274 interrupts = <0 83 4>;
275 clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
276 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
277 <&mio_rst 15>;
278 };
279
280 sysctrl@f1840000 {
281 compatible = "socionext,uniphier-sld3-sysctrl",
282 "simple-mfd", "syscon";
283 reg = <0xf1840000 0x10000>;
284
285 sys_clk: clock {
286 compatible = "socionext,uniphier-sld3-clock";
287 #clock-cells = <1>;
288 };
289
290 sys_rst: reset {
291 compatible = "socionext,uniphier-sld3-reset";
292 #reset-cells = <1>;
293 };
294 };
295 };
296};