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1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra124-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra124-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/reset/tegra124-car.h>
8#include <dt-bindings/thermal/tegra124-soctherm.h>
9
10/ {
11 compatible = "nvidia,tegra124";
12 interrupt-parent = <&lic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 memory@80000000 {
17 device_type = "memory";
18 reg = <0x0 0x80000000 0x0 0x0>;
19 };
20
21 pcie@1003000 {
22 compatible = "nvidia,tegra124-pcie";
23 device_type = "pci";
24 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
25 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
26 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
27 reg-names = "pads", "afi", "cs";
28 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
29 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
30 interrupt-names = "intr", "msi";
31
32 #interrupt-cells = <1>;
33 interrupt-map-mask = <0 0 0 0>;
34 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
35
36 bus-range = <0x00 0xff>;
37 #address-cells = <3>;
38 #size-cells = <2>;
39
40 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
41 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
42 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
43 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
44 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
45
46 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
47 <&tegra_car TEGRA124_CLK_AFI>,
48 <&tegra_car TEGRA124_CLK_PLL_E>,
49 <&tegra_car TEGRA124_CLK_CML0>;
50 clock-names = "pex", "afi", "pll_e", "cml";
51 resets = <&tegra_car 70>,
52 <&tegra_car 72>,
53 <&tegra_car 74>;
54 reset-names = "pex", "afi", "pcie_x";
55 status = "disabled";
56
57 pci@1,0 {
58 device_type = "pci";
59 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
61 bus-range = <0x00 0xff>;
62 status = "disabled";
63
64 #address-cells = <3>;
65 #size-cells = <2>;
66 ranges;
67
68 nvidia,num-lanes = <2>;
69 };
70
71 pci@2,0 {
72 device_type = "pci";
73 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
74 reg = <0x001000 0 0 0 0>;
75 bus-range = <0x00 0xff>;
76 status = "disabled";
77
78 #address-cells = <3>;
79 #size-cells = <2>;
80 ranges;
81
82 nvidia,num-lanes = <1>;
83 };
84 };
85
86 host1x@50000000 {
87 compatible = "nvidia,tegra124-host1x", "simple-bus";
88 reg = <0x0 0x50000000 0x0 0x00034000>;
89 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
90 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
91 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
92 resets = <&tegra_car 28>;
93 reset-names = "host1x";
94 iommus = <&mc TEGRA_SWGROUP_HC>;
95
96 #address-cells = <2>;
97 #size-cells = <2>;
98
99 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
100
101 dc@54200000 {
102 compatible = "nvidia,tegra124-dc";
103 reg = <0x0 0x54200000 0x0 0x00040000>;
104 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
106 <&tegra_car TEGRA124_CLK_PLL_P>;
107 clock-names = "dc", "parent";
108 resets = <&tegra_car 27>;
109 reset-names = "dc";
110
111 iommus = <&mc TEGRA_SWGROUP_DC>;
112
113 nvidia,head = <0>;
114 };
115
116 dc@54240000 {
117 compatible = "nvidia,tegra124-dc";
118 reg = <0x0 0x54240000 0x0 0x00040000>;
119 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
121 <&tegra_car TEGRA124_CLK_PLL_P>;
122 clock-names = "dc", "parent";
123 resets = <&tegra_car 26>;
124 reset-names = "dc";
125
126 iommus = <&mc TEGRA_SWGROUP_DCB>;
127
128 nvidia,head = <1>;
129 };
130
131 hdmi: hdmi@54280000 {
132 compatible = "nvidia,tegra124-hdmi";
133 reg = <0x0 0x54280000 0x0 0x00040000>;
134 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
136 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
137 clock-names = "hdmi", "parent";
138 resets = <&tegra_car 51>;
139 reset-names = "hdmi";
140 status = "disabled";
141 };
142
143 vic@54340000 {
144 compatible = "nvidia,tegra124-vic";
145 reg = <0x0 0x54340000 0x0 0x00040000>;
146 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&tegra_car TEGRA124_CLK_VIC03>;
148 clock-names = "vic";
149 resets = <&tegra_car 178>;
150 reset-names = "vic";
151
152 iommus = <&mc TEGRA_SWGROUP_VIC>;
153 };
154
155 sor@54540000 {
156 compatible = "nvidia,tegra124-sor";
157 reg = <0x0 0x54540000 0x0 0x00040000>;
158 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
160 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
161 <&tegra_car TEGRA124_CLK_PLL_DP>,
162 <&tegra_car TEGRA124_CLK_CLK_M>;
163 clock-names = "sor", "parent", "dp", "safe";
164 resets = <&tegra_car 182>;
165 reset-names = "sor";
166 status = "disabled";
167 };
168
169 dpaux: dpaux@545c0000 {
170 compatible = "nvidia,tegra124-dpaux";
171 reg = <0x0 0x545c0000 0x0 0x00040000>;
172 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
174 <&tegra_car TEGRA124_CLK_PLL_DP>;
175 clock-names = "dpaux", "parent";
176 resets = <&tegra_car 181>;
177 reset-names = "dpaux";
178 status = "disabled";
179 };
180 };
181
182 gic: interrupt-controller@50041000 {
183 compatible = "arm,cortex-a15-gic";
184 #interrupt-cells = <3>;
185 interrupt-controller;
186 reg = <0x0 0x50041000 0x0 0x1000>,
187 <0x0 0x50042000 0x0 0x1000>,
188 <0x0 0x50044000 0x0 0x2000>,
189 <0x0 0x50046000 0x0 0x2000>;
190 interrupts = <GIC_PPI 9
191 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
192 interrupt-parent = <&gic>;
193 };
194
195 /*
196 * Please keep the following 0, notation in place as a former mainline
197 * U-Boot version was looking for that particular notation in order to
198 * perform required fix-ups on that GPU node.
199 */
200 gpu@0,57000000 {
201 compatible = "nvidia,gk20a";
202 reg = <0x0 0x57000000 0x0 0x01000000>,
203 <0x0 0x58000000 0x0 0x01000000>;
204 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
206 interrupt-names = "stall", "nonstall";
207 clocks = <&tegra_car TEGRA124_CLK_GPU>,
208 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
209 clock-names = "gpu", "pwr";
210 resets = <&tegra_car 184>;
211 reset-names = "gpu";
212
213 iommus = <&mc TEGRA_SWGROUP_GPU>;
214
215 status = "disabled";
216 };
217
218 lic: interrupt-controller@60004000 {
219 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
220 reg = <0x0 0x60004000 0x0 0x100>,
221 <0x0 0x60004100 0x0 0x100>,
222 <0x0 0x60004200 0x0 0x100>,
223 <0x0 0x60004300 0x0 0x100>,
224 <0x0 0x60004400 0x0 0x100>;
225 interrupt-controller;
226 #interrupt-cells = <3>;
227 interrupt-parent = <&gic>;
228 };
229
230 timer@60005000 {
231 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
232 reg = <0x0 0x60005000 0x0 0x400>;
233 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
240 };
241
242 tegra_car: clock@60006000 {
243 compatible = "nvidia,tegra124-car";
244 reg = <0x0 0x60006000 0x0 0x1000>;
245 #clock-cells = <1>;
246 #reset-cells = <1>;
247 nvidia,external-memory-controller = <&emc>;
248 };
249
250 flow-controller@60007000 {
251 compatible = "nvidia,tegra124-flowctrl";
252 reg = <0x0 0x60007000 0x0 0x1000>;
253 };
254
255 actmon@6000c800 {
256 compatible = "nvidia,tegra124-actmon";
257 reg = <0x0 0x6000c800 0x0 0x400>;
258 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
260 <&tegra_car TEGRA124_CLK_EMC>;
261 clock-names = "actmon", "emc";
262 resets = <&tegra_car 119>;
263 reset-names = "actmon";
264 };
265
266 gpio: gpio@6000d000 {
267 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
268 reg = <0x0 0x6000d000 0x0 0x1000>;
269 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
277 #gpio-cells = <2>;
278 gpio-controller;
279 #interrupt-cells = <2>;
280 interrupt-controller;
281 /*
282 gpio-ranges = <&pinmux 0 0 251>;
283 */
284 };
285
286 apbdma: dma@60020000 {
287 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
288 reg = <0x0 0x60020000 0x0 0x1400>;
289 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
322 resets = <&tegra_car 34>;
323 reset-names = "dma";
324 #dma-cells = <1>;
325 };
326
327 apbmisc@70000800 {
328 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
329 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
330 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
331 };
332
333 pinmux: pinmux@70000868 {
334 compatible = "nvidia,tegra124-pinmux";
335 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
336 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
337 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
338 };
339
340 /*
341 * There are two serial driver i.e. 8250 based simple serial
342 * driver and APB DMA based serial driver for higher baudrate
343 * and performace. To enable the 8250 based driver, the compatible
344 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
345 * the APB DMA based serial driver, the compatible is
346 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
347 */
348 uarta: serial@70006000 {
349 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
350 reg = <0x0 0x70006000 0x0 0x40>;
351 reg-shift = <2>;
352 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
354 resets = <&tegra_car 6>;
355 reset-names = "serial";
356 dmas = <&apbdma 8>, <&apbdma 8>;
357 dma-names = "rx", "tx";
358 status = "disabled";
359 };
360
361 uartb: serial@70006040 {
362 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
363 reg = <0x0 0x70006040 0x0 0x40>;
364 reg-shift = <2>;
365 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
367 resets = <&tegra_car 7>;
368 reset-names = "serial";
369 dmas = <&apbdma 9>, <&apbdma 9>;
370 dma-names = "rx", "tx";
371 status = "disabled";
372 };
373
374 uartc: serial@70006200 {
375 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
376 reg = <0x0 0x70006200 0x0 0x40>;
377 reg-shift = <2>;
378 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
380 resets = <&tegra_car 55>;
381 reset-names = "serial";
382 dmas = <&apbdma 10>, <&apbdma 10>;
383 dma-names = "rx", "tx";
384 status = "disabled";
385 };
386
387 uartd: serial@70006300 {
388 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
389 reg = <0x0 0x70006300 0x0 0x40>;
390 reg-shift = <2>;
391 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
393 resets = <&tegra_car 65>;
394 reset-names = "serial";
395 dmas = <&apbdma 19>, <&apbdma 19>;
396 dma-names = "rx", "tx";
397 status = "disabled";
398 };
399
400 pwm: pwm@7000a000 {
401 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
402 reg = <0x0 0x7000a000 0x0 0x100>;
403 #pwm-cells = <2>;
404 clocks = <&tegra_car TEGRA124_CLK_PWM>;
405 resets = <&tegra_car 17>;
406 reset-names = "pwm";
407 status = "disabled";
408 };
409
410 i2c@7000c000 {
411 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
412 reg = <0x0 0x7000c000 0x0 0x100>;
413 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
417 clock-names = "div-clk";
418 resets = <&tegra_car 12>;
419 reset-names = "i2c";
420 dmas = <&apbdma 21>, <&apbdma 21>;
421 dma-names = "rx", "tx";
422 status = "disabled";
423 };
424
425 i2c@7000c400 {
426 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
427 reg = <0x0 0x7000c400 0x0 0x100>;
428 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
432 clock-names = "div-clk";
433 resets = <&tegra_car 54>;
434 reset-names = "i2c";
435 dmas = <&apbdma 22>, <&apbdma 22>;
436 dma-names = "rx", "tx";
437 status = "disabled";
438 };
439
440 i2c@7000c500 {
441 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
442 reg = <0x0 0x7000c500 0x0 0x100>;
443 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
447 clock-names = "div-clk";
448 resets = <&tegra_car 67>;
449 reset-names = "i2c";
450 dmas = <&apbdma 23>, <&apbdma 23>;
451 dma-names = "rx", "tx";
452 status = "disabled";
453 };
454
455 i2c@7000c700 {
456 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
457 reg = <0x0 0x7000c700 0x0 0x100>;
458 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
462 clock-names = "div-clk";
463 resets = <&tegra_car 103>;
464 reset-names = "i2c";
465 dmas = <&apbdma 26>, <&apbdma 26>;
466 dma-names = "rx", "tx";
467 status = "disabled";
468 };
469
470 i2c@7000d000 {
471 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
472 reg = <0x0 0x7000d000 0x0 0x100>;
473 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
477 clock-names = "div-clk";
478 resets = <&tegra_car 47>;
479 reset-names = "i2c";
480 dmas = <&apbdma 24>, <&apbdma 24>;
481 dma-names = "rx", "tx";
482 status = "disabled";
483 };
484
485 i2c@7000d100 {
486 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
487 reg = <0x0 0x7000d100 0x0 0x100>;
488 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
489 #address-cells = <1>;
490 #size-cells = <0>;
491 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
492 clock-names = "div-clk";
493 resets = <&tegra_car 166>;
494 reset-names = "i2c";
495 dmas = <&apbdma 30>, <&apbdma 30>;
496 dma-names = "rx", "tx";
497 status = "disabled";
498 };
499
500 spi@7000d400 {
501 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
502 reg = <0x0 0x7000d400 0x0 0x200>;
503 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
504 #address-cells = <1>;
505 #size-cells = <0>;
506 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
507 clock-names = "spi";
508 resets = <&tegra_car 41>;
509 reset-names = "spi";
510 dmas = <&apbdma 15>, <&apbdma 15>;
511 dma-names = "rx", "tx";
512 status = "disabled";
513 };
514
515 spi@7000d600 {
516 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
517 reg = <0x0 0x7000d600 0x0 0x200>;
518 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
522 clock-names = "spi";
523 resets = <&tegra_car 44>;
524 reset-names = "spi";
525 dmas = <&apbdma 16>, <&apbdma 16>;
526 dma-names = "rx", "tx";
527 status = "disabled";
528 };
529
530 spi@7000d800 {
531 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
532 reg = <0x0 0x7000d800 0x0 0x200>;
533 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
534 #address-cells = <1>;
535 #size-cells = <0>;
536 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
537 clock-names = "spi";
538 resets = <&tegra_car 46>;
539 reset-names = "spi";
540 dmas = <&apbdma 17>, <&apbdma 17>;
541 dma-names = "rx", "tx";
542 status = "disabled";
543 };
544
545 spi@7000da00 {
546 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
547 reg = <0x0 0x7000da00 0x0 0x200>;
548 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>;
550 #size-cells = <0>;
551 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
552 clock-names = "spi";
553 resets = <&tegra_car 68>;
554 reset-names = "spi";
555 dmas = <&apbdma 18>, <&apbdma 18>;
556 dma-names = "rx", "tx";
557 status = "disabled";
558 };
559
560 spi@7000dc00 {
561 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
562 reg = <0x0 0x7000dc00 0x0 0x200>;
563 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>;
565 #size-cells = <0>;
566 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
567 clock-names = "spi";
568 resets = <&tegra_car 104>;
569 reset-names = "spi";
570 dmas = <&apbdma 27>, <&apbdma 27>;
571 dma-names = "rx", "tx";
572 status = "disabled";
573 };
574
575 spi@7000de00 {
576 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
577 reg = <0x0 0x7000de00 0x0 0x200>;
578 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
579 #address-cells = <1>;
580 #size-cells = <0>;
581 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
582 clock-names = "spi";
583 resets = <&tegra_car 105>;
584 reset-names = "spi";
585 dmas = <&apbdma 28>, <&apbdma 28>;
586 dma-names = "rx", "tx";
587 status = "disabled";
588 };
589
590 rtc@7000e000 {
591 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
592 reg = <0x0 0x7000e000 0x0 0x100>;
593 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&tegra_car TEGRA124_CLK_RTC>;
595 };
596
597 pmc@7000e400 {
598 compatible = "nvidia,tegra124-pmc";
599 reg = <0x0 0x7000e400 0x0 0x400>;
600 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
601 clock-names = "pclk", "clk32k_in";
602 };
603
604 fuse@7000f800 {
605 compatible = "nvidia,tegra124-efuse";
606 reg = <0x0 0x7000f800 0x0 0x400>;
607 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
608 clock-names = "fuse";
609 resets = <&tegra_car 39>;
610 reset-names = "fuse";
611 };
612
613 mc: memory-controller@70019000 {
614 compatible = "nvidia,tegra124-mc";
615 reg = <0x0 0x70019000 0x0 0x1000>;
616 clocks = <&tegra_car TEGRA124_CLK_MC>;
617 clock-names = "mc";
618
619 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
620
621 #iommu-cells = <1>;
622 };
623
624 emc: emc@7001b000 {
625 compatible = "nvidia,tegra124-emc";
626 reg = <0x0 0x7001b000 0x0 0x1000>;
627
628 nvidia,memory-controller = <&mc>;
629 };
630
631 sata@70020000 {
632 compatible = "nvidia,tegra124-ahci";
633 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
634 <0x0 0x70020000 0x0 0x7000>; /* SATA */
635 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&tegra_car TEGRA124_CLK_SATA>,
637 <&tegra_car TEGRA124_CLK_SATA_OOB>,
638 <&tegra_car TEGRA124_CLK_CML1>,
639 <&tegra_car TEGRA124_CLK_PLL_E>;
640 clock-names = "sata", "sata-oob", "cml1", "pll_e";
641 resets = <&tegra_car 124>,
642 <&tegra_car 123>,
643 <&tegra_car 129>;
644 reset-names = "sata", "sata-oob", "sata-cold";
645 status = "disabled";
646 };
647
648 hda@70030000 {
649 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
650 reg = <0x0 0x70030000 0x0 0x10000>;
651 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&tegra_car TEGRA124_CLK_HDA>,
653 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
654 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
655 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
656 resets = <&tegra_car 125>, /* hda */
657 <&tegra_car 128>, /* hda2hdmi */
658 <&tegra_car 111>; /* hda2codec_2x */
659 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
660 status = "disabled";
661 };
662
663 usb@70090000 {
664 compatible = "nvidia,tegra124-xusb";
665 reg = <0x0 0x70090000 0x0 0x8000>,
666 <0x0 0x70098000 0x0 0x1000>,
667 <0x0 0x70099000 0x0 0x1000>;
668 reg-names = "hcd", "fpci", "ipfs";
669
670 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
672
673 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
674 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
675 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
676 <&tegra_car TEGRA124_CLK_XUSB_SS>,
677 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
678 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
679 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
680 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
681 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
682 <&tegra_car TEGRA124_CLK_CLK_M>,
683 <&tegra_car TEGRA124_CLK_PLL_E>;
684 clock-names = "xusb_host", "xusb_host_src",
685 "xusb_falcon_src", "xusb_ss",
686 "xusb_ss_div2", "xusb_ss_src",
687 "xusb_hs_src", "xusb_fs_src",
688 "pll_u_480m", "clk_m", "pll_e";
689 resets = <&tegra_car 89>, <&tegra_car 156>,
690 <&tegra_car 143>;
691 reset-names = "xusb_host", "xusb_ss", "xusb_src";
692
693 nvidia,xusb-padctl = <&padctl>;
694
695 status = "disabled";
696 };
697
698 padctl: padctl@7009f000 {
699 compatible = "nvidia,tegra124-xusb-padctl";
700 reg = <0x0 0x7009f000 0x0 0x1000>;
701 resets = <&tegra_car 142>;
702 reset-names = "padctl";
703
704 pads {
705 usb2 {
706 status = "disabled";
707
708 lanes {
709 usb2-0 {
710 status = "disabled";
711 #phy-cells = <0>;
712 };
713
714 usb2-1 {
715 status = "disabled";
716 #phy-cells = <0>;
717 };
718
719 usb2-2 {
720 status = "disabled";
721 #phy-cells = <0>;
722 };
723 };
724 };
725
726 ulpi {
727 status = "disabled";
728
729 lanes {
730 ulpi-0 {
731 status = "disabled";
732 #phy-cells = <0>;
733 };
734 };
735 };
736
737 hsic {
738 status = "disabled";
739
740 lanes {
741 hsic-0 {
742 status = "disabled";
743 #phy-cells = <0>;
744 };
745
746 hsic-1 {
747 status = "disabled";
748 #phy-cells = <0>;
749 };
750 };
751 };
752
753 pcie {
754 status = "disabled";
755
756 lanes {
757 pcie-0 {
758 status = "disabled";
759 #phy-cells = <0>;
760 };
761
762 pcie-1 {
763 status = "disabled";
764 #phy-cells = <0>;
765 };
766
767 pcie-2 {
768 status = "disabled";
769 #phy-cells = <0>;
770 };
771
772 pcie-3 {
773 status = "disabled";
774 #phy-cells = <0>;
775 };
776
777 pcie-4 {
778 status = "disabled";
779 #phy-cells = <0>;
780 };
781 };
782 };
783
784 sata {
785 status = "disabled";
786
787 lanes {
788 sata-0 {
789 status = "disabled";
790 #phy-cells = <0>;
791 };
792 };
793 };
794 };
795
796 ports {
797 usb2-0 {
798 status = "disabled";
799 };
800
801 usb2-1 {
802 status = "disabled";
803 };
804
805 usb2-2 {
806 status = "disabled";
807 };
808
809 ulpi-0 {
810 status = "disabled";
811 };
812
813 hsic-0 {
814 status = "disabled";
815 };
816
817 hsic-1 {
818 status = "disabled";
819 };
820
821 usb3-0 {
822 status = "disabled";
823 };
824
825 usb3-1 {
826 status = "disabled";
827 };
828 };
829 };
830
831 sdhci@700b0000 {
832 compatible = "nvidia,tegra124-sdhci";
833 reg = <0x0 0x700b0000 0x0 0x200>;
834 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
836 resets = <&tegra_car 14>;
837 reset-names = "sdhci";
838 status = "disabled";
839 };
840
841 sdhci@700b0200 {
842 compatible = "nvidia,tegra124-sdhci";
843 reg = <0x0 0x700b0200 0x0 0x200>;
844 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
846 resets = <&tegra_car 9>;
847 reset-names = "sdhci";
848 status = "disabled";
849 };
850
851 sdhci@700b0400 {
852 compatible = "nvidia,tegra124-sdhci";
853 reg = <0x0 0x700b0400 0x0 0x200>;
854 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
856 resets = <&tegra_car 69>;
857 reset-names = "sdhci";
858 status = "disabled";
859 };
860
861 sdhci@700b0600 {
862 compatible = "nvidia,tegra124-sdhci";
863 reg = <0x0 0x700b0600 0x0 0x200>;
864 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
866 resets = <&tegra_car 15>;
867 reset-names = "sdhci";
868 status = "disabled";
869 };
870
871 cec@70015000 {
872 compatible = "nvidia,tegra124-cec";
873 reg = <0x0 0x70015000 0x0 0x00001000>;
874 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&tegra_car TEGRA124_CLK_CEC>;
876 clock-names = "cec";
877 status = "disabled";
878 hdmi-phandle = <&hdmi>;
879 };
880
881 soctherm: thermal-sensor@700e2000 {
882 compatible = "nvidia,tegra124-soctherm";
883 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
884 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
885 reg-names = "soctherm-reg", "car-reg";
886 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
888 <&tegra_car TEGRA124_CLK_SOC_THERM>;
889 clock-names = "tsensor", "soctherm";
890 resets = <&tegra_car 78>;
891 reset-names = "soctherm";
892 #thermal-sensor-cells = <1>;
893
894 throttle-cfgs {
895 throttle_heavy: heavy {
896 nvidia,priority = <100>;
897 nvidia,cpu-throt-percent = <85>;
898
899 #cooling-cells = <2>;
900 };
901 };
902 };
903
904 dfll: clock@70110000 {
905 compatible = "nvidia,tegra124-dfll";
906 reg = <0 0x70110000 0 0x100>, /* DFLL control */
907 <0 0x70110000 0 0x100>, /* I2C output control */
908 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
909 <0 0x70110200 0 0x100>; /* Look-up table RAM */
910 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
912 <&tegra_car TEGRA124_CLK_DFLL_REF>,
913 <&tegra_car TEGRA124_CLK_I2C5>;
914 clock-names = "soc", "ref", "i2c";
915 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
916 reset-names = "dvco";
917 #clock-cells = <0>;
918 clock-output-names = "dfllCPU_out";
919 nvidia,sample-rate = <12500>;
920 nvidia,droop-ctrl = <0x00000f00>;
921 nvidia,force-mode = <1>;
922 nvidia,cf = <10>;
923 nvidia,ci = <0>;
924 nvidia,cg = <2>;
925 status = "disabled";
926 };
927
928 ahub@70300000 {
929 compatible = "nvidia,tegra124-ahub";
930 reg = <0x0 0x70300000 0x0 0x200>,
931 <0x0 0x70300800 0x0 0x800>,
932 <0x0 0x70300200 0x0 0x600>;
933 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
935 <&tegra_car TEGRA124_CLK_APBIF>;
936 clock-names = "d_audio", "apbif";
937 resets = <&tegra_car 106>, /* d_audio */
938 <&tegra_car 107>, /* apbif */
939 <&tegra_car 30>, /* i2s0 */
940 <&tegra_car 11>, /* i2s1 */
941 <&tegra_car 18>, /* i2s2 */
942 <&tegra_car 101>, /* i2s3 */
943 <&tegra_car 102>, /* i2s4 */
944 <&tegra_car 108>, /* dam0 */
945 <&tegra_car 109>, /* dam1 */
946 <&tegra_car 110>, /* dam2 */
947 <&tegra_car 10>, /* spdif */
948 <&tegra_car 153>, /* amx */
949 <&tegra_car 185>, /* amx1 */
950 <&tegra_car 154>, /* adx */
951 <&tegra_car 180>, /* adx1 */
952 <&tegra_car 186>, /* afc0 */
953 <&tegra_car 187>, /* afc1 */
954 <&tegra_car 188>, /* afc2 */
955 <&tegra_car 189>, /* afc3 */
956 <&tegra_car 190>, /* afc4 */
957 <&tegra_car 191>; /* afc5 */
958 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
959 "i2s3", "i2s4", "dam0", "dam1", "dam2",
960 "spdif", "amx", "amx1", "adx", "adx1",
961 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
962 dmas = <&apbdma 1>, <&apbdma 1>,
963 <&apbdma 2>, <&apbdma 2>,
964 <&apbdma 3>, <&apbdma 3>,
965 <&apbdma 4>, <&apbdma 4>,
966 <&apbdma 6>, <&apbdma 6>,
967 <&apbdma 7>, <&apbdma 7>,
968 <&apbdma 12>, <&apbdma 12>,
969 <&apbdma 13>, <&apbdma 13>,
970 <&apbdma 14>, <&apbdma 14>,
971 <&apbdma 29>, <&apbdma 29>;
972 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
973 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
974 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
975 "rx9", "tx9";
976 ranges;
977 #address-cells = <2>;
978 #size-cells = <2>;
979
980 tegra_i2s0: i2s@70301000 {
981 compatible = "nvidia,tegra124-i2s";
982 reg = <0x0 0x70301000 0x0 0x100>;
983 nvidia,ahub-cif-ids = <4 4>;
984 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
985 resets = <&tegra_car 30>;
986 reset-names = "i2s";
987 status = "disabled";
988 };
989
990 tegra_i2s1: i2s@70301100 {
991 compatible = "nvidia,tegra124-i2s";
992 reg = <0x0 0x70301100 0x0 0x100>;
993 nvidia,ahub-cif-ids = <5 5>;
994 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
995 resets = <&tegra_car 11>;
996 reset-names = "i2s";
997 status = "disabled";
998 };
999
1000 tegra_i2s2: i2s@70301200 {
1001 compatible = "nvidia,tegra124-i2s";
1002 reg = <0x0 0x70301200 0x0 0x100>;
1003 nvidia,ahub-cif-ids = <6 6>;
1004 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1005 resets = <&tegra_car 18>;
1006 reset-names = "i2s";
1007 status = "disabled";
1008 };
1009
1010 tegra_i2s3: i2s@70301300 {
1011 compatible = "nvidia,tegra124-i2s";
1012 reg = <0x0 0x70301300 0x0 0x100>;
1013 nvidia,ahub-cif-ids = <7 7>;
1014 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1015 resets = <&tegra_car 101>;
1016 reset-names = "i2s";
1017 status = "disabled";
1018 };
1019
1020 tegra_i2s4: i2s@70301400 {
1021 compatible = "nvidia,tegra124-i2s";
1022 reg = <0x0 0x70301400 0x0 0x100>;
1023 nvidia,ahub-cif-ids = <8 8>;
1024 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1025 resets = <&tegra_car 102>;
1026 reset-names = "i2s";
1027 status = "disabled";
1028 };
1029 };
1030
1031 usb@7d000000 {
1032 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1033 reg = <0x0 0x7d000000 0x0 0x4000>;
1034 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1035 phy_type = "utmi";
1036 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1037 resets = <&tegra_car 22>;
1038 reset-names = "usb";
1039 nvidia,phy = <&phy1>;
1040 status = "disabled";
1041 };
1042
1043 phy1: usb-phy@7d000000 {
1044 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1045 reg = <0x0 0x7d000000 0x0 0x4000>,
1046 <0x0 0x7d000000 0x0 0x4000>;
1047 phy_type = "utmi";
1048 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1049 <&tegra_car TEGRA124_CLK_PLL_U>,
1050 <&tegra_car TEGRA124_CLK_USBD>;
1051 clock-names = "reg", "pll_u", "utmi-pads";
1052 resets = <&tegra_car 22>, <&tegra_car 22>;
1053 reset-names = "usb", "utmi-pads";
1054 nvidia,hssync-start-delay = <0>;
1055 nvidia,idle-wait-delay = <17>;
1056 nvidia,elastic-limit = <16>;
1057 nvidia,term-range-adj = <6>;
1058 nvidia,xcvr-setup = <9>;
1059 nvidia,xcvr-lsfslew = <0>;
1060 nvidia,xcvr-lsrslew = <3>;
1061 nvidia,hssquelch-level = <2>;
1062 nvidia,hsdiscon-level = <5>;
1063 nvidia,xcvr-hsslew = <12>;
1064 nvidia,has-utmi-pad-registers;
1065 status = "disabled";
1066 };
1067
1068 usb@7d004000 {
1069 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1070 reg = <0x0 0x7d004000 0x0 0x4000>;
1071 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1072 phy_type = "utmi";
1073 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1074 resets = <&tegra_car 58>;
1075 reset-names = "usb";
1076 nvidia,phy = <&phy2>;
1077 status = "disabled";
1078 };
1079
1080 phy2: usb-phy@7d004000 {
1081 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1082 reg = <0x0 0x7d004000 0x0 0x4000>,
1083 <0x0 0x7d000000 0x0 0x4000>;
1084 phy_type = "utmi";
1085 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1086 <&tegra_car TEGRA124_CLK_PLL_U>,
1087 <&tegra_car TEGRA124_CLK_USBD>;
1088 clock-names = "reg", "pll_u", "utmi-pads";
1089 resets = <&tegra_car 58>, <&tegra_car 22>;
1090 reset-names = "usb", "utmi-pads";
1091 nvidia,hssync-start-delay = <0>;
1092 nvidia,idle-wait-delay = <17>;
1093 nvidia,elastic-limit = <16>;
1094 nvidia,term-range-adj = <6>;
1095 nvidia,xcvr-setup = <9>;
1096 nvidia,xcvr-lsfslew = <0>;
1097 nvidia,xcvr-lsrslew = <3>;
1098 nvidia,hssquelch-level = <2>;
1099 nvidia,hsdiscon-level = <5>;
1100 nvidia,xcvr-hsslew = <12>;
1101 status = "disabled";
1102 };
1103
1104 usb@7d008000 {
1105 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1106 reg = <0x0 0x7d008000 0x0 0x4000>;
1107 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1108 phy_type = "utmi";
1109 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1110 resets = <&tegra_car 59>;
1111 reset-names = "usb";
1112 nvidia,phy = <&phy3>;
1113 status = "disabled";
1114 };
1115
1116 phy3: usb-phy@7d008000 {
1117 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1118 reg = <0x0 0x7d008000 0x0 0x4000>,
1119 <0x0 0x7d000000 0x0 0x4000>;
1120 phy_type = "utmi";
1121 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1122 <&tegra_car TEGRA124_CLK_PLL_U>,
1123 <&tegra_car TEGRA124_CLK_USBD>;
1124 clock-names = "reg", "pll_u", "utmi-pads";
1125 resets = <&tegra_car 59>, <&tegra_car 22>;
1126 reset-names = "usb", "utmi-pads";
1127 nvidia,hssync-start-delay = <0>;
1128 nvidia,idle-wait-delay = <17>;
1129 nvidia,elastic-limit = <16>;
1130 nvidia,term-range-adj = <6>;
1131 nvidia,xcvr-setup = <9>;
1132 nvidia,xcvr-lsfslew = <0>;
1133 nvidia,xcvr-lsrslew = <3>;
1134 nvidia,hssquelch-level = <2>;
1135 nvidia,hsdiscon-level = <5>;
1136 nvidia,xcvr-hsslew = <12>;
1137 status = "disabled";
1138 };
1139
1140 cpus {
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143
1144 cpu@0 {
1145 device_type = "cpu";
1146 compatible = "arm,cortex-a15";
1147 reg = <0>;
1148
1149 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1150 <&tegra_car TEGRA124_CLK_CCLK_LP>,
1151 <&tegra_car TEGRA124_CLK_PLL_X>,
1152 <&tegra_car TEGRA124_CLK_PLL_P>,
1153 <&dfll>;
1154 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1155 /* FIXME: what's the actual transition time? */
1156 clock-latency = <300000>;
1157 };
1158
1159 cpu@1 {
1160 device_type = "cpu";
1161 compatible = "arm,cortex-a15";
1162 reg = <1>;
1163 };
1164
1165 cpu@2 {
1166 device_type = "cpu";
1167 compatible = "arm,cortex-a15";
1168 reg = <2>;
1169 };
1170
1171 cpu@3 {
1172 device_type = "cpu";
1173 compatible = "arm,cortex-a15";
1174 reg = <3>;
1175 };
1176 };
1177
1178 pmu {
1179 compatible = "arm,cortex-a15-pmu";
1180 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1181 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1184 interrupt-affinity = <&{/cpus/cpu@0}>,
1185 <&{/cpus/cpu@1}>,
1186 <&{/cpus/cpu@2}>,
1187 <&{/cpus/cpu@3}>;
1188 };
1189
1190 thermal-zones {
1191 cpu {
1192 polling-delay-passive = <1000>;
1193 polling-delay = <1000>;
1194
1195 thermal-sensors =
1196 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1197
1198 trips {
1199 cpu-shutdown-trip {
1200 temperature = <103000>;
1201 hysteresis = <0>;
1202 type = "critical";
1203 };
1204 cpu_throttle_trip: throttle-trip {
1205 temperature = <100000>;
1206 hysteresis = <1000>;
1207 type = "hot";
1208 };
1209 };
1210
1211 cooling-maps {
1212 map0 {
1213 trip = <&cpu_throttle_trip>;
1214 cooling-device = <&throttle_heavy 1 1>;
1215 };
1216 };
1217 };
1218
1219 mem {
1220 polling-delay-passive = <1000>;
1221 polling-delay = <1000>;
1222
1223 thermal-sensors =
1224 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1225
1226 trips {
1227 mem-shutdown-trip {
1228 temperature = <103000>;
1229 hysteresis = <0>;
1230 type = "critical";
1231 };
1232 };
1233
1234 cooling-maps {
1235 /*
1236 * There are currently no cooling maps,
1237 * because there are no cooling devices.
1238 */
1239 };
1240 };
1241
1242 gpu {
1243 polling-delay-passive = <1000>;
1244 polling-delay = <1000>;
1245
1246 thermal-sensors =
1247 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1248
1249 trips {
1250 gpu-shutdown-trip {
1251 temperature = <101000>;
1252 hysteresis = <0>;
1253 type = "critical";
1254 };
1255 gpu_throttle_trip: throttle-trip {
1256 temperature = <99000>;
1257 hysteresis = <1000>;
1258 type = "hot";
1259 };
1260 };
1261
1262 cooling-maps {
1263 map0 {
1264 trip = <&gpu_throttle_trip>;
1265 cooling-device = <&throttle_heavy 1 1>;
1266 };
1267 };
1268 };
1269
1270 pllx {
1271 polling-delay-passive = <1000>;
1272 polling-delay = <1000>;
1273
1274 thermal-sensors =
1275 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1276
1277 trips {
1278 pllx-shutdown-trip {
1279 temperature = <103000>;
1280 hysteresis = <0>;
1281 type = "critical";
1282 };
1283 };
1284
1285 cooling-maps {
1286 /*
1287 * There are currently no cooling maps,
1288 * because there are no cooling devices.
1289 */
1290 };
1291 };
1292 };
1293
1294 timer {
1295 compatible = "arm,armv7-timer";
1296 interrupts = <GIC_PPI 13
1297 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1298 <GIC_PPI 14
1299 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1300 <GIC_PPI 11
1301 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1302 <GIC_PPI 10
1303 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1304 interrupt-parent = <&gic>;
1305 };
1306};
1#include <dt-bindings/clock/tegra124-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/memory/tegra124-mc.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/reset/tegra124-car.h>
7#include <dt-bindings/thermal/tegra124-soctherm.h>
8
9#include "skeleton.dtsi"
10
11/ {
12 compatible = "nvidia,tegra124";
13 interrupt-parent = <&lic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 pcie-controller@01003000 {
18 compatible = "nvidia,tegra124-pcie";
19 device_type = "pci";
20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
23 reg-names = "pads", "afi", "cs";
24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
26 interrupt-names = "intr", "msi";
27
28 #interrupt-cells = <1>;
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
31
32 bus-range = <0x00 0xff>;
33 #address-cells = <3>;
34 #size-cells = <2>;
35
36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
41
42 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
43 <&tegra_car TEGRA124_CLK_AFI>,
44 <&tegra_car TEGRA124_CLK_PLL_E>,
45 <&tegra_car TEGRA124_CLK_CML0>;
46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
48 <&tegra_car 72>,
49 <&tegra_car 74>;
50 reset-names = "pex", "afi", "pcie_x";
51 status = "disabled";
52
53 pci@1,0 {
54 device_type = "pci";
55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
57 status = "disabled";
58
59 #address-cells = <3>;
60 #size-cells = <2>;
61 ranges;
62
63 nvidia,num-lanes = <2>;
64 };
65
66 pci@2,0 {
67 device_type = "pci";
68 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
69 reg = <0x001000 0 0 0 0>;
70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <1>;
77 };
78 };
79
80 host1x@50000000 {
81 compatible = "nvidia,tegra124-host1x", "simple-bus";
82 reg = <0x0 0x50000000 0x0 0x00034000>;
83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
84 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
85 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
86 resets = <&tegra_car 28>;
87 reset-names = "host1x";
88
89 #address-cells = <2>;
90 #size-cells = <2>;
91
92 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
93
94 dc@54200000 {
95 compatible = "nvidia,tegra124-dc";
96 reg = <0x0 0x54200000 0x0 0x00040000>;
97 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
99 <&tegra_car TEGRA124_CLK_PLL_P>;
100 clock-names = "dc", "parent";
101 resets = <&tegra_car 27>;
102 reset-names = "dc";
103
104 iommus = <&mc TEGRA_SWGROUP_DC>;
105
106 nvidia,head = <0>;
107 };
108
109 dc@54240000 {
110 compatible = "nvidia,tegra124-dc";
111 reg = <0x0 0x54240000 0x0 0x00040000>;
112 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
114 <&tegra_car TEGRA124_CLK_PLL_P>;
115 clock-names = "dc", "parent";
116 resets = <&tegra_car 26>;
117 reset-names = "dc";
118
119 iommus = <&mc TEGRA_SWGROUP_DCB>;
120
121 nvidia,head = <1>;
122 };
123
124 hdmi@54280000 {
125 compatible = "nvidia,tegra124-hdmi";
126 reg = <0x0 0x54280000 0x0 0x00040000>;
127 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
129 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
130 clock-names = "hdmi", "parent";
131 resets = <&tegra_car 51>;
132 reset-names = "hdmi";
133 status = "disabled";
134 };
135
136 sor@54540000 {
137 compatible = "nvidia,tegra124-sor";
138 reg = <0x0 0x54540000 0x0 0x00040000>;
139 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
141 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
142 <&tegra_car TEGRA124_CLK_PLL_DP>,
143 <&tegra_car TEGRA124_CLK_CLK_M>;
144 clock-names = "sor", "parent", "dp", "safe";
145 resets = <&tegra_car 182>;
146 reset-names = "sor";
147 status = "disabled";
148 };
149
150 dpaux: dpaux@545c0000 {
151 compatible = "nvidia,tegra124-dpaux";
152 reg = <0x0 0x545c0000 0x0 0x00040000>;
153 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
155 <&tegra_car TEGRA124_CLK_PLL_DP>;
156 clock-names = "dpaux", "parent";
157 resets = <&tegra_car 181>;
158 reset-names = "dpaux";
159 status = "disabled";
160 };
161 };
162
163 gic: interrupt-controller@50041000 {
164 compatible = "arm,cortex-a15-gic";
165 #interrupt-cells = <3>;
166 interrupt-controller;
167 reg = <0x0 0x50041000 0x0 0x1000>,
168 <0x0 0x50042000 0x0 0x1000>,
169 <0x0 0x50044000 0x0 0x2000>,
170 <0x0 0x50046000 0x0 0x2000>;
171 interrupts = <GIC_PPI 9
172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
173 interrupt-parent = <&gic>;
174 };
175
176 /*
177 * Please keep the following 0, notation in place as a former mainline
178 * U-Boot version was looking for that particular notation in order to
179 * perform required fix-ups on that GPU node.
180 */
181 gpu@0,57000000 {
182 compatible = "nvidia,gk20a";
183 reg = <0x0 0x57000000 0x0 0x01000000>,
184 <0x0 0x58000000 0x0 0x01000000>;
185 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-names = "stall", "nonstall";
188 clocks = <&tegra_car TEGRA124_CLK_GPU>,
189 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
190 clock-names = "gpu", "pwr";
191 resets = <&tegra_car 184>;
192 reset-names = "gpu";
193
194 iommus = <&mc TEGRA_SWGROUP_GPU>;
195
196 status = "disabled";
197 };
198
199 lic: interrupt-controller@60004000 {
200 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
201 reg = <0x0 0x60004000 0x0 0x100>,
202 <0x0 0x60004100 0x0 0x100>,
203 <0x0 0x60004200 0x0 0x100>,
204 <0x0 0x60004300 0x0 0x100>,
205 <0x0 0x60004400 0x0 0x100>;
206 interrupt-controller;
207 #interrupt-cells = <3>;
208 interrupt-parent = <&gic>;
209 };
210
211 timer@60005000 {
212 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
213 reg = <0x0 0x60005000 0x0 0x400>;
214 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
221 };
222
223 tegra_car: clock@60006000 {
224 compatible = "nvidia,tegra124-car";
225 reg = <0x0 0x60006000 0x0 0x1000>;
226 #clock-cells = <1>;
227 #reset-cells = <1>;
228 nvidia,external-memory-controller = <&emc>;
229 };
230
231 flow-controller@60007000 {
232 compatible = "nvidia,tegra124-flowctrl";
233 reg = <0x0 0x60007000 0x0 0x1000>;
234 };
235
236 actmon@6000c800 {
237 compatible = "nvidia,tegra124-actmon";
238 reg = <0x0 0x6000c800 0x0 0x400>;
239 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
241 <&tegra_car TEGRA124_CLK_EMC>;
242 clock-names = "actmon", "emc";
243 resets = <&tegra_car 119>;
244 reset-names = "actmon";
245 };
246
247 gpio: gpio@6000d000 {
248 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
249 reg = <0x0 0x6000d000 0x0 0x1000>;
250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
258 #gpio-cells = <2>;
259 gpio-controller;
260 #interrupt-cells = <2>;
261 interrupt-controller;
262 /*
263 gpio-ranges = <&pinmux 0 0 251>;
264 */
265 };
266
267 apbdma: dma@60020000 {
268 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
269 reg = <0x0 0x60020000 0x0 0x1400>;
270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
303 resets = <&tegra_car 34>;
304 reset-names = "dma";
305 #dma-cells = <1>;
306 };
307
308 apbmisc@70000800 {
309 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
310 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
311 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
312 };
313
314 pinmux: pinmux@70000868 {
315 compatible = "nvidia,tegra124-pinmux";
316 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
317 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
318 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
319 };
320
321 /*
322 * There are two serial driver i.e. 8250 based simple serial
323 * driver and APB DMA based serial driver for higher baudrate
324 * and performace. To enable the 8250 based driver, the compatible
325 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
326 * the APB DMA based serial driver, the compatible is
327 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
328 */
329 uarta: serial@70006000 {
330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
331 reg = <0x0 0x70006000 0x0 0x40>;
332 reg-shift = <2>;
333 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
335 resets = <&tegra_car 6>;
336 reset-names = "serial";
337 dmas = <&apbdma 8>, <&apbdma 8>;
338 dma-names = "rx", "tx";
339 status = "disabled";
340 };
341
342 uartb: serial@70006040 {
343 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
344 reg = <0x0 0x70006040 0x0 0x40>;
345 reg-shift = <2>;
346 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
348 resets = <&tegra_car 7>;
349 reset-names = "serial";
350 dmas = <&apbdma 9>, <&apbdma 9>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
354
355 uartc: serial@70006200 {
356 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
357 reg = <0x0 0x70006200 0x0 0x40>;
358 reg-shift = <2>;
359 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
361 resets = <&tegra_car 55>;
362 reset-names = "serial";
363 dmas = <&apbdma 10>, <&apbdma 10>;
364 dma-names = "rx", "tx";
365 status = "disabled";
366 };
367
368 uartd: serial@70006300 {
369 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
370 reg = <0x0 0x70006300 0x0 0x40>;
371 reg-shift = <2>;
372 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
374 resets = <&tegra_car 65>;
375 reset-names = "serial";
376 dmas = <&apbdma 19>, <&apbdma 19>;
377 dma-names = "rx", "tx";
378 status = "disabled";
379 };
380
381 pwm: pwm@7000a000 {
382 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
383 reg = <0x0 0x7000a000 0x0 0x100>;
384 #pwm-cells = <2>;
385 clocks = <&tegra_car TEGRA124_CLK_PWM>;
386 resets = <&tegra_car 17>;
387 reset-names = "pwm";
388 status = "disabled";
389 };
390
391 i2c@7000c000 {
392 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
393 reg = <0x0 0x7000c000 0x0 0x100>;
394 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
395 #address-cells = <1>;
396 #size-cells = <0>;
397 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
398 clock-names = "div-clk";
399 resets = <&tegra_car 12>;
400 reset-names = "i2c";
401 dmas = <&apbdma 21>, <&apbdma 21>;
402 dma-names = "rx", "tx";
403 status = "disabled";
404 };
405
406 i2c@7000c400 {
407 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
408 reg = <0x0 0x7000c400 0x0 0x100>;
409 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
410 #address-cells = <1>;
411 #size-cells = <0>;
412 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
413 clock-names = "div-clk";
414 resets = <&tegra_car 54>;
415 reset-names = "i2c";
416 dmas = <&apbdma 22>, <&apbdma 22>;
417 dma-names = "rx", "tx";
418 status = "disabled";
419 };
420
421 i2c@7000c500 {
422 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
423 reg = <0x0 0x7000c500 0x0 0x100>;
424 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
428 clock-names = "div-clk";
429 resets = <&tegra_car 67>;
430 reset-names = "i2c";
431 dmas = <&apbdma 23>, <&apbdma 23>;
432 dma-names = "rx", "tx";
433 status = "disabled";
434 };
435
436 i2c@7000c700 {
437 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
438 reg = <0x0 0x7000c700 0x0 0x100>;
439 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
441 #size-cells = <0>;
442 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
443 clock-names = "div-clk";
444 resets = <&tegra_car 103>;
445 reset-names = "i2c";
446 dmas = <&apbdma 26>, <&apbdma 26>;
447 dma-names = "rx", "tx";
448 status = "disabled";
449 };
450
451 i2c@7000d000 {
452 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
453 reg = <0x0 0x7000d000 0x0 0x100>;
454 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
458 clock-names = "div-clk";
459 resets = <&tegra_car 47>;
460 reset-names = "i2c";
461 dmas = <&apbdma 24>, <&apbdma 24>;
462 dma-names = "rx", "tx";
463 status = "disabled";
464 };
465
466 i2c@7000d100 {
467 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
468 reg = <0x0 0x7000d100 0x0 0x100>;
469 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
470 #address-cells = <1>;
471 #size-cells = <0>;
472 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
473 clock-names = "div-clk";
474 resets = <&tegra_car 166>;
475 reset-names = "i2c";
476 dmas = <&apbdma 30>, <&apbdma 30>;
477 dma-names = "rx", "tx";
478 status = "disabled";
479 };
480
481 spi@7000d400 {
482 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
483 reg = <0x0 0x7000d400 0x0 0x200>;
484 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
485 #address-cells = <1>;
486 #size-cells = <0>;
487 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
488 clock-names = "spi";
489 resets = <&tegra_car 41>;
490 reset-names = "spi";
491 dmas = <&apbdma 15>, <&apbdma 15>;
492 dma-names = "rx", "tx";
493 status = "disabled";
494 };
495
496 spi@7000d600 {
497 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
498 reg = <0x0 0x7000d600 0x0 0x200>;
499 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
500 #address-cells = <1>;
501 #size-cells = <0>;
502 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
503 clock-names = "spi";
504 resets = <&tegra_car 44>;
505 reset-names = "spi";
506 dmas = <&apbdma 16>, <&apbdma 16>;
507 dma-names = "rx", "tx";
508 status = "disabled";
509 };
510
511 spi@7000d800 {
512 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
513 reg = <0x0 0x7000d800 0x0 0x200>;
514 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
518 clock-names = "spi";
519 resets = <&tegra_car 46>;
520 reset-names = "spi";
521 dmas = <&apbdma 17>, <&apbdma 17>;
522 dma-names = "rx", "tx";
523 status = "disabled";
524 };
525
526 spi@7000da00 {
527 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
528 reg = <0x0 0x7000da00 0x0 0x200>;
529 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
533 clock-names = "spi";
534 resets = <&tegra_car 68>;
535 reset-names = "spi";
536 dmas = <&apbdma 18>, <&apbdma 18>;
537 dma-names = "rx", "tx";
538 status = "disabled";
539 };
540
541 spi@7000dc00 {
542 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
543 reg = <0x0 0x7000dc00 0x0 0x200>;
544 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
548 clock-names = "spi";
549 resets = <&tegra_car 104>;
550 reset-names = "spi";
551 dmas = <&apbdma 27>, <&apbdma 27>;
552 dma-names = "rx", "tx";
553 status = "disabled";
554 };
555
556 spi@7000de00 {
557 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
558 reg = <0x0 0x7000de00 0x0 0x200>;
559 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>;
561 #size-cells = <0>;
562 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
563 clock-names = "spi";
564 resets = <&tegra_car 105>;
565 reset-names = "spi";
566 dmas = <&apbdma 28>, <&apbdma 28>;
567 dma-names = "rx", "tx";
568 status = "disabled";
569 };
570
571 rtc@7000e000 {
572 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
573 reg = <0x0 0x7000e000 0x0 0x100>;
574 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&tegra_car TEGRA124_CLK_RTC>;
576 };
577
578 pmc@7000e400 {
579 compatible = "nvidia,tegra124-pmc";
580 reg = <0x0 0x7000e400 0x0 0x400>;
581 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
582 clock-names = "pclk", "clk32k_in";
583 };
584
585 fuse@7000f800 {
586 compatible = "nvidia,tegra124-efuse";
587 reg = <0x0 0x7000f800 0x0 0x400>;
588 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
589 clock-names = "fuse";
590 resets = <&tegra_car 39>;
591 reset-names = "fuse";
592 };
593
594 mc: memory-controller@70019000 {
595 compatible = "nvidia,tegra124-mc";
596 reg = <0x0 0x70019000 0x0 0x1000>;
597 clocks = <&tegra_car TEGRA124_CLK_MC>;
598 clock-names = "mc";
599
600 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
601
602 #iommu-cells = <1>;
603 };
604
605 emc: emc@7001b000 {
606 compatible = "nvidia,tegra124-emc";
607 reg = <0x0 0x7001b000 0x0 0x1000>;
608
609 nvidia,memory-controller = <&mc>;
610 };
611
612 sata@70020000 {
613 compatible = "nvidia,tegra124-ahci";
614 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
615 <0x0 0x70020000 0x0 0x7000>; /* SATA */
616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&tegra_car TEGRA124_CLK_SATA>,
618 <&tegra_car TEGRA124_CLK_SATA_OOB>,
619 <&tegra_car TEGRA124_CLK_CML1>,
620 <&tegra_car TEGRA124_CLK_PLL_E>;
621 clock-names = "sata", "sata-oob", "cml1", "pll_e";
622 resets = <&tegra_car 124>,
623 <&tegra_car 123>,
624 <&tegra_car 129>;
625 reset-names = "sata", "sata-oob", "sata-cold";
626 status = "disabled";
627 };
628
629 hda@70030000 {
630 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
631 reg = <0x0 0x70030000 0x0 0x10000>;
632 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&tegra_car TEGRA124_CLK_HDA>,
634 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
635 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
636 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
637 resets = <&tegra_car 125>, /* hda */
638 <&tegra_car 128>, /* hda2hdmi */
639 <&tegra_car 111>; /* hda2codec_2x */
640 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
641 status = "disabled";
642 };
643
644 usb@70090000 {
645 compatible = "nvidia,tegra124-xusb";
646 reg = <0x0 0x70090000 0x0 0x8000>,
647 <0x0 0x70098000 0x0 0x1000>,
648 <0x0 0x70099000 0x0 0x1000>;
649 reg-names = "hcd", "fpci", "ipfs";
650
651 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
653
654 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
655 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
656 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
657 <&tegra_car TEGRA124_CLK_XUSB_SS>,
658 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
659 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
660 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
661 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
662 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
663 <&tegra_car TEGRA124_CLK_CLK_M>,
664 <&tegra_car TEGRA124_CLK_PLL_E>;
665 clock-names = "xusb_host", "xusb_host_src",
666 "xusb_falcon_src", "xusb_ss",
667 "xusb_ss_div2", "xusb_ss_src",
668 "xusb_hs_src", "xusb_fs_src",
669 "pll_u_480m", "clk_m", "pll_e";
670 resets = <&tegra_car 89>, <&tegra_car 156>,
671 <&tegra_car 143>;
672 reset-names = "xusb_host", "xusb_ss", "xusb_src";
673
674 nvidia,xusb-padctl = <&padctl>;
675
676 status = "disabled";
677 };
678
679 padctl: padctl@7009f000 {
680 compatible = "nvidia,tegra124-xusb-padctl";
681 reg = <0x0 0x7009f000 0x0 0x1000>;
682 resets = <&tegra_car 142>;
683 reset-names = "padctl";
684
685 pads {
686 usb2 {
687 status = "disabled";
688
689 lanes {
690 usb2-0 {
691 status = "disabled";
692 #phy-cells = <0>;
693 };
694
695 usb2-1 {
696 status = "disabled";
697 #phy-cells = <0>;
698 };
699
700 usb2-2 {
701 status = "disabled";
702 #phy-cells = <0>;
703 };
704 };
705 };
706
707 ulpi {
708 status = "disabled";
709
710 lanes {
711 ulpi-0 {
712 status = "disabled";
713 #phy-cells = <0>;
714 };
715 };
716 };
717
718 hsic {
719 status = "disabled";
720
721 lanes {
722 hsic-0 {
723 status = "disabled";
724 #phy-cells = <0>;
725 };
726
727 hsic-1 {
728 status = "disabled";
729 #phy-cells = <0>;
730 };
731 };
732 };
733
734 pcie {
735 status = "disabled";
736
737 lanes {
738 pcie-0 {
739 status = "disabled";
740 #phy-cells = <0>;
741 };
742
743 pcie-1 {
744 status = "disabled";
745 #phy-cells = <0>;
746 };
747
748 pcie-2 {
749 status = "disabled";
750 #phy-cells = <0>;
751 };
752
753 pcie-3 {
754 status = "disabled";
755 #phy-cells = <0>;
756 };
757
758 pcie-4 {
759 status = "disabled";
760 #phy-cells = <0>;
761 };
762 };
763 };
764
765 sata {
766 status = "disabled";
767
768 lanes {
769 sata-0 {
770 status = "disabled";
771 #phy-cells = <0>;
772 };
773 };
774 };
775 };
776
777 ports {
778 usb2-0 {
779 status = "disabled";
780 };
781
782 usb2-1 {
783 status = "disabled";
784 };
785
786 usb2-2 {
787 status = "disabled";
788 };
789
790 ulpi-0 {
791 status = "disabled";
792 };
793
794 hsic-0 {
795 status = "disabled";
796 };
797
798 hsic-1 {
799 status = "disabled";
800 };
801
802 usb3-0 {
803 status = "disabled";
804 };
805
806 usb3-1 {
807 status = "disabled";
808 };
809 };
810 };
811
812 sdhci@700b0000 {
813 compatible = "nvidia,tegra124-sdhci";
814 reg = <0x0 0x700b0000 0x0 0x200>;
815 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
817 resets = <&tegra_car 14>;
818 reset-names = "sdhci";
819 status = "disabled";
820 };
821
822 sdhci@700b0200 {
823 compatible = "nvidia,tegra124-sdhci";
824 reg = <0x0 0x700b0200 0x0 0x200>;
825 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
827 resets = <&tegra_car 9>;
828 reset-names = "sdhci";
829 status = "disabled";
830 };
831
832 sdhci@700b0400 {
833 compatible = "nvidia,tegra124-sdhci";
834 reg = <0x0 0x700b0400 0x0 0x200>;
835 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
837 resets = <&tegra_car 69>;
838 reset-names = "sdhci";
839 status = "disabled";
840 };
841
842 sdhci@700b0600 {
843 compatible = "nvidia,tegra124-sdhci";
844 reg = <0x0 0x700b0600 0x0 0x200>;
845 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
847 resets = <&tegra_car 15>;
848 reset-names = "sdhci";
849 status = "disabled";
850 };
851
852 soctherm: thermal-sensor@700e2000 {
853 compatible = "nvidia,tegra124-soctherm";
854 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
855 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
856 reg-names = "soctherm-reg", "car-reg";
857 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
859 <&tegra_car TEGRA124_CLK_SOC_THERM>;
860 clock-names = "tsensor", "soctherm";
861 resets = <&tegra_car 78>;
862 reset-names = "soctherm";
863 #thermal-sensor-cells = <1>;
864
865 throttle-cfgs {
866 throttle_heavy: heavy {
867 nvidia,priority = <100>;
868 nvidia,cpu-throt-percent = <85>;
869
870 #cooling-cells = <2>;
871 };
872 };
873 };
874
875 dfll: clock@70110000 {
876 compatible = "nvidia,tegra124-dfll";
877 reg = <0 0x70110000 0 0x100>, /* DFLL control */
878 <0 0x70110000 0 0x100>, /* I2C output control */
879 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
880 <0 0x70110200 0 0x100>; /* Look-up table RAM */
881 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
883 <&tegra_car TEGRA124_CLK_DFLL_REF>,
884 <&tegra_car TEGRA124_CLK_I2C5>;
885 clock-names = "soc", "ref", "i2c";
886 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
887 reset-names = "dvco";
888 #clock-cells = <0>;
889 clock-output-names = "dfllCPU_out";
890 nvidia,sample-rate = <12500>;
891 nvidia,droop-ctrl = <0x00000f00>;
892 nvidia,force-mode = <1>;
893 nvidia,cf = <10>;
894 nvidia,ci = <0>;
895 nvidia,cg = <2>;
896 status = "disabled";
897 };
898
899 ahub@70300000 {
900 compatible = "nvidia,tegra124-ahub";
901 reg = <0x0 0x70300000 0x0 0x200>,
902 <0x0 0x70300800 0x0 0x800>,
903 <0x0 0x70300200 0x0 0x600>;
904 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
906 <&tegra_car TEGRA124_CLK_APBIF>;
907 clock-names = "d_audio", "apbif";
908 resets = <&tegra_car 106>, /* d_audio */
909 <&tegra_car 107>, /* apbif */
910 <&tegra_car 30>, /* i2s0 */
911 <&tegra_car 11>, /* i2s1 */
912 <&tegra_car 18>, /* i2s2 */
913 <&tegra_car 101>, /* i2s3 */
914 <&tegra_car 102>, /* i2s4 */
915 <&tegra_car 108>, /* dam0 */
916 <&tegra_car 109>, /* dam1 */
917 <&tegra_car 110>, /* dam2 */
918 <&tegra_car 10>, /* spdif */
919 <&tegra_car 153>, /* amx */
920 <&tegra_car 185>, /* amx1 */
921 <&tegra_car 154>, /* adx */
922 <&tegra_car 180>, /* adx1 */
923 <&tegra_car 186>, /* afc0 */
924 <&tegra_car 187>, /* afc1 */
925 <&tegra_car 188>, /* afc2 */
926 <&tegra_car 189>, /* afc3 */
927 <&tegra_car 190>, /* afc4 */
928 <&tegra_car 191>; /* afc5 */
929 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
930 "i2s3", "i2s4", "dam0", "dam1", "dam2",
931 "spdif", "amx", "amx1", "adx", "adx1",
932 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
933 dmas = <&apbdma 1>, <&apbdma 1>,
934 <&apbdma 2>, <&apbdma 2>,
935 <&apbdma 3>, <&apbdma 3>,
936 <&apbdma 4>, <&apbdma 4>,
937 <&apbdma 6>, <&apbdma 6>,
938 <&apbdma 7>, <&apbdma 7>,
939 <&apbdma 12>, <&apbdma 12>,
940 <&apbdma 13>, <&apbdma 13>,
941 <&apbdma 14>, <&apbdma 14>,
942 <&apbdma 29>, <&apbdma 29>;
943 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
944 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
945 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
946 "rx9", "tx9";
947 ranges;
948 #address-cells = <2>;
949 #size-cells = <2>;
950
951 tegra_i2s0: i2s@70301000 {
952 compatible = "nvidia,tegra124-i2s";
953 reg = <0x0 0x70301000 0x0 0x100>;
954 nvidia,ahub-cif-ids = <4 4>;
955 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
956 resets = <&tegra_car 30>;
957 reset-names = "i2s";
958 status = "disabled";
959 };
960
961 tegra_i2s1: i2s@70301100 {
962 compatible = "nvidia,tegra124-i2s";
963 reg = <0x0 0x70301100 0x0 0x100>;
964 nvidia,ahub-cif-ids = <5 5>;
965 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
966 resets = <&tegra_car 11>;
967 reset-names = "i2s";
968 status = "disabled";
969 };
970
971 tegra_i2s2: i2s@70301200 {
972 compatible = "nvidia,tegra124-i2s";
973 reg = <0x0 0x70301200 0x0 0x100>;
974 nvidia,ahub-cif-ids = <6 6>;
975 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
976 resets = <&tegra_car 18>;
977 reset-names = "i2s";
978 status = "disabled";
979 };
980
981 tegra_i2s3: i2s@70301300 {
982 compatible = "nvidia,tegra124-i2s";
983 reg = <0x0 0x70301300 0x0 0x100>;
984 nvidia,ahub-cif-ids = <7 7>;
985 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
986 resets = <&tegra_car 101>;
987 reset-names = "i2s";
988 status = "disabled";
989 };
990
991 tegra_i2s4: i2s@70301400 {
992 compatible = "nvidia,tegra124-i2s";
993 reg = <0x0 0x70301400 0x0 0x100>;
994 nvidia,ahub-cif-ids = <8 8>;
995 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
996 resets = <&tegra_car 102>;
997 reset-names = "i2s";
998 status = "disabled";
999 };
1000 };
1001
1002 usb@7d000000 {
1003 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1004 reg = <0x0 0x7d000000 0x0 0x4000>;
1005 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1006 phy_type = "utmi";
1007 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1008 resets = <&tegra_car 22>;
1009 reset-names = "usb";
1010 nvidia,phy = <&phy1>;
1011 status = "disabled";
1012 };
1013
1014 phy1: usb-phy@7d000000 {
1015 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1016 reg = <0x0 0x7d000000 0x0 0x4000>,
1017 <0x0 0x7d000000 0x0 0x4000>;
1018 phy_type = "utmi";
1019 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1020 <&tegra_car TEGRA124_CLK_PLL_U>,
1021 <&tegra_car TEGRA124_CLK_USBD>;
1022 clock-names = "reg", "pll_u", "utmi-pads";
1023 resets = <&tegra_car 22>, <&tegra_car 22>;
1024 reset-names = "usb", "utmi-pads";
1025 nvidia,hssync-start-delay = <0>;
1026 nvidia,idle-wait-delay = <17>;
1027 nvidia,elastic-limit = <16>;
1028 nvidia,term-range-adj = <6>;
1029 nvidia,xcvr-setup = <9>;
1030 nvidia,xcvr-lsfslew = <0>;
1031 nvidia,xcvr-lsrslew = <3>;
1032 nvidia,hssquelch-level = <2>;
1033 nvidia,hsdiscon-level = <5>;
1034 nvidia,xcvr-hsslew = <12>;
1035 nvidia,has-utmi-pad-registers;
1036 status = "disabled";
1037 };
1038
1039 usb@7d004000 {
1040 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1041 reg = <0x0 0x7d004000 0x0 0x4000>;
1042 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1043 phy_type = "utmi";
1044 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1045 resets = <&tegra_car 58>;
1046 reset-names = "usb";
1047 nvidia,phy = <&phy2>;
1048 status = "disabled";
1049 };
1050
1051 phy2: usb-phy@7d004000 {
1052 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1053 reg = <0x0 0x7d004000 0x0 0x4000>,
1054 <0x0 0x7d000000 0x0 0x4000>;
1055 phy_type = "utmi";
1056 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1057 <&tegra_car TEGRA124_CLK_PLL_U>,
1058 <&tegra_car TEGRA124_CLK_USBD>;
1059 clock-names = "reg", "pll_u", "utmi-pads";
1060 resets = <&tegra_car 58>, <&tegra_car 22>;
1061 reset-names = "usb", "utmi-pads";
1062 nvidia,hssync-start-delay = <0>;
1063 nvidia,idle-wait-delay = <17>;
1064 nvidia,elastic-limit = <16>;
1065 nvidia,term-range-adj = <6>;
1066 nvidia,xcvr-setup = <9>;
1067 nvidia,xcvr-lsfslew = <0>;
1068 nvidia,xcvr-lsrslew = <3>;
1069 nvidia,hssquelch-level = <2>;
1070 nvidia,hsdiscon-level = <5>;
1071 nvidia,xcvr-hsslew = <12>;
1072 status = "disabled";
1073 };
1074
1075 usb@7d008000 {
1076 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1077 reg = <0x0 0x7d008000 0x0 0x4000>;
1078 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1079 phy_type = "utmi";
1080 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1081 resets = <&tegra_car 59>;
1082 reset-names = "usb";
1083 nvidia,phy = <&phy3>;
1084 status = "disabled";
1085 };
1086
1087 phy3: usb-phy@7d008000 {
1088 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1089 reg = <0x0 0x7d008000 0x0 0x4000>,
1090 <0x0 0x7d000000 0x0 0x4000>;
1091 phy_type = "utmi";
1092 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1093 <&tegra_car TEGRA124_CLK_PLL_U>,
1094 <&tegra_car TEGRA124_CLK_USBD>;
1095 clock-names = "reg", "pll_u", "utmi-pads";
1096 resets = <&tegra_car 59>, <&tegra_car 22>;
1097 reset-names = "usb", "utmi-pads";
1098 nvidia,hssync-start-delay = <0>;
1099 nvidia,idle-wait-delay = <17>;
1100 nvidia,elastic-limit = <16>;
1101 nvidia,term-range-adj = <6>;
1102 nvidia,xcvr-setup = <9>;
1103 nvidia,xcvr-lsfslew = <0>;
1104 nvidia,xcvr-lsrslew = <3>;
1105 nvidia,hssquelch-level = <2>;
1106 nvidia,hsdiscon-level = <5>;
1107 nvidia,xcvr-hsslew = <12>;
1108 status = "disabled";
1109 };
1110
1111 cpus {
1112 #address-cells = <1>;
1113 #size-cells = <0>;
1114
1115 cpu@0 {
1116 device_type = "cpu";
1117 compatible = "arm,cortex-a15";
1118 reg = <0>;
1119
1120 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1121 <&tegra_car TEGRA124_CLK_CCLK_LP>,
1122 <&tegra_car TEGRA124_CLK_PLL_X>,
1123 <&tegra_car TEGRA124_CLK_PLL_P>,
1124 <&dfll>;
1125 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1126 /* FIXME: what's the actual transition time? */
1127 clock-latency = <300000>;
1128 };
1129
1130 cpu@1 {
1131 device_type = "cpu";
1132 compatible = "arm,cortex-a15";
1133 reg = <1>;
1134 };
1135
1136 cpu@2 {
1137 device_type = "cpu";
1138 compatible = "arm,cortex-a15";
1139 reg = <2>;
1140 };
1141
1142 cpu@3 {
1143 device_type = "cpu";
1144 compatible = "arm,cortex-a15";
1145 reg = <3>;
1146 };
1147 };
1148
1149 pmu {
1150 compatible = "arm,cortex-a15-pmu";
1151 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1152 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1155 interrupt-affinity = <&{/cpus/cpu@0}>,
1156 <&{/cpus/cpu@1}>,
1157 <&{/cpus/cpu@2}>,
1158 <&{/cpus/cpu@3}>;
1159 };
1160
1161 thermal-zones {
1162 cpu {
1163 polling-delay-passive = <1000>;
1164 polling-delay = <1000>;
1165
1166 thermal-sensors =
1167 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1168
1169 trips {
1170 cpu-shutdown-trip {
1171 temperature = <103000>;
1172 hysteresis = <0>;
1173 type = "critical";
1174 };
1175 cpu_throttle_trip: throttle-trip {
1176 temperature = <100000>;
1177 hysteresis = <1000>;
1178 type = "hot";
1179 };
1180 };
1181
1182 cooling-maps {
1183 map0 {
1184 trip = <&cpu_throttle_trip>;
1185 cooling-device = <&throttle_heavy 1 1>;
1186 };
1187 };
1188 };
1189
1190 mem {
1191 polling-delay-passive = <1000>;
1192 polling-delay = <1000>;
1193
1194 thermal-sensors =
1195 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1196
1197 trips {
1198 mem-shutdown-trip {
1199 temperature = <103000>;
1200 hysteresis = <0>;
1201 type = "critical";
1202 };
1203 };
1204
1205 cooling-maps {
1206 /*
1207 * There are currently no cooling maps,
1208 * because there are no cooling devices.
1209 */
1210 };
1211 };
1212
1213 gpu {
1214 polling-delay-passive = <1000>;
1215 polling-delay = <1000>;
1216
1217 thermal-sensors =
1218 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1219
1220 trips {
1221 gpu-shutdown-trip {
1222 temperature = <101000>;
1223 hysteresis = <0>;
1224 type = "critical";
1225 };
1226 gpu_throttle_trip: throttle-trip {
1227 temperature = <99000>;
1228 hysteresis = <1000>;
1229 type = "hot";
1230 };
1231 };
1232
1233 cooling-maps {
1234 map0 {
1235 trip = <&gpu_throttle_trip>;
1236 cooling-device = <&throttle_heavy 1 1>;
1237 };
1238 };
1239 };
1240
1241 pllx {
1242 polling-delay-passive = <1000>;
1243 polling-delay = <1000>;
1244
1245 thermal-sensors =
1246 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1247
1248 trips {
1249 pllx-shutdown-trip {
1250 temperature = <103000>;
1251 hysteresis = <0>;
1252 type = "critical";
1253 };
1254 };
1255
1256 cooling-maps {
1257 /*
1258 * There are currently no cooling maps,
1259 * because there are no cooling devices.
1260 */
1261 };
1262 };
1263 };
1264
1265 timer {
1266 compatible = "arm,armv7-timer";
1267 interrupts = <GIC_PPI 13
1268 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1269 <GIC_PPI 14
1270 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1271 <GIC_PPI 11
1272 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1273 <GIC_PPI 10
1274 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1275 interrupt-parent = <&gic>;
1276 };
1277};