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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 STMicroelectronics Limited.
4 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
5 */
6#include "stih407-pinctrl.dtsi"
7#include <dt-bindings/mfd/st-lpc.h>
8#include <dt-bindings/phy/phy.h>
9#include <dt-bindings/reset/stih407-resets.h>
10#include <dt-bindings/interrupt-controller/irq-st.h>
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
19
20 gp0_reserved: rproc@45000000 {
21 compatible = "shared-dma-pool";
22 reg = <0x45000000 0x00400000>;
23 no-map;
24 };
25
26 delta_reserved: rproc@44000000 {
27 compatible = "shared-dma-pool";
28 reg = <0x44000000 0x01000000>;
29 no-map;
30 };
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0>;
40
41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
42 cpu-release-addr = <0x94100A4>;
43
44 /* kHz uV */
45 operating-points = <1500000 0
46 1200000 0
47 800000 0
48 500000 0>;
49
50 clocks = <&clk_m_a9>;
51 clock-names = "cpu";
52 clock-latency = <100000>;
53 cpu0-supply = <&pwm_regulator>;
54 st,syscfg = <&syscfg_core 0x8e0>;
55 };
56 cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a9";
59 reg = <1>;
60
61 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
62 cpu-release-addr = <0x94100A4>;
63
64 /* kHz uV */
65 operating-points = <1500000 0
66 1200000 0
67 800000 0
68 500000 0>;
69 };
70 };
71
72 intc: interrupt-controller@8761000 {
73 compatible = "arm,cortex-a9-gic";
74 #interrupt-cells = <3>;
75 interrupt-controller;
76 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
77 };
78
79 scu@8760000 {
80 compatible = "arm,cortex-a9-scu";
81 reg = <0x08760000 0x1000>;
82 };
83
84 timer@8760200 {
85 interrupt-parent = <&intc>;
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x08760200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&arm_periph_clk>;
90 };
91
92 l2: cache-controller@8762000 {
93 compatible = "arm,pl310-cache";
94 reg = <0x08762000 0x1000>;
95 arm,data-latency = <3 3 3>;
96 arm,tag-latency = <2 2 2>;
97 cache-unified;
98 cache-level = <2>;
99 };
100
101 arm-pmu {
102 interrupt-parent = <&intc>;
103 compatible = "arm,cortex-a9-pmu";
104 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
105 };
106
107 pwm_regulator: pwm-regulator {
108 compatible = "pwm-regulator";
109 pwms = <&pwm1 3 8448>;
110 regulator-name = "CPU_1V0_AVS";
111 regulator-min-microvolt = <784000>;
112 regulator-max-microvolt = <1299000>;
113 regulator-always-on;
114 max-duty-cycle = <255>;
115 status = "okay";
116 };
117
118 soc {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 interrupt-parent = <&intc>;
122 ranges;
123 compatible = "simple-bus";
124
125 restart: restart-controller@0 {
126 compatible = "st,stih407-restart";
127 reg = <0 0>;
128 st,syscfg = <&syscfg_sbc_reg>;
129 status = "okay";
130 };
131
132 powerdown: powerdown-controller@0 {
133 compatible = "st,stih407-powerdown";
134 reg = <0 0>;
135 #reset-cells = <1>;
136 };
137
138 softreset: softreset-controller@0 {
139 compatible = "st,stih407-softreset";
140 reg = <0 0>;
141 #reset-cells = <1>;
142 };
143
144 picophyreset: picophyreset-controller@0 {
145 compatible = "st,stih407-picophyreset";
146 reg = <0 0>;
147 #reset-cells = <1>;
148 };
149
150 syscfg_sbc: sbc-syscfg@9620000 {
151 compatible = "st,stih407-sbc-syscfg", "syscon";
152 reg = <0x9620000 0x1000>;
153 };
154
155 syscfg_front: front-syscfg@9280000 {
156 compatible = "st,stih407-front-syscfg", "syscon";
157 reg = <0x9280000 0x1000>;
158 };
159
160 syscfg_rear: rear-syscfg@9290000 {
161 compatible = "st,stih407-rear-syscfg", "syscon";
162 reg = <0x9290000 0x1000>;
163 };
164
165 syscfg_flash: flash-syscfg@92a0000 {
166 compatible = "st,stih407-flash-syscfg", "syscon";
167 reg = <0x92a0000 0x1000>;
168 };
169
170 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
171 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
172 reg = <0x9600000 0x1000>;
173 };
174
175 syscfg_core: core-syscfg@92b0000 {
176 compatible = "st,stih407-core-syscfg", "syscon";
177 reg = <0x92b0000 0x1000>;
178
179 sti_sasg_codec: sti-sasg-codec {
180 compatible = "st,stih407-sas-codec";
181 #sound-dai-cells = <1>;
182 status = "disabled";
183 st,syscfg = <&syscfg_core>;
184 };
185 };
186
187 syscfg_lpm: lpm-syscfg@94b5100 {
188 compatible = "st,stih407-lpm-syscfg", "syscon";
189 reg = <0x94b5100 0x1000>;
190 };
191
192 irq-syscfg@0 {
193 compatible = "st,stih407-irq-syscfg";
194 reg = <0 0>;
195 st,syscfg = <&syscfg_core>;
196 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
197 <ST_IRQ_SYSCFG_PMU_1>;
198 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
199 <ST_IRQ_SYSCFG_DISABLED>;
200 };
201
202 /* Display */
203 vtg_main: sti-vtg-main@8d02800 {
204 compatible = "st,vtg";
205 reg = <0x8d02800 0x200>;
206 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
207 };
208
209 vtg_aux: sti-vtg-aux@8d00200 {
210 compatible = "st,vtg";
211 reg = <0x8d00200 0x100>;
212 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
213 };
214
215 serial@9830000 {
216 compatible = "st,asc";
217 reg = <0x9830000 0x2c>;
218 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
220 /* Pinctrl moved out to a per-board configuration */
221
222 status = "disabled";
223 };
224
225 serial@9831000 {
226 compatible = "st,asc";
227 reg = <0x9831000 0x2c>;
228 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_serial1>;
231 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
232
233 status = "disabled";
234 };
235
236 serial@9832000 {
237 compatible = "st,asc";
238 reg = <0x9832000 0x2c>;
239 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_serial2>;
242 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
243
244 status = "disabled";
245 };
246
247 /* SBC_ASC0 - UART10 */
248 sbc_serial0: serial@9530000 {
249 compatible = "st,asc";
250 reg = <0x9530000 0x2c>;
251 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_sbc_serial0>;
254 clocks = <&clk_sysin>;
255
256 status = "disabled";
257 };
258
259 serial@9531000 {
260 compatible = "st,asc";
261 reg = <0x9531000 0x2c>;
262 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_sbc_serial1>;
265 clocks = <&clk_sysin>;
266
267 status = "disabled";
268 };
269
270 i2c@9840000 {
271 compatible = "st,comms-ssc4-i2c";
272 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
273 reg = <0x9840000 0x110>;
274 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
275 clock-names = "ssc";
276 clock-frequency = <400000>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_i2c0_default>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281
282 status = "disabled";
283 };
284
285 i2c@9841000 {
286 compatible = "st,comms-ssc4-i2c";
287 reg = <0x9841000 0x110>;
288 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
290 clock-names = "ssc";
291 clock-frequency = <400000>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c1_default>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 status = "disabled";
298 };
299
300 i2c@9842000 {
301 compatible = "st,comms-ssc4-i2c";
302 reg = <0x9842000 0x110>;
303 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
305 clock-names = "ssc";
306 clock-frequency = <400000>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_i2c2_default>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311
312 status = "disabled";
313 };
314
315 i2c@9843000 {
316 compatible = "st,comms-ssc4-i2c";
317 reg = <0x9843000 0x110>;
318 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
320 clock-names = "ssc";
321 clock-frequency = <400000>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_i2c3_default>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326
327 status = "disabled";
328 };
329
330 i2c@9844000 {
331 compatible = "st,comms-ssc4-i2c";
332 reg = <0x9844000 0x110>;
333 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
335 clock-names = "ssc";
336 clock-frequency = <400000>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_i2c4_default>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341
342 status = "disabled";
343 };
344
345 i2c@9845000 {
346 compatible = "st,comms-ssc4-i2c";
347 reg = <0x9845000 0x110>;
348 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
350 clock-names = "ssc";
351 clock-frequency = <400000>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_i2c5_default>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356
357 status = "disabled";
358 };
359
360
361 /* SSCs on SBC */
362 i2c@9540000 {
363 compatible = "st,comms-ssc4-i2c";
364 reg = <0x9540000 0x110>;
365 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clk_sysin>;
367 clock-names = "ssc";
368 clock-frequency = <400000>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_i2c10_default>;
371 #address-cells = <1>;
372 #size-cells = <0>;
373
374 status = "disabled";
375 };
376
377 i2c@9541000 {
378 compatible = "st,comms-ssc4-i2c";
379 reg = <0x9541000 0x110>;
380 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clk_sysin>;
382 clock-names = "ssc";
383 clock-frequency = <400000>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_i2c11_default>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388
389 status = "disabled";
390 };
391
392 usb2_picophy0: phy1@0 {
393 compatible = "st,stih407-usb2-phy";
394 reg = <0 0>;
395 #phy-cells = <0>;
396 st,syscfg = <&syscfg_core 0x100 0xf4>;
397 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
398 <&picophyreset STIH407_PICOPHY2_RESET>;
399 reset-names = "global", "port";
400 };
401
402 miphy28lp_phy: miphy28lp@0 {
403 compatible = "st,miphy28lp-phy";
404 st,syscfg = <&syscfg_core>;
405 #address-cells = <1>;
406 #size-cells = <1>;
407 ranges;
408 reg = <0 0>;
409
410 phy_port0: port@9b22000 {
411 reg = <0x9b22000 0xff>,
412 <0x9b09000 0xff>,
413 <0x9b04000 0xff>;
414 reg-names = "sata-up",
415 "pcie-up",
416 "pipew";
417
418 st,syscfg = <0x114 0x818 0xe0 0xec>;
419 #phy-cells = <1>;
420
421 reset-names = "miphy-sw-rst";
422 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
423 };
424
425 phy_port1: port@9b2a000 {
426 reg = <0x9b2a000 0xff>,
427 <0x9b19000 0xff>,
428 <0x9b14000 0xff>;
429 reg-names = "sata-up",
430 "pcie-up",
431 "pipew";
432
433 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
434
435 #phy-cells = <1>;
436
437 reset-names = "miphy-sw-rst";
438 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
439 };
440
441 phy_port2: port@8f95000 {
442 reg = <0x8f95000 0xff>,
443 <0x8f90000 0xff>;
444 reg-names = "pipew",
445 "usb3-up";
446
447 st,syscfg = <0x11c 0x820>;
448
449 #phy-cells = <1>;
450
451 reset-names = "miphy-sw-rst";
452 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
453 };
454 };
455
456 spi@9840000 {
457 compatible = "st,comms-ssc4-spi";
458 reg = <0x9840000 0x110>;
459 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
461 clock-names = "ssc";
462 pinctrl-0 = <&pinctrl_spi0_default>;
463 pinctrl-names = "default";
464 #address-cells = <1>;
465 #size-cells = <0>;
466
467 status = "disabled";
468 };
469
470 spi@9841000 {
471 compatible = "st,comms-ssc4-spi";
472 reg = <0x9841000 0x110>;
473 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
475 clock-names = "ssc";
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_spi1_default>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480
481 status = "disabled";
482 };
483
484 spi@9842000 {
485 compatible = "st,comms-ssc4-spi";
486 reg = <0x9842000 0x110>;
487 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
489 clock-names = "ssc";
490 pinctrl-names = "default";
491 pinctrl-0 = <&pinctrl_spi2_default>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494
495 status = "disabled";
496 };
497
498 spi@9843000 {
499 compatible = "st,comms-ssc4-spi";
500 reg = <0x9843000 0x110>;
501 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
503 clock-names = "ssc";
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_spi3_default>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508
509 status = "disabled";
510 };
511
512 spi@9844000 {
513 compatible = "st,comms-ssc4-spi";
514 reg = <0x9844000 0x110>;
515 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
517 clock-names = "ssc";
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_spi4_default>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522
523 status = "disabled";
524 };
525
526 /* SBC SSC */
527 spi@9540000 {
528 compatible = "st,comms-ssc4-spi";
529 reg = <0x9540000 0x110>;
530 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clk_sysin>;
532 clock-names = "ssc";
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_spi10_default>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537
538 status = "disabled";
539 };
540
541 spi@9541000 {
542 compatible = "st,comms-ssc4-spi";
543 reg = <0x9541000 0x110>;
544 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clk_sysin>;
546 clock-names = "ssc";
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_spi11_default>;
549 #address-cells = <1>;
550 #size-cells = <0>;
551
552 status = "disabled";
553 };
554
555 spi@9542000 {
556 compatible = "st,comms-ssc4-spi";
557 reg = <0x9542000 0x110>;
558 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clk_sysin>;
560 clock-names = "ssc";
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_spi12_default>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565
566 status = "disabled";
567 };
568
569 mmc0: sdhci@9060000 {
570 compatible = "st,sdhci-stih407", "st,sdhci";
571 status = "disabled";
572 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
573 reg-names = "mmc", "top-mmc-delay";
574 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
575 interrupt-names = "mmcirq";
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_mmc0>;
578 clock-names = "mmc", "icn";
579 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
580 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
581 bus-width = <8>;
582 };
583
584 mmc1: sdhci@9080000 {
585 compatible = "st,sdhci-stih407", "st,sdhci";
586 status = "disabled";
587 reg = <0x09080000 0x7ff>;
588 reg-names = "mmc";
589 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
590 interrupt-names = "mmcirq";
591 pinctrl-names = "default";
592 pinctrl-0 = <&pinctrl_sd1>;
593 clock-names = "mmc", "icn";
594 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
595 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
596 resets = <&softreset STIH407_MMC1_SOFTRESET>;
597 bus-width = <4>;
598 };
599
600 /* Watchdog and Real-Time Clock */
601 lpc@8787000 {
602 compatible = "st,stih407-lpc";
603 reg = <0x8787000 0x1000>;
604 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
605 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
606 timeout-sec = <120>;
607 st,syscfg = <&syscfg_core>;
608 st,lpc-mode = <ST_LPC_MODE_WDT>;
609 };
610
611 lpc@8788000 {
612 compatible = "st,stih407-lpc";
613 reg = <0x8788000 0x1000>;
614 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
615 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
616 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
617 };
618
619 sata0: sata@9b20000 {
620 compatible = "st,ahci";
621 reg = <0x9b20000 0x1000>;
622
623 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
624 interrupt-names = "hostc";
625
626 phys = <&phy_port0 PHY_TYPE_SATA>;
627 phy-names = "ahci_phy";
628
629 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
630 <&softreset STIH407_SATA0_SOFTRESET>,
631 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
632 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
633
634 clock-names = "ahci_clk";
635 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
636
637 ports-implemented = <0x1>;
638
639 status = "disabled";
640 };
641
642 sata1: sata@9b28000 {
643 compatible = "st,ahci";
644 reg = <0x9b28000 0x1000>;
645
646 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
647 interrupt-names = "hostc";
648
649 phys = <&phy_port1 PHY_TYPE_SATA>;
650 phy-names = "ahci_phy";
651
652 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
653 <&softreset STIH407_SATA1_SOFTRESET>,
654 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
655 reset-names = "pwr-dwn",
656 "sw-rst",
657 "pwr-rst";
658
659 clock-names = "ahci_clk";
660 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
661
662 ports-implemented = <0x1>;
663
664 status = "disabled";
665 };
666
667
668 st_dwc3: dwc3@8f94000 {
669 compatible = "st,stih407-dwc3";
670 reg = <0x08f94000 0x1000>, <0x110 0x4>;
671 reg-names = "reg-glue", "syscfg-reg";
672 st,syscfg = <&syscfg_core>;
673 resets = <&powerdown STIH407_USB3_POWERDOWN>,
674 <&softreset STIH407_MIPHY2_SOFTRESET>;
675 reset-names = "powerdown", "softreset";
676 #address-cells = <1>;
677 #size-cells = <1>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&pinctrl_usb3>;
680 ranges;
681
682 status = "disabled";
683
684 dwc3: dwc3@9900000 {
685 compatible = "snps,dwc3";
686 reg = <0x09900000 0x100000>;
687 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
688 dr_mode = "host";
689 phy-names = "usb2-phy", "usb3-phy";
690 phys = <&usb2_picophy0>,
691 <&phy_port2 PHY_TYPE_USB3>;
692 snps,dis_u3_susphy_quirk;
693 };
694 };
695
696 /* COMMS PWM Module */
697 pwm0: pwm@9810000 {
698 compatible = "st,sti-pwm";
699 #pwm-cells = <2>;
700 reg = <0x9810000 0x68>;
701 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
704 clock-names = "pwm";
705 clocks = <&clk_sysin>;
706 st,pwm-num-chan = <1>;
707
708 status = "disabled";
709 };
710
711 /* SBC PWM Module */
712 pwm1: pwm@9510000 {
713 compatible = "st,sti-pwm";
714 #pwm-cells = <2>;
715 reg = <0x9510000 0x68>;
716 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&pinctrl_pwm1_chan0_default
719 &pinctrl_pwm1_chan1_default
720 &pinctrl_pwm1_chan2_default
721 &pinctrl_pwm1_chan3_default>;
722 clock-names = "pwm";
723 clocks = <&clk_sysin>;
724 st,pwm-num-chan = <4>;
725
726 status = "disabled";
727 };
728
729 rng10: rng@8a89000 {
730 compatible = "st,rng";
731 reg = <0x08a89000 0x1000>;
732 clocks = <&clk_sysin>;
733 status = "okay";
734 };
735
736 rng11: rng@8a8a000 {
737 compatible = "st,rng";
738 reg = <0x08a8a000 0x1000>;
739 clocks = <&clk_sysin>;
740 status = "okay";
741 };
742
743 ethernet0: dwmac@9630000 {
744 device_type = "network";
745 status = "disabled";
746 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
747 reg = <0x9630000 0x8000>, <0x80 0x4>;
748 reg-names = "stmmaceth", "sti-ethconf";
749
750 st,syscon = <&syscfg_sbc_reg 0x80>;
751 st,gmac_en;
752 resets = <&softreset STIH407_ETH1_SOFTRESET>;
753 reset-names = "stmmaceth";
754
755 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
757 interrupt-names = "macirq", "eth_wake_irq";
758
759 /* DMA Bus Mode */
760 snps,pbl = <8>;
761
762 pinctrl-names = "default";
763 pinctrl-0 = <&pinctrl_rgmii1>;
764
765 clock-names = "stmmaceth", "sti-ethclk";
766 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
767 <&clk_s_c0_flexgen CLK_ETH_PHY>;
768 };
769
770 rng10: rng@8a89000 {
771 compatible = "st,rng";
772 reg = <0x08a89000 0x1000>;
773 clocks = <&clk_sysin>;
774 status = "okay";
775 };
776
777 rng11: rng@8a8a000 {
778 compatible = "st,rng";
779 reg = <0x08a8a000 0x1000>;
780 clocks = <&clk_sysin>;
781 status = "okay";
782 };
783
784 mailbox0: mailbox@8f00000 {
785 compatible = "st,stih407-mailbox";
786 reg = <0x8f00000 0x1000>;
787 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
788 #mbox-cells = <2>;
789 mbox-name = "a9";
790 status = "okay";
791 };
792
793 mailbox1: mailbox@8f01000 {
794 compatible = "st,stih407-mailbox";
795 reg = <0x8f01000 0x1000>;
796 #mbox-cells = <2>;
797 mbox-name = "st231_gp_1";
798 status = "okay";
799 };
800
801 mailbox2: mailbox@8f02000 {
802 compatible = "st,stih407-mailbox";
803 reg = <0x8f02000 0x1000>;
804 #mbox-cells = <2>;
805 mbox-name = "st231_gp_0";
806 status = "okay";
807 };
808
809 mailbox3: mailbox@8f03000 {
810 compatible = "st,stih407-mailbox";
811 reg = <0x8f03000 0x1000>;
812 #mbox-cells = <2>;
813 mbox-name = "st231_audio_video";
814 status = "okay";
815 };
816
817 st231_gp0: st231-gp0@0 {
818 compatible = "st,st231-rproc";
819 reg = <0 0>;
820 memory-region = <&gp0_reserved>;
821 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
822 reset-names = "sw_reset";
823 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
824 clock-frequency = <600000000>;
825 st,syscfg = <&syscfg_core 0x22c>;
826 #mbox-cells = <1>;
827 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
828 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
829 };
830
831 st231_delta: st231-delta@0 {
832 compatible = "st,st231-rproc";
833 reg = <0 0>;
834 memory-region = <&delta_reserved>;
835 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
836 reset-names = "sw_reset";
837 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
838 clock-frequency = <600000000>;
839 st,syscfg = <&syscfg_core 0x224>;
840 #mbox-cells = <1>;
841 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
842 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
843 };
844
845 /* fdma audio */
846 fdma0: dma-controller@8e20000 {
847 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
848 reg = <0x8e20000 0x8000>,
849 <0x8e30000 0x3000>,
850 <0x8e37000 0x1000>,
851 <0x8e38000 0x8000>;
852 reg-names = "slimcore", "dmem", "peripherals", "imem";
853 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
854 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
855 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
856 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
857 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
858 dma-channels = <16>;
859 #dma-cells = <3>;
860 };
861
862 /* fdma app */
863 fdma1: dma-controller@8e40000 {
864 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
865 reg = <0x8e40000 0x8000>,
866 <0x8e50000 0x3000>,
867 <0x8e57000 0x1000>,
868 <0x8e58000 0x8000>;
869 reg-names = "slimcore", "dmem", "peripherals", "imem";
870 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
871 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
872 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
873 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
874
875 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
876 dma-channels = <16>;
877 #dma-cells = <3>;
878
879 status = "disabled";
880 };
881
882 /* fdma free running */
883 fdma2: dma-controller@8e60000 {
884 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
885 reg = <0x8e60000 0x8000>,
886 <0x8e70000 0x3000>,
887 <0x8e77000 0x1000>,
888 <0x8e78000 0x8000>;
889 reg-names = "slimcore", "dmem", "peripherals", "imem";
890 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
891 dma-channels = <16>;
892 #dma-cells = <3>;
893 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
894 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
895 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
896 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
897
898 status = "disabled";
899 };
900
901 sti_uni_player0: sti-uni-player@8d80000 {
902 compatible = "st,stih407-uni-player-hdmi";
903 #sound-dai-cells = <0>;
904 st,syscfg = <&syscfg_core>;
905 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
906 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
907 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
908 assigned-clock-rates = <50000000>;
909 reg = <0x8d80000 0x158>;
910 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
911 dmas = <&fdma0 2 0 1>;
912 dma-names = "tx";
913
914 status = "disabled";
915 };
916
917 sti_uni_player1: sti-uni-player@8d81000 {
918 compatible = "st,stih407-uni-player-pcm-out";
919 #sound-dai-cells = <0>;
920 st,syscfg = <&syscfg_core>;
921 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
922 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
923 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
924 assigned-clock-rates = <50000000>;
925 reg = <0x8d81000 0x158>;
926 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
927 dmas = <&fdma0 3 0 1>;
928 dma-names = "tx";
929
930 status = "disabled";
931 };
932
933 sti_uni_player2: sti-uni-player@8d82000 {
934 compatible = "st,stih407-uni-player-dac";
935 #sound-dai-cells = <0>;
936 st,syscfg = <&syscfg_core>;
937 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
938 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
939 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
940 assigned-clock-rates = <50000000>;
941 reg = <0x8d82000 0x158>;
942 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
943 dmas = <&fdma0 4 0 1>;
944 dma-names = "tx";
945
946 status = "disabled";
947 };
948
949 sti_uni_player3: sti-uni-player@8d85000 {
950 compatible = "st,stih407-uni-player-spdif";
951 #sound-dai-cells = <0>;
952 st,syscfg = <&syscfg_core>;
953 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
954 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
955 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
956 assigned-clock-rates = <50000000>;
957 reg = <0x8d85000 0x158>;
958 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
959 dmas = <&fdma0 7 0 1>;
960 dma-names = "tx";
961
962 status = "disabled";
963 };
964
965 sti_uni_reader0: sti-uni-reader@8d83000 {
966 compatible = "st,stih407-uni-reader-pcm_in";
967 #sound-dai-cells = <0>;
968 st,syscfg = <&syscfg_core>;
969 reg = <0x8d83000 0x158>;
970 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
971 dmas = <&fdma0 5 0 1>;
972 dma-names = "rx";
973
974 status = "disabled";
975 };
976
977 sti_uni_reader1: sti-uni-reader@8d84000 {
978 compatible = "st,stih407-uni-reader-hdmi";
979 #sound-dai-cells = <0>;
980 st,syscfg = <&syscfg_core>;
981 reg = <0x8d84000 0x158>;
982 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
983 dmas = <&fdma0 6 0 1>;
984 dma-names = "rx";
985
986 status = "disabled";
987 };
988
989 delta0@0 {
990 compatible = "st,st-delta";
991 reg = <0 0>;
992 clock-names = "delta",
993 "delta-st231",
994 "delta-flash-promip";
995 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
996 <&clk_s_c0_flexgen CLK_ST231_DMU>,
997 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
998 };
999 };
1000};
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih407-pinctrl.dtsi"
10#include <dt-bindings/mfd/st-lpc.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/reset/stih407-resets.h>
13#include <dt-bindings/interrupt-controller/irq-st.h>
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 gp0_reserved: rproc@40000000 {
24 compatible = "shared-dma-pool";
25 reg = <0x40000000 0x01000000>;
26 no-map;
27 status = "disabled";
28 };
29
30 gp1_reserved: rproc@41000000 {
31 compatible = "shared-dma-pool";
32 reg = <0x41000000 0x01000000>;
33 no-map;
34 status = "disabled";
35 };
36
37 audio_reserved: rproc@42000000 {
38 compatible = "shared-dma-pool";
39 reg = <0x42000000 0x01000000>;
40 no-map;
41 status = "disabled";
42 };
43
44 dmu_reserved: rproc@43000000 {
45 compatible = "shared-dma-pool";
46 reg = <0x43000000 0x01000000>;
47 no-map;
48 };
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a9";
57 reg = <0>;
58
59 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
60 cpu-release-addr = <0x94100A4>;
61
62 /* kHz uV */
63 operating-points = <1500000 0
64 1200000 0
65 800000 0
66 500000 0>;
67
68 clocks = <&clk_m_a9>;
69 clock-names = "cpu";
70 clock-latency = <100000>;
71 cpu0-supply = <&pwm_regulator>;
72 st,syscfg = <&syscfg_core 0x8e0>;
73 };
74 cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a9";
77 reg = <1>;
78
79 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
80 cpu-release-addr = <0x94100A4>;
81
82 /* kHz uV */
83 operating-points = <1500000 0
84 1200000 0
85 800000 0
86 500000 0>;
87 };
88 };
89
90 intc: interrupt-controller@08761000 {
91 compatible = "arm,cortex-a9-gic";
92 #interrupt-cells = <3>;
93 interrupt-controller;
94 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
95 };
96
97 scu@08760000 {
98 compatible = "arm,cortex-a9-scu";
99 reg = <0x08760000 0x1000>;
100 };
101
102 timer@08760200 {
103 interrupt-parent = <&intc>;
104 compatible = "arm,cortex-a9-global-timer";
105 reg = <0x08760200 0x100>;
106 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&arm_periph_clk>;
108 };
109
110 l2: cache-controller {
111 compatible = "arm,pl310-cache";
112 reg = <0x08762000 0x1000>;
113 arm,data-latency = <3 3 3>;
114 arm,tag-latency = <2 2 2>;
115 cache-unified;
116 cache-level = <2>;
117 };
118
119 arm-pmu {
120 interrupt-parent = <&intc>;
121 compatible = "arm,cortex-a9-pmu";
122 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
123 };
124
125 pwm_regulator: pwm-regulator {
126 compatible = "pwm-regulator";
127 pwms = <&pwm1 3 8448>;
128 regulator-name = "CPU_1V0_AVS";
129 regulator-min-microvolt = <784000>;
130 regulator-max-microvolt = <1299000>;
131 regulator-always-on;
132 max-duty-cycle = <255>;
133 status = "okay";
134 };
135
136 soc {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 interrupt-parent = <&intc>;
140 ranges;
141 compatible = "simple-bus";
142
143 restart {
144 compatible = "st,stih407-restart";
145 st,syscfg = <&syscfg_sbc_reg>;
146 status = "okay";
147 };
148
149 powerdown: powerdown-controller {
150 compatible = "st,stih407-powerdown";
151 #reset-cells = <1>;
152 };
153
154 softreset: softreset-controller {
155 compatible = "st,stih407-softreset";
156 #reset-cells = <1>;
157 };
158
159 picophyreset: picophyreset-controller {
160 compatible = "st,stih407-picophyreset";
161 #reset-cells = <1>;
162 };
163
164 syscfg_sbc: sbc-syscfg@9620000 {
165 compatible = "st,stih407-sbc-syscfg", "syscon";
166 reg = <0x9620000 0x1000>;
167 };
168
169 syscfg_front: front-syscfg@9280000 {
170 compatible = "st,stih407-front-syscfg", "syscon";
171 reg = <0x9280000 0x1000>;
172 };
173
174 syscfg_rear: rear-syscfg@9290000 {
175 compatible = "st,stih407-rear-syscfg", "syscon";
176 reg = <0x9290000 0x1000>;
177 };
178
179 syscfg_flash: flash-syscfg@92a0000 {
180 compatible = "st,stih407-flash-syscfg", "syscon";
181 reg = <0x92a0000 0x1000>;
182 };
183
184 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
185 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
186 reg = <0x9600000 0x1000>;
187 };
188
189 syscfg_core: core-syscfg@92b0000 {
190 compatible = "st,stih407-core-syscfg", "syscon";
191 reg = <0x92b0000 0x1000>;
192 };
193
194 syscfg_lpm: lpm-syscfg@94b5100 {
195 compatible = "st,stih407-lpm-syscfg", "syscon";
196 reg = <0x94b5100 0x1000>;
197 };
198
199 irq-syscfg {
200 compatible = "st,stih407-irq-syscfg";
201 st,syscfg = <&syscfg_core>;
202 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
203 <ST_IRQ_SYSCFG_PMU_1>;
204 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
205 <ST_IRQ_SYSCFG_DISABLED>;
206 };
207
208 /* Display */
209 vtg_main: sti-vtg-main@8d02800 {
210 compatible = "st,vtg";
211 reg = <0x8d02800 0x200>;
212 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
213 };
214
215 vtg_aux: sti-vtg-aux@8d00200 {
216 compatible = "st,vtg";
217 reg = <0x8d00200 0x100>;
218 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
219 };
220
221 serial@9830000 {
222 compatible = "st,asc";
223 reg = <0x9830000 0x2c>;
224 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_serial0>;
227 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
228
229 status = "disabled";
230 };
231
232 serial@9831000 {
233 compatible = "st,asc";
234 reg = <0x9831000 0x2c>;
235 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_serial1>;
238 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
239
240 status = "disabled";
241 };
242
243 serial@9832000 {
244 compatible = "st,asc";
245 reg = <0x9832000 0x2c>;
246 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_serial2>;
249 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
250
251 status = "disabled";
252 };
253
254 /* SBC_ASC0 - UART10 */
255 sbc_serial0: serial@9530000 {
256 compatible = "st,asc";
257 reg = <0x9530000 0x2c>;
258 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_sbc_serial0>;
261 clocks = <&clk_sysin>;
262
263 status = "disabled";
264 };
265
266 serial@9531000 {
267 compatible = "st,asc";
268 reg = <0x9531000 0x2c>;
269 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_sbc_serial1>;
272 clocks = <&clk_sysin>;
273
274 status = "disabled";
275 };
276
277 i2c@9840000 {
278 compatible = "st,comms-ssc4-i2c";
279 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
280 reg = <0x9840000 0x110>;
281 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
282 clock-names = "ssc";
283 clock-frequency = <400000>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_i2c0_default>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288
289 status = "disabled";
290 };
291
292 i2c@9841000 {
293 compatible = "st,comms-ssc4-i2c";
294 reg = <0x9841000 0x110>;
295 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
297 clock-names = "ssc";
298 clock-frequency = <400000>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_i2c1_default>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303
304 status = "disabled";
305 };
306
307 i2c@9842000 {
308 compatible = "st,comms-ssc4-i2c";
309 reg = <0x9842000 0x110>;
310 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
312 clock-names = "ssc";
313 clock-frequency = <400000>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_i2c2_default>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318
319 status = "disabled";
320 };
321
322 i2c@9843000 {
323 compatible = "st,comms-ssc4-i2c";
324 reg = <0x9843000 0x110>;
325 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
327 clock-names = "ssc";
328 clock-frequency = <400000>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c3_default>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333
334 status = "disabled";
335 };
336
337 i2c@9844000 {
338 compatible = "st,comms-ssc4-i2c";
339 reg = <0x9844000 0x110>;
340 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
342 clock-names = "ssc";
343 clock-frequency = <400000>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_i2c4_default>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348
349 status = "disabled";
350 };
351
352 i2c@9845000 {
353 compatible = "st,comms-ssc4-i2c";
354 reg = <0x9845000 0x110>;
355 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
357 clock-names = "ssc";
358 clock-frequency = <400000>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_i2c5_default>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363
364 status = "disabled";
365 };
366
367
368 /* SSCs on SBC */
369 i2c@9540000 {
370 compatible = "st,comms-ssc4-i2c";
371 reg = <0x9540000 0x110>;
372 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&clk_sysin>;
374 clock-names = "ssc";
375 clock-frequency = <400000>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_i2c10_default>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380
381 status = "disabled";
382 };
383
384 i2c@9541000 {
385 compatible = "st,comms-ssc4-i2c";
386 reg = <0x9541000 0x110>;
387 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clk_sysin>;
389 clock-names = "ssc";
390 clock-frequency = <400000>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_i2c11_default>;
393 #address-cells = <1>;
394 #size-cells = <0>;
395
396 status = "disabled";
397 };
398
399 usb2_picophy0: phy1 {
400 compatible = "st,stih407-usb2-phy";
401 #phy-cells = <0>;
402 st,syscfg = <&syscfg_core 0x100 0xf4>;
403 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
404 <&picophyreset STIH407_PICOPHY2_RESET>;
405 reset-names = "global", "port";
406 };
407
408 miphy28lp_phy: miphy28lp@9b22000 {
409 compatible = "st,miphy28lp-phy";
410 st,syscfg = <&syscfg_core>;
411 #address-cells = <1>;
412 #size-cells = <1>;
413 ranges;
414
415 phy_port0: port@9b22000 {
416 reg = <0x9b22000 0xff>,
417 <0x9b09000 0xff>,
418 <0x9b04000 0xff>;
419 reg-names = "sata-up",
420 "pcie-up",
421 "pipew";
422
423 st,syscfg = <0x114 0x818 0xe0 0xec>;
424 #phy-cells = <1>;
425
426 reset-names = "miphy-sw-rst";
427 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
428 };
429
430 phy_port1: port@9b2a000 {
431 reg = <0x9b2a000 0xff>,
432 <0x9b19000 0xff>,
433 <0x9b14000 0xff>;
434 reg-names = "sata-up",
435 "pcie-up",
436 "pipew";
437
438 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
439
440 #phy-cells = <1>;
441
442 reset-names = "miphy-sw-rst";
443 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
444 };
445
446 phy_port2: port@8f95000 {
447 reg = <0x8f95000 0xff>,
448 <0x8f90000 0xff>;
449 reg-names = "pipew",
450 "usb3-up";
451
452 st,syscfg = <0x11c 0x820>;
453
454 #phy-cells = <1>;
455
456 reset-names = "miphy-sw-rst";
457 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
458 };
459 };
460
461 spi@9840000 {
462 compatible = "st,comms-ssc4-spi";
463 reg = <0x9840000 0x110>;
464 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
466 clock-names = "ssc";
467 pinctrl-0 = <&pinctrl_spi0_default>;
468 pinctrl-names = "default";
469 #address-cells = <1>;
470 #size-cells = <0>;
471
472 status = "disabled";
473 };
474
475 spi@9841000 {
476 compatible = "st,comms-ssc4-spi";
477 reg = <0x9841000 0x110>;
478 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
480 clock-names = "ssc";
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_spi1_default>;
483
484 status = "disabled";
485 };
486
487 spi@9842000 {
488 compatible = "st,comms-ssc4-spi";
489 reg = <0x9842000 0x110>;
490 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
492 clock-names = "ssc";
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_spi2_default>;
495
496 status = "disabled";
497 };
498
499 spi@9843000 {
500 compatible = "st,comms-ssc4-spi";
501 reg = <0x9843000 0x110>;
502 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
504 clock-names = "ssc";
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_spi3_default>;
507
508 status = "disabled";
509 };
510
511 spi@9844000 {
512 compatible = "st,comms-ssc4-spi";
513 reg = <0x9844000 0x110>;
514 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
516 clock-names = "ssc";
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_spi4_default>;
519
520 status = "disabled";
521 };
522
523 /* SBC SSC */
524 spi@9540000 {
525 compatible = "st,comms-ssc4-spi";
526 reg = <0x9540000 0x110>;
527 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&clk_sysin>;
529 clock-names = "ssc";
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_spi10_default>;
532
533 status = "disabled";
534 };
535
536 spi@9541000 {
537 compatible = "st,comms-ssc4-spi";
538 reg = <0x9541000 0x110>;
539 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clk_sysin>;
541 clock-names = "ssc";
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_spi11_default>;
544
545 status = "disabled";
546 };
547
548 spi@9542000 {
549 compatible = "st,comms-ssc4-spi";
550 reg = <0x9542000 0x110>;
551 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&clk_sysin>;
553 clock-names = "ssc";
554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_spi12_default>;
556
557 status = "disabled";
558 };
559
560 mmc0: sdhci@09060000 {
561 compatible = "st,sdhci-stih407", "st,sdhci";
562 status = "disabled";
563 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
564 reg-names = "mmc", "top-mmc-delay";
565 interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
566 interrupt-names = "mmcirq";
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_mmc0>;
569 clock-names = "mmc", "icn";
570 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
571 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
572 bus-width = <8>;
573 };
574
575 mmc1: sdhci@09080000 {
576 compatible = "st,sdhci-stih407", "st,sdhci";
577 status = "disabled";
578 reg = <0x09080000 0x7ff>;
579 reg-names = "mmc";
580 interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
581 interrupt-names = "mmcirq";
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_sd1>;
584 clock-names = "mmc", "icn";
585 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
586 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
587 resets = <&softreset STIH407_MMC1_SOFTRESET>;
588 bus-width = <4>;
589 };
590
591 /* Watchdog and Real-Time Clock */
592 lpc@8787000 {
593 compatible = "st,stih407-lpc";
594 reg = <0x8787000 0x1000>;
595 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
596 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
597 timeout-sec = <120>;
598 st,syscfg = <&syscfg_core>;
599 st,lpc-mode = <ST_LPC_MODE_WDT>;
600 };
601
602 lpc@8788000 {
603 compatible = "st,stih407-lpc";
604 reg = <0x8788000 0x1000>;
605 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
606 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
607 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
608 };
609
610 sata0: sata@9b20000 {
611 compatible = "st,ahci";
612 reg = <0x9b20000 0x1000>;
613
614 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
615 interrupt-names = "hostc";
616
617 phys = <&phy_port0 PHY_TYPE_SATA>;
618 phy-names = "ahci_phy";
619
620 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
621 <&softreset STIH407_SATA0_SOFTRESET>,
622 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
623 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
624
625 clock-names = "ahci_clk";
626 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
627
628 ports-implemented = <0x1>;
629
630 status = "disabled";
631 };
632
633 sata1: sata@9b28000 {
634 compatible = "st,ahci";
635 reg = <0x9b28000 0x1000>;
636
637 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
638 interrupt-names = "hostc";
639
640 phys = <&phy_port1 PHY_TYPE_SATA>;
641 phy-names = "ahci_phy";
642
643 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
644 <&softreset STIH407_SATA1_SOFTRESET>,
645 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
646 reset-names = "pwr-dwn",
647 "sw-rst",
648 "pwr-rst";
649
650 clock-names = "ahci_clk";
651 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
652
653 ports-implemented = <0x1>;
654
655 status = "disabled";
656 };
657
658
659 st_dwc3: dwc3@8f94000 {
660 compatible = "st,stih407-dwc3";
661 reg = <0x08f94000 0x1000>, <0x110 0x4>;
662 reg-names = "reg-glue", "syscfg-reg";
663 st,syscfg = <&syscfg_core>;
664 resets = <&powerdown STIH407_USB3_POWERDOWN>,
665 <&softreset STIH407_MIPHY2_SOFTRESET>;
666 reset-names = "powerdown", "softreset";
667 #address-cells = <1>;
668 #size-cells = <1>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&pinctrl_usb3>;
671 ranges;
672
673 status = "disabled";
674
675 dwc3: dwc3@9900000 {
676 compatible = "snps,dwc3";
677 reg = <0x09900000 0x100000>;
678 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
679 dr_mode = "host";
680 phy-names = "usb2-phy", "usb3-phy";
681 phys = <&usb2_picophy0>,
682 <&phy_port2 PHY_TYPE_USB3>;
683 snps,dis_u3_susphy_quirk;
684 };
685 };
686
687 /* COMMS PWM Module */
688 pwm0: pwm@9810000 {
689 compatible = "st,sti-pwm";
690 #pwm-cells = <2>;
691 reg = <0x9810000 0x68>;
692 interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
695 clock-names = "pwm";
696 clocks = <&clk_sysin>;
697 st,pwm-num-chan = <1>;
698
699 status = "disabled";
700 };
701
702 /* SBC PWM Module */
703 pwm1: pwm@9510000 {
704 compatible = "st,sti-pwm";
705 #pwm-cells = <2>;
706 reg = <0x9510000 0x68>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&pinctrl_pwm1_chan0_default
709 &pinctrl_pwm1_chan1_default
710 &pinctrl_pwm1_chan2_default
711 &pinctrl_pwm1_chan3_default>;
712 clock-names = "pwm";
713 clocks = <&clk_sysin>;
714 st,pwm-num-chan = <4>;
715
716 status = "disabled";
717 };
718
719 rng10: rng@08a89000 {
720 compatible = "st,rng";
721 reg = <0x08a89000 0x1000>;
722 clocks = <&clk_sysin>;
723 status = "okay";
724 };
725
726 rng11: rng@08a8a000 {
727 compatible = "st,rng";
728 reg = <0x08a8a000 0x1000>;
729 clocks = <&clk_sysin>;
730 status = "okay";
731 };
732
733 ethernet0: dwmac@9630000 {
734 device_type = "network";
735 status = "disabled";
736 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
737 reg = <0x9630000 0x8000>, <0x80 0x4>;
738 reg-names = "stmmaceth", "sti-ethconf";
739
740 st,syscon = <&syscfg_sbc_reg 0x80>;
741 st,gmac_en;
742 resets = <&softreset STIH407_ETH1_SOFTRESET>;
743 reset-names = "stmmaceth";
744
745 interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
746 <GIC_SPI 99 IRQ_TYPE_NONE>;
747 interrupt-names = "macirq", "eth_wake_irq";
748
749 /* DMA Bus Mode */
750 snps,pbl = <8>;
751
752 pinctrl-names = "default";
753 pinctrl-0 = <&pinctrl_rgmii1>;
754
755 clock-names = "stmmaceth", "sti-ethclk";
756 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
757 <&clk_s_c0_flexgen CLK_ETH_PHY>;
758 };
759
760 cec: sti-cec@094a087c {
761 compatible = "st,stih-cec";
762 reg = <0x94a087c 0x64>;
763 clocks = <&clk_sysin>;
764 clock-names = "cec-clk";
765 interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
766 interrupt-names = "cec-irq";
767 pinctrl-names = "default";
768 pinctrl-0 = <&pinctrl_cec0_default>;
769 resets = <&softreset STIH407_LPM_SOFTRESET>;
770 };
771
772 rng10: rng@08a89000 {
773 compatible = "st,rng";
774 reg = <0x08a89000 0x1000>;
775 clocks = <&clk_sysin>;
776 status = "okay";
777 };
778
779 rng11: rng@08a8a000 {
780 compatible = "st,rng";
781 reg = <0x08a8a000 0x1000>;
782 clocks = <&clk_sysin>;
783 status = "okay";
784 };
785
786 mailbox0: mailbox@8f00000 {
787 compatible = "st,stih407-mailbox";
788 reg = <0x8f00000 0x1000>;
789 interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
790 #mbox-cells = <2>;
791 mbox-name = "a9";
792 status = "okay";
793 };
794
795 mailbox1: mailbox@8f01000 {
796 compatible = "st,stih407-mailbox";
797 reg = <0x8f01000 0x1000>;
798 #mbox-cells = <2>;
799 mbox-name = "st231_gp_1";
800 status = "okay";
801 };
802
803 mailbox2: mailbox@8f02000 {
804 compatible = "st,stih407-mailbox";
805 reg = <0x8f02000 0x1000>;
806 #mbox-cells = <2>;
807 mbox-name = "st231_gp_0";
808 status = "okay";
809 };
810
811 mailbox3: mailbox@8f03000 {
812 compatible = "st,stih407-mailbox";
813 reg = <0x8f03000 0x1000>;
814 #mbox-cells = <2>;
815 mbox-name = "st231_audio_video";
816 status = "okay";
817 };
818
819 st231_gp0: remote-processor {
820 compatible = "st,st231-rproc";
821 memory-region = <&gp0_reserved>;
822 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
823 reset-names = "sw_reset";
824 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
825 clock-frequency = <600000000>;
826 st,syscfg = <&syscfg_core 0x22c>;
827 };
828
829
830 st231_gp1: remote-processor {
831 compatible = "st,st231-rproc";
832 memory-region = <&gp1_reserved>;
833 resets = <&softreset STIH407_ST231_GP1_SOFTRESET>;
834 reset-names = "sw_reset";
835 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_1>;
836 clock-frequency = <600000000>;
837 st,syscfg = <&syscfg_core 0x220>;
838 };
839
840 st231_audio: remote-processor {
841 compatible = "st,st231-rproc";
842 memory-region = <&audio_reserved>;
843 resets = <&softreset STIH407_ST231_AUD_SOFTRESET>;
844 reset-names = "sw_reset";
845 clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
846 clock-frequency = <600000000>;
847 st,syscfg = <&syscfg_core 0x228>;
848 };
849
850 st231_dmu: remote-processor {
851 compatible = "st,st231-rproc";
852 memory-region = <&dmu_reserved>;
853 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
854 reset-names = "sw_reset";
855 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
856 clock-frequency = <600000000>;
857 st,syscfg = <&syscfg_core 0x224>;
858 };
859
860 /* fdma audio */
861 fdma0: dma-controller@8e20000 {
862 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
863 reg = <0x8e20000 0x8000>,
864 <0x8e30000 0x3000>,
865 <0x8e37000 0x1000>,
866 <0x8e38000 0x8000>;
867 reg-names = "slimcore", "dmem", "peripherals", "imem";
868 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
869 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
870 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
871 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
872 interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
873 dma-channels = <16>;
874 #dma-cells = <3>;
875 };
876
877 /* fdma app */
878 fdma1: dma-controller@8e40000 {
879 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
880 reg = <0x8e40000 0x8000>,
881 <0x8e50000 0x3000>,
882 <0x8e57000 0x1000>,
883 <0x8e58000 0x8000>;
884 reg-names = "slimcore", "dmem", "peripherals", "imem";
885 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
886 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
887 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
888 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
889
890 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
891 dma-channels = <16>;
892 #dma-cells = <3>;
893 };
894
895 /* fdma free running */
896 fdma2: dma-controller@8e60000 {
897 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
898 reg = <0x8e60000 0x8000>,
899 <0x8e70000 0x3000>,
900 <0x8e77000 0x1000>,
901 <0x8e78000 0x8000>;
902 reg-names = "slimcore", "dmem", "peripherals", "imem";
903 interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
904 dma-channels = <16>;
905 #dma-cells = <3>;
906 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
907 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
908 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
909 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
910 };
911
912 sti_sasg_codec: sti-sasg-codec {
913 compatible = "st,stih407-sas-codec";
914 #sound-dai-cells = <1>;
915 status = "disabled";
916 st,syscfg = <&syscfg_core>;
917 };
918
919 sti_uni_player0: sti-uni-player@8d80000 {
920 compatible = "st,stih407-uni-player-hdmi";
921 #sound-dai-cells = <0>;
922 st,syscfg = <&syscfg_core>;
923 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
924 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
925 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
926 assigned-clock-rates = <50000000>;
927 reg = <0x8d80000 0x158>;
928 interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
929 dmas = <&fdma0 2 0 1>;
930 dma-names = "tx";
931
932 status = "disabled";
933 };
934
935 sti_uni_player1: sti-uni-player@8d81000 {
936 compatible = "st,stih407-uni-player-pcm-out";
937 #sound-dai-cells = <0>;
938 st,syscfg = <&syscfg_core>;
939 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
940 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
941 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
942 assigned-clock-rates = <50000000>;
943 reg = <0x8d81000 0x158>;
944 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
945 dmas = <&fdma0 3 0 1>;
946 dma-names = "tx";
947
948 status = "disabled";
949 };
950
951 sti_uni_player2: sti-uni-player@8d82000 {
952 compatible = "st,stih407-uni-player-dac";
953 #sound-dai-cells = <0>;
954 st,syscfg = <&syscfg_core>;
955 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
956 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
957 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
958 assigned-clock-rates = <50000000>;
959 reg = <0x8d82000 0x158>;
960 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
961 dmas = <&fdma0 4 0 1>;
962 dma-names = "tx";
963
964 status = "disabled";
965 };
966
967 sti_uni_player3: sti-uni-player@8d85000 {
968 compatible = "st,stih407-uni-player-spdif";
969 #sound-dai-cells = <0>;
970 st,syscfg = <&syscfg_core>;
971 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
972 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
973 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
974 assigned-clock-rates = <50000000>;
975 reg = <0x8d85000 0x158>;
976 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
977 dmas = <&fdma0 7 0 1>;
978 dma-names = "tx";
979
980 status = "disabled";
981 };
982
983 sti_uni_reader0: sti-uni-reader@8d83000 {
984 compatible = "st,stih407-uni-reader-pcm_in";
985 #sound-dai-cells = <0>;
986 st,syscfg = <&syscfg_core>;
987 reg = <0x8d83000 0x158>;
988 interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
989 dmas = <&fdma0 5 0 1>;
990 dma-names = "rx";
991
992 status = "disabled";
993 };
994
995 sti_uni_reader1: sti-uni-reader@8d84000 {
996 compatible = "st,stih407-uni-reader-hdmi";
997 #sound-dai-cells = <0>;
998 st,syscfg = <&syscfg_core>;
999 reg = <0x8d84000 0x158>;
1000 interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
1001 dmas = <&fdma0 6 0 1>;
1002 dma-names = "rx";
1003
1004 status = "disabled";
1005 };
1006 };
1007};