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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Linaro Ltd.
4 */
5
6#include "ste-nomadik-pinctrl.dtsi"
7
8/ {
9 soc {
10 pinctrl {
11 /* Settings for all UART default and sleep states */
12 uart0 {
13 uart0_default_mode: uart0_default {
14 default_mux {
15 function = "u0";
16 groups = "u0_a_1";
17 };
18 default_cfg1 {
19 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
20 ste,config = <&in_pu>;
21 };
22
23 default_cfg2 {
24 pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
25 ste,config = <&out_hi>;
26 };
27 };
28
29 uart0_sleep_mode: uart0_sleep {
30 sleep_cfg1 {
31 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
32 ste,config = <&slpm_in_wkup_pdis>;
33 };
34
35 sleep_cfg2 {
36 pins = "GPIO1_AJ3"; /* RTS */
37 ste,config = <&slpm_out_hi_wkup_pdis>;
38 };
39
40 sleep_cfg3 {
41 pins = "GPIO3_AH3"; /* TXD */
42 ste,config = <&slpm_out_wkup_pdis>;
43 };
44 };
45 };
46
47 uart1 {
48 uart1_default_mode: uart1_default {
49 default_mux {
50 function = "u1";
51 groups = "u1rxtx_a_1";
52 };
53 default_cfg1 {
54 pins = "GPIO4_AH6"; /* RXD */
55 ste,config = <&in_pu>;
56 };
57
58 default_cfg2 {
59 pins = "GPIO5_AG6"; /* TXD */
60 ste,config = <&out_hi>;
61 };
62 };
63
64 uart1_sleep_mode: uart1_sleep {
65 sleep_cfg1 {
66 pins = "GPIO4_AH6"; /* RXD */
67 ste,config = <&slpm_in_wkup_pdis>;
68 };
69
70 sleep_cfg2 {
71 pins = "GPIO5_AG6"; /* TXD */
72 ste,config = <&slpm_out_wkup_pdis>;
73 };
74 };
75 };
76
77 uart2 {
78 uart2_default_mode: uart2_default {
79 default_mux {
80 function = "u2";
81 groups = "u2rxtx_c_1";
82 };
83 default_cfg1 {
84 pins = "GPIO29_W2"; /* RXD */
85 ste,config = <&in_pu>;
86 };
87
88 default_cfg2 {
89 pins = "GPIO30_W3"; /* TXD */
90 ste,config = <&out_hi>;
91 };
92 };
93
94 uart2_sleep_mode: uart2_sleep {
95 sleep_cfg1 {
96 pins = "GPIO29_W2"; /* RXD */
97 ste,config = <&in_wkup_pdis>;
98 };
99
100 sleep_cfg2 {
101 pins = "GPIO30_W3"; /* TXD */
102 ste,config = <&out_wkup_pdis>;
103 };
104 };
105 };
106
107 /* Settings for all I2C default and sleep states */
108 i2c0 {
109 i2c0_default_mode: i2c_default {
110 default_mux {
111 function = "i2c0";
112 groups = "i2c0_a_1";
113 };
114 default_cfg1 {
115 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
116 ste,config = <&in_pu>;
117 };
118 };
119
120 i2c0_sleep_mode: i2c_sleep {
121 sleep_cfg1 {
122 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
123 ste,config = <&slpm_in_wkup_pdis>;
124 };
125 };
126 };
127
128 i2c1 {
129 i2c1_default_mode: i2c_default {
130 default_mux {
131 function = "i2c1";
132 groups = "i2c1_b_2";
133 };
134 default_cfg1 {
135 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
136 ste,config = <&in_pu>;
137 };
138 };
139
140 i2c1_sleep_mode: i2c_sleep {
141 sleep_cfg1 {
142 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
143 ste,config = <&slpm_in_wkup_pdis>;
144 };
145 };
146 };
147
148 i2c2 {
149 i2c2_default_mode: i2c_default {
150 default_mux {
151 function = "i2c2";
152 groups = "i2c2_b_2";
153 };
154 default_cfg1 {
155 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
156 ste,config = <&in_pu>;
157 };
158 };
159
160 i2c2_sleep_mode: i2c_sleep {
161 sleep_cfg1 {
162 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
163 ste,config = <&slpm_in_wkup_pdis>;
164 };
165 };
166 };
167
168 i2c3 {
169 i2c3_default_mode: i2c_default {
170 default_mux {
171 function = "i2c3";
172 groups = "i2c3_c_2";
173 };
174 default_cfg1 {
175 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
176 ste,config = <&in_pu>;
177 };
178 };
179
180 i2c3_sleep_mode: i2c_sleep {
181 sleep_cfg1 {
182 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
183 ste,config = <&slpm_in_wkup_pdis>;
184 };
185 };
186 };
187
188 /*
189 * Activating I2C4 will conflict with UART1 about the same pins so do not
190 * enable I2C4 and UART1 at the same time.
191 */
192 i2c4 {
193 i2c4_default_mode: i2c_default {
194 default_mux {
195 function = "i2c4";
196 groups = "i2c4_b_1";
197 };
198 default_cfg1 {
199 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
200 ste,config = <&in_pu>;
201 };
202 };
203
204 i2c4_sleep_mode: i2c_sleep {
205 sleep_cfg1 {
206 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
207 ste,config = <&slpm_in_wkup_pdis>;
208 };
209 };
210 };
211
212 /* Settings for all SPI default and sleep states */
213 spi2 {
214 spi2_default_mode: spi_default {
215 default_mux {
216 function = "spi2";
217 groups = "spi2_oc1_2";
218 };
219 default_cfg1 {
220 pins = "GPIO216_AG12"; /* FRM */
221 ste,config = <&gpio_out_hi>;
222 };
223 default_cfg2 {
224 pins = "GPIO218_AH11"; /* RXD */
225 ste,config = <&in_pd>;
226 };
227 default_cfg3 {
228 pins =
229 "GPIO215_AH13", /* TXD */
230 "GPIO217_AH12"; /* CLK */
231 ste,config = <&out_lo>;
232 };
233 };
234
235 spi2_idle_mode: spi_idle {
236 /*
237 * The idle mode is basically sleep mode sans wakeups. Also
238 * note that we have muxes the pins off the function here
239 * as we do not state any muxing.
240 */
241 idle_cfg1 {
242 pins = "GPIO218_AH11"; /* RXD */
243 ste,config = <&slpm_in_pdis>;
244 };
245 idle_cfg2 {
246 pins = "GPIO215_AH13"; /* TXD */
247 ste,config = <&slpm_out_lo_pdis>;
248 };
249 idle_cfg3 {
250 pins = "GPIO217_AH12"; /* CLK */
251 ste,config = <&slpm_pdis>;
252 };
253 };
254
255 spi2_sleep_mode: spi_sleep {
256 sleep_cfg1 {
257 pins =
258 "GPIO216_AG12", /* FRM */
259 "GPIO218_AH11"; /* RXD */
260 ste,config = <&slpm_in_wkup_pdis>;
261 };
262 sleep_cfg2 {
263 pins = "GPIO215_AH13"; /* TXD */
264 ste,config = <&slpm_out_lo_wkup_pdis>;
265 };
266 sleep_cfg3 {
267 pins = "GPIO217_AH12"; /* CLK */
268 ste,config = <&slpm_wkup_pdis>;
269 };
270 };
271 };
272
273 /* Settings for all MMC/SD/SDIO default and sleep states */
274 sdi0 {
275 /* This is the external SD card slot, 4 bits wide */
276 sdi0_default_mode: sdi0_default {
277 default_mux {
278 function = "mc0";
279 groups = "mc0_a_1";
280 };
281 default_cfg1 {
282 pins =
283 "GPIO18_AC2", /* CMDDIR */
284 "GPIO19_AC1", /* DAT0DIR */
285 "GPIO20_AB4"; /* DAT2DIR */
286 ste,config = <&out_hi>;
287 };
288 default_cfg2 {
289 pins = "GPIO22_AA3"; /* FBCLK */
290 ste,config = <&in_nopull>;
291 };
292 default_cfg3 {
293 pins = "GPIO23_AA4"; /* CLK */
294 ste,config = <&out_lo>;
295 };
296 default_cfg4 {
297 pins =
298 "GPIO24_AB2", /* CMD */
299 "GPIO25_Y4", /* DAT0 */
300 "GPIO26_Y2", /* DAT1 */
301 "GPIO27_AA2", /* DAT2 */
302 "GPIO28_AA1"; /* DAT3 */
303 ste,config = <&in_pu>;
304 };
305 };
306
307 sdi0_sleep_mode: sdi0_sleep {
308 sleep_cfg1 {
309 pins =
310 "GPIO18_AC2", /* CMDDIR */
311 "GPIO19_AC1", /* DAT0DIR */
312 "GPIO20_AB4"; /* DAT2DIR */
313 ste,config = <&slpm_out_hi_wkup_pdis>;
314 };
315 sleep_cfg2 {
316 pins =
317 "GPIO22_AA3", /* FBCLK */
318 "GPIO24_AB2", /* CMD */
319 "GPIO25_Y4", /* DAT0 */
320 "GPIO26_Y2", /* DAT1 */
321 "GPIO27_AA2", /* DAT2 */
322 "GPIO28_AA1"; /* DAT3 */
323 ste,config = <&slpm_in_wkup_pdis>;
324 };
325 sleep_cfg3 {
326 pins = "GPIO23_AA4"; /* CLK */
327 ste,config = <&slpm_out_lo_wkup_pdis>;
328 };
329 };
330 };
331
332 sdi1 {
333 /* This is the WLAN SDIO 4 bits wide */
334 sdi1_default_mode: sdi1_default {
335 default_mux {
336 function = "mc1";
337 groups = "mc1_a_1";
338 };
339 default_cfg1 {
340 pins = "GPIO208_AH16"; /* CLK */
341 ste,config = <&out_lo>;
342 };
343 default_cfg2 {
344 pins = "GPIO209_AG15"; /* FBCLK */
345 ste,config = <&in_nopull>;
346 };
347 default_cfg3 {
348 pins =
349 "GPIO210_AJ15", /* CMD */
350 "GPIO211_AG14", /* DAT0 */
351 "GPIO212_AF13", /* DAT1 */
352 "GPIO213_AG13", /* DAT2 */
353 "GPIO214_AH15"; /* DAT3 */
354 ste,config = <&in_pu>;
355 };
356 };
357
358 sdi1_sleep_mode: sdi1_sleep {
359 sleep_cfg1 {
360 pins = "GPIO208_AH16"; /* CLK */
361 ste,config = <&slpm_out_lo_wkup_pdis>;
362 };
363 sleep_cfg2 {
364 pins =
365 "GPIO209_AG15", /* FBCLK */
366 "GPIO210_AJ15", /* CMD */
367 "GPIO211_AG14", /* DAT0 */
368 "GPIO212_AF13", /* DAT1 */
369 "GPIO213_AG13", /* DAT2 */
370 "GPIO214_AH15"; /* DAT3 */
371 ste,config = <&slpm_in_wkup_pdis>;
372 };
373 };
374 };
375
376 sdi2 {
377 /* This is the eMMC 8 bits wide, usually PoP eMMC */
378 sdi2_default_mode: sdi2_default {
379 default_mux {
380 function = "mc2";
381 groups = "mc2_a_1";
382 };
383 default_cfg1 {
384 pins = "GPIO128_A5"; /* CLK */
385 ste,config = <&out_lo>;
386 };
387 default_cfg2 {
388 pins = "GPIO130_C8"; /* FBCLK */
389 ste,config = <&in_nopull>;
390 };
391 default_cfg3 {
392 pins =
393 "GPIO129_B4", /* CMD */
394 "GPIO131_A12", /* DAT0 */
395 "GPIO132_C10", /* DAT1 */
396 "GPIO133_B10", /* DAT2 */
397 "GPIO134_B9", /* DAT3 */
398 "GPIO135_A9", /* DAT4 */
399 "GPIO136_C7", /* DAT5 */
400 "GPIO137_A7", /* DAT6 */
401 "GPIO138_C5"; /* DAT7 */
402 ste,config = <&in_pu>;
403 };
404 };
405
406 sdi2_sleep_mode: sdi2_sleep {
407 sleep_cfg1 {
408 pins = "GPIO128_A5"; /* CLK */
409 ste,config = <&out_lo_wkup_pdis>;
410 };
411 sleep_cfg2 {
412 pins =
413 "GPIO130_C8", /* FBCLK */
414 "GPIO129_B4"; /* CMD */
415 ste,config = <&in_wkup_pdis_en>;
416 };
417 sleep_cfg3 {
418 pins =
419 "GPIO131_A12", /* DAT0 */
420 "GPIO132_C10", /* DAT1 */
421 "GPIO133_B10", /* DAT2 */
422 "GPIO134_B9", /* DAT3 */
423 "GPIO135_A9", /* DAT4 */
424 "GPIO136_C7", /* DAT5 */
425 "GPIO137_A7", /* DAT6 */
426 "GPIO138_C5"; /* DAT7 */
427 ste,config = <&in_wkup_pdis>;
428 };
429 };
430 };
431
432 sdi4 {
433 /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
434 sdi4_default_mode: sdi4_default {
435 default_mux {
436 function = "mc4";
437 groups = "mc4_a_1";
438 };
439 default_cfg1 {
440 pins = "GPIO203_AE23"; /* CLK */
441 ste,config = <&out_lo>;
442 };
443 default_cfg2 {
444 pins = "GPIO202_AF25"; /* FBCLK */
445 ste,config = <&in_nopull>;
446 };
447 default_cfg3 {
448 pins =
449 "GPIO201_AF24", /* CMD */
450 "GPIO200_AH26", /* DAT0 */
451 "GPIO199_AH23", /* DAT1 */
452 "GPIO198_AG25", /* DAT2 */
453 "GPIO197_AH24", /* DAT3 */
454 "GPIO207_AJ23", /* DAT4 */
455 "GPIO206_AG24", /* DAT5 */
456 "GPIO205_AG23", /* DAT6 */
457 "GPIO204_AF23"; /* DAT7 */
458 ste,config = <&in_pu>;
459 };
460 };
461
462 sdi4_sleep_mode: sdi4_sleep {
463 sleep_cfg1 {
464 pins = "GPIO203_AE23"; /* CLK */
465 ste,config = <&out_lo_wkup_pdis>;
466 };
467 sleep_cfg2 {
468 pins =
469 "GPIO202_AF25", /* FBCLK */
470 "GPIO201_AF24", /* CMD */
471 "GPIO200_AH26", /* DAT0 */
472 "GPIO199_AH23", /* DAT1 */
473 "GPIO198_AG25", /* DAT2 */
474 "GPIO197_AH24", /* DAT3 */
475 "GPIO207_AJ23", /* DAT4 */
476 "GPIO206_AG24", /* DAT5 */
477 "GPIO205_AG23", /* DAT6 */
478 "GPIO204_AF23"; /* DAT7 */
479 ste,config = <&slpm_in_wkup_pdis>;
480 };
481 };
482 };
483
484 /*
485 * Multi-rate serial ports (MSPs) - MSP3 output is internal and
486 * cannot be muxed onto any pins.
487 */
488 msp0 {
489 msp0_default_mode: msp0_default {
490 default_msp0_mux {
491 function = "msp0";
492 groups = "msp0txrx_a_1", "msp0tfstck_a_1";
493 };
494 default_msp0_cfg {
495 pins =
496 "GPIO12_AC4", /* TXD */
497 "GPIO15_AC3", /* RXD */
498 "GPIO13_AF3", /* TFS */
499 "GPIO14_AE3"; /* TCK */
500 ste,config = <&in_nopull>;
501 };
502 };
503 };
504
505 msp1 {
506 msp1_default_mode: msp1_default {
507 default_mux {
508 function = "msp1";
509 groups = "msp1txrx_a_1", "msp1_a_1";
510 };
511 default_cfg1 {
512 pins = "GPIO33_AF2";
513 ste,config = <&out_lo>;
514 };
515 default_cfg2 {
516 pins =
517 "GPIO34_AE1",
518 "GPIO35_AE2",
519 "GPIO36_AG2";
520 ste,config = <&in_nopull>;
521 };
522
523 };
524 };
525
526 msp2 {
527 msp2_default_mode: msp2_default {
528 /* MSP2 usually used for HDMI audio */
529 default_mux {
530 function = "msp2";
531 groups = "msp2_a_1";
532 };
533 default_cfg1 {
534 pins =
535 "GPIO193_AH27", /* TXD */
536 "GPIO194_AF27", /* TCK */
537 "GPIO195_AG28"; /* TFS */
538 ste,config = <&in_pd>;
539 };
540 default_cfg2 {
541 pins = "GPIO196_AG26"; /* RXD */
542 ste,config = <&out_lo>;
543 };
544 };
545 };
546
547
548 musb {
549 musb_default_mode: musb_default {
550 default_mux {
551 function = "usb";
552 groups = "usb_a_1";
553 };
554 default_cfg1 {
555 pins =
556 "GPIO256_AF28", /* NXT */
557 "GPIO258_AD29", /* XCLK */
558 "GPIO259_AC29", /* DIR */
559 "GPIO260_AD28", /* DAT7 */
560 "GPIO261_AD26", /* DAT6 */
561 "GPIO262_AE26", /* DAT5 */
562 "GPIO263_AG29", /* DAT4 */
563 "GPIO264_AE27", /* DAT3 */
564 "GPIO265_AD27", /* DAT2 */
565 "GPIO266_AC28", /* DAT1 */
566 "GPIO267_AC27"; /* DAT0 */
567 ste,config = <&in_nopull>;
568 };
569 default_cfg2 {
570 pins = "GPIO257_AE29"; /* STP */
571 ste,config = <&out_hi>;
572 };
573 };
574
575 musb_sleep_mode: musb_sleep {
576 sleep_cfg1 {
577 pins =
578 "GPIO256_AF28", /* NXT */
579 "GPIO258_AD29", /* XCLK */
580 "GPIO259_AC29"; /* DIR */
581 ste,config = <&slpm_wkup_pdis_en>;
582 };
583 sleep_cfg2 {
584 pins = "GPIO257_AE29"; /* STP */
585 ste,config = <&slpm_out_hi_wkup_pdis>;
586 };
587 sleep_cfg3 {
588 pins =
589 "GPIO260_AD28", /* DAT7 */
590 "GPIO261_AD26", /* DAT6 */
591 "GPIO262_AE26", /* DAT5 */
592 "GPIO263_AG29", /* DAT4 */
593 "GPIO264_AE27", /* DAT3 */
594 "GPIO265_AD27", /* DAT2 */
595 "GPIO266_AC28", /* DAT1 */
596 "GPIO267_AC27"; /* DAT0 */
597 ste,config = <&slpm_in_wkup_pdis_en>;
598 };
599 };
600 };
601
602 mcde {
603 lcd_default_mode: lcd_default {
604 default_mux1 {
605 /* Mux in VSI0 and all the data lines */
606 function = "lcd";
607 groups =
608 "lcdvsi0_a_1", /* VSI0 for LCD */
609 "lcd_d0_d7_a_1", /* Data lines */
610 "lcdvsi1_a_1"; /* VSI1 for HDMI */
611 };
612 default_mux2 {
613 function = "lcda";
614 groups =
615 "lcdaclk_b_1"; /* Clock line for TV-out */
616 };
617 default_cfg1 {
618 pins =
619 "GPIO68_E1", /* VSI0 */
620 "GPIO69_E2"; /* VSI1 */
621 ste,config = <&in_pu>;
622 };
623 };
624 lcd_sleep_mode: lcd_sleep {
625 sleep_cfg1 {
626 pins = "GPIO69_E2"; /* VSI1 */
627 ste,config = <&slpm_in_wkup_pdis>;
628 };
629 };
630 };
631
632 ske {
633 /* SKE keys on position 2 in an 8x8 matrix */
634 ske_kpa2_default_mode: ske_kpa2_default {
635 default_mux {
636 function = "kp";
637 groups = "kp_a_2";
638 };
639 default_cfg1 {
640 pins =
641 "GPIO153_B17", /* I7 */
642 "GPIO154_C16", /* I6 */
643 "GPIO155_C19", /* I5 */
644 "GPIO156_C17", /* I4 */
645 "GPIO161_D21", /* I3 */
646 "GPIO162_D20", /* I2 */
647 "GPIO163_C20", /* I1 */
648 "GPIO164_B21"; /* I0 */
649 ste,config = <&in_pd>;
650 };
651 default_cfg2 {
652 pins =
653 "GPIO157_A18", /* O7 */
654 "GPIO158_C18", /* O6 */
655 "GPIO159_B19", /* O5 */
656 "GPIO160_B20", /* O4 */
657 "GPIO165_C21", /* O3 */
658 "GPIO166_A22", /* O2 */
659 "GPIO167_B24", /* O1 */
660 "GPIO168_C22"; /* O0 */
661 ste,config = <&out_lo>;
662 };
663 };
664 ske_kpa2_sleep_mode: ske_kpa2_sleep {
665 sleep_cfg1 {
666 pins =
667 "GPIO153_B17", /* I7 */
668 "GPIO154_C16", /* I6 */
669 "GPIO155_C19", /* I5 */
670 "GPIO156_C17", /* I4 */
671 "GPIO161_D21", /* I3 */
672 "GPIO162_D20", /* I2 */
673 "GPIO163_C20", /* I1 */
674 "GPIO164_B21"; /* I0 */
675 ste,config = <&slpm_in_pu_wkup_pdis_en>;
676 };
677 sleep_cfg2 {
678 pins =
679 "GPIO157_A18", /* O7 */
680 "GPIO158_C18", /* O6 */
681 "GPIO159_B19", /* O5 */
682 "GPIO160_B20", /* O4 */
683 "GPIO165_C21", /* O3 */
684 "GPIO166_A22", /* O2 */
685 "GPIO167_B24", /* O1 */
686 "GPIO168_C22"; /* O0 */
687 ste,config = <&slpm_out_lo_pdis>;
688 };
689 };
690 /*
691 * SKE keys on position 1 and "other C1" combi giving
692 * six rows of six keys.
693 */
694 ske_kpaoc1_default_mode: ske_kpaoc1_default {
695 default_mux {
696 function = "kp";
697 groups = "kp_a_1", "kp_oc1_1";
698 };
699 default_cfg1 {
700 pins =
701 "GPIO91_B6", /* KP_O0 */
702 "GPIO90_A3", /* KP_O1 */
703 "GPIO87_B3", /* KP_O2 */
704 "GPIO86_C6", /* KP_O3 */
705 "GPIO96_D8", /* KP_O6 */
706 "GPIO94_D7"; /* KP_O7 */
707 ste,config = <&out_lo>;
708 };
709 default_cfg2 {
710 pins =
711 "GPIO93_B7", /* KP_I0 */
712 "GPIO92_D6", /* KP_I1 */
713 "GPIO89_E6", /* KP_I2 */
714 "GPIO88_C4", /* KP_I3 */
715 "GPIO97_D9", /* KP_I6 */
716 "GPIO95_E8"; /* KP_I7 */
717 ste,config = <&in_pu>;
718 };
719 };
720 };
721
722 wlan {
723 wlan_default_mode: wlan_default {
724 /*
725 * Activate this mode with the WLAN chip.
726 * These are plain GPIO pins used by WLAN
727 */
728 default_cfg1 {
729 pins =
730 "GPIO226_AF8", /* WLAN_PMU_EN */
731 "GPIO85_D5"; /* WLAN_ENA */
732 ste,config = <&gpio_out_lo>;
733 };
734 default_cfg2 {
735 pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
736 ste,config = <&gpio_in_pu>;
737 };
738 };
739 };
740 };
741 };
742};
1/*
2 * Copyright 2013 Linaro Ltd.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "ste-nomadik-pinctrl.dtsi"
13
14/ {
15 soc {
16 pinctrl {
17 /* Settings for all UART default and sleep states */
18 uart0 {
19 uart0_default_mode: uart0_default {
20 default_mux {
21 function = "u0";
22 groups = "u0_a_1";
23 };
24 default_cfg1 {
25 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
26 ste,config = <&in_pu>;
27 };
28
29 default_cfg2 {
30 pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
31 ste,config = <&out_hi>;
32 };
33 };
34
35 uart0_sleep_mode: uart0_sleep {
36 sleep_cfg1 {
37 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
38 ste,config = <&slpm_in_wkup_pdis>;
39 };
40
41 sleep_cfg2 {
42 pins = "GPIO1_AJ3"; /* RTS */
43 ste,config = <&slpm_out_hi_wkup_pdis>;
44 };
45
46 sleep_cfg3 {
47 pins = "GPIO3_AH3"; /* TXD */
48 ste,config = <&slpm_out_wkup_pdis>;
49 };
50 };
51 };
52
53 uart1 {
54 uart1_default_mode: uart1_default {
55 default_mux {
56 function = "u1";
57 groups = "u1rxtx_a_1";
58 };
59 default_cfg1 {
60 pins = "GPIO4_AH6"; /* RXD */
61 ste,config = <&in_pu>;
62 };
63
64 default_cfg2 {
65 pins = "GPIO5_AG6"; /* TXD */
66 ste,config = <&out_hi>;
67 };
68 };
69
70 uart1_sleep_mode: uart1_sleep {
71 sleep_cfg1 {
72 pins = "GPIO4_AH6"; /* RXD */
73 ste,config = <&slpm_in_wkup_pdis>;
74 };
75
76 sleep_cfg2 {
77 pins = "GPIO5_AG6"; /* TXD */
78 ste,config = <&slpm_out_wkup_pdis>;
79 };
80 };
81 };
82
83 uart2 {
84 uart2_default_mode: uart2_default {
85 default_mux {
86 function = "u2";
87 groups = "u2rxtx_c_1";
88 };
89 default_cfg1 {
90 pins = "GPIO29_W2"; /* RXD */
91 ste,config = <&in_pu>;
92 };
93
94 default_cfg2 {
95 pins = "GPIO30_W3"; /* TXD */
96 ste,config = <&out_hi>;
97 };
98 };
99
100 uart2_sleep_mode: uart2_sleep {
101 sleep_cfg1 {
102 pins = "GPIO29_W2"; /* RXD */
103 ste,config = <&in_wkup_pdis>;
104 };
105
106 sleep_cfg2 {
107 pins = "GPIO30_W3"; /* TXD */
108 ste,config = <&out_wkup_pdis>;
109 };
110 };
111 };
112
113 /* Settings for all I2C default and sleep states */
114 i2c0 {
115 i2c0_default_mode: i2c_default {
116 default_mux {
117 function = "i2c0";
118 groups = "i2c0_a_1";
119 };
120 default_cfg1 {
121 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
122 ste,config = <&in_pu>;
123 };
124 };
125
126 i2c0_sleep_mode: i2c_sleep {
127 sleep_cfg1 {
128 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
129 ste,config = <&slpm_in_wkup_pdis>;
130 };
131 };
132 };
133
134 i2c1 {
135 i2c1_default_mode: i2c_default {
136 default_mux {
137 function = "i2c1";
138 groups = "i2c1_b_2";
139 };
140 default_cfg1 {
141 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
142 ste,config = <&in_pu>;
143 };
144 };
145
146 i2c1_sleep_mode: i2c_sleep {
147 sleep_cfg1 {
148 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
149 ste,config = <&slpm_in_wkup_pdis>;
150 };
151 };
152 };
153
154 i2c2 {
155 i2c2_default_mode: i2c_default {
156 default_mux {
157 function = "i2c2";
158 groups = "i2c2_b_2";
159 };
160 default_cfg1 {
161 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
162 ste,config = <&in_pu>;
163 };
164 };
165
166 i2c2_sleep_mode: i2c_sleep {
167 sleep_cfg1 {
168 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
169 ste,config = <&slpm_in_wkup_pdis>;
170 };
171 };
172 };
173
174 i2c3 {
175 i2c3_default_mode: i2c_default {
176 default_mux {
177 function = "i2c3";
178 groups = "i2c3_c_2";
179 };
180 default_cfg1 {
181 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
182 ste,config = <&in_pu>;
183 };
184 };
185
186 i2c3_sleep_mode: i2c_sleep {
187 sleep_cfg1 {
188 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
189 ste,config = <&slpm_in_wkup_pdis>;
190 };
191 };
192 };
193
194 /*
195 * Activating I2C4 will conflict with UART1 about the same pins so do not
196 * enable I2C4 and UART1 at the same time.
197 */
198 i2c4 {
199 i2c4_default_mode: i2c_default {
200 default_mux {
201 function = "i2c4";
202 groups = "i2c4_b_1";
203 };
204 default_cfg1 {
205 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
206 ste,config = <&in_pu>;
207 };
208 };
209
210 i2c4_sleep_mode: i2c_sleep {
211 sleep_cfg1 {
212 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
213 ste,config = <&slpm_in_wkup_pdis>;
214 };
215 };
216 };
217
218 /* Settings for all SPI default and sleep states */
219 spi2 {
220 spi2_default_mode: spi_default {
221 default_mux {
222 function = "spi2";
223 groups = "spi2_oc1_2";
224 };
225 default_cfg1 {
226 pins = "GPIO216_AG12"; /* FRM */
227 ste,config = <&gpio_out_hi>;
228 };
229 default_cfg2 {
230 pins = "GPIO218_AH11"; /* RXD */
231 ste,config = <&in_pd>;
232 };
233 default_cfg3 {
234 pins =
235 "GPIO215_AH13", /* TXD */
236 "GPIO217_AH12"; /* CLK */
237 ste,config = <&out_lo>;
238 };
239 };
240
241 spi2_idle_mode: spi_idle {
242 /*
243 * The idle mode is basically sleep mode sans wakeups. Also
244 * note that we have muxes the pins off the function here
245 * as we do not state any muxing.
246 */
247 idle_cfg1 {
248 pins = "GPIO218_AH11"; /* RXD */
249 ste,config = <&slpm_in_pdis>;
250 };
251 idle_cfg2 {
252 pins = "GPIO215_AH13"; /* TXD */
253 ste,config = <&slpm_out_lo_pdis>;
254 };
255 idle_cfg3 {
256 pins = "GPIO217_AH12"; /* CLK */
257 ste,config = <&slpm_pdis>;
258 };
259 };
260
261 spi2_sleep_mode: spi_sleep {
262 sleep_cfg1 {
263 pins =
264 "GPIO216_AG12", /* FRM */
265 "GPIO218_AH11"; /* RXD */
266 ste,config = <&slpm_in_wkup_pdis>;
267 };
268 sleep_cfg2 {
269 pins = "GPIO215_AH13"; /* TXD */
270 ste,config = <&slpm_out_lo_wkup_pdis>;
271 };
272 sleep_cfg3 {
273 pins = "GPIO217_AH12"; /* CLK */
274 ste,config = <&slpm_wkup_pdis>;
275 };
276 };
277 };
278
279 /* Settings for all MMC/SD/SDIO default and sleep states */
280 sdi0 {
281 /* This is the external SD card slot, 4 bits wide */
282 sdi0_default_mode: sdi0_default {
283 default_mux {
284 function = "mc0";
285 groups = "mc0_a_1";
286 };
287 default_cfg1 {
288 pins =
289 "GPIO18_AC2", /* CMDDIR */
290 "GPIO19_AC1", /* DAT0DIR */
291 "GPIO20_AB4"; /* DAT2DIR */
292 ste,config = <&out_hi>;
293 };
294 default_cfg2 {
295 pins = "GPIO22_AA3"; /* FBCLK */
296 ste,config = <&in_nopull>;
297 };
298 default_cfg3 {
299 pins = "GPIO23_AA4"; /* CLK */
300 ste,config = <&out_lo>;
301 };
302 default_cfg4 {
303 pins =
304 "GPIO24_AB2", /* CMD */
305 "GPIO25_Y4", /* DAT0 */
306 "GPIO26_Y2", /* DAT1 */
307 "GPIO27_AA2", /* DAT2 */
308 "GPIO28_AA1"; /* DAT3 */
309 ste,config = <&in_pu>;
310 };
311 };
312
313 sdi0_sleep_mode: sdi0_sleep {
314 sleep_cfg1 {
315 pins =
316 "GPIO18_AC2", /* CMDDIR */
317 "GPIO19_AC1", /* DAT0DIR */
318 "GPIO20_AB4"; /* DAT2DIR */
319 ste,config = <&slpm_out_hi_wkup_pdis>;
320 };
321 sleep_cfg2 {
322 pins =
323 "GPIO22_AA3", /* FBCLK */
324 "GPIO24_AB2", /* CMD */
325 "GPIO25_Y4", /* DAT0 */
326 "GPIO26_Y2", /* DAT1 */
327 "GPIO27_AA2", /* DAT2 */
328 "GPIO28_AA1"; /* DAT3 */
329 ste,config = <&slpm_in_wkup_pdis>;
330 };
331 sleep_cfg3 {
332 pins = "GPIO23_AA4"; /* CLK */
333 ste,config = <&slpm_out_lo_wkup_pdis>;
334 };
335 };
336 };
337
338 sdi1 {
339 /* This is the WLAN SDIO 4 bits wide */
340 sdi1_default_mode: sdi1_default {
341 default_mux {
342 function = "mc1";
343 groups = "mc1_a_1";
344 };
345 default_cfg1 {
346 pins = "GPIO208_AH16"; /* CLK */
347 ste,config = <&out_lo>;
348 };
349 default_cfg2 {
350 pins = "GPIO209_AG15"; /* FBCLK */
351 ste,config = <&in_nopull>;
352 };
353 default_cfg3 {
354 pins =
355 "GPIO210_AJ15", /* CMD */
356 "GPIO211_AG14", /* DAT0 */
357 "GPIO212_AF13", /* DAT1 */
358 "GPIO213_AG13", /* DAT2 */
359 "GPIO214_AH15"; /* DAT3 */
360 ste,config = <&in_pu>;
361 };
362 };
363
364 sdi1_sleep_mode: sdi1_sleep {
365 sleep_cfg1 {
366 pins = "GPIO208_AH16"; /* CLK */
367 ste,config = <&slpm_out_lo_wkup_pdis>;
368 };
369 sleep_cfg2 {
370 pins =
371 "GPIO209_AG15", /* FBCLK */
372 "GPIO210_AJ15", /* CMD */
373 "GPIO211_AG14", /* DAT0 */
374 "GPIO212_AF13", /* DAT1 */
375 "GPIO213_AG13", /* DAT2 */
376 "GPIO214_AH15"; /* DAT3 */
377 ste,config = <&slpm_in_wkup_pdis>;
378 };
379 };
380 };
381
382 sdi2 {
383 /* This is the eMMC 8 bits wide, usually PoP eMMC */
384 sdi2_default_mode: sdi2_default {
385 default_mux {
386 function = "mc2";
387 groups = "mc2_a_1";
388 };
389 default_cfg1 {
390 pins = "GPIO128_A5"; /* CLK */
391 ste,config = <&out_lo>;
392 };
393 default_cfg2 {
394 pins = "GPIO130_C8"; /* FBCLK */
395 ste,config = <&in_nopull>;
396 };
397 default_cfg3 {
398 pins =
399 "GPIO129_B4", /* CMD */
400 "GPIO131_A12", /* DAT0 */
401 "GPIO132_C10", /* DAT1 */
402 "GPIO133_B10", /* DAT2 */
403 "GPIO134_B9", /* DAT3 */
404 "GPIO135_A9", /* DAT4 */
405 "GPIO136_C7", /* DAT5 */
406 "GPIO137_A7", /* DAT6 */
407 "GPIO138_C5"; /* DAT7 */
408 ste,config = <&in_pu>;
409 };
410 };
411
412 sdi2_sleep_mode: sdi2_sleep {
413 sleep_cfg1 {
414 pins = "GPIO128_A5"; /* CLK */
415 ste,config = <&out_lo_wkup_pdis>;
416 };
417 sleep_cfg2 {
418 pins =
419 "GPIO130_C8", /* FBCLK */
420 "GPIO129_B4"; /* CMD */
421 ste,config = <&in_wkup_pdis_en>;
422 };
423 sleep_cfg3 {
424 pins =
425 "GPIO131_A12", /* DAT0 */
426 "GPIO132_C10", /* DAT1 */
427 "GPIO133_B10", /* DAT2 */
428 "GPIO134_B9", /* DAT3 */
429 "GPIO135_A9", /* DAT4 */
430 "GPIO136_C7", /* DAT5 */
431 "GPIO137_A7", /* DAT6 */
432 "GPIO138_C5"; /* DAT7 */
433 ste,config = <&in_wkup_pdis>;
434 };
435 };
436 };
437
438 sdi4 {
439 /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
440 sdi4_default_mode: sdi4_default {
441 default_mux {
442 function = "mc4";
443 groups = "mc4_a_1";
444 };
445 default_cfg1 {
446 pins = "GPIO203_AE23"; /* CLK */
447 ste,config = <&out_lo>;
448 };
449 default_cfg2 {
450 pins = "GPIO202_AF25"; /* FBCLK */
451 ste,config = <&in_nopull>;
452 };
453 default_cfg3 {
454 pins =
455 "GPIO201_AF24", /* CMD */
456 "GPIO200_AH26", /* DAT0 */
457 "GPIO199_AH23", /* DAT1 */
458 "GPIO198_AG25", /* DAT2 */
459 "GPIO197_AH24", /* DAT3 */
460 "GPIO207_AJ23", /* DAT4 */
461 "GPIO206_AG24", /* DAT5 */
462 "GPIO205_AG23", /* DAT6 */
463 "GPIO204_AF23"; /* DAT7 */
464 ste,config = <&in_pu>;
465 };
466 };
467
468 sdi4_sleep_mode: sdi4_sleep {
469 sleep_cfg1 {
470 pins = "GPIO203_AE23"; /* CLK */
471 ste,config = <&out_lo_wkup_pdis>;
472 };
473 sleep_cfg2 {
474 pins =
475 "GPIO202_AF25", /* FBCLK */
476 "GPIO201_AF24", /* CMD */
477 "GPIO200_AH26", /* DAT0 */
478 "GPIO199_AH23", /* DAT1 */
479 "GPIO198_AG25", /* DAT2 */
480 "GPIO197_AH24", /* DAT3 */
481 "GPIO207_AJ23", /* DAT4 */
482 "GPIO206_AG24", /* DAT5 */
483 "GPIO205_AG23", /* DAT6 */
484 "GPIO204_AF23"; /* DAT7 */
485 ste,config = <&slpm_in_wkup_pdis>;
486 };
487 };
488 };
489
490 /*
491 * Multi-rate serial ports (MSPs) - MSP3 output is internal and
492 * cannot be muxed onto any pins.
493 */
494 msp0 {
495 msp0_default_mode: msp0_default {
496 default_msp0_mux {
497 function = "msp0";
498 groups = "msp0txrx_a_1", "msp0tfstck_a_1";
499 };
500 default_msp0_cfg {
501 pins =
502 "GPIO12_AC4", /* TXD */
503 "GPIO15_AC3", /* RXD */
504 "GPIO13_AF3", /* TFS */
505 "GPIO14_AE3"; /* TCK */
506 ste,config = <&in_nopull>;
507 };
508 };
509 };
510
511 msp1 {
512 msp1_default_mode: msp1_default {
513 default_mux {
514 function = "msp1";
515 groups = "msp1txrx_a_1", "msp1_a_1";
516 };
517 default_cfg1 {
518 pins = "GPIO33_AF2";
519 ste,config = <&out_lo>;
520 };
521 default_cfg2 {
522 pins =
523 "GPIO34_AE1",
524 "GPIO35_AE2",
525 "GPIO36_AG2";
526 ste,config = <&in_nopull>;
527 };
528
529 };
530 };
531
532 msp2 {
533 msp2_default_mode: msp2_default {
534 /* MSP2 usually used for HDMI audio */
535 default_mux {
536 function = "msp2";
537 groups = "msp2_a_1";
538 };
539 default_cfg1 {
540 pins =
541 "GPIO193_AH27", /* TXD */
542 "GPIO194_AF27", /* TCK */
543 "GPIO195_AG28"; /* TFS */
544 ste,config = <&in_pd>;
545 };
546 default_cfg2 {
547 pins = "GPIO196_AG26"; /* RXD */
548 ste,config = <&out_lo>;
549 };
550 };
551 };
552
553
554 musb {
555 musb_default_mode: musb_default {
556 default_mux {
557 function = "usb";
558 groups = "usb_a_1";
559 };
560 default_cfg1 {
561 pins =
562 "GPIO256_AF28", /* NXT */
563 "GPIO258_AD29", /* XCLK */
564 "GPIO259_AC29", /* DIR */
565 "GPIO260_AD28", /* DAT7 */
566 "GPIO261_AD26", /* DAT6 */
567 "GPIO262_AE26", /* DAT5 */
568 "GPIO263_AG29", /* DAT4 */
569 "GPIO264_AE27", /* DAT3 */
570 "GPIO265_AD27", /* DAT2 */
571 "GPIO266_AC28", /* DAT1 */
572 "GPIO267_AC27"; /* DAT0 */
573 ste,config = <&in_nopull>;
574 };
575 default_cfg2 {
576 pins = "GPIO257_AE29"; /* STP */
577 ste,config = <&out_hi>;
578 };
579 };
580
581 musb_sleep_mode: musb_sleep {
582 sleep_cfg1 {
583 pins =
584 "GPIO256_AF28", /* NXT */
585 "GPIO258_AD29", /* XCLK */
586 "GPIO259_AC29"; /* DIR */
587 ste,config = <&slpm_wkup_pdis_en>;
588 };
589 sleep_cfg2 {
590 pins = "GPIO257_AE29"; /* STP */
591 ste,config = <&slpm_out_hi_wkup_pdis>;
592 };
593 sleep_cfg3 {
594 pins =
595 "GPIO260_AD28", /* DAT7 */
596 "GPIO261_AD26", /* DAT6 */
597 "GPIO262_AE26", /* DAT5 */
598 "GPIO263_AG29", /* DAT4 */
599 "GPIO264_AE27", /* DAT3 */
600 "GPIO265_AD27", /* DAT2 */
601 "GPIO266_AC28", /* DAT1 */
602 "GPIO267_AC27"; /* DAT0 */
603 ste,config = <&slpm_in_wkup_pdis_en>;
604 };
605 };
606 };
607
608 mcde {
609 lcd_default_mode: lcd_default {
610 default_mux {
611 /* Mux in VSI0 and all the data lines */
612 function = "lcd";
613 groups =
614 "lcdvsi0_a_1", /* VSI0 for LCD */
615 "lcd_d0_d7_a_1", /* Data lines */
616 "lcd_d8_d11_a_1", /* TV-out */
617 "lcdaclk_b_1", /* Clock line for TV-out */
618 "lcdvsi1_a_1"; /* VSI1 for HDMI */
619 };
620 default_cfg1 {
621 pins =
622 "GPIO68_E1", /* VSI0 */
623 "GPIO69_E2"; /* VSI1 */
624 ste,config = <&in_pu>;
625 };
626 };
627 lcd_sleep_mode: lcd_sleep {
628 sleep_cfg1 {
629 pins = "GPIO69_E2"; /* VSI1 */
630 ste,config = <&slpm_in_wkup_pdis>;
631 };
632 };
633 };
634
635 ske {
636 /* SKE keys on position 2 in an 8x8 matrix */
637 ske_kpa2_default_mode: ske_kpa2_default {
638 default_mux {
639 function = "kp";
640 groups = "kp_a_2";
641 };
642 default_cfg1 {
643 pins =
644 "GPIO153_B17", /* I7 */
645 "GPIO154_C16", /* I6 */
646 "GPIO155_C19", /* I5 */
647 "GPIO156_C17", /* I4 */
648 "GPIO161_D21", /* I3 */
649 "GPIO162_D20", /* I2 */
650 "GPIO163_C20", /* I1 */
651 "GPIO164_B21"; /* I0 */
652 ste,config = <&in_pd>;
653 };
654 default_cfg2 {
655 pins =
656 "GPIO157_A18", /* O7 */
657 "GPIO158_C18", /* O6 */
658 "GPIO159_B19", /* O5 */
659 "GPIO160_B20", /* O4 */
660 "GPIO165_C21", /* O3 */
661 "GPIO166_A22", /* O2 */
662 "GPIO167_B24", /* O1 */
663 "GPIO168_C22"; /* O0 */
664 ste,config = <&out_lo>;
665 };
666 };
667 ske_kpa2_sleep_mode: ske_kpa2_sleep {
668 sleep_cfg1 {
669 pins =
670 "GPIO153_B17", /* I7 */
671 "GPIO154_C16", /* I6 */
672 "GPIO155_C19", /* I5 */
673 "GPIO156_C17", /* I4 */
674 "GPIO161_D21", /* I3 */
675 "GPIO162_D20", /* I2 */
676 "GPIO163_C20", /* I1 */
677 "GPIO164_B21"; /* I0 */
678 ste,config = <&slpm_in_pu_wkup_pdis_en>;
679 };
680 sleep_cfg2 {
681 pins =
682 "GPIO157_A18", /* O7 */
683 "GPIO158_C18", /* O6 */
684 "GPIO159_B19", /* O5 */
685 "GPIO160_B20", /* O4 */
686 "GPIO165_C21", /* O3 */
687 "GPIO166_A22", /* O2 */
688 "GPIO167_B24", /* O1 */
689 "GPIO168_C22"; /* O0 */
690 ste,config = <&slpm_out_lo_pdis>;
691 };
692 };
693 /*
694 * SKE keys on position 1 and "other C1" combi giving
695 * six rows of six keys.
696 */
697 ske_kpaoc1_default_mode: ske_kpaoc1_default {
698 default_mux {
699 function = "kp";
700 groups = "kp_a_1", "kp_oc1_1";
701 };
702 default_cfg1 {
703 pins =
704 "GPIO91_B6", /* KP_O0 */
705 "GPIO90_A3", /* KP_O1 */
706 "GPIO87_B3", /* KP_O2 */
707 "GPIO86_C6", /* KP_O3 */
708 "GPIO96_D8", /* KP_O6 */
709 "GPIO94_D7"; /* KP_O7 */
710 ste,config = <&out_lo>;
711 };
712 default_cfg2 {
713 pins =
714 "GPIO93_B7", /* KP_I0 */
715 "GPIO92_D6", /* KP_I1 */
716 "GPIO89_E6", /* KP_I2 */
717 "GPIO88_C4", /* KP_I3 */
718 "GPIO97_D9", /* KP_I6 */
719 "GPIO95_E8"; /* KP_I7 */
720 ste,config = <&in_pu>;
721 };
722 };
723 };
724
725 wlan {
726 wlan_default_mode: wlan_default {
727 /*
728 * Activate this mode with the WLAN chip.
729 * These are plain GPIO pins used by WLAN
730 */
731 default_cfg1 {
732 pins =
733 "GPIO226_AF8", /* WLAN_PMU_EN */
734 "GPIO85_D5"; /* WLAN_ENA */
735 ste,config = <&gpio_out_lo>;
736 };
737 default_cfg2 {
738 pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
739 ste,config = <&gpio_in_pu>;
740 };
741 };
742 };
743 };
744 };
745};