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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */
7
8#include <dt-bindings/clock/sh73a0-clock.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13 compatible = "renesas,sh73a0";
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a9";
25 reg = <0>;
26 clock-frequency = <1196000000>;
27 clocks = <&cpg_clocks SH73A0_CLK_Z>;
28 power-domains = <&pd_a2sl>;
29 next-level-cache = <&L2>;
30 };
31 cpu1: cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 reg = <1>;
35 clock-frequency = <1196000000>;
36 clocks = <&cpg_clocks SH73A0_CLK_Z>;
37 power-domains = <&pd_a2sl>;
38 next-level-cache = <&L2>;
39 };
40 };
41
42 timer@f0000600 {
43 compatible = "arm,cortex-a9-twd-timer";
44 reg = <0xf0000600 0x20>;
45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
46 clocks = <&twd_clk>;
47 };
48
49 gic: interrupt-controller@f0001000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
53 reg = <0xf0001000 0x1000>,
54 <0xf0000100 0x100>;
55 };
56
57 L2: cache-controller@f0100000 {
58 compatible = "arm,pl310-cache";
59 reg = <0xf0100000 0x1000>;
60 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
61 power-domains = <&pd_a3sm>;
62 arm,data-latency = <3 3 3>;
63 arm,tag-latency = <2 2 2>;
64 arm,shared-override;
65 cache-unified;
66 cache-level = <2>;
67 };
68
69 sbsc2: memory-controller@fb400000 {
70 compatible = "renesas,sbsc-sh73a0";
71 reg = <0xfb400000 0x400>;
72 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-names = "sec", "temp";
75 power-domains = <&pd_a4bc1>;
76 };
77
78 sbsc1: memory-controller@fe400000 {
79 compatible = "renesas,sbsc-sh73a0";
80 reg = <0xfe400000 0x400>;
81 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-names = "sec", "temp";
84 power-domains = <&pd_a4bc0>;
85 };
86
87 pmu {
88 compatible = "arm,cortex-a9-pmu";
89 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
91 interrupt-affinity = <&cpu0>, <&cpu1>;
92 };
93
94 cmt1: timer@e6138000 {
95 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
96 reg = <0xe6138000 0x200>;
97 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
99 clock-names = "fck";
100 power-domains = <&pd_c5>;
101 status = "disabled";
102 };
103
104 irqpin0: interrupt-controller@e6900000 {
105 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
106 #interrupt-cells = <2>;
107 interrupt-controller;
108 reg = <0xe6900000 4>,
109 <0xe6900010 4>,
110 <0xe6900020 1>,
111 <0xe6900040 1>,
112 <0xe6900060 1>;
113 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
114 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
115 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
116 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
117 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
118 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
122 power-domains = <&pd_a4s>;
123 control-parent;
124 };
125
126 irqpin1: interrupt-controller@e6900004 {
127 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
128 #interrupt-cells = <2>;
129 interrupt-controller;
130 reg = <0xe6900004 4>,
131 <0xe6900014 4>,
132 <0xe6900024 1>,
133 <0xe6900044 1>,
134 <0xe6900064 1>;
135 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
136 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
137 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
138 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
139 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
144 power-domains = <&pd_a4s>;
145 control-parent;
146 };
147
148 irqpin2: interrupt-controller@e6900008 {
149 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
150 #interrupt-cells = <2>;
151 interrupt-controller;
152 reg = <0xe6900008 4>,
153 <0xe6900018 4>,
154 <0xe6900028 1>,
155 <0xe6900048 1>,
156 <0xe6900068 1>;
157 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
158 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
159 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
160 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
161 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
162 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
163 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
164 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
166 power-domains = <&pd_a4s>;
167 control-parent;
168 };
169
170 irqpin3: interrupt-controller@e690000c {
171 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
172 #interrupt-cells = <2>;
173 interrupt-controller;
174 reg = <0xe690000c 4>,
175 <0xe690001c 4>,
176 <0xe690002c 1>,
177 <0xe690004c 1>,
178 <0xe690006c 1>;
179 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
180 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
181 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
182 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
183 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
184 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
185 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
186 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
188 power-domains = <&pd_a4s>;
189 control-parent;
190 };
191
192 i2c0: i2c@e6820000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
196 reg = <0xe6820000 0x425>;
197 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
198 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
199 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
200 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
202 power-domains = <&pd_a3sp>;
203 status = "disabled";
204 };
205
206 i2c1: i2c@e6822000 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
210 reg = <0xe6822000 0x425>;
211 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
212 GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
213 GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
214 GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
216 power-domains = <&pd_a3sp>;
217 status = "disabled";
218 };
219
220 i2c2: i2c@e6824000 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
224 reg = <0xe6824000 0x425>;
225 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
226 GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
227 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
228 GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
230 power-domains = <&pd_a3sp>;
231 status = "disabled";
232 };
233
234 i2c3: i2c@e6826000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
238 reg = <0xe6826000 0x425>;
239 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
240 GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
241 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
244 power-domains = <&pd_a3sp>;
245 status = "disabled";
246 };
247
248 i2c4: i2c@e6828000 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
252 reg = <0xe6828000 0x425>;
253 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
254 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
255 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
256 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
258 power-domains = <&pd_c5>;
259 status = "disabled";
260 };
261
262 mmcif: mmc@e6bd0000 {
263 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
264 reg = <0xe6bd0000 0x100>;
265 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
266 GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
268 power-domains = <&pd_a3sp>;
269 reg-io-width = <4>;
270 status = "disabled";
271 };
272
273 msiof0: spi@e6e20000 {
274 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
275 reg = <0xe6e20000 0x0064>;
276 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
278 power-domains = <&pd_a3sp>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 status = "disabled";
282 };
283
284 msiof1: spi@e6e10000 {
285 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
286 reg = <0xe6e10000 0x0064>;
287 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
289 power-domains = <&pd_a3sp>;
290 #address-cells = <1>;
291 #size-cells = <0>;
292 status = "disabled";
293 };
294
295 msiof2: spi@e6e00000 {
296 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
297 reg = <0xe6e00000 0x0064>;
298 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
300 power-domains = <&pd_a3sp>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 status = "disabled";
304 };
305
306 msiof3: spi@e6c90000 {
307 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
308 reg = <0xe6c90000 0x0064>;
309 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
311 power-domains = <&pd_a3sp>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 status = "disabled";
315 };
316
317 sdhi0: sd@ee100000 {
318 compatible = "renesas,sdhi-sh73a0";
319 reg = <0xee100000 0x100>;
320 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
324 power-domains = <&pd_a3sp>;
325 cap-sd-highspeed;
326 status = "disabled";
327 };
328
329 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
330 sdhi1: sd@ee120000 {
331 compatible = "renesas,sdhi-sh73a0";
332 reg = <0xee120000 0x100>;
333 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
336 power-domains = <&pd_a3sp>;
337 disable-wp;
338 cap-sd-highspeed;
339 status = "disabled";
340 };
341
342 sdhi2: sd@ee140000 {
343 compatible = "renesas,sdhi-sh73a0";
344 reg = <0xee140000 0x100>;
345 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
348 power-domains = <&pd_a3sp>;
349 disable-wp;
350 cap-sd-highspeed;
351 status = "disabled";
352 };
353
354 scifa0: serial@e6c40000 {
355 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
356 reg = <0xe6c40000 0x100>;
357 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
359 clock-names = "fck";
360 power-domains = <&pd_a3sp>;
361 status = "disabled";
362 };
363
364 scifa1: serial@e6c50000 {
365 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
366 reg = <0xe6c50000 0x100>;
367 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
369 clock-names = "fck";
370 power-domains = <&pd_a3sp>;
371 status = "disabled";
372 };
373
374 scifa2: serial@e6c60000 {
375 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
376 reg = <0xe6c60000 0x100>;
377 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
379 clock-names = "fck";
380 power-domains = <&pd_a3sp>;
381 status = "disabled";
382 };
383
384 scifa3: serial@e6c70000 {
385 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
386 reg = <0xe6c70000 0x100>;
387 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
389 clock-names = "fck";
390 power-domains = <&pd_a3sp>;
391 status = "disabled";
392 };
393
394 scifa4: serial@e6c80000 {
395 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
396 reg = <0xe6c80000 0x100>;
397 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
399 clock-names = "fck";
400 power-domains = <&pd_a3sp>;
401 status = "disabled";
402 };
403
404 scifa5: serial@e6cb0000 {
405 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
406 reg = <0xe6cb0000 0x100>;
407 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
409 clock-names = "fck";
410 power-domains = <&pd_a3sp>;
411 status = "disabled";
412 };
413
414 scifa6: serial@e6cc0000 {
415 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
416 reg = <0xe6cc0000 0x100>;
417 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
419 clock-names = "fck";
420 power-domains = <&pd_a3sp>;
421 status = "disabled";
422 };
423
424 scifa7: serial@e6cd0000 {
425 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
426 reg = <0xe6cd0000 0x100>;
427 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
429 clock-names = "fck";
430 power-domains = <&pd_a3sp>;
431 status = "disabled";
432 };
433
434 scifb: serial@e6c30000 {
435 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
436 reg = <0xe6c30000 0x100>;
437 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
439 clock-names = "fck";
440 power-domains = <&pd_a3sp>;
441 status = "disabled";
442 };
443
444 pfc: pin-controller@e6050000 {
445 compatible = "renesas,pfc-sh73a0";
446 reg = <0xe6050000 0x8000>,
447 <0xe605801c 0x1c>;
448 gpio-controller;
449 #gpio-cells = <2>;
450 gpio-ranges =
451 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
452 <&pfc 288 288 22>;
453 interrupts-extended =
454 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
455 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
456 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
457 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
458 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
459 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
460 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
461 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
462 power-domains = <&pd_c5>;
463 };
464
465 sysc: system-controller@e6180000 {
466 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
467 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
468
469 pm-domains {
470 pd_c5: c5 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 #power-domain-cells = <0>;
474
475 pd_c4: c4@0 {
476 reg = <0>;
477 #power-domain-cells = <0>;
478 };
479
480 pd_d4: d4@1 {
481 reg = <1>;
482 #power-domain-cells = <0>;
483 };
484
485 pd_a4bc0: a4bc0@4 {
486 reg = <4>;
487 #power-domain-cells = <0>;
488 };
489
490 pd_a4bc1: a4bc1@5 {
491 reg = <5>;
492 #power-domain-cells = <0>;
493 };
494
495 pd_a4lc0: a4lc0@6 {
496 reg = <6>;
497 #power-domain-cells = <0>;
498 };
499
500 pd_a4lc1: a4lc1@7 {
501 reg = <7>;
502 #power-domain-cells = <0>;
503 };
504
505 pd_a4mp: a4mp@8 {
506 reg = <8>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 #power-domain-cells = <0>;
510
511 pd_a3mp: a3mp@9 {
512 reg = <9>;
513 #power-domain-cells = <0>;
514 };
515
516 pd_a3vc: a3vc@10 {
517 reg = <10>;
518 #power-domain-cells = <0>;
519 };
520 };
521
522 pd_a4rm: a4rm@12 {
523 reg = <12>;
524 #address-cells = <1>;
525 #size-cells = <0>;
526 #power-domain-cells = <0>;
527
528 pd_a3r: a3r@13 {
529 reg = <13>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <0>;
533
534 pd_a2rv: a2rv@14 {
535 reg = <14>;
536 #address-cells = <1>;
537 #size-cells = <0>;
538 #power-domain-cells = <0>;
539 };
540 };
541 };
542
543 pd_a4s: a4s@16 {
544 reg = <16>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 #power-domain-cells = <0>;
548
549 pd_a3sp: a3sp@17 {
550 reg = <17>;
551 #power-domain-cells = <0>;
552 };
553
554 pd_a3sg: a3sg@18 {
555 reg = <18>;
556 #power-domain-cells = <0>;
557 };
558
559 pd_a3sm: a3sm@19 {
560 reg = <19>;
561 #address-cells = <1>;
562 #size-cells = <0>;
563 #power-domain-cells = <0>;
564
565 pd_a2sl: a2sl@20 {
566 reg = <20>;
567 #power-domain-cells = <0>;
568 };
569 };
570 };
571 };
572 };
573 };
574
575 sh_fsi2: sound@ec230000 {
576 #sound-dai-cells = <1>;
577 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
578 reg = <0xec230000 0x400>;
579 interrupts = <GIC_SPI 146 0x4>;
580 power-domains = <&pd_a4mp>;
581 status = "disabled";
582 };
583
584 bsc: bus@fec10000 {
585 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
586 "simple-pm-bus";
587 #address-cells = <1>;
588 #size-cells = <1>;
589 ranges = <0 0 0x20000000>;
590 reg = <0xfec10000 0x400>;
591 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&zb_clk>;
593 power-domains = <&pd_a4s>;
594 };
595
596 clocks {
597 #address-cells = <1>;
598 #size-cells = <1>;
599 ranges;
600
601 /* External root clocks */
602 extalr_clk: extalr {
603 compatible = "fixed-clock";
604 #clock-cells = <0>;
605 clock-frequency = <32768>;
606 };
607 extal1_clk: extal1 {
608 compatible = "fixed-clock";
609 #clock-cells = <0>;
610 clock-frequency = <26000000>;
611 };
612 extal2_clk: extal2 {
613 compatible = "fixed-clock";
614 #clock-cells = <0>;
615 };
616 extcki_clk: extcki {
617 compatible = "fixed-clock";
618 #clock-cells = <0>;
619 };
620 fsiack_clk: fsiack {
621 compatible = "fixed-clock";
622 #clock-cells = <0>;
623 clock-frequency = <0>;
624 };
625 fsibck_clk: fsibck {
626 compatible = "fixed-clock";
627 #clock-cells = <0>;
628 clock-frequency = <0>;
629 };
630
631 /* Special CPG clocks */
632 cpg_clocks: cpg_clocks@e6150000 {
633 compatible = "renesas,sh73a0-cpg-clocks";
634 reg = <0xe6150000 0x10000>;
635 clocks = <&extal1_clk>, <&extal2_clk>;
636 #clock-cells = <1>;
637 clock-output-names = "main", "pll0", "pll1", "pll2",
638 "pll3", "dsi0phy", "dsi1phy",
639 "zg", "m3", "b", "m1", "m2",
640 "z", "zx", "hp";
641 };
642
643 /* Variable factor clocks (DIV6) */
644 vclk1_clk: vclk1@e6150008 {
645 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
646 reg = <0xe6150008 4>;
647 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
648 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
649 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
650 <0>;
651 #clock-cells = <0>;
652 };
653 vclk2_clk: vclk2@e615000c {
654 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
655 reg = <0xe615000c 4>;
656 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
657 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
658 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
659 <0>;
660 #clock-cells = <0>;
661 };
662 vclk3_clk: vclk3@e615001c {
663 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
664 reg = <0xe615001c 4>;
665 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
666 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
667 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
668 <0>;
669 #clock-cells = <0>;
670 };
671 zb_clk: zb_clk@e6150010 {
672 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
673 reg = <0xe6150010 4>;
674 clocks = <&pll1_div2_clk>, <0>,
675 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
676 #clock-cells = <0>;
677 clock-output-names = "zb";
678 };
679 flctl_clk: flctlck@e6150014 {
680 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
681 reg = <0xe6150014 4>;
682 clocks = <&pll1_div2_clk>, <0>,
683 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
684 #clock-cells = <0>;
685 };
686 sdhi0_clk: sdhi0ck@e6150074 {
687 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
688 reg = <0xe6150074 4>;
689 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
690 <&pll1_div13_clk>, <0>;
691 #clock-cells = <0>;
692 };
693 sdhi1_clk: sdhi1ck@e6150078 {
694 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
695 reg = <0xe6150078 4>;
696 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
697 <&pll1_div13_clk>, <0>;
698 #clock-cells = <0>;
699 };
700 sdhi2_clk: sdhi2ck@e615007c {
701 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
702 reg = <0xe615007c 4>;
703 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
704 <&pll1_div13_clk>, <0>;
705 #clock-cells = <0>;
706 };
707 fsia_clk: fsia@e6150018 {
708 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
709 reg = <0xe6150018 4>;
710 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
711 <&fsiack_clk>, <&fsiack_clk>;
712 #clock-cells = <0>;
713 };
714 fsib_clk: fsib@e6150090 {
715 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
716 reg = <0xe6150090 4>;
717 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
718 <&fsibck_clk>, <&fsibck_clk>;
719 #clock-cells = <0>;
720 };
721 sub_clk: sub@e6150080 {
722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
723 reg = <0xe6150080 4>;
724 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
725 <&extal2_clk>, <&extal2_clk>;
726 #clock-cells = <0>;
727 };
728 spua_clk: spua@e6150084 {
729 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
730 reg = <0xe6150084 4>;
731 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
732 <&extal2_clk>, <&extal2_clk>;
733 #clock-cells = <0>;
734 };
735 spuv_clk: spuv@e6150094 {
736 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
737 reg = <0xe6150094 4>;
738 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
739 <&extal2_clk>, <&extal2_clk>;
740 #clock-cells = <0>;
741 };
742 msu_clk: msu@e6150088 {
743 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
744 reg = <0xe6150088 4>;
745 clocks = <&pll1_div2_clk>, <0>,
746 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
747 #clock-cells = <0>;
748 };
749 hsi_clk: hsi@e615008c {
750 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
751 reg = <0xe615008c 4>;
752 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
753 <&pll1_div7_clk>, <0>;
754 #clock-cells = <0>;
755 };
756 mfg1_clk: mfg1@e6150098 {
757 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
758 reg = <0xe6150098 4>;
759 clocks = <&pll1_div2_clk>, <0>,
760 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
761 #clock-cells = <0>;
762 };
763 mfg2_clk: mfg2@e615009c {
764 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
765 reg = <0xe615009c 4>;
766 clocks = <&pll1_div2_clk>, <0>,
767 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
768 #clock-cells = <0>;
769 };
770 dsit_clk: dsit@e6150060 {
771 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
772 reg = <0xe6150060 4>;
773 clocks = <&pll1_div2_clk>, <0>,
774 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
775 #clock-cells = <0>;
776 };
777 dsi0p_clk: dsi0pck@e6150064 {
778 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
779 reg = <0xe6150064 4>;
780 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
781 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
782 <&extcki_clk>, <0>, <0>, <0>;
783 #clock-cells = <0>;
784 };
785
786 /* Fixed factor clocks */
787 main_div2_clk: main_div2 {
788 compatible = "fixed-factor-clock";
789 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
790 #clock-cells = <0>;
791 clock-div = <2>;
792 clock-mult = <1>;
793 };
794 pll1_div2_clk: pll1_div2 {
795 compatible = "fixed-factor-clock";
796 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
797 #clock-cells = <0>;
798 clock-div = <2>;
799 clock-mult = <1>;
800 };
801 pll1_div7_clk: pll1_div7 {
802 compatible = "fixed-factor-clock";
803 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
804 #clock-cells = <0>;
805 clock-div = <7>;
806 clock-mult = <1>;
807 };
808 pll1_div13_clk: pll1_div13 {
809 compatible = "fixed-factor-clock";
810 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
811 #clock-cells = <0>;
812 clock-div = <13>;
813 clock-mult = <1>;
814 };
815 twd_clk: twd {
816 compatible = "fixed-factor-clock";
817 clocks = <&cpg_clocks SH73A0_CLK_Z>;
818 #clock-cells = <0>;
819 clock-div = <4>;
820 clock-mult = <1>;
821 };
822
823 /* Gate clocks */
824 mstp0_clks: mstp0_clks@e6150130 {
825 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
826 reg = <0xe6150130 4>, <0xe6150030 4>;
827 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
828 #clock-cells = <1>;
829 clock-indices = <
830 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
831 >;
832 clock-output-names =
833 "iic2", "msiof0";
834 };
835 mstp1_clks: mstp1_clks@e6150134 {
836 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
837 reg = <0xe6150134 4>, <0xe6150038 4>;
838 clocks = <&cpg_clocks SH73A0_CLK_B>,
839 <&cpg_clocks SH73A0_CLK_B>,
840 <&cpg_clocks SH73A0_CLK_B>,
841 <&cpg_clocks SH73A0_CLK_B>,
842 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
843 <&cpg_clocks SH73A0_CLK_HP>,
844 <&cpg_clocks SH73A0_CLK_ZG>,
845 <&cpg_clocks SH73A0_CLK_B>;
846 #clock-cells = <1>;
847 clock-indices = <
848 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
849 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
850 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
851 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
852 SH73A0_CLK_LCDC0
853 >;
854 clock-output-names =
855 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
856 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
857 };
858 mstp2_clks: mstp2_clks@e6150138 {
859 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
860 reg = <0xe6150138 4>, <0xe6150040 4>;
861 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
862 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
863 <&sub_clk>, <&sub_clk>, <&sub_clk>,
864 <&sub_clk>, <&sub_clk>, <&sub_clk>,
865 <&sub_clk>, <&sub_clk>, <&sub_clk>;
866 #clock-cells = <1>;
867 clock-indices = <
868 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
869 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
870 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
871 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
872 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
873 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
874 SH73A0_CLK_SCIFA4
875 >;
876 clock-output-names =
877 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
878 "msiof1", "scifa5", "scifb", "msiof2",
879 "scifa0", "scifa1", "scifa2", "scifa3",
880 "scifa4";
881 };
882 mstp3_clks: mstp3_clks@e615013c {
883 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
884 reg = <0xe615013c 4>, <0xe6150048 4>;
885 clocks = <&sub_clk>, <&extalr_clk>,
886 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
887 <&cpg_clocks SH73A0_CLK_HP>,
888 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
889 <&sdhi0_clk>, <&sdhi1_clk>,
890 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
891 <&main_div2_clk>, <&main_div2_clk>,
892 <&main_div2_clk>, <&main_div2_clk>,
893 <&main_div2_clk>;
894 #clock-cells = <1>;
895 clock-indices = <
896 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
897 SH73A0_CLK_FSI SH73A0_CLK_IRDA
898 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
899 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
900 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
901 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
902 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
903 SH73A0_CLK_TPU4
904 >;
905 clock-output-names =
906 "scifa6", "cmt1", "fsi", "irda", "iic1",
907 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
908 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
909 };
910 mstp4_clks: mstp4_clks@e6150140 {
911 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
912 reg = <0xe6150140 4>, <0xe615004c 4>;
913 clocks = <&cpg_clocks SH73A0_CLK_HP>,
914 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
915 #clock-cells = <1>;
916 clock-indices = <
917 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
918 SH73A0_CLK_KEYSC
919 >;
920 clock-output-names =
921 "iic3", "iic4", "keysc";
922 };
923 mstp5_clks: mstp5_clks@e6150144 {
924 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
925 reg = <0xe6150144 4>, <0xe615003c 4>;
926 clocks = <&cpg_clocks SH73A0_CLK_HP>;
927 #clock-cells = <1>;
928 clock-indices = <
929 SH73A0_CLK_INTCA0
930 >;
931 clock-output-names =
932 "intca0";
933 };
934 };
935};
1/*
2 * Device Tree Source for the SH73A0 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/sh73a0-clock.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15/ {
16 compatible = "renesas,sh73a0";
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <0>;
29 clock-frequency = <1196000000>;
30 power-domains = <&pd_a2sl>;
31 next-level-cache = <&L2>;
32 };
33 cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a9";
36 reg = <1>;
37 clock-frequency = <1196000000>;
38 power-domains = <&pd_a2sl>;
39 next-level-cache = <&L2>;
40 };
41 };
42
43 timer@f0000600 {
44 compatible = "arm,cortex-a9-twd-timer";
45 reg = <0xf0000600 0x20>;
46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
47 clocks = <&twd_clk>;
48 };
49
50 gic: interrupt-controller@f0001000 {
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
53 interrupt-controller;
54 reg = <0xf0001000 0x1000>,
55 <0xf0000100 0x100>;
56 };
57
58 L2: cache-controller@f0100000 {
59 compatible = "arm,pl310-cache";
60 reg = <0xf0100000 0x1000>;
61 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
62 power-domains = <&pd_a3sm>;
63 arm,data-latency = <3 3 3>;
64 arm,tag-latency = <2 2 2>;
65 arm,shared-override;
66 cache-unified;
67 cache-level = <2>;
68 };
69
70 sbsc2: memory-controller@fb400000 {
71 compatible = "renesas,sbsc-sh73a0";
72 reg = <0xfb400000 0x400>;
73 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
75 interrupt-names = "sec", "temp";
76 power-domains = <&pd_a4bc1>;
77 };
78
79 sbsc1: memory-controller@fe400000 {
80 compatible = "renesas,sbsc-sh73a0";
81 reg = <0xfe400000 0x400>;
82 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-names = "sec", "temp";
85 power-domains = <&pd_a4bc0>;
86 };
87
88 pmu {
89 compatible = "arm,cortex-a9-pmu";
90 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
92 };
93
94 cmt1: timer@e6138000 {
95 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
96 reg = <0xe6138000 0x200>;
97 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
99 clock-names = "fck";
100 power-domains = <&pd_c5>;
101
102 renesas,channels-mask = <0x3f>;
103
104 status = "disabled";
105 };
106
107 irqpin0: interrupt-controller@e6900000 {
108 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 reg = <0xe6900000 4>,
112 <0xe6900010 4>,
113 <0xe6900020 1>,
114 <0xe6900040 1>,
115 <0xe6900060 1>;
116 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
117 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
118 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
121 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
122 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
123 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
125 power-domains = <&pd_a4s>;
126 control-parent;
127 };
128
129 irqpin1: interrupt-controller@e6900004 {
130 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
131 #interrupt-cells = <2>;
132 interrupt-controller;
133 reg = <0xe6900004 4>,
134 <0xe6900014 4>,
135 <0xe6900024 1>,
136 <0xe6900044 1>,
137 <0xe6900064 1>;
138 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
139 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
143 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
144 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
145 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
147 power-domains = <&pd_a4s>;
148 control-parent;
149 };
150
151 irqpin2: interrupt-controller@e6900008 {
152 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
153 #interrupt-cells = <2>;
154 interrupt-controller;
155 reg = <0xe6900008 4>,
156 <0xe6900018 4>,
157 <0xe6900028 1>,
158 <0xe6900048 1>,
159 <0xe6900068 1>;
160 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
161 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
162 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
163 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
164 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
165 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
166 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
167 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
169 power-domains = <&pd_a4s>;
170 control-parent;
171 };
172
173 irqpin3: interrupt-controller@e690000c {
174 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
175 #interrupt-cells = <2>;
176 interrupt-controller;
177 reg = <0xe690000c 4>,
178 <0xe690001c 4>,
179 <0xe690002c 1>,
180 <0xe690004c 1>,
181 <0xe690006c 1>;
182 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
183 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
184 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
185 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
186 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
187 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
188 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
189 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
191 power-domains = <&pd_a4s>;
192 control-parent;
193 };
194
195 i2c0: i2c@e6820000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
199 reg = <0xe6820000 0x425>;
200 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
201 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
202 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
203 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
205 power-domains = <&pd_a3sp>;
206 status = "disabled";
207 };
208
209 i2c1: i2c@e6822000 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
213 reg = <0xe6822000 0x425>;
214 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
215 GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
216 GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
217 GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
219 power-domains = <&pd_a3sp>;
220 status = "disabled";
221 };
222
223 i2c2: i2c@e6824000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
227 reg = <0xe6824000 0x425>;
228 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
229 GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
230 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
231 GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
233 power-domains = <&pd_a3sp>;
234 status = "disabled";
235 };
236
237 i2c3: i2c@e6826000 {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
241 reg = <0xe6826000 0x425>;
242 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
243 GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
247 power-domains = <&pd_a3sp>;
248 status = "disabled";
249 };
250
251 i2c4: i2c@e6828000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
255 reg = <0xe6828000 0x425>;
256 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
257 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
258 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
259 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
261 power-domains = <&pd_c5>;
262 status = "disabled";
263 };
264
265 mmcif: mmc@e6bd0000 {
266 compatible = "renesas,sh-mmcif";
267 reg = <0xe6bd0000 0x100>;
268 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
269 GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
271 power-domains = <&pd_a3sp>;
272 reg-io-width = <4>;
273 status = "disabled";
274 };
275
276 msiof0: spi@e6e20000 {
277 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
278 reg = <0xe6e20000 0x0064>;
279 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
281 power-domains = <&pd_a3sp>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 status = "disabled";
285 };
286
287 msiof1: spi@e6e10000 {
288 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
289 reg = <0xe6e10000 0x0064>;
290 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
292 power-domains = <&pd_a3sp>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 status = "disabled";
296 };
297
298 msiof2: spi@e6e00000 {
299 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
300 reg = <0xe6e00000 0x0064>;
301 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
303 power-domains = <&pd_a3sp>;
304 #address-cells = <1>;
305 #size-cells = <0>;
306 status = "disabled";
307 };
308
309 msiof3: spi@e6c90000 {
310 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
311 reg = <0xe6c90000 0x0064>;
312 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
314 power-domains = <&pd_a3sp>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 status = "disabled";
318 };
319
320 sdhi0: sd@ee100000 {
321 compatible = "renesas,sdhi-sh73a0";
322 reg = <0xee100000 0x100>;
323 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
327 power-domains = <&pd_a3sp>;
328 cap-sd-highspeed;
329 status = "disabled";
330 };
331
332 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
333 sdhi1: sd@ee120000 {
334 compatible = "renesas,sdhi-sh73a0";
335 reg = <0xee120000 0x100>;
336 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
339 power-domains = <&pd_a3sp>;
340 toshiba,mmc-wrprotect-disable;
341 cap-sd-highspeed;
342 status = "disabled";
343 };
344
345 sdhi2: sd@ee140000 {
346 compatible = "renesas,sdhi-sh73a0";
347 reg = <0xee140000 0x100>;
348 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
351 power-domains = <&pd_a3sp>;
352 toshiba,mmc-wrprotect-disable;
353 cap-sd-highspeed;
354 status = "disabled";
355 };
356
357 scifa0: serial@e6c40000 {
358 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
359 reg = <0xe6c40000 0x100>;
360 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
362 clock-names = "fck";
363 power-domains = <&pd_a3sp>;
364 status = "disabled";
365 };
366
367 scifa1: serial@e6c50000 {
368 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
369 reg = <0xe6c50000 0x100>;
370 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
372 clock-names = "fck";
373 power-domains = <&pd_a3sp>;
374 status = "disabled";
375 };
376
377 scifa2: serial@e6c60000 {
378 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
379 reg = <0xe6c60000 0x100>;
380 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
382 clock-names = "fck";
383 power-domains = <&pd_a3sp>;
384 status = "disabled";
385 };
386
387 scifa3: serial@e6c70000 {
388 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
389 reg = <0xe6c70000 0x100>;
390 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
392 clock-names = "fck";
393 power-domains = <&pd_a3sp>;
394 status = "disabled";
395 };
396
397 scifa4: serial@e6c80000 {
398 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
399 reg = <0xe6c80000 0x100>;
400 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
402 clock-names = "fck";
403 power-domains = <&pd_a3sp>;
404 status = "disabled";
405 };
406
407 scifa5: serial@e6cb0000 {
408 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
409 reg = <0xe6cb0000 0x100>;
410 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
412 clock-names = "fck";
413 power-domains = <&pd_a3sp>;
414 status = "disabled";
415 };
416
417 scifa6: serial@e6cc0000 {
418 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
419 reg = <0xe6cc0000 0x100>;
420 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
422 clock-names = "fck";
423 power-domains = <&pd_a3sp>;
424 status = "disabled";
425 };
426
427 scifa7: serial@e6cd0000 {
428 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
429 reg = <0xe6cd0000 0x100>;
430 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
432 clock-names = "fck";
433 power-domains = <&pd_a3sp>;
434 status = "disabled";
435 };
436
437 scifb: serial@e6c30000 {
438 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
439 reg = <0xe6c30000 0x100>;
440 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
442 clock-names = "fck";
443 power-domains = <&pd_a3sp>;
444 status = "disabled";
445 };
446
447 pfc: pfc@e6050000 {
448 compatible = "renesas,pfc-sh73a0";
449 reg = <0xe6050000 0x8000>,
450 <0xe605801c 0x1c>;
451 gpio-controller;
452 #gpio-cells = <2>;
453 gpio-ranges =
454 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
455 <&pfc 288 288 22>;
456 interrupts-extended =
457 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
458 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
459 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
460 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
461 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
462 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
463 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
464 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
465 power-domains = <&pd_c5>;
466 };
467
468 sysc: system-controller@e6180000 {
469 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
470 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
471
472 pm-domains {
473 pd_c5: c5 {
474 #address-cells = <1>;
475 #size-cells = <0>;
476 #power-domain-cells = <0>;
477
478 pd_c4: c4@0 {
479 reg = <0>;
480 #power-domain-cells = <0>;
481 };
482
483 pd_d4: d4@1 {
484 reg = <1>;
485 #power-domain-cells = <0>;
486 };
487
488 pd_a4bc0: a4bc0@4 {
489 reg = <4>;
490 #power-domain-cells = <0>;
491 };
492
493 pd_a4bc1: a4bc1@5 {
494 reg = <5>;
495 #power-domain-cells = <0>;
496 };
497
498 pd_a4lc0: a4lc0@6 {
499 reg = <6>;
500 #power-domain-cells = <0>;
501 };
502
503 pd_a4lc1: a4lc1@7 {
504 reg = <7>;
505 #power-domain-cells = <0>;
506 };
507
508 pd_a4mp: a4mp@8 {
509 reg = <8>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 #power-domain-cells = <0>;
513
514 pd_a3mp: a3mp@9 {
515 reg = <9>;
516 #power-domain-cells = <0>;
517 };
518
519 pd_a3vc: a3vc@10 {
520 reg = <10>;
521 #power-domain-cells = <0>;
522 };
523 };
524
525 pd_a4rm: a4rm@12 {
526 reg = <12>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 #power-domain-cells = <0>;
530
531 pd_a3r: a3r@13 {
532 reg = <13>;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 #power-domain-cells = <0>;
536
537 pd_a2rv: a2rv@14 {
538 reg = <14>;
539 #address-cells = <1>;
540 #size-cells = <0>;
541 #power-domain-cells = <0>;
542 };
543 };
544 };
545
546 pd_a4s: a4s@16 {
547 reg = <16>;
548 #address-cells = <1>;
549 #size-cells = <0>;
550 #power-domain-cells = <0>;
551
552 pd_a3sp: a3sp@17 {
553 reg = <17>;
554 #power-domain-cells = <0>;
555 };
556
557 pd_a3sg: a3sg@18 {
558 reg = <18>;
559 #power-domain-cells = <0>;
560 };
561
562 pd_a3sm: a3sm@19 {
563 reg = <19>;
564 #address-cells = <1>;
565 #size-cells = <0>;
566 #power-domain-cells = <0>;
567
568 pd_a2sl: a2sl@20 {
569 reg = <20>;
570 #power-domain-cells = <0>;
571 };
572 };
573 };
574 };
575 };
576 };
577
578 sh_fsi2: sound@ec230000 {
579 #sound-dai-cells = <1>;
580 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
581 reg = <0xec230000 0x400>;
582 interrupts = <GIC_SPI 146 0x4>;
583 power-domains = <&pd_a4mp>;
584 status = "disabled";
585 };
586
587 bsc: bus@fec10000 {
588 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
589 "simple-pm-bus";
590 #address-cells = <1>;
591 #size-cells = <1>;
592 ranges = <0 0 0x20000000>;
593 reg = <0xfec10000 0x400>;
594 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&zb_clk>;
596 power-domains = <&pd_a4s>;
597 };
598
599 clocks {
600 #address-cells = <1>;
601 #size-cells = <1>;
602 ranges;
603
604 /* External root clocks */
605 extalr_clk: extalr {
606 compatible = "fixed-clock";
607 #clock-cells = <0>;
608 clock-frequency = <32768>;
609 };
610 extal1_clk: extal1 {
611 compatible = "fixed-clock";
612 #clock-cells = <0>;
613 clock-frequency = <26000000>;
614 };
615 extal2_clk: extal2 {
616 compatible = "fixed-clock";
617 #clock-cells = <0>;
618 };
619 extcki_clk: extcki {
620 compatible = "fixed-clock";
621 #clock-cells = <0>;
622 };
623 fsiack_clk: fsiack {
624 compatible = "fixed-clock";
625 #clock-cells = <0>;
626 clock-frequency = <0>;
627 };
628 fsibck_clk: fsibck {
629 compatible = "fixed-clock";
630 #clock-cells = <0>;
631 clock-frequency = <0>;
632 };
633
634 /* Special CPG clocks */
635 cpg_clocks: cpg_clocks@e6150000 {
636 compatible = "renesas,sh73a0-cpg-clocks";
637 reg = <0xe6150000 0x10000>;
638 clocks = <&extal1_clk>, <&extal2_clk>;
639 #clock-cells = <1>;
640 clock-output-names = "main", "pll0", "pll1", "pll2",
641 "pll3", "dsi0phy", "dsi1phy",
642 "zg", "m3", "b", "m1", "m2",
643 "z", "zx", "hp";
644 };
645
646 /* Variable factor clocks (DIV6) */
647 vclk1_clk: vclk1@e6150008 {
648 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
649 reg = <0xe6150008 4>;
650 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
651 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
652 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
653 <0>;
654 #clock-cells = <0>;
655 };
656 vclk2_clk: vclk2@e615000c {
657 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
658 reg = <0xe615000c 4>;
659 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
660 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
661 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
662 <0>;
663 #clock-cells = <0>;
664 };
665 vclk3_clk: vclk3@e615001c {
666 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
667 reg = <0xe615001c 4>;
668 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
669 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
670 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
671 <0>;
672 #clock-cells = <0>;
673 };
674 zb_clk: zb_clk@e6150010 {
675 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
676 reg = <0xe6150010 4>;
677 clocks = <&pll1_div2_clk>, <0>,
678 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
679 #clock-cells = <0>;
680 clock-output-names = "zb";
681 };
682 flctl_clk: flctlck@e6150014 {
683 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
684 reg = <0xe6150014 4>;
685 clocks = <&pll1_div2_clk>, <0>,
686 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
687 #clock-cells = <0>;
688 };
689 sdhi0_clk: sdhi0ck@e6150074 {
690 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
691 reg = <0xe6150074 4>;
692 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
693 <&pll1_div13_clk>, <0>;
694 #clock-cells = <0>;
695 };
696 sdhi1_clk: sdhi1ck@e6150078 {
697 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
698 reg = <0xe6150078 4>;
699 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
700 <&pll1_div13_clk>, <0>;
701 #clock-cells = <0>;
702 };
703 sdhi2_clk: sdhi2ck@e615007c {
704 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
705 reg = <0xe615007c 4>;
706 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
707 <&pll1_div13_clk>, <0>;
708 #clock-cells = <0>;
709 };
710 fsia_clk: fsia@e6150018 {
711 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
712 reg = <0xe6150018 4>;
713 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
714 <&fsiack_clk>, <&fsiack_clk>;
715 #clock-cells = <0>;
716 };
717 fsib_clk: fsib@e6150090 {
718 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
719 reg = <0xe6150090 4>;
720 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
721 <&fsibck_clk>, <&fsibck_clk>;
722 #clock-cells = <0>;
723 };
724 sub_clk: sub@e6150080 {
725 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
726 reg = <0xe6150080 4>;
727 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
728 <&extal2_clk>, <&extal2_clk>;
729 #clock-cells = <0>;
730 };
731 spua_clk: spua@e6150084 {
732 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
733 reg = <0xe6150084 4>;
734 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
735 <&extal2_clk>, <&extal2_clk>;
736 #clock-cells = <0>;
737 };
738 spuv_clk: spuv@e6150094 {
739 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
740 reg = <0xe6150094 4>;
741 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
742 <&extal2_clk>, <&extal2_clk>;
743 #clock-cells = <0>;
744 };
745 msu_clk: msu@e6150088 {
746 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
747 reg = <0xe6150088 4>;
748 clocks = <&pll1_div2_clk>, <0>,
749 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
750 #clock-cells = <0>;
751 };
752 hsi_clk: hsi@e615008c {
753 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
754 reg = <0xe615008c 4>;
755 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
756 <&pll1_div7_clk>, <0>;
757 #clock-cells = <0>;
758 };
759 mfg1_clk: mfg1@e6150098 {
760 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
761 reg = <0xe6150098 4>;
762 clocks = <&pll1_div2_clk>, <0>,
763 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
764 #clock-cells = <0>;
765 };
766 mfg2_clk: mfg2@e615009c {
767 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
768 reg = <0xe615009c 4>;
769 clocks = <&pll1_div2_clk>, <0>,
770 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
771 #clock-cells = <0>;
772 };
773 dsit_clk: dsit@e6150060 {
774 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
775 reg = <0xe6150060 4>;
776 clocks = <&pll1_div2_clk>, <0>,
777 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
778 #clock-cells = <0>;
779 };
780 dsi0p_clk: dsi0pck@e6150064 {
781 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
782 reg = <0xe6150064 4>;
783 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
784 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
785 <&extcki_clk>, <0>, <0>, <0>;
786 #clock-cells = <0>;
787 };
788
789 /* Fixed factor clocks */
790 main_div2_clk: main_div2 {
791 compatible = "fixed-factor-clock";
792 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
793 #clock-cells = <0>;
794 clock-div = <2>;
795 clock-mult = <1>;
796 };
797 pll1_div2_clk: pll1_div2 {
798 compatible = "fixed-factor-clock";
799 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
800 #clock-cells = <0>;
801 clock-div = <2>;
802 clock-mult = <1>;
803 };
804 pll1_div7_clk: pll1_div7 {
805 compatible = "fixed-factor-clock";
806 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
807 #clock-cells = <0>;
808 clock-div = <7>;
809 clock-mult = <1>;
810 };
811 pll1_div13_clk: pll1_div13 {
812 compatible = "fixed-factor-clock";
813 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
814 #clock-cells = <0>;
815 clock-div = <13>;
816 clock-mult = <1>;
817 };
818 twd_clk: twd {
819 compatible = "fixed-factor-clock";
820 clocks = <&cpg_clocks SH73A0_CLK_Z>;
821 #clock-cells = <0>;
822 clock-div = <4>;
823 clock-mult = <1>;
824 };
825
826 /* Gate clocks */
827 mstp0_clks: mstp0_clks@e6150130 {
828 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
829 reg = <0xe6150130 4>, <0xe6150030 4>;
830 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
831 #clock-cells = <1>;
832 clock-indices = <
833 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
834 >;
835 clock-output-names =
836 "iic2", "msiof0";
837 };
838 mstp1_clks: mstp1_clks@e6150134 {
839 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
840 reg = <0xe6150134 4>, <0xe6150038 4>;
841 clocks = <&cpg_clocks SH73A0_CLK_B>,
842 <&cpg_clocks SH73A0_CLK_B>,
843 <&cpg_clocks SH73A0_CLK_B>,
844 <&cpg_clocks SH73A0_CLK_B>,
845 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
846 <&cpg_clocks SH73A0_CLK_HP>,
847 <&cpg_clocks SH73A0_CLK_ZG>,
848 <&cpg_clocks SH73A0_CLK_B>;
849 #clock-cells = <1>;
850 clock-indices = <
851 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
852 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
853 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
854 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
855 SH73A0_CLK_LCDC0
856 >;
857 clock-output-names =
858 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
859 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
860 };
861 mstp2_clks: mstp2_clks@e6150138 {
862 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
863 reg = <0xe6150138 4>, <0xe6150040 4>;
864 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
865 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
866 <&sub_clk>, <&sub_clk>, <&sub_clk>,
867 <&sub_clk>, <&sub_clk>, <&sub_clk>,
868 <&sub_clk>, <&sub_clk>, <&sub_clk>;
869 #clock-cells = <1>;
870 clock-indices = <
871 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
872 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
873 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
874 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
875 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
876 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
877 SH73A0_CLK_SCIFA4
878 >;
879 clock-output-names =
880 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
881 "msiof1", "scifa5", "scifb", "msiof2",
882 "scifa0", "scifa1", "scifa2", "scifa3",
883 "scifa4";
884 };
885 mstp3_clks: mstp3_clks@e615013c {
886 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
887 reg = <0xe615013c 4>, <0xe6150048 4>;
888 clocks = <&sub_clk>, <&extalr_clk>,
889 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
890 <&cpg_clocks SH73A0_CLK_HP>,
891 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
892 <&sdhi0_clk>, <&sdhi1_clk>,
893 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
894 <&main_div2_clk>, <&main_div2_clk>,
895 <&main_div2_clk>, <&main_div2_clk>,
896 <&main_div2_clk>;
897 #clock-cells = <1>;
898 clock-indices = <
899 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
900 SH73A0_CLK_FSI SH73A0_CLK_IRDA
901 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
902 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
903 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
904 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
905 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
906 SH73A0_CLK_TPU4
907 >;
908 clock-output-names =
909 "scifa6", "cmt1", "fsi", "irda", "iic1",
910 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
911 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
912 };
913 mstp4_clks: mstp4_clks@e6150140 {
914 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
915 reg = <0xe6150140 4>, <0xe615004c 4>;
916 clocks = <&cpg_clocks SH73A0_CLK_HP>,
917 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
918 #clock-cells = <1>;
919 clock-indices = <
920 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
921 SH73A0_CLK_KEYSC
922 >;
923 clock-output-names =
924 "iic3", "iic4", "keysc";
925 };
926 mstp5_clks: mstp5_clks@e6150144 {
927 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
928 reg = <0xe6150144 4>, <0xe615003c 4>;
929 clocks = <&cpg_clocks SH73A0_CLK_HP>;
930 #clock-cells = <1>;
931 clock-indices = <
932 SH73A0_CLK_INTCA0
933 >;
934 clock-output-names =
935 "intca0";
936 };
937 };
938};