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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <dt-bindings/clock/rk3228-cru.h>
8#include <dt-bindings/thermal/thermal.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 interrupt-parent = <&gic>;
15
16 aliases {
17 serial0 = &uart0;
18 serial1 = &uart1;
19 serial2 = &uart2;
20 spi0 = &spi0;
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu0: cpu@f00 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a7";
30 reg = <0xf00>;
31 resets = <&cru SRST_CORE0>;
32 operating-points-v2 = <&cpu0_opp_table>;
33 #cooling-cells = <2>; /* min followed by max */
34 clock-latency = <40000>;
35 clocks = <&cru ARMCLK>;
36 enable-method = "psci";
37 };
38
39 cpu1: cpu@f01 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a7";
42 reg = <0xf01>;
43 resets = <&cru SRST_CORE1>;
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
46 enable-method = "psci";
47 };
48
49 cpu2: cpu@f02 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a7";
52 reg = <0xf02>;
53 resets = <&cru SRST_CORE2>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
56 enable-method = "psci";
57 };
58
59 cpu3: cpu@f03 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a7";
62 reg = <0xf03>;
63 resets = <&cru SRST_CORE3>;
64 operating-points-v2 = <&cpu0_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
66 enable-method = "psci";
67 };
68 };
69
70 cpu0_opp_table: opp_table0 {
71 compatible = "operating-points-v2";
72 opp-shared;
73
74 opp-408000000 {
75 opp-hz = /bits/ 64 <408000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
78 opp-suspend;
79 };
80 opp-600000000 {
81 opp-hz = /bits/ 64 <600000000>;
82 opp-microvolt = <975000>;
83 };
84 opp-816000000 {
85 opp-hz = /bits/ 64 <816000000>;
86 opp-microvolt = <1000000>;
87 };
88 opp-1008000000 {
89 opp-hz = /bits/ 64 <1008000000>;
90 opp-microvolt = <1175000>;
91 };
92 opp-1200000000 {
93 opp-hz = /bits/ 64 <1200000000>;
94 opp-microvolt = <1275000>;
95 };
96 };
97
98 amba {
99 compatible = "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103
104 pdma: pdma@110f0000 {
105 compatible = "arm,pl330", "arm,primecell";
106 reg = <0x110f0000 0x4000>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
109 #dma-cells = <1>;
110 clocks = <&cru ACLK_DMAC>;
111 clock-names = "apb_pclk";
112 };
113 };
114
115 arm-pmu {
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
122 };
123
124 psci {
125 compatible = "arm,psci-1.0", "arm,psci-0.2";
126 method = "smc";
127 };
128
129 timer {
130 compatible = "arm,armv7-timer";
131 arm,cpu-registers-not-fw-configured;
132 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
136 clock-frequency = <24000000>;
137 };
138
139 xin24m: oscillator {
140 compatible = "fixed-clock";
141 clock-frequency = <24000000>;
142 clock-output-names = "xin24m";
143 #clock-cells = <0>;
144 };
145
146 display_subsystem: display-subsystem {
147 compatible = "rockchip,display-subsystem";
148 ports = <&vop_out>;
149 };
150
151 i2s1: i2s1@100b0000 {
152 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
153 reg = <0x100b0000 0x4000>;
154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 clock-names = "i2s_clk", "i2s_hclk";
158 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
159 dmas = <&pdma 14>, <&pdma 15>;
160 dma-names = "tx", "rx";
161 pinctrl-names = "default";
162 pinctrl-0 = <&i2s1_bus>;
163 status = "disabled";
164 };
165
166 i2s0: i2s0@100c0000 {
167 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
168 reg = <0x100c0000 0x4000>;
169 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 clock-names = "i2s_clk", "i2s_hclk";
173 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
174 dmas = <&pdma 11>, <&pdma 12>;
175 dma-names = "tx", "rx";
176 status = "disabled";
177 };
178
179 spdif: spdif@100d0000 {
180 compatible = "rockchip,rk3228-spdif";
181 reg = <0x100d0000 0x1000>;
182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
184 clock-names = "mclk", "hclk";
185 dmas = <&pdma 10>;
186 dma-names = "tx";
187 pinctrl-names = "default";
188 pinctrl-0 = <&spdif_tx>;
189 status = "disabled";
190 };
191
192 i2s2: i2s2@100e0000 {
193 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
194 reg = <0x100e0000 0x4000>;
195 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
196 #address-cells = <1>;
197 #size-cells = <0>;
198 clock-names = "i2s_clk", "i2s_hclk";
199 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
200 dmas = <&pdma 0>, <&pdma 1>;
201 dma-names = "tx", "rx";
202 status = "disabled";
203 };
204
205 grf: syscon@11000000 {
206 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
207 reg = <0x11000000 0x1000>;
208 #address-cells = <1>;
209 #size-cells = <1>;
210
211 io_domains: io-domains {
212 compatible = "rockchip,rk3228-io-voltage-domain";
213 status = "disabled";
214 };
215
216 u2phy0: usb2-phy@760 {
217 compatible = "rockchip,rk3228-usb2phy";
218 reg = <0x0760 0x0c>;
219 clocks = <&cru SCLK_OTGPHY0>;
220 clock-names = "phyclk";
221 clock-output-names = "usb480m_phy0";
222 #clock-cells = <0>;
223 status = "disabled";
224
225 u2phy0_otg: otg-port {
226 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
229 interrupt-names = "otg-bvalid", "otg-id",
230 "linestate";
231 #phy-cells = <0>;
232 status = "disabled";
233 };
234
235 u2phy0_host: host-port {
236 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-names = "linestate";
238 #phy-cells = <0>;
239 status = "disabled";
240 };
241 };
242
243 u2phy1: usb2-phy@800 {
244 compatible = "rockchip,rk3228-usb2phy";
245 reg = <0x0800 0x0c>;
246 clocks = <&cru SCLK_OTGPHY1>;
247 clock-names = "phyclk";
248 clock-output-names = "usb480m_phy1";
249 #clock-cells = <0>;
250 status = "disabled";
251
252 u2phy1_otg: otg-port {
253 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-names = "linestate";
255 #phy-cells = <0>;
256 status = "disabled";
257 };
258
259 u2phy1_host: host-port {
260 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-names = "linestate";
262 #phy-cells = <0>;
263 status = "disabled";
264 };
265 };
266 };
267
268 uart0: serial@11010000 {
269 compatible = "snps,dw-apb-uart";
270 reg = <0x11010000 0x100>;
271 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
272 clock-frequency = <24000000>;
273 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
274 clock-names = "baudclk", "apb_pclk";
275 pinctrl-names = "default";
276 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
277 reg-shift = <2>;
278 reg-io-width = <4>;
279 status = "disabled";
280 };
281
282 uart1: serial@11020000 {
283 compatible = "snps,dw-apb-uart";
284 reg = <0x11020000 0x100>;
285 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
286 clock-frequency = <24000000>;
287 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
288 clock-names = "baudclk", "apb_pclk";
289 pinctrl-names = "default";
290 pinctrl-0 = <&uart1_xfer>;
291 reg-shift = <2>;
292 reg-io-width = <4>;
293 status = "disabled";
294 };
295
296 uart2: serial@11030000 {
297 compatible = "snps,dw-apb-uart";
298 reg = <0x11030000 0x100>;
299 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
300 clock-frequency = <24000000>;
301 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
302 clock-names = "baudclk", "apb_pclk";
303 pinctrl-names = "default";
304 pinctrl-0 = <&uart2_xfer>;
305 reg-shift = <2>;
306 reg-io-width = <4>;
307 status = "disabled";
308 };
309
310 efuse: efuse@11040000 {
311 compatible = "rockchip,rk3228-efuse";
312 reg = <0x11040000 0x20>;
313 clocks = <&cru PCLK_EFUSE_256>;
314 clock-names = "pclk_efuse";
315 #address-cells = <1>;
316 #size-cells = <1>;
317
318 /* Data cells */
319 efuse_id: id@7 {
320 reg = <0x7 0x10>;
321 };
322 cpu_leakage: cpu_leakage@17 {
323 reg = <0x17 0x1>;
324 };
325 };
326
327 i2c0: i2c@11050000 {
328 compatible = "rockchip,rk3228-i2c";
329 reg = <0x11050000 0x1000>;
330 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 clock-names = "i2c";
334 clocks = <&cru PCLK_I2C0>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&i2c0_xfer>;
337 status = "disabled";
338 };
339
340 i2c1: i2c@11060000 {
341 compatible = "rockchip,rk3228-i2c";
342 reg = <0x11060000 0x1000>;
343 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clock-names = "i2c";
347 clocks = <&cru PCLK_I2C1>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c1_xfer>;
350 status = "disabled";
351 };
352
353 i2c2: i2c@11070000 {
354 compatible = "rockchip,rk3228-i2c";
355 reg = <0x11070000 0x1000>;
356 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 clock-names = "i2c";
360 clocks = <&cru PCLK_I2C2>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c2_xfer>;
363 status = "disabled";
364 };
365
366 i2c3: i2c@11080000 {
367 compatible = "rockchip,rk3228-i2c";
368 reg = <0x11080000 0x1000>;
369 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 clock-names = "i2c";
373 clocks = <&cru PCLK_I2C3>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c3_xfer>;
376 status = "disabled";
377 };
378
379 spi0: spi@11090000 {
380 compatible = "rockchip,rk3228-spi";
381 reg = <0x11090000 0x1000>;
382 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
386 clock-names = "spiclk", "apb_pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
389 status = "disabled";
390 };
391
392 wdt: watchdog@110a0000 {
393 compatible = "snps,dw-wdt";
394 reg = <0x110a0000 0x100>;
395 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cru PCLK_CPU>;
397 status = "disabled";
398 };
399
400 pwm0: pwm@110b0000 {
401 compatible = "rockchip,rk3288-pwm";
402 reg = <0x110b0000 0x10>;
403 #pwm-cells = <3>;
404 clocks = <&cru PCLK_PWM>;
405 clock-names = "pwm";
406 pinctrl-names = "default";
407 pinctrl-0 = <&pwm0_pin>;
408 status = "disabled";
409 };
410
411 pwm1: pwm@110b0010 {
412 compatible = "rockchip,rk3288-pwm";
413 reg = <0x110b0010 0x10>;
414 #pwm-cells = <3>;
415 clocks = <&cru PCLK_PWM>;
416 clock-names = "pwm";
417 pinctrl-names = "default";
418 pinctrl-0 = <&pwm1_pin>;
419 status = "disabled";
420 };
421
422 pwm2: pwm@110b0020 {
423 compatible = "rockchip,rk3288-pwm";
424 reg = <0x110b0020 0x10>;
425 #pwm-cells = <3>;
426 clocks = <&cru PCLK_PWM>;
427 clock-names = "pwm";
428 pinctrl-names = "default";
429 pinctrl-0 = <&pwm2_pin>;
430 status = "disabled";
431 };
432
433 pwm3: pwm@110b0030 {
434 compatible = "rockchip,rk3288-pwm";
435 reg = <0x110b0030 0x10>;
436 #pwm-cells = <2>;
437 clocks = <&cru PCLK_PWM>;
438 clock-names = "pwm";
439 pinctrl-names = "default";
440 pinctrl-0 = <&pwm3_pin>;
441 status = "disabled";
442 };
443
444 timer: timer@110c0000 {
445 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
446 reg = <0x110c0000 0x20>;
447 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&xin24m>, <&cru PCLK_TIMER>;
449 clock-names = "timer", "pclk";
450 };
451
452 cru: clock-controller@110e0000 {
453 compatible = "rockchip,rk3228-cru";
454 reg = <0x110e0000 0x1000>;
455 rockchip,grf = <&grf>;
456 #clock-cells = <1>;
457 #reset-cells = <1>;
458 assigned-clocks =
459 <&cru PLL_GPLL>, <&cru ARMCLK>,
460 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
461 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
462 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
463 <&cru PCLK_CPU>;
464 assigned-clock-rates =
465 <594000000>, <816000000>,
466 <500000000>, <150000000>,
467 <150000000>, <75000000>,
468 <150000000>, <150000000>,
469 <75000000>;
470 };
471
472 thermal-zones {
473 cpu_thermal: cpu-thermal {
474 polling-delay-passive = <100>; /* milliseconds */
475 polling-delay = <5000>; /* milliseconds */
476
477 thermal-sensors = <&tsadc 0>;
478
479 trips {
480 cpu_alert0: cpu_alert0 {
481 temperature = <70000>; /* millicelsius */
482 hysteresis = <2000>; /* millicelsius */
483 type = "passive";
484 };
485 cpu_alert1: cpu_alert1 {
486 temperature = <75000>; /* millicelsius */
487 hysteresis = <2000>; /* millicelsius */
488 type = "passive";
489 };
490 cpu_crit: cpu_crit {
491 temperature = <90000>; /* millicelsius */
492 hysteresis = <2000>; /* millicelsius */
493 type = "critical";
494 };
495 };
496
497 cooling-maps {
498 map0 {
499 trip = <&cpu_alert0>;
500 cooling-device =
501 <&cpu0 THERMAL_NO_LIMIT 6>,
502 <&cpu1 THERMAL_NO_LIMIT 6>,
503 <&cpu2 THERMAL_NO_LIMIT 6>,
504 <&cpu3 THERMAL_NO_LIMIT 6>;
505 };
506 map1 {
507 trip = <&cpu_alert1>;
508 cooling-device =
509 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
510 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
511 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
512 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
513 };
514 };
515 };
516 };
517
518 tsadc: tsadc@11150000 {
519 compatible = "rockchip,rk3228-tsadc";
520 reg = <0x11150000 0x100>;
521 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
523 clock-names = "tsadc", "apb_pclk";
524 assigned-clocks = <&cru SCLK_TSADC>;
525 assigned-clock-rates = <32768>;
526 resets = <&cru SRST_TSADC>;
527 reset-names = "tsadc-apb";
528 pinctrl-names = "init", "default", "sleep";
529 pinctrl-0 = <&otp_gpio>;
530 pinctrl-1 = <&otp_out>;
531 pinctrl-2 = <&otp_gpio>;
532 #thermal-sensor-cells = <0>;
533 rockchip,hw-tshut-temp = <95000>;
534 status = "disabled";
535 };
536
537 hdmi_phy: hdmi-phy@12030000 {
538 compatible = "rockchip,rk3228-hdmi-phy";
539 reg = <0x12030000 0x10000>;
540 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
541 clock-names = "sysclk", "refoclk", "refpclk";
542 #clock-cells = <0>;
543 clock-output-names = "hdmiphy_phy";
544 #phy-cells = <0>;
545 status = "disabled";
546 };
547
548 gpu: gpu@20000000 {
549 compatible = "rockchip,rk3228-mali", "arm,mali-400";
550 reg = <0x20000000 0x10000>;
551 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "gp",
558 "gpmmu",
559 "pp0",
560 "ppmmu0",
561 "pp1",
562 "ppmmu1";
563 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
564 clock-names = "core", "bus";
565 resets = <&cru SRST_GPU_A>;
566 status = "disabled";
567 };
568
569 vpu_mmu: iommu@20020800 {
570 compatible = "rockchip,iommu";
571 reg = <0x20020800 0x100>;
572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "vpu_mmu";
574 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
575 clock-names = "aclk", "iface";
576 iommu-cells = <0>;
577 status = "disabled";
578 };
579
580 vdec_mmu: iommu@20030480 {
581 compatible = "rockchip,iommu";
582 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
583 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
584 interrupt-names = "vdec_mmu";
585 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
586 clock-names = "aclk", "iface";
587 iommu-cells = <0>;
588 status = "disabled";
589 };
590
591 vop: vop@20050000 {
592 compatible = "rockchip,rk3228-vop";
593 reg = <0x20050000 0x1ffc>;
594 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
596 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
597 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
598 reset-names = "axi", "ahb", "dclk";
599 iommus = <&vop_mmu>;
600 status = "disabled";
601
602 vop_out: port {
603 #address-cells = <1>;
604 #size-cells = <0>;
605
606 vop_out_hdmi: endpoint@0 {
607 reg = <0>;
608 remote-endpoint = <&hdmi_in_vop>;
609 };
610 };
611 };
612
613 vop_mmu: iommu@20053f00 {
614 compatible = "rockchip,iommu";
615 reg = <0x20053f00 0x100>;
616 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "vop_mmu";
618 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
619 clock-names = "aclk", "iface";
620 #iommu-cells = <0>;
621 status = "disabled";
622 };
623
624 iep_mmu: iommu@20070800 {
625 compatible = "rockchip,iommu";
626 reg = <0x20070800 0x100>;
627 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-names = "iep_mmu";
629 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
630 clock-names = "aclk", "iface";
631 iommu-cells = <0>;
632 status = "disabled";
633 };
634
635 hdmi: hdmi@200a0000 {
636 compatible = "rockchip,rk3228-dw-hdmi";
637 reg = <0x200a0000 0x20000>;
638 reg-io-width = <4>;
639 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
640 assigned-clocks = <&cru SCLK_HDMI_PHY>;
641 assigned-clock-parents = <&hdmi_phy>;
642 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
643 clock-names = "isfr", "iahb", "cec";
644 pinctrl-names = "default";
645 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
646 resets = <&cru SRST_HDMI_P>;
647 reset-names = "hdmi";
648 phys = <&hdmi_phy>;
649 phy-names = "hdmi";
650 rockchip,grf = <&grf>;
651 status = "disabled";
652
653 ports {
654 hdmi_in: port {
655 #address-cells = <1>;
656 #size-cells = <0>;
657 hdmi_in_vop: endpoint@0 {
658 reg = <0>;
659 remote-endpoint = <&vop_out_hdmi>;
660 };
661 };
662 };
663 };
664
665 sdmmc: dwmmc@30000000 {
666 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
667 reg = <0x30000000 0x4000>;
668 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
670 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
671 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
672 fifo-depth = <0x100>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
675 status = "disabled";
676 };
677
678 sdio: dwmmc@30010000 {
679 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
680 reg = <0x30010000 0x4000>;
681 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
683 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
684 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
685 fifo-depth = <0x100>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
688 status = "disabled";
689 };
690
691 emmc: dwmmc@30020000 {
692 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
693 reg = <0x30020000 0x4000>;
694 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
695 clock-frequency = <37500000>;
696 max-frequency = <37500000>;
697 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
698 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
699 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
700 bus-width = <8>;
701 default-sample-phase = <158>;
702 fifo-depth = <0x100>;
703 pinctrl-names = "default";
704 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
705 resets = <&cru SRST_EMMC>;
706 reset-names = "reset";
707 status = "disabled";
708 };
709
710 usb_otg: usb@30040000 {
711 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
712 "snps,dwc2";
713 reg = <0x30040000 0x40000>;
714 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cru HCLK_OTG>;
716 clock-names = "otg";
717 dr_mode = "otg";
718 g-np-tx-fifo-size = <16>;
719 g-rx-fifo-size = <280>;
720 g-tx-fifo-size = <256 128 128 64 32 16>;
721 g-use-dma;
722 phys = <&u2phy0_otg>;
723 phy-names = "usb2-phy";
724 status = "disabled";
725 };
726
727 usb_host0_ehci: usb@30080000 {
728 compatible = "generic-ehci";
729 reg = <0x30080000 0x20000>;
730 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
732 clock-names = "usbhost", "utmi";
733 phys = <&u2phy0_host>;
734 phy-names = "usb";
735 status = "disabled";
736 };
737
738 usb_host0_ohci: usb@300a0000 {
739 compatible = "generic-ohci";
740 reg = <0x300a0000 0x20000>;
741 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
743 clock-names = "usbhost", "utmi";
744 phys = <&u2phy0_host>;
745 phy-names = "usb";
746 status = "disabled";
747 };
748
749 usb_host1_ehci: usb@300c0000 {
750 compatible = "generic-ehci";
751 reg = <0x300c0000 0x20000>;
752 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
754 clock-names = "usbhost", "utmi";
755 phys = <&u2phy1_otg>;
756 phy-names = "usb";
757 status = "disabled";
758 };
759
760 usb_host1_ohci: usb@300e0000 {
761 compatible = "generic-ohci";
762 reg = <0x300e0000 0x20000>;
763 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
765 clock-names = "usbhost", "utmi";
766 phys = <&u2phy1_otg>;
767 phy-names = "usb";
768 status = "disabled";
769 };
770
771 usb_host2_ehci: usb@30100000 {
772 compatible = "generic-ehci";
773 reg = <0x30100000 0x20000>;
774 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
776 phys = <&u2phy1_host>;
777 phy-names = "usb";
778 clock-names = "usbhost", "utmi";
779 status = "disabled";
780 };
781
782 usb_host2_ohci: usb@30120000 {
783 compatible = "generic-ohci";
784 reg = <0x30120000 0x20000>;
785 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
787 clock-names = "usbhost", "utmi";
788 phys = <&u2phy1_host>;
789 phy-names = "usb";
790 status = "disabled";
791 };
792
793 gmac: ethernet@30200000 {
794 compatible = "rockchip,rk3228-gmac";
795 reg = <0x30200000 0x10000>;
796 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
797 interrupt-names = "macirq";
798 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
799 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
800 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
801 <&cru PCLK_GMAC>;
802 clock-names = "stmmaceth", "mac_clk_rx",
803 "mac_clk_tx", "clk_mac_ref",
804 "clk_mac_refout", "aclk_mac",
805 "pclk_mac";
806 resets = <&cru SRST_GMAC>;
807 reset-names = "stmmaceth";
808 rockchip,grf = <&grf>;
809 status = "disabled";
810 };
811
812 gic: interrupt-controller@32010000 {
813 compatible = "arm,gic-400";
814 interrupt-controller;
815 #interrupt-cells = <3>;
816 #address-cells = <0>;
817
818 reg = <0x32011000 0x1000>,
819 <0x32012000 0x2000>,
820 <0x32014000 0x2000>,
821 <0x32016000 0x2000>;
822 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
823 };
824
825 pinctrl: pinctrl {
826 compatible = "rockchip,rk3228-pinctrl";
827 rockchip,grf = <&grf>;
828 #address-cells = <1>;
829 #size-cells = <1>;
830 ranges;
831
832 gpio0: gpio0@11110000 {
833 compatible = "rockchip,gpio-bank";
834 reg = <0x11110000 0x100>;
835 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&cru PCLK_GPIO0>;
837
838 gpio-controller;
839 #gpio-cells = <2>;
840
841 interrupt-controller;
842 #interrupt-cells = <2>;
843 };
844
845 gpio1: gpio1@11120000 {
846 compatible = "rockchip,gpio-bank";
847 reg = <0x11120000 0x100>;
848 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&cru PCLK_GPIO1>;
850
851 gpio-controller;
852 #gpio-cells = <2>;
853
854 interrupt-controller;
855 #interrupt-cells = <2>;
856 };
857
858 gpio2: gpio2@11130000 {
859 compatible = "rockchip,gpio-bank";
860 reg = <0x11130000 0x100>;
861 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&cru PCLK_GPIO2>;
863
864 gpio-controller;
865 #gpio-cells = <2>;
866
867 interrupt-controller;
868 #interrupt-cells = <2>;
869 };
870
871 gpio3: gpio3@11140000 {
872 compatible = "rockchip,gpio-bank";
873 reg = <0x11140000 0x100>;
874 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&cru PCLK_GPIO3>;
876
877 gpio-controller;
878 #gpio-cells = <2>;
879
880 interrupt-controller;
881 #interrupt-cells = <2>;
882 };
883
884 pcfg_pull_up: pcfg-pull-up {
885 bias-pull-up;
886 };
887
888 pcfg_pull_down: pcfg-pull-down {
889 bias-pull-down;
890 };
891
892 pcfg_pull_none: pcfg-pull-none {
893 bias-disable;
894 };
895
896 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
897 drive-strength = <12>;
898 };
899
900 sdmmc {
901 sdmmc_clk: sdmmc-clk {
902 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
903 };
904
905 sdmmc_cmd: sdmmc-cmd {
906 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
907 };
908
909 sdmmc_bus4: sdmmc-bus4 {
910 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
911 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
912 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
913 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
914 };
915 };
916
917 sdio {
918 sdio_clk: sdio-clk {
919 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
920 };
921
922 sdio_cmd: sdio-cmd {
923 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
924 };
925
926 sdio_bus4: sdio-bus4 {
927 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
928 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
929 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
930 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
931 };
932 };
933
934 emmc {
935 emmc_clk: emmc-clk {
936 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
937 };
938
939 emmc_cmd: emmc-cmd {
940 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
941 };
942
943 emmc_bus8: emmc-bus8 {
944 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
945 <1 RK_PD1 2 &pcfg_pull_none>,
946 <1 RK_PD2 2 &pcfg_pull_none>,
947 <1 RK_PD3 2 &pcfg_pull_none>,
948 <1 RK_PD4 2 &pcfg_pull_none>,
949 <1 RK_PD5 2 &pcfg_pull_none>,
950 <1 RK_PD6 2 &pcfg_pull_none>,
951 <1 RK_PD7 2 &pcfg_pull_none>;
952 };
953 };
954
955 gmac {
956 rgmii_pins: rgmii-pins {
957 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
958 <2 RK_PB4 1 &pcfg_pull_none>,
959 <2 RK_PD1 1 &pcfg_pull_none>,
960 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
961 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
962 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
963 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
964 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
965 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
966 <2 RK_PC1 1 &pcfg_pull_none>,
967 <2 RK_PC0 1 &pcfg_pull_none>,
968 <2 RK_PC5 2 &pcfg_pull_none>,
969 <2 RK_PC4 2 &pcfg_pull_none>,
970 <2 RK_PB3 1 &pcfg_pull_none>,
971 <2 RK_PB0 1 &pcfg_pull_none>;
972 };
973
974 rmii_pins: rmii-pins {
975 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
976 <2 RK_PB4 1 &pcfg_pull_none>,
977 <2 RK_PD1 1 &pcfg_pull_none>,
978 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
979 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
980 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
981 <2 RK_PC1 1 &pcfg_pull_none>,
982 <2 RK_PC0 1 &pcfg_pull_none>,
983 <2 RK_PB0 1 &pcfg_pull_none>,
984 <2 RK_PB7 1 &pcfg_pull_none>;
985 };
986
987 phy_pins: phy-pins {
988 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
989 <2 RK_PB0 2 &pcfg_pull_none>;
990 };
991 };
992
993 hdmi {
994 hdmi_hpd: hdmi-hpd {
995 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
996 };
997
998 hdmii2c_xfer: hdmii2c-xfer {
999 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1000 <0 RK_PA7 2 &pcfg_pull_none>;
1001 };
1002
1003 hdmi_cec: hdmi-cec {
1004 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1005 };
1006 };
1007
1008 i2c0 {
1009 i2c0_xfer: i2c0-xfer {
1010 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1011 <0 RK_PA1 1 &pcfg_pull_none>;
1012 };
1013 };
1014
1015 i2c1 {
1016 i2c1_xfer: i2c1-xfer {
1017 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1018 <0 RK_PA3 1 &pcfg_pull_none>;
1019 };
1020 };
1021
1022 i2c2 {
1023 i2c2_xfer: i2c2-xfer {
1024 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1025 <2 RK_PC5 1 &pcfg_pull_none>;
1026 };
1027 };
1028
1029 i2c3 {
1030 i2c3_xfer: i2c3-xfer {
1031 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1032 <0 RK_PA7 1 &pcfg_pull_none>;
1033 };
1034 };
1035
1036 spi-0 {
1037 spi0_clk: spi0-clk {
1038 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1039 };
1040 spi0_cs0: spi0-cs0 {
1041 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1042 };
1043 spi0_tx: spi0-tx {
1044 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1045 };
1046 spi0_rx: spi0-rx {
1047 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1048 };
1049 spi0_cs1: spi0-cs1 {
1050 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1051 };
1052 };
1053
1054 spi-1 {
1055 spi1_clk: spi1-clk {
1056 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1057 };
1058 spi1_cs0: spi1-cs0 {
1059 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1060 };
1061 spi1_rx: spi1-rx {
1062 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1063 };
1064 spi1_tx: spi1-tx {
1065 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1066 };
1067 spi1_cs1: spi1-cs1 {
1068 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1069 };
1070 };
1071
1072 i2s1 {
1073 i2s1_bus: i2s1-bus {
1074 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1075 <0 RK_PB1 1 &pcfg_pull_none>,
1076 <0 RK_PB3 1 &pcfg_pull_none>,
1077 <0 RK_PB4 1 &pcfg_pull_none>,
1078 <0 RK_PB5 1 &pcfg_pull_none>,
1079 <0 RK_PB6 1 &pcfg_pull_none>,
1080 <1 RK_PA2 2 &pcfg_pull_none>,
1081 <1 RK_PA4 2 &pcfg_pull_none>,
1082 <1 RK_PA5 2 &pcfg_pull_none>;
1083 };
1084 };
1085
1086 pwm0 {
1087 pwm0_pin: pwm0-pin {
1088 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1089 };
1090 };
1091
1092 pwm1 {
1093 pwm1_pin: pwm1-pin {
1094 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1095 };
1096 };
1097
1098 pwm2 {
1099 pwm2_pin: pwm2-pin {
1100 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1101 };
1102 };
1103
1104 pwm3 {
1105 pwm3_pin: pwm3-pin {
1106 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1107 };
1108 };
1109
1110 spdif {
1111 spdif_tx: spdif-tx {
1112 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1113 };
1114 };
1115
1116 tsadc {
1117 otp_gpio: otp-gpio {
1118 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1119 };
1120
1121 otp_out: otp-out {
1122 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1123 };
1124 };
1125
1126 uart0 {
1127 uart0_xfer: uart0-xfer {
1128 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1129 <2 RK_PD3 1 &pcfg_pull_none>;
1130 };
1131
1132 uart0_cts: uart0-cts {
1133 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1134 };
1135
1136 uart0_rts: uart0-rts {
1137 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1138 };
1139 };
1140
1141 uart1 {
1142 uart1_xfer: uart1-xfer {
1143 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1144 <1 RK_PB2 1 &pcfg_pull_none>;
1145 };
1146
1147 uart1_cts: uart1-cts {
1148 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1149 };
1150
1151 uart1_rts: uart1-rts {
1152 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1153 };
1154 };
1155
1156 uart2 {
1157 uart2_xfer: uart2-xfer {
1158 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1159 <1 RK_PC3 2 &pcfg_pull_none>;
1160 };
1161
1162 uart21_xfer: uart21-xfer {
1163 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1164 <1 RK_PB1 2 &pcfg_pull_none>;
1165 };
1166
1167 uart2_cts: uart2-cts {
1168 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1169 };
1170
1171 uart2_rts: uart2-rts {
1172 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1173 };
1174 };
1175 };
1176};
1/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/pinctrl/rockchip.h>
45#include <dt-bindings/clock/rk3228-cru.h>
46#include <dt-bindings/thermal/thermal.h>
47
48/ {
49 #address-cells = <1>;
50 #size-cells = <1>;
51
52 interrupt-parent = <&gic>;
53
54 aliases {
55 serial0 = &uart0;
56 serial1 = &uart1;
57 serial2 = &uart2;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 cpu0: cpu@f00 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a7";
67 reg = <0xf00>;
68 resets = <&cru SRST_CORE0>;
69 operating-points = <
70 /* KHz uV */
71 816000 1000000
72 >;
73 #cooling-cells = <2>; /* min followed by max */
74 clock-latency = <40000>;
75 clocks = <&cru ARMCLK>;
76 };
77
78 cpu1: cpu@f01 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a7";
81 reg = <0xf01>;
82 resets = <&cru SRST_CORE1>;
83 };
84
85 cpu2: cpu@f02 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a7";
88 reg = <0xf02>;
89 resets = <&cru SRST_CORE2>;
90 };
91
92 cpu3: cpu@f03 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a7";
95 reg = <0xf03>;
96 resets = <&cru SRST_CORE3>;
97 };
98 };
99
100 amba {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges;
105
106 pdma: pdma@110f0000 {
107 compatible = "arm,pl330", "arm,primecell";
108 reg = <0x110f0000 0x4000>;
109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
111 #dma-cells = <1>;
112 clocks = <&cru ACLK_DMAC>;
113 clock-names = "apb_pclk";
114 };
115 };
116
117 arm-pmu {
118 compatible = "arm,cortex-a7-pmu";
119 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
123 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
124 };
125
126 timer {
127 compatible = "arm,armv7-timer";
128 arm,cpu-registers-not-fw-configured;
129 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
130 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
131 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
132 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
133 clock-frequency = <24000000>;
134 };
135
136 xin24m: oscillator {
137 compatible = "fixed-clock";
138 clock-frequency = <24000000>;
139 clock-output-names = "xin24m";
140 #clock-cells = <0>;
141 };
142
143 i2s1: i2s1@100b0000 {
144 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
145 reg = <0x100b0000 0x4000>;
146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 clock-names = "i2s_clk", "i2s_hclk";
150 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
151 dmas = <&pdma 14>, <&pdma 15>;
152 dma-names = "tx", "rx";
153 pinctrl-names = "default";
154 pinctrl-0 = <&i2s1_bus>;
155 status = "disabled";
156 };
157
158 i2s0: i2s0@100c0000 {
159 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
160 reg = <0x100c0000 0x4000>;
161 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 clock-names = "i2s_clk", "i2s_hclk";
165 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
166 dmas = <&pdma 11>, <&pdma 12>;
167 dma-names = "tx", "rx";
168 status = "disabled";
169 };
170
171 i2s2: i2s2@100e0000 {
172 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
173 reg = <0x100e0000 0x4000>;
174 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 clock-names = "i2s_clk", "i2s_hclk";
178 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
179 dmas = <&pdma 0>, <&pdma 1>;
180 dma-names = "tx", "rx";
181 status = "disabled";
182 };
183
184 grf: syscon@11000000 {
185 compatible = "syscon";
186 reg = <0x11000000 0x1000>;
187 };
188
189 uart0: serial@11010000 {
190 compatible = "snps,dw-apb-uart";
191 reg = <0x11010000 0x100>;
192 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
193 clock-frequency = <24000000>;
194 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
195 clock-names = "baudclk", "apb_pclk";
196 pinctrl-names = "default";
197 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
198 reg-shift = <2>;
199 reg-io-width = <4>;
200 status = "disabled";
201 };
202
203 uart1: serial@11020000 {
204 compatible = "snps,dw-apb-uart";
205 reg = <0x11020000 0x100>;
206 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
207 clock-frequency = <24000000>;
208 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
209 clock-names = "baudclk", "apb_pclk";
210 pinctrl-names = "default";
211 pinctrl-0 = <&uart1_xfer>;
212 reg-shift = <2>;
213 reg-io-width = <4>;
214 status = "disabled";
215 };
216
217 uart2: serial@11030000 {
218 compatible = "snps,dw-apb-uart";
219 reg = <0x11030000 0x100>;
220 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
221 clock-frequency = <24000000>;
222 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
223 clock-names = "baudclk", "apb_pclk";
224 pinctrl-names = "default";
225 pinctrl-0 = <&uart2_xfer>;
226 reg-shift = <2>;
227 reg-io-width = <4>;
228 status = "disabled";
229 };
230
231 i2c0: i2c@11050000 {
232 compatible = "rockchip,rk3228-i2c";
233 reg = <0x11050000 0x1000>;
234 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 clock-names = "i2c";
238 clocks = <&cru PCLK_I2C0>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&i2c0_xfer>;
241 status = "disabled";
242 };
243
244 i2c1: i2c@11060000 {
245 compatible = "rockchip,rk3228-i2c";
246 reg = <0x11060000 0x1000>;
247 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
248 #address-cells = <1>;
249 #size-cells = <0>;
250 clock-names = "i2c";
251 clocks = <&cru PCLK_I2C1>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&i2c1_xfer>;
254 status = "disabled";
255 };
256
257 i2c2: i2c@11070000 {
258 compatible = "rockchip,rk3228-i2c";
259 reg = <0x11070000 0x1000>;
260 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
261 #address-cells = <1>;
262 #size-cells = <0>;
263 clock-names = "i2c";
264 clocks = <&cru PCLK_I2C2>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&i2c2_xfer>;
267 status = "disabled";
268 };
269
270 i2c3: i2c@11080000 {
271 compatible = "rockchip,rk3228-i2c";
272 reg = <0x11080000 0x1000>;
273 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
274 #address-cells = <1>;
275 #size-cells = <0>;
276 clock-names = "i2c";
277 clocks = <&cru PCLK_I2C3>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&i2c3_xfer>;
280 status = "disabled";
281 };
282
283 pwm0: pwm@110b0000 {
284 compatible = "rockchip,rk3288-pwm";
285 reg = <0x110b0000 0x10>;
286 #pwm-cells = <3>;
287 clocks = <&cru PCLK_PWM>;
288 clock-names = "pwm";
289 pinctrl-names = "default";
290 pinctrl-0 = <&pwm0_pin>;
291 status = "disabled";
292 };
293
294 pwm1: pwm@110b0010 {
295 compatible = "rockchip,rk3288-pwm";
296 reg = <0x110b0010 0x10>;
297 #pwm-cells = <3>;
298 clocks = <&cru PCLK_PWM>;
299 clock-names = "pwm";
300 pinctrl-names = "default";
301 pinctrl-0 = <&pwm1_pin>;
302 status = "disabled";
303 };
304
305 pwm2: pwm@110b0020 {
306 compatible = "rockchip,rk3288-pwm";
307 reg = <0x110b0020 0x10>;
308 #pwm-cells = <3>;
309 clocks = <&cru PCLK_PWM>;
310 clock-names = "pwm";
311 pinctrl-names = "default";
312 pinctrl-0 = <&pwm2_pin>;
313 status = "disabled";
314 };
315
316 pwm3: pwm@110b0030 {
317 compatible = "rockchip,rk3288-pwm";
318 reg = <0x110b0030 0x10>;
319 #pwm-cells = <2>;
320 clocks = <&cru PCLK_PWM>;
321 clock-names = "pwm";
322 pinctrl-names = "default";
323 pinctrl-0 = <&pwm3_pin>;
324 status = "disabled";
325 };
326
327 timer: timer@110c0000 {
328 compatible = "rockchip,rk3288-timer";
329 reg = <0x110c0000 0x20>;
330 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&xin24m>, <&cru PCLK_TIMER>;
332 clock-names = "timer", "pclk";
333 };
334
335 cru: clock-controller@110e0000 {
336 compatible = "rockchip,rk3228-cru";
337 reg = <0x110e0000 0x1000>;
338 rockchip,grf = <&grf>;
339 #clock-cells = <1>;
340 #reset-cells = <1>;
341 assigned-clocks = <&cru PLL_GPLL>;
342 assigned-clock-rates = <594000000>;
343 };
344
345 thermal-zones {
346 cpu_thermal: cpu-thermal {
347 polling-delay-passive = <100>; /* milliseconds */
348 polling-delay = <5000>; /* milliseconds */
349
350 thermal-sensors = <&tsadc 0>;
351
352 trips {
353 cpu_alert0: cpu_alert0 {
354 temperature = <70000>; /* millicelsius */
355 hysteresis = <2000>; /* millicelsius */
356 type = "passive";
357 };
358 cpu_alert1: cpu_alert1 {
359 temperature = <75000>; /* millicelsius */
360 hysteresis = <2000>; /* millicelsius */
361 type = "passive";
362 };
363 cpu_crit: cpu_crit {
364 temperature = <90000>; /* millicelsius */
365 hysteresis = <2000>; /* millicelsius */
366 type = "critical";
367 };
368 };
369
370 cooling-maps {
371 map0 {
372 trip = <&cpu_alert0>;
373 cooling-device =
374 <&cpu0 THERMAL_NO_LIMIT 6>;
375 };
376 map1 {
377 trip = <&cpu_alert1>;
378 cooling-device =
379 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
380 };
381 };
382 };
383 };
384
385 tsadc: tsadc@11150000 {
386 compatible = "rockchip,rk3228-tsadc";
387 reg = <0x11150000 0x100>;
388 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
390 clock-names = "tsadc", "apb_pclk";
391 resets = <&cru SRST_TSADC>;
392 reset-names = "tsadc-apb";
393 pinctrl-names = "init", "default", "sleep";
394 pinctrl-0 = <&otp_gpio>;
395 pinctrl-1 = <&otp_out>;
396 pinctrl-2 = <&otp_gpio>;
397 #thermal-sensor-cells = <0>;
398 rockchip,hw-tshut-temp = <95000>;
399 status = "disabled";
400 };
401
402 emmc: dwmmc@30020000 {
403 compatible = "rockchip,rk3288-dw-mshc";
404 reg = <0x30020000 0x4000>;
405 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
406 clock-frequency = <37500000>;
407 max-frequency = <37500000>;
408 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
409 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
410 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
411 bus-width = <8>;
412 default-sample-phase = <158>;
413 num-slots = <1>;
414 fifo-depth = <0x100>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
417 status = "disabled";
418 };
419
420 gmac: ethernet@30200000 {
421 compatible = "rockchip,rk3228-gmac";
422 reg = <0x30200000 0x10000>;
423 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
424 interrupt-names = "macirq";
425 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
426 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
427 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
428 <&cru PCLK_GMAC>;
429 clock-names = "stmmaceth", "mac_clk_rx",
430 "mac_clk_tx", "clk_mac_ref",
431 "clk_mac_refout", "aclk_mac",
432 "pclk_mac";
433 resets = <&cru SRST_GMAC>;
434 reset-names = "stmmaceth";
435 rockchip,grf = <&grf>;
436 status = "disabled";
437 };
438
439 gic: interrupt-controller@32010000 {
440 compatible = "arm,gic-400";
441 interrupt-controller;
442 #interrupt-cells = <3>;
443 #address-cells = <0>;
444
445 reg = <0x32011000 0x1000>,
446 <0x32012000 0x1000>,
447 <0x32014000 0x2000>,
448 <0x32016000 0x2000>;
449 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
450 };
451
452 pinctrl: pinctrl {
453 compatible = "rockchip,rk3228-pinctrl";
454 rockchip,grf = <&grf>;
455 #address-cells = <1>;
456 #size-cells = <1>;
457 ranges;
458
459 gpio0: gpio0@11110000 {
460 compatible = "rockchip,gpio-bank";
461 reg = <0x11110000 0x100>;
462 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&cru PCLK_GPIO0>;
464
465 gpio-controller;
466 #gpio-cells = <2>;
467
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 };
471
472 gpio1: gpio1@11120000 {
473 compatible = "rockchip,gpio-bank";
474 reg = <0x11120000 0x100>;
475 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&cru PCLK_GPIO1>;
477
478 gpio-controller;
479 #gpio-cells = <2>;
480
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 };
484
485 gpio2: gpio2@11130000 {
486 compatible = "rockchip,gpio-bank";
487 reg = <0x11130000 0x100>;
488 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&cru PCLK_GPIO2>;
490
491 gpio-controller;
492 #gpio-cells = <2>;
493
494 interrupt-controller;
495 #interrupt-cells = <2>;
496 };
497
498 gpio3: gpio3@11140000 {
499 compatible = "rockchip,gpio-bank";
500 reg = <0x11140000 0x100>;
501 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru PCLK_GPIO3>;
503
504 gpio-controller;
505 #gpio-cells = <2>;
506
507 interrupt-controller;
508 #interrupt-cells = <2>;
509 };
510
511 pcfg_pull_up: pcfg-pull-up {
512 bias-pull-up;
513 };
514
515 pcfg_pull_down: pcfg-pull-down {
516 bias-pull-down;
517 };
518
519 pcfg_pull_none: pcfg-pull-none {
520 bias-disable;
521 };
522
523 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
524 drive-strength = <12>;
525 };
526
527 emmc {
528 emmc_clk: emmc-clk {
529 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
530 };
531
532 emmc_cmd: emmc-cmd {
533 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
534 };
535
536 emmc_bus8: emmc-bus8 {
537 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
538 <1 25 RK_FUNC_2 &pcfg_pull_none>,
539 <1 26 RK_FUNC_2 &pcfg_pull_none>,
540 <1 27 RK_FUNC_2 &pcfg_pull_none>,
541 <1 28 RK_FUNC_2 &pcfg_pull_none>,
542 <1 29 RK_FUNC_2 &pcfg_pull_none>,
543 <1 30 RK_FUNC_2 &pcfg_pull_none>,
544 <1 31 RK_FUNC_2 &pcfg_pull_none>;
545 };
546 };
547
548 gmac {
549 rgmii_pins: rgmii-pins {
550 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
551 <2 12 RK_FUNC_1 &pcfg_pull_none>,
552 <2 25 RK_FUNC_1 &pcfg_pull_none>,
553 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
554 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
555 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
556 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
557 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
558 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
559 <2 17 RK_FUNC_1 &pcfg_pull_none>,
560 <2 16 RK_FUNC_1 &pcfg_pull_none>,
561 <2 21 RK_FUNC_2 &pcfg_pull_none>,
562 <2 20 RK_FUNC_2 &pcfg_pull_none>,
563 <2 11 RK_FUNC_1 &pcfg_pull_none>,
564 <2 8 RK_FUNC_1 &pcfg_pull_none>;
565 };
566
567 rmii_pins: rmii-pins {
568 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
569 <2 12 RK_FUNC_1 &pcfg_pull_none>,
570 <2 25 RK_FUNC_1 &pcfg_pull_none>,
571 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
572 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
573 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
574 <2 17 RK_FUNC_1 &pcfg_pull_none>,
575 <2 16 RK_FUNC_1 &pcfg_pull_none>,
576 <2 8 RK_FUNC_1 &pcfg_pull_none>,
577 <2 15 RK_FUNC_1 &pcfg_pull_none>;
578 };
579
580 phy_pins: phy-pins {
581 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
582 <2 8 RK_FUNC_2 &pcfg_pull_none>;
583 };
584 };
585
586 i2c0 {
587 i2c0_xfer: i2c0-xfer {
588 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
589 <0 1 RK_FUNC_1 &pcfg_pull_none>;
590 };
591 };
592
593 i2c1 {
594 i2c1_xfer: i2c1-xfer {
595 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
596 <0 3 RK_FUNC_1 &pcfg_pull_none>;
597 };
598 };
599
600 i2c2 {
601 i2c2_xfer: i2c2-xfer {
602 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
603 <2 21 RK_FUNC_1 &pcfg_pull_none>;
604 };
605 };
606
607 i2c3 {
608 i2c3_xfer: i2c3-xfer {
609 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
610 <0 7 RK_FUNC_1 &pcfg_pull_none>;
611 };
612 };
613
614 i2s1 {
615 i2s1_bus: i2s1-bus {
616 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
617 <0 9 RK_FUNC_1 &pcfg_pull_none>,
618 <0 11 RK_FUNC_1 &pcfg_pull_none>,
619 <0 12 RK_FUNC_1 &pcfg_pull_none>,
620 <0 13 RK_FUNC_1 &pcfg_pull_none>,
621 <0 14 RK_FUNC_1 &pcfg_pull_none>,
622 <1 2 RK_FUNC_1 &pcfg_pull_none>,
623 <1 4 RK_FUNC_1 &pcfg_pull_none>,
624 <1 5 RK_FUNC_1 &pcfg_pull_none>;
625 };
626 };
627
628 pwm0 {
629 pwm0_pin: pwm0-pin {
630 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
631 };
632 };
633
634 pwm1 {
635 pwm1_pin: pwm1-pin {
636 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
637 };
638 };
639
640 pwm2 {
641 pwm2_pin: pwm2-pin {
642 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
643 };
644 };
645
646 pwm3 {
647 pwm3_pin: pwm3-pin {
648 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
649 };
650 };
651
652 tsadc {
653 otp_gpio: otp-gpio {
654 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
655 };
656
657 otp_out: otp-out {
658 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
659 };
660 };
661
662 uart0 {
663 uart0_xfer: uart0-xfer {
664 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
665 <2 27 RK_FUNC_1 &pcfg_pull_none>;
666 };
667
668 uart0_cts: uart0-cts {
669 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
670 };
671
672 uart0_rts: uart0-rts {
673 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
674 };
675 };
676
677 uart1 {
678 uart1_xfer: uart1-xfer {
679 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
680 <1 10 RK_FUNC_1 &pcfg_pull_none>;
681 };
682
683 uart1_cts: uart1-cts {
684 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
685 };
686
687 uart1_rts: uart1-rts {
688 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
689 };
690 };
691
692 uart2 {
693 uart2_xfer: uart2-xfer {
694 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
695 <1 19 RK_FUNC_2 &pcfg_pull_none>;
696 };
697
698 uart2_cts: uart2-cts {
699 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
700 };
701
702 uart2_rts: uart2-rts {
703 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
704 };
705 };
706 };
707};