1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * Device Tree Source for the SK-RZG1M board
 4 *
 5 * Copyright (C) 2016-2017 Cogent Embedded, Inc.
 
 
 
 
 6 */
 7
 8/dts-v1/;
 9#include "r8a7743.dtsi"
10
11/ {
12	model = "SK-RZG1M";
13	compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
14
15	aliases {
16		serial0 = &scif0;
17	};
18
19	chosen {
20		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
21		stdout-path = "serial0:115200n8";
22	};
23
24	memory@40000000 {
25		device_type = "memory";
26		reg = <0 0x40000000 0 0x40000000>;
27	};
28
29	memory@200000000 {
30		device_type = "memory";
31		reg = <2 0x00000000 0 0x40000000>;
32	};
33};
34
35&extal_clk {
36	clock-frequency = <20000000>;
37};
38
39&pfc {
40	scif0_pins: scif0 {
41		groups = "scif0_data_d";
42		function = "scif0";
43	};
44
45	ether_pins: ether {
46		groups = "eth_link", "eth_mdio", "eth_rmii";
47		function = "eth";
48	};
49
50	phy1_pins: phy1 {
51		groups = "intc_irq0";
52		function = "intc";
53	};
54};
55
56&scif0 {
57	pinctrl-0 = <&scif0_pins>;
58	pinctrl-names = "default";
59
60	status = "okay";
61};
62
63&ether {
64	pinctrl-0 = <&ether_pins &phy1_pins>;
65	pinctrl-names = "default";
66
67	phy-handle = <&phy1>;
68	renesas,ether-link-active-low;
69	status = "okay";
70
71	phy1: ethernet-phy@1 {
72		reg = <1>;
73		interrupt-parent = <&irqc>;
74		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
75		micrel,led-mode = <1>;
76	};
77};

 
 1/*
 2 * Device Tree Source for the SK-RZG1M board
 3 *
 4 * Copyright (C) 2016 Cogent Embedded, Inc.
 5 *
 6 * This file is licensed under the terms of the GNU General Public License
 7 * version 2. This program is licensed "as is" without any warranty of any
 8 * kind, whether express or implied.
 9 */
10
11/dts-v1/;
12#include "r8a7743.dtsi"
13
14/ {
15	model = "SK-RZG1M";
16	compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
17
18	aliases {
19		serial0 = &scif0;
20	};
21
22	chosen {
23		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
24		stdout-path = "serial0:115200n8";
25	};
26
27	memory@40000000 {
28		device_type = "memory";
29		reg = <0 0x40000000 0 0x40000000>;
30	};
31
32	memory@200000000 {
33		device_type = "memory";
34		reg = <2 0x00000000 0 0x40000000>;
35	};
36};
37
38&extal_clk {
39	clock-frequency = <20000000>;
40};
41
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
42&scif0 {
 
 
 
43	status = "okay";
44};
45
46&ether {
 
 
 
47	phy-handle = <&phy1>;
48	renesas,ether-link-active-low;
49	status = "okay";
50
51	phy1: ethernet-phy@1 {
52		reg = <1>;
53		interrupt-parent = <&irqc>;
54		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
55		micrel,led-mode = <1>;
56	};
57};