Loading...
Note: File does not exist in v4.10.11.
1&l4_abe { /* 0x40100000 */
2 compatible = "ti,omap4-l4-abe", "simple-bus";
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
5 reg-names = "la", "ap";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
9 <0x49000000 0x49000000 0x100000>;
10 segment@0 { /* 0x40100000 */
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges =
15 /* CPU to L4 ABE mapping */
16 <0x00000000 0x00000000 0x000400>, /* ap 0 */
17 <0x00000400 0x00000400 0x000400>, /* ap 1 */
18 <0x00022000 0x00022000 0x001000>, /* ap 2 */
19 <0x00023000 0x00023000 0x001000>, /* ap 3 */
20 <0x00024000 0x00024000 0x001000>, /* ap 4 */
21 <0x00025000 0x00025000 0x001000>, /* ap 5 */
22 <0x00026000 0x00026000 0x001000>, /* ap 6 */
23 <0x00027000 0x00027000 0x001000>, /* ap 7 */
24 <0x00028000 0x00028000 0x001000>, /* ap 8 */
25 <0x00029000 0x00029000 0x001000>, /* ap 9 */
26 <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
27 <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
28 <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
29 <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
30 <0x00030000 0x00030000 0x001000>, /* ap 14 */
31 <0x00031000 0x00031000 0x001000>, /* ap 15 */
32 <0x00032000 0x00032000 0x001000>, /* ap 16 */
33 <0x00033000 0x00033000 0x001000>, /* ap 17 */
34 <0x00038000 0x00038000 0x001000>, /* ap 18 */
35 <0x00039000 0x00039000 0x001000>, /* ap 19 */
36 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
37 <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
38 <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
39 <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
40 <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
41 <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
42 <0x00080000 0x00080000 0x010000>, /* ap 26 */
43 <0x00080000 0x00080000 0x001000>, /* ap 27 */
44 <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
45 <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
46 <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
47 <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
48 <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
49 <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
50
51 /* L3 to L4 ABE mapping */
52 <0x49000000 0x49000000 0x000400>, /* ap 0 */
53 <0x49000400 0x49000400 0x000400>, /* ap 1 */
54 <0x49022000 0x49022000 0x001000>, /* ap 2 */
55 <0x49023000 0x49023000 0x001000>, /* ap 3 */
56 <0x49024000 0x49024000 0x001000>, /* ap 4 */
57 <0x49025000 0x49025000 0x001000>, /* ap 5 */
58 <0x49026000 0x49026000 0x001000>, /* ap 6 */
59 <0x49027000 0x49027000 0x001000>, /* ap 7 */
60 <0x49028000 0x49028000 0x001000>, /* ap 8 */
61 <0x49029000 0x49029000 0x001000>, /* ap 9 */
62 <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
63 <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
64 <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
65 <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
66 <0x49030000 0x49030000 0x001000>, /* ap 14 */
67 <0x49031000 0x49031000 0x001000>, /* ap 15 */
68 <0x49032000 0x49032000 0x001000>, /* ap 16 */
69 <0x49033000 0x49033000 0x001000>, /* ap 17 */
70 <0x49038000 0x49038000 0x001000>, /* ap 18 */
71 <0x49039000 0x49039000 0x001000>, /* ap 19 */
72 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
73 <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
74 <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
75 <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
76 <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
77 <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
78 <0x49080000 0x49080000 0x010000>, /* ap 26 */
79 <0x49080000 0x49080000 0x001000>, /* ap 27 */
80 <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
81 <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
82 <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
83 <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
84 <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
85 <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
86
87 target-module@22000 { /* 0x40122000, ap 2 02.0 */
88 compatible = "ti,sysc-omap2", "ti,sysc";
89 ti,hwmods = "mcbsp1";
90 reg = <0x2208c 0x4>;
91 reg-names = "sysc";
92 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
93 SYSC_OMAP2_ENAWAKEUP |
94 SYSC_OMAP2_SOFTRESET)>;
95 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
96 <SYSC_IDLE_NO>,
97 <SYSC_IDLE_SMART>;
98 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
99 clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
100 clock-names = "fck";
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges = <0x0 0x22000 0x1000>,
104 <0x49022000 0x49022000 0x1000>;
105
106 mcbsp1: mcbsp@0 {
107 compatible = "ti,omap4-mcbsp";
108 reg = <0x0 0xff>, /* MPU private access */
109 <0x49022000 0xff>; /* L3 Interconnect */
110 reg-names = "mpu", "dma";
111 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-names = "common";
113 ti,buffer-size = <128>;
114 dmas = <&sdma 33>,
115 <&sdma 34>;
116 dma-names = "tx", "rx";
117 status = "disabled";
118 };
119 };
120
121 target-module@24000 { /* 0x40124000, ap 4 04.0 */
122 compatible = "ti,sysc-omap2", "ti,sysc";
123 ti,hwmods = "mcbsp2";
124 reg = <0x2408c 0x4>;
125 reg-names = "sysc";
126 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
127 SYSC_OMAP2_ENAWAKEUP |
128 SYSC_OMAP2_SOFTRESET)>;
129 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
130 <SYSC_IDLE_NO>,
131 <SYSC_IDLE_SMART>;
132 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
133 clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
134 clock-names = "fck";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges = <0x0 0x24000 0x1000>,
138 <0x49024000 0x49024000 0x1000>;
139
140 mcbsp2: mcbsp@0 {
141 compatible = "ti,omap4-mcbsp";
142 reg = <0x0 0xff>, /* MPU private access */
143 <0x49024000 0xff>; /* L3 Interconnect */
144 reg-names = "mpu", "dma";
145 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-names = "common";
147 ti,buffer-size = <128>;
148 dmas = <&sdma 17>,
149 <&sdma 18>;
150 dma-names = "tx", "rx";
151 status = "disabled";
152 };
153 };
154
155 target-module@26000 { /* 0x40126000, ap 6 06.0 */
156 compatible = "ti,sysc-omap2", "ti,sysc";
157 ti,hwmods = "mcbsp3";
158 reg = <0x2608c 0x4>;
159 reg-names = "sysc";
160 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
161 SYSC_OMAP2_ENAWAKEUP |
162 SYSC_OMAP2_SOFTRESET)>;
163 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
164 <SYSC_IDLE_NO>,
165 <SYSC_IDLE_SMART>;
166 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
167 clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
168 clock-names = "fck";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0x26000 0x1000>,
172 <0x49026000 0x49026000 0x1000>;
173
174 mcbsp3: mcbsp@0 {
175 compatible = "ti,omap4-mcbsp";
176 reg = <0x0 0xff>, /* MPU private access */
177 <0x49026000 0xff>; /* L3 Interconnect */
178 reg-names = "mpu", "dma";
179 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "common";
181 ti,buffer-size = <128>;
182 dmas = <&sdma 19>,
183 <&sdma 20>;
184 dma-names = "tx", "rx";
185 status = "disabled";
186 };
187 };
188
189 target-module@28000 { /* 0x40128000, ap 8 08.0 */
190 compatible = "ti,sysc-mcasp", "ti,sysc";
191 ti,hwmods = "mcasp";
192 reg = <0x28000 0x4>,
193 <0x28004 0x4>;
194 reg-names = "rev", "sysc";
195 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
196 <SYSC_IDLE_NO>,
197 <SYSC_IDLE_SMART>,
198 <SYSC_IDLE_SMART_WKUP>;
199 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
200 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
201 clock-names = "fck";
202 #address-cells = <1>;
203 #size-cells = <1>;
204 ranges = <0x0 0x28000 0x1000>,
205 <0x49028000 0x49028000 0x1000>;
206
207 /*
208 * Child device unsupported by davinci-mcasp. At least
209 * RX path is disabled for omap4, and only DIT mode
210 * works with no I2S. See also old Android kernel
211 * omap-mcasp driver for more information.
212 */
213 };
214
215 target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
216 compatible = "ti,sysc";
217 status = "disabled";
218 #address-cells = <1>;
219 #size-cells = <1>;
220 ranges = <0x0 0x2a000 0x1000>,
221 <0x4902a000 0x4902a000 0x1000>;
222 };
223
224 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
225 compatible = "ti,sysc-omap4", "ti,sysc";
226 ti,hwmods = "dmic";
227 reg = <0x2e000 0x4>,
228 <0x2e010 0x4>;
229 reg-names = "rev", "sysc";
230 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
231 SYSC_OMAP4_SOFTRESET)>;
232 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
233 <SYSC_IDLE_NO>,
234 <SYSC_IDLE_SMART>,
235 <SYSC_IDLE_SMART_WKUP>;
236 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
237 clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
238 clock-names = "fck";
239 #address-cells = <1>;
240 #size-cells = <1>;
241 ranges = <0x0 0x2e000 0x1000>,
242 <0x4902e000 0x4902e000 0x1000>;
243
244 dmic: dmic@0 {
245 compatible = "ti,omap4-dmic";
246 reg = <0x0 0x7f>, /* MPU private access */
247 <0x4902e000 0x7f>; /* L3 Interconnect */
248 reg-names = "mpu", "dma";
249 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
250 dmas = <&sdma 67>;
251 dma-names = "up_link";
252 status = "disabled";
253 };
254 };
255
256 target-module@30000 { /* 0x40130000, ap 14 0e.0 */
257 compatible = "ti,sysc-omap2", "ti,sysc";
258 reg = <0x30000 0x4>,
259 <0x30010 0x4>,
260 <0x30014 0x4>;
261 reg-names = "rev", "sysc", "syss";
262 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
263 SYSC_OMAP2_SOFTRESET)>;
264 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
265 <SYSC_IDLE_NO>,
266 <SYSC_IDLE_SMART>,
267 <SYSC_IDLE_SMART_WKUP>;
268 ti,syss-mask = <1>;
269 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
270 clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
271 clock-names = "fck";
272 #address-cells = <1>;
273 #size-cells = <1>;
274 ranges = <0x0 0x30000 0x1000>,
275 <0x49030000 0x49030000 0x1000>;
276
277 wdt3: wdt@0 {
278 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
279 reg = <0x0 0x80>;
280 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
281 };
282 };
283
284 mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
285 compatible = "ti,sysc-omap4", "ti,sysc";
286 ti,hwmods = "mcpdm";
287 reg = <0x32000 0x4>,
288 <0x32010 0x4>;
289 reg-names = "rev", "sysc";
290 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
291 SYSC_OMAP4_SOFTRESET)>;
292 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
293 <SYSC_IDLE_NO>,
294 <SYSC_IDLE_SMART>,
295 <SYSC_IDLE_SMART_WKUP>;
296 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
297 clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
298 clock-names = "fck";
299 #address-cells = <1>;
300 #size-cells = <1>;
301 ranges = <0x0 0x32000 0x1000>,
302 <0x49032000 0x49032000 0x1000>;
303
304 /* Must be only enabled for boards with pdmclk wired */
305 status = "disabled";
306
307 mcpdm: mcpdm@0 {
308 compatible = "ti,omap4-mcpdm";
309 reg = <0x0 0x7f>, /* MPU private access */
310 <0x49032000 0x7f>; /* L3 Interconnect */
311 reg-names = "mpu", "dma";
312 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
313 dmas = <&sdma 65>,
314 <&sdma 66>;
315 dma-names = "up_link", "dn_link";
316 };
317 };
318
319 target-module@38000 { /* 0x40138000, ap 18 12.0 */
320 compatible = "ti,sysc-omap4-timer", "ti,sysc";
321 ti,hwmods = "timer5";
322 reg = <0x38000 0x4>,
323 <0x38010 0x4>;
324 reg-names = "rev", "sysc";
325 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
326 SYSC_OMAP4_SOFTRESET)>;
327 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
328 <SYSC_IDLE_NO>,
329 <SYSC_IDLE_SMART>,
330 <SYSC_IDLE_SMART_WKUP>;
331 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
332 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
333 clock-names = "fck";
334 #address-cells = <1>;
335 #size-cells = <1>;
336 ranges = <0x0 0x38000 0x1000>,
337 <0x49038000 0x49038000 0x1000>;
338
339 timer5: timer@0 {
340 compatible = "ti,omap4430-timer";
341 reg = <0x00000000 0x80>,
342 <0x49038000 0x80>;
343 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
344 clock-names = "fck";
345 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
346 ti,timer-dsp;
347 };
348 };
349
350 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
351 compatible = "ti,sysc-omap4-timer", "ti,sysc";
352 ti,hwmods = "timer6";
353 reg = <0x3a000 0x4>,
354 <0x3a010 0x4>;
355 reg-names = "rev", "sysc";
356 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
357 SYSC_OMAP4_SOFTRESET)>;
358 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
359 <SYSC_IDLE_NO>,
360 <SYSC_IDLE_SMART>,
361 <SYSC_IDLE_SMART_WKUP>;
362 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
363 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
364 clock-names = "fck";
365 #address-cells = <1>;
366 #size-cells = <1>;
367 ranges = <0x0 0x3a000 0x1000>,
368 <0x4903a000 0x4903a000 0x1000>;
369
370 timer6: timer@0 {
371 compatible = "ti,omap4430-timer";
372 reg = <0x00000000 0x80>,
373 <0x4903a000 0x80>;
374 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
375 clock-names = "fck";
376 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
377 ti,timer-dsp;
378 };
379 };
380
381 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
382 compatible = "ti,sysc-omap4-timer", "ti,sysc";
383 ti,hwmods = "timer7";
384 reg = <0x3c000 0x4>,
385 <0x3c010 0x4>;
386 reg-names = "rev", "sysc";
387 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
388 SYSC_OMAP4_SOFTRESET)>;
389 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
390 <SYSC_IDLE_NO>,
391 <SYSC_IDLE_SMART>,
392 <SYSC_IDLE_SMART_WKUP>;
393 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
394 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
395 clock-names = "fck";
396 #address-cells = <1>;
397 #size-cells = <1>;
398 ranges = <0x0 0x3c000 0x1000>,
399 <0x4903c000 0x4903c000 0x1000>;
400
401 timer7: timer@0 {
402 compatible = "ti,omap4430-timer";
403 reg = <0x00000000 0x80>,
404 <0x4903c000 0x80>;
405 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
406 clock-names = "fck";
407 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
408 ti,timer-dsp;
409 };
410 };
411
412 target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
413 compatible = "ti,sysc-omap4-timer", "ti,sysc";
414 ti,hwmods = "timer8";
415 reg = <0x3e000 0x4>,
416 <0x3e010 0x4>;
417 reg-names = "rev", "sysc";
418 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
419 SYSC_OMAP4_SOFTRESET)>;
420 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
421 <SYSC_IDLE_NO>,
422 <SYSC_IDLE_SMART>,
423 <SYSC_IDLE_SMART_WKUP>;
424 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
425 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
426 clock-names = "fck";
427 #address-cells = <1>;
428 #size-cells = <1>;
429 ranges = <0x0 0x3e000 0x1000>,
430 <0x4903e000 0x4903e000 0x1000>;
431
432 timer8: timer@0 {
433 compatible = "ti,omap4430-timer";
434 reg = <0x00000000 0x80>,
435 <0x4903e000 0x80>;
436 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
437 clock-names = "fck";
438 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
439 ti,timer-pwm;
440 ti,timer-dsp;
441 };
442 };
443
444 target-module@80000 { /* 0x40180000, ap 26 1a.0 */
445 compatible = "ti,sysc";
446 status = "disabled";
447 #address-cells = <1>;
448 #size-cells = <1>;
449 ranges = <0x0 0x80000 0x10000>,
450 <0x49080000 0x49080000 0x10000>;
451 };
452
453 target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
454 compatible = "ti,sysc";
455 status = "disabled";
456 #address-cells = <1>;
457 #size-cells = <1>;
458 ranges = <0x0 0xa0000 0x10000>,
459 <0x490a0000 0x490a0000 0x10000>;
460 };
461
462 target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
463 compatible = "ti,sysc";
464 status = "disabled";
465 #address-cells = <1>;
466 #size-cells = <1>;
467 ranges = <0x0 0xc0000 0x10000>,
468 <0x490c0000 0x490c0000 0x10000>;
469 };
470
471 target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
472 compatible = "ti,sysc-omap4", "ti,sysc";
473 ti,hwmods = "aess";
474 reg = <0xf1000 0x4>,
475 <0xf1010 0x4>;
476 reg-names = "rev", "sysc";
477 ti,sysc-midle = <SYSC_IDLE_FORCE>,
478 <SYSC_IDLE_NO>,
479 <SYSC_IDLE_SMART>,
480 <SYSC_IDLE_SMART_WKUP>;
481 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
482 <SYSC_IDLE_NO>,
483 <SYSC_IDLE_SMART>;
484 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
485 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
486 clock-names = "fck";
487 #address-cells = <1>;
488 #size-cells = <1>;
489 ranges = <0x0 0xf1000 0x1000>,
490 <0x490f1000 0x490f1000 0x1000>;
491
492 /*
493 * No child device binding or driver in mainline.
494 * See Android tree and related upstreaming efforts
495 * for the old driver.
496 */
497 };
498 };
499};
500