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1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/clock/imx6ul-clock.h>
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include "imx6ul-pinfunc.h"
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 /*
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
18 */
19 chosen {};
20
21 aliases {
22 ethernet0 = &fec1;
23 ethernet1 = &fec2;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
32 i2c3 = &i2c4;
33 mmc0 = &usdhc1;
34 mmc1 = &usdhc2;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 serial4 = &uart5;
40 serial5 = &uart6;
41 serial6 = &uart7;
42 serial7 = &uart8;
43 sai1 = &sai1;
44 sai2 = &sai2;
45 sai3 = &sai3;
46 spi0 = &ecspi1;
47 spi1 = &ecspi2;
48 spi2 = &ecspi3;
49 spi3 = &ecspi4;
50 usbphy0 = &usbphy1;
51 usbphy1 = &usbphy2;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu0: cpu@0 {
59 compatible = "arm,cortex-a7";
60 device_type = "cpu";
61 reg = <0>;
62 clock-frequency = <696000000>;
63 clock-latency = <61036>; /* two CLK32 periods */
64 #cooling-cells = <2>;
65 operating-points = <
66 /* kHz uV */
67 696000 1275000
68 528000 1175000
69 396000 1025000
70 198000 950000
71 >;
72 fsl,soc-operating-points = <
73 /* KHz uV */
74 696000 1275000
75 528000 1175000
76 396000 1175000
77 198000 1175000
78 >;
79 clocks = <&clks IMX6UL_CLK_ARM>,
80 <&clks IMX6UL_CLK_PLL2_BUS>,
81 <&clks IMX6UL_CLK_PLL2_PFD2>,
82 <&clks IMX6UL_CA7_SECONDARY_SEL>,
83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
85 <&clks IMX6UL_CLK_PLL1_SYS>;
86 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
87 "secondary_sel", "step", "pll1_sw",
88 "pll1_sys";
89 arm-supply = <®_arm>;
90 soc-supply = <®_soc>;
91 nvmem-cells = <&cpu_speed_grade>;
92 nvmem-cell-names = "speed_grade";
93 };
94 };
95
96 timer {
97 compatible = "arm,armv7-timer";
98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
102 interrupt-parent = <&intc>;
103 status = "disabled";
104 };
105
106 ckil: clock-cli {
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <32768>;
110 clock-output-names = "ckil";
111 };
112
113 osc: clock-osc {
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 clock-frequency = <24000000>;
117 clock-output-names = "osc";
118 };
119
120 ipp_di0: clock-di0 {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <0>;
124 clock-output-names = "ipp_di0";
125 };
126
127 ipp_di1: clock-di1 {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <0>;
131 clock-output-names = "ipp_di1";
132 };
133
134 tempmon: tempmon {
135 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
136 interrupt-parent = <&gpc>;
137 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
138 fsl,tempmon = <&anatop>;
139 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
140 nvmem-cell-names = "calib", "temp_grade";
141 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
142 };
143
144 pmu {
145 compatible = "arm,cortex-a7-pmu";
146 interrupt-parent = <&gpc>;
147 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
148 };
149
150 soc {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "simple-bus";
154 interrupt-parent = <&gpc>;
155 ranges;
156
157 ocram: sram@900000 {
158 compatible = "mmio-sram";
159 reg = <0x00900000 0x20000>;
160 };
161
162 intc: interrupt-controller@a01000 {
163 compatible = "arm,gic-400", "arm,cortex-a7-gic";
164 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
165 #interrupt-cells = <3>;
166 interrupt-controller;
167 interrupt-parent = <&intc>;
168 reg = <0x00a01000 0x1000>,
169 <0x00a02000 0x2000>,
170 <0x00a04000 0x2000>,
171 <0x00a06000 0x2000>;
172 };
173
174 dma_apbh: dma-apbh@1804000 {
175 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
176 reg = <0x01804000 0x2000>;
177 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
178 <0 13 IRQ_TYPE_LEVEL_HIGH>,
179 <0 13 IRQ_TYPE_LEVEL_HIGH>,
180 <0 13 IRQ_TYPE_LEVEL_HIGH>;
181 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
182 #dma-cells = <1>;
183 dma-channels = <4>;
184 clocks = <&clks IMX6UL_CLK_APBHDMA>;
185 };
186
187 gpmi: gpmi-nand@1806000 {
188 compatible = "fsl,imx6q-gpmi-nand";
189 #address-cells = <1>;
190 #size-cells = <1>;
191 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
192 reg-names = "gpmi-nand", "bch";
193 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
194 interrupt-names = "bch";
195 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
196 <&clks IMX6UL_CLK_GPMI_APB>,
197 <&clks IMX6UL_CLK_GPMI_BCH>,
198 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
199 <&clks IMX6UL_CLK_PER_BCH>;
200 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
201 "gpmi_bch_apb", "per1_bch";
202 dmas = <&dma_apbh 0>;
203 dma-names = "rx-tx";
204 status = "disabled";
205 };
206
207 aips1: aips-bus@2000000 {
208 compatible = "fsl,aips-bus", "simple-bus";
209 #address-cells = <1>;
210 #size-cells = <1>;
211 reg = <0x02000000 0x100000>;
212 ranges;
213
214 spba-bus@2000000 {
215 compatible = "fsl,spba-bus", "simple-bus";
216 #address-cells = <1>;
217 #size-cells = <1>;
218 reg = <0x02000000 0x40000>;
219 ranges;
220
221 ecspi1: spi@2008000 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
225 reg = <0x02008000 0x4000>;
226 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks IMX6UL_CLK_ECSPI1>,
228 <&clks IMX6UL_CLK_ECSPI1>;
229 clock-names = "ipg", "per";
230 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
231 dma-names = "rx", "tx";
232 status = "disabled";
233 };
234
235 ecspi2: spi@200c000 {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
239 reg = <0x0200c000 0x4000>;
240 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clks IMX6UL_CLK_ECSPI2>,
242 <&clks IMX6UL_CLK_ECSPI2>;
243 clock-names = "ipg", "per";
244 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
245 dma-names = "rx", "tx";
246 status = "disabled";
247 };
248
249 ecspi3: spi@2010000 {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
253 reg = <0x02010000 0x4000>;
254 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clks IMX6UL_CLK_ECSPI3>,
256 <&clks IMX6UL_CLK_ECSPI3>;
257 clock-names = "ipg", "per";
258 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
259 dma-names = "rx", "tx";
260 status = "disabled";
261 };
262
263 ecspi4: spi@2014000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02014000 0x4000>;
268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6UL_CLK_ECSPI4>,
270 <&clks IMX6UL_CLK_ECSPI4>;
271 clock-names = "ipg", "per";
272 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
273 dma-names = "rx", "tx";
274 status = "disabled";
275 };
276
277 uart7: serial@2018000 {
278 compatible = "fsl,imx6ul-uart",
279 "fsl,imx6q-uart";
280 reg = <0x02018000 0x4000>;
281 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
283 <&clks IMX6UL_CLK_UART7_SERIAL>;
284 clock-names = "ipg", "per";
285 status = "disabled";
286 };
287
288 uart1: serial@2020000 {
289 compatible = "fsl,imx6ul-uart",
290 "fsl,imx6q-uart";
291 reg = <0x02020000 0x4000>;
292 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
294 <&clks IMX6UL_CLK_UART1_SERIAL>;
295 clock-names = "ipg", "per";
296 status = "disabled";
297 };
298
299 uart8: serial@2024000 {
300 compatible = "fsl,imx6ul-uart",
301 "fsl,imx6q-uart";
302 reg = <0x02024000 0x4000>;
303 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
305 <&clks IMX6UL_CLK_UART8_SERIAL>;
306 clock-names = "ipg", "per";
307 status = "disabled";
308 };
309
310 sai1: sai@2028000 {
311 #sound-dai-cells = <0>;
312 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
313 reg = <0x02028000 0x4000>;
314 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
316 <&clks IMX6UL_CLK_SAI1>,
317 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
318 clock-names = "bus", "mclk1", "mclk2", "mclk3";
319 dmas = <&sdma 35 24 0>,
320 <&sdma 36 24 0>;
321 dma-names = "rx", "tx";
322 status = "disabled";
323 };
324
325 sai2: sai@202c000 {
326 #sound-dai-cells = <0>;
327 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
328 reg = <0x0202c000 0x4000>;
329 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
331 <&clks IMX6UL_CLK_SAI2>,
332 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
333 clock-names = "bus", "mclk1", "mclk2", "mclk3";
334 dmas = <&sdma 37 24 0>,
335 <&sdma 38 24 0>;
336 dma-names = "rx", "tx";
337 status = "disabled";
338 };
339
340 sai3: sai@2030000 {
341 #sound-dai-cells = <0>;
342 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
343 reg = <0x02030000 0x4000>;
344 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
346 <&clks IMX6UL_CLK_SAI3>,
347 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
348 clock-names = "bus", "mclk1", "mclk2", "mclk3";
349 dmas = <&sdma 39 24 0>,
350 <&sdma 40 24 0>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
354 };
355
356 tsc: tsc@2040000 {
357 compatible = "fsl,imx6ul-tsc";
358 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
359 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks IMX6UL_CLK_IPG>,
362 <&clks IMX6UL_CLK_ADC2>;
363 clock-names = "tsc", "adc";
364 status = "disabled";
365 };
366
367 pwm1: pwm@2080000 {
368 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
369 reg = <0x02080000 0x4000>;
370 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks IMX6UL_CLK_PWM1>,
372 <&clks IMX6UL_CLK_PWM1>;
373 clock-names = "ipg", "per";
374 #pwm-cells = <2>;
375 status = "disabled";
376 };
377
378 pwm2: pwm@2084000 {
379 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
380 reg = <0x02084000 0x4000>;
381 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clks IMX6UL_CLK_PWM2>,
383 <&clks IMX6UL_CLK_PWM2>;
384 clock-names = "ipg", "per";
385 #pwm-cells = <2>;
386 status = "disabled";
387 };
388
389 pwm3: pwm@2088000 {
390 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
391 reg = <0x02088000 0x4000>;
392 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clks IMX6UL_CLK_PWM3>,
394 <&clks IMX6UL_CLK_PWM3>;
395 clock-names = "ipg", "per";
396 #pwm-cells = <2>;
397 status = "disabled";
398 };
399
400 pwm4: pwm@208c000 {
401 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
402 reg = <0x0208c000 0x4000>;
403 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clks IMX6UL_CLK_PWM4>,
405 <&clks IMX6UL_CLK_PWM4>;
406 clock-names = "ipg", "per";
407 #pwm-cells = <2>;
408 status = "disabled";
409 };
410
411 can1: flexcan@2090000 {
412 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
413 reg = <0x02090000 0x4000>;
414 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
416 <&clks IMX6UL_CLK_CAN1_SERIAL>;
417 clock-names = "ipg", "per";
418 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
419 status = "disabled";
420 };
421
422 can2: flexcan@2094000 {
423 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
424 reg = <0x02094000 0x4000>;
425 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
427 <&clks IMX6UL_CLK_CAN2_SERIAL>;
428 clock-names = "ipg", "per";
429 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
430 status = "disabled";
431 };
432
433 gpt1: gpt@2098000 {
434 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
435 reg = <0x02098000 0x4000>;
436 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
438 <&clks IMX6UL_CLK_GPT1_SERIAL>;
439 clock-names = "ipg", "per";
440 };
441
442 gpio1: gpio@209c000 {
443 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
444 reg = <0x0209c000 0x4000>;
445 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&clks IMX6UL_CLK_GPIO1>;
448 gpio-controller;
449 #gpio-cells = <2>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
453 <&iomuxc 16 33 16>;
454 };
455
456 gpio2: gpio@20a0000 {
457 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
458 reg = <0x020a0000 0x4000>;
459 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX6UL_CLK_GPIO2>;
462 gpio-controller;
463 #gpio-cells = <2>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
467 };
468
469 gpio3: gpio@20a4000 {
470 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
471 reg = <0x020a4000 0x4000>;
472 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clks IMX6UL_CLK_GPIO3>;
475 gpio-controller;
476 #gpio-cells = <2>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 gpio-ranges = <&iomuxc 0 65 29>;
480 };
481
482 gpio4: gpio@20a8000 {
483 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
484 reg = <0x020a8000 0x4000>;
485 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clks IMX6UL_CLK_GPIO4>;
488 gpio-controller;
489 #gpio-cells = <2>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
493 };
494
495 gpio5: gpio@20ac000 {
496 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
497 reg = <0x020ac000 0x4000>;
498 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&clks IMX6UL_CLK_GPIO5>;
501 gpio-controller;
502 #gpio-cells = <2>;
503 interrupt-controller;
504 #interrupt-cells = <2>;
505 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
506 };
507
508 fec2: ethernet@20b4000 {
509 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
510 reg = <0x020b4000 0x4000>;
511 interrupt-names = "int0", "pps";
512 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clks IMX6UL_CLK_ENET>,
515 <&clks IMX6UL_CLK_ENET_AHB>,
516 <&clks IMX6UL_CLK_ENET_PTP>,
517 <&clks IMX6UL_CLK_ENET2_REF_125M>,
518 <&clks IMX6UL_CLK_ENET2_REF_125M>;
519 clock-names = "ipg", "ahb", "ptp",
520 "enet_clk_ref", "enet_out";
521 fsl,num-tx-queues = <1>;
522 fsl,num-rx-queues = <1>;
523 status = "disabled";
524 };
525
526 kpp: kpp@20b8000 {
527 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
528 reg = <0x020b8000 0x4000>;
529 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&clks IMX6UL_CLK_KPP>;
531 status = "disabled";
532 };
533
534 wdog1: wdog@20bc000 {
535 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
536 reg = <0x020bc000 0x4000>;
537 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&clks IMX6UL_CLK_WDOG1>;
539 };
540
541 wdog2: wdog@20c0000 {
542 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
543 reg = <0x020c0000 0x4000>;
544 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clks IMX6UL_CLK_WDOG2>;
546 status = "disabled";
547 };
548
549 clks: ccm@20c4000 {
550 compatible = "fsl,imx6ul-ccm";
551 reg = <0x020c4000 0x4000>;
552 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
554 #clock-cells = <1>;
555 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
556 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
557 };
558
559 anatop: anatop@20c8000 {
560 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
561 "syscon", "simple-bus";
562 reg = <0x020c8000 0x1000>;
563 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
566
567 reg_3p0: regulator-3p0 {
568 compatible = "fsl,anatop-regulator";
569 regulator-name = "vdd3p0";
570 regulator-min-microvolt = <2625000>;
571 regulator-max-microvolt = <3400000>;
572 anatop-reg-offset = <0x120>;
573 anatop-vol-bit-shift = <8>;
574 anatop-vol-bit-width = <5>;
575 anatop-min-bit-val = <0>;
576 anatop-min-voltage = <2625000>;
577 anatop-max-voltage = <3400000>;
578 anatop-enable-bit = <0>;
579 };
580
581 reg_arm: regulator-vddcore {
582 compatible = "fsl,anatop-regulator";
583 regulator-name = "cpu";
584 regulator-min-microvolt = <725000>;
585 regulator-max-microvolt = <1450000>;
586 regulator-always-on;
587 anatop-reg-offset = <0x140>;
588 anatop-vol-bit-shift = <0>;
589 anatop-vol-bit-width = <5>;
590 anatop-delay-reg-offset = <0x170>;
591 anatop-delay-bit-shift = <24>;
592 anatop-delay-bit-width = <2>;
593 anatop-min-bit-val = <1>;
594 anatop-min-voltage = <725000>;
595 anatop-max-voltage = <1450000>;
596 };
597
598 reg_soc: regulator-vddsoc {
599 compatible = "fsl,anatop-regulator";
600 regulator-name = "vddsoc";
601 regulator-min-microvolt = <725000>;
602 regulator-max-microvolt = <1450000>;
603 regulator-always-on;
604 anatop-reg-offset = <0x140>;
605 anatop-vol-bit-shift = <18>;
606 anatop-vol-bit-width = <5>;
607 anatop-delay-reg-offset = <0x170>;
608 anatop-delay-bit-shift = <28>;
609 anatop-delay-bit-width = <2>;
610 anatop-min-bit-val = <1>;
611 anatop-min-voltage = <725000>;
612 anatop-max-voltage = <1450000>;
613 };
614 };
615
616 usbphy1: usbphy@20c9000 {
617 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
618 reg = <0x020c9000 0x1000>;
619 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&clks IMX6UL_CLK_USBPHY1>;
621 phy-3p0-supply = <®_3p0>;
622 fsl,anatop = <&anatop>;
623 };
624
625 usbphy2: usbphy@20ca000 {
626 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
627 reg = <0x020ca000 0x1000>;
628 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clks IMX6UL_CLK_USBPHY2>;
630 phy-3p0-supply = <®_3p0>;
631 fsl,anatop = <&anatop>;
632 };
633
634 snvs: snvs@20cc000 {
635 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
636 reg = <0x020cc000 0x4000>;
637
638 snvs_rtc: snvs-rtc-lp {
639 compatible = "fsl,sec-v4.0-mon-rtc-lp";
640 regmap = <&snvs>;
641 offset = <0x34>;
642 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
644 };
645
646 snvs_poweroff: snvs-poweroff {
647 compatible = "syscon-poweroff";
648 regmap = <&snvs>;
649 offset = <0x38>;
650 value = <0x60>;
651 mask = <0x60>;
652 status = "disabled";
653 };
654
655 snvs_pwrkey: snvs-powerkey {
656 compatible = "fsl,sec-v4.0-pwrkey";
657 regmap = <&snvs>;
658 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
659 linux,keycode = <KEY_POWER>;
660 wakeup-source;
661 status = "disabled";
662 };
663
664 snvs_lpgpr: snvs-lpgpr {
665 compatible = "fsl,imx6ul-snvs-lpgpr";
666 };
667 };
668
669 epit1: epit@20d0000 {
670 reg = <0x020d0000 0x4000>;
671 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
672 };
673
674 epit2: epit@20d4000 {
675 reg = <0x020d4000 0x4000>;
676 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
677 };
678
679 src: src@20d8000 {
680 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
681 reg = <0x020d8000 0x4000>;
682 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
684 #reset-cells = <1>;
685 };
686
687 gpc: gpc@20dc000 {
688 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
689 reg = <0x020dc000 0x4000>;
690 interrupt-controller;
691 #interrupt-cells = <3>;
692 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
693 interrupt-parent = <&intc>;
694 };
695
696 iomuxc: iomuxc@20e0000 {
697 compatible = "fsl,imx6ul-iomuxc";
698 reg = <0x020e0000 0x4000>;
699 };
700
701 gpr: iomuxc-gpr@20e4000 {
702 compatible = "fsl,imx6ul-iomuxc-gpr",
703 "fsl,imx6q-iomuxc-gpr", "syscon";
704 reg = <0x020e4000 0x4000>;
705 };
706
707 gpt2: gpt@20e8000 {
708 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
709 reg = <0x020e8000 0x4000>;
710 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
712 <&clks IMX6UL_CLK_GPT2_SERIAL>;
713 clock-names = "ipg", "per";
714 };
715
716 sdma: sdma@20ec000 {
717 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
718 "fsl,imx35-sdma";
719 reg = <0x020ec000 0x4000>;
720 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&clks IMX6UL_CLK_IPG>,
722 <&clks IMX6UL_CLK_SDMA>;
723 clock-names = "ipg", "ahb";
724 #dma-cells = <3>;
725 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
726 };
727
728 pwm5: pwm@20f0000 {
729 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
730 reg = <0x020f0000 0x4000>;
731 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clks IMX6UL_CLK_PWM5>,
733 <&clks IMX6UL_CLK_PWM5>;
734 clock-names = "ipg", "per";
735 #pwm-cells = <2>;
736 status = "disabled";
737 };
738
739 pwm6: pwm@20f4000 {
740 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
741 reg = <0x020f4000 0x4000>;
742 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clks IMX6UL_CLK_PWM6>,
744 <&clks IMX6UL_CLK_PWM6>;
745 clock-names = "ipg", "per";
746 #pwm-cells = <2>;
747 status = "disabled";
748 };
749
750 pwm7: pwm@20f8000 {
751 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
752 reg = <0x020f8000 0x4000>;
753 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&clks IMX6UL_CLK_PWM7>,
755 <&clks IMX6UL_CLK_PWM7>;
756 clock-names = "ipg", "per";
757 #pwm-cells = <2>;
758 status = "disabled";
759 };
760
761 pwm8: pwm@20fc000 {
762 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
763 reg = <0x020fc000 0x4000>;
764 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&clks IMX6UL_CLK_PWM8>,
766 <&clks IMX6UL_CLK_PWM8>;
767 clock-names = "ipg", "per";
768 #pwm-cells = <2>;
769 status = "disabled";
770 };
771 };
772
773 aips2: aips-bus@2100000 {
774 compatible = "fsl,aips-bus", "simple-bus";
775 #address-cells = <1>;
776 #size-cells = <1>;
777 reg = <0x02100000 0x100000>;
778 ranges;
779
780 crypto: caam@2140000 {
781 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
782 #address-cells = <1>;
783 #size-cells = <1>;
784 reg = <0x2140000 0x3c000>;
785 ranges = <0 0x2140000 0x3c000>;
786 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
788 <&clks IMX6UL_CLK_CAAM_MEM>;
789 clock-names = "ipg", "aclk", "mem";
790
791 sec_jr0: jr0@1000 {
792 compatible = "fsl,sec-v4.0-job-ring";
793 reg = <0x1000 0x1000>;
794 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
795 };
796
797 sec_jr1: jr1@2000 {
798 compatible = "fsl,sec-v4.0-job-ring";
799 reg = <0x2000 0x1000>;
800 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
801 };
802
803 sec_jr2: jr2@3000 {
804 compatible = "fsl,sec-v4.0-job-ring";
805 reg = <0x3000 0x1000>;
806 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
807 };
808 };
809
810 usbotg1: usb@2184000 {
811 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
812 reg = <0x02184000 0x200>;
813 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&clks IMX6UL_CLK_USBOH3>;
815 fsl,usbphy = <&usbphy1>;
816 fsl,usbmisc = <&usbmisc 0>;
817 fsl,anatop = <&anatop>;
818 ahb-burst-config = <0x0>;
819 tx-burst-size-dword = <0x10>;
820 rx-burst-size-dword = <0x10>;
821 status = "disabled";
822 };
823
824 usbotg2: usb@2184200 {
825 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
826 reg = <0x02184200 0x200>;
827 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&clks IMX6UL_CLK_USBOH3>;
829 fsl,usbphy = <&usbphy2>;
830 fsl,usbmisc = <&usbmisc 1>;
831 ahb-burst-config = <0x0>;
832 tx-burst-size-dword = <0x10>;
833 rx-burst-size-dword = <0x10>;
834 status = "disabled";
835 };
836
837 usbmisc: usbmisc@2184800 {
838 #index-cells = <1>;
839 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
840 reg = <0x02184800 0x200>;
841 };
842
843 fec1: ethernet@2188000 {
844 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
845 reg = <0x02188000 0x4000>;
846 interrupt-names = "int0", "pps";
847 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&clks IMX6UL_CLK_ENET>,
850 <&clks IMX6UL_CLK_ENET_AHB>,
851 <&clks IMX6UL_CLK_ENET_PTP>,
852 <&clks IMX6UL_CLK_ENET_REF>,
853 <&clks IMX6UL_CLK_ENET_REF>;
854 clock-names = "ipg", "ahb", "ptp",
855 "enet_clk_ref", "enet_out";
856 fsl,num-tx-queues = <1>;
857 fsl,num-rx-queues = <1>;
858 status = "disabled";
859 };
860
861 usdhc1: usdhc@2190000 {
862 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
863 reg = <0x02190000 0x4000>;
864 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clks IMX6UL_CLK_USDHC1>,
866 <&clks IMX6UL_CLK_USDHC1>,
867 <&clks IMX6UL_CLK_USDHC1>;
868 clock-names = "ipg", "ahb", "per";
869 fsl,tuning-step = <2>;
870 fsl,tuning-start-tap = <20>;
871 bus-width = <4>;
872 status = "disabled";
873 };
874
875 usdhc2: usdhc@2194000 {
876 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
877 reg = <0x02194000 0x4000>;
878 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clks IMX6UL_CLK_USDHC2>,
880 <&clks IMX6UL_CLK_USDHC2>,
881 <&clks IMX6UL_CLK_USDHC2>;
882 clock-names = "ipg", "ahb", "per";
883 bus-width = <4>;
884 fsl,tuning-step = <2>;
885 fsl,tuning-start-tap = <20>;
886 status = "disabled";
887 };
888
889 adc1: adc@2198000 {
890 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
891 reg = <0x02198000 0x4000>;
892 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clks IMX6UL_CLK_ADC1>;
894 num-channels = <2>;
895 clock-names = "adc";
896 fsl,adck-max-frequency = <30000000>, <40000000>,
897 <20000000>;
898 status = "disabled";
899 };
900
901 i2c1: i2c@21a0000 {
902 #address-cells = <1>;
903 #size-cells = <0>;
904 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
905 reg = <0x021a0000 0x4000>;
906 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&clks IMX6UL_CLK_I2C1>;
908 status = "disabled";
909 };
910
911 i2c2: i2c@21a4000 {
912 #address-cells = <1>;
913 #size-cells = <0>;
914 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
915 reg = <0x021a4000 0x4000>;
916 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&clks IMX6UL_CLK_I2C2>;
918 status = "disabled";
919 };
920
921 i2c3: i2c@21a8000 {
922 #address-cells = <1>;
923 #size-cells = <0>;
924 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
925 reg = <0x021a8000 0x4000>;
926 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&clks IMX6UL_CLK_I2C3>;
928 status = "disabled";
929 };
930
931 memory-controller@21b0000 {
932 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
933 reg = <0x021b0000 0x4000>;
934 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
935 };
936
937 weim: weim@21b8000 {
938 #address-cells = <2>;
939 #size-cells = <1>;
940 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
941 reg = <0x021b8000 0x4000>;
942 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&clks IMX6UL_CLK_EIM>;
944 fsl,weim-cs-gpr = <&gpr>;
945 status = "disabled";
946 };
947
948 ocotp: ocotp-ctrl@21bc000 {
949 #address-cells = <1>;
950 #size-cells = <1>;
951 compatible = "fsl,imx6ul-ocotp", "syscon";
952 reg = <0x021bc000 0x4000>;
953 clocks = <&clks IMX6UL_CLK_OCOTP>;
954
955 tempmon_calib: calib@38 {
956 reg = <0x38 4>;
957 };
958
959 tempmon_temp_grade: temp-grade@20 {
960 reg = <0x20 4>;
961 };
962
963 cpu_speed_grade: speed-grade@10 {
964 reg = <0x10 4>;
965 };
966 };
967
968 csi: csi@21c4000 {
969 compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
970 reg = <0x021c4000 0x4000>;
971 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
972 clocks = <&clks IMX6UL_CLK_CSI>;
973 clock-names = "mclk";
974 status = "disabled";
975 };
976
977 lcdif: lcdif@21c8000 {
978 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
979 reg = <0x021c8000 0x4000>;
980 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
982 <&clks IMX6UL_CLK_LCDIF_APB>,
983 <&clks IMX6UL_CLK_DUMMY>;
984 clock-names = "pix", "axi", "disp_axi";
985 status = "disabled";
986 };
987
988 pxp: pxp@21cc000 {
989 compatible = "fsl,imx6ul-pxp";
990 reg = <0x021cc000 0x4000>;
991 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clks IMX6UL_CLK_PXP>;
993 clock-names = "axi";
994 };
995
996 qspi: spi@21e0000 {
997 #address-cells = <1>;
998 #size-cells = <0>;
999 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
1000 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1001 reg-names = "QuadSPI", "QuadSPI-memory";
1002 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1003 clocks = <&clks IMX6UL_CLK_QSPI>,
1004 <&clks IMX6UL_CLK_QSPI>;
1005 clock-names = "qspi_en", "qspi";
1006 status = "disabled";
1007 };
1008
1009 wdog3: wdog@21e4000 {
1010 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1011 reg = <0x021e4000 0x4000>;
1012 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&clks IMX6UL_CLK_WDOG3>;
1014 status = "disabled";
1015 };
1016
1017 uart2: serial@21e8000 {
1018 compatible = "fsl,imx6ul-uart",
1019 "fsl,imx6q-uart";
1020 reg = <0x021e8000 0x4000>;
1021 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1023 <&clks IMX6UL_CLK_UART2_SERIAL>;
1024 clock-names = "ipg", "per";
1025 status = "disabled";
1026 };
1027
1028 uart3: serial@21ec000 {
1029 compatible = "fsl,imx6ul-uart",
1030 "fsl,imx6q-uart";
1031 reg = <0x021ec000 0x4000>;
1032 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1034 <&clks IMX6UL_CLK_UART3_SERIAL>;
1035 clock-names = "ipg", "per";
1036 status = "disabled";
1037 };
1038
1039 uart4: serial@21f0000 {
1040 compatible = "fsl,imx6ul-uart",
1041 "fsl,imx6q-uart";
1042 reg = <0x021f0000 0x4000>;
1043 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1045 <&clks IMX6UL_CLK_UART4_SERIAL>;
1046 clock-names = "ipg", "per";
1047 status = "disabled";
1048 };
1049
1050 uart5: serial@21f4000 {
1051 compatible = "fsl,imx6ul-uart",
1052 "fsl,imx6q-uart";
1053 reg = <0x021f4000 0x4000>;
1054 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1056 <&clks IMX6UL_CLK_UART5_SERIAL>;
1057 clock-names = "ipg", "per";
1058 status = "disabled";
1059 };
1060
1061 i2c4: i2c@21f8000 {
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1064 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1065 reg = <0x021f8000 0x4000>;
1066 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&clks IMX6UL_CLK_I2C4>;
1068 status = "disabled";
1069 };
1070
1071 uart6: serial@21fc000 {
1072 compatible = "fsl,imx6ul-uart",
1073 "fsl,imx6q-uart";
1074 reg = <0x021fc000 0x4000>;
1075 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1077 <&clks IMX6UL_CLK_UART6_SERIAL>;
1078 clock-names = "ipg", "per";
1079 status = "disabled";
1080 };
1081 };
1082 };
1083};
1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6ul-pinfunc.h"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 /*
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
23 */
24 chosen {};
25 memory { device_type = "memory"; reg = <0 0>; };
26
27 aliases {
28 ethernet0 = &fec1;
29 ethernet1 = &fec2;
30 gpio0 = &gpio1;
31 gpio1 = &gpio2;
32 gpio2 = &gpio3;
33 gpio3 = &gpio4;
34 gpio4 = &gpio5;
35 i2c0 = &i2c1;
36 i2c1 = &i2c2;
37 i2c2 = &i2c3;
38 i2c3 = &i2c4;
39 mmc0 = &usdhc1;
40 mmc1 = &usdhc2;
41 serial0 = &uart1;
42 serial1 = &uart2;
43 serial2 = &uart3;
44 serial3 = &uart4;
45 serial4 = &uart5;
46 serial5 = &uart6;
47 serial6 = &uart7;
48 serial7 = &uart8;
49 sai1 = &sai1;
50 sai2 = &sai2;
51 sai3 = &sai3;
52 spi0 = &ecspi1;
53 spi1 = &ecspi2;
54 spi2 = &ecspi3;
55 spi3 = &ecspi4;
56 usbphy0 = &usbphy1;
57 usbphy1 = &usbphy2;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 cpu0: cpu@0 {
65 compatible = "arm,cortex-a7";
66 device_type = "cpu";
67 reg = <0>;
68 clock-latency = <61036>; /* two CLK32 periods */
69 operating-points = <
70 /* kHz uV */
71 528000 1175000
72 396000 1025000
73 198000 950000
74 >;
75 fsl,soc-operating-points = <
76 /* KHz uV */
77 528000 1175000
78 396000 1175000
79 198000 1175000
80 >;
81 clocks = <&clks IMX6UL_CLK_ARM>,
82 <&clks IMX6UL_CLK_PLL2_BUS>,
83 <&clks IMX6UL_CLK_PLL2_PFD2>,
84 <&clks IMX6UL_CA7_SECONDARY_SEL>,
85 <&clks IMX6UL_CLK_STEP>,
86 <&clks IMX6UL_CLK_PLL1_SW>,
87 <&clks IMX6UL_CLK_PLL1_SYS>,
88 <&clks IMX6UL_PLL1_BYPASS>,
89 <&clks IMX6UL_CLK_PLL1>,
90 <&clks IMX6UL_PLL1_BYPASS_SRC>,
91 <&clks IMX6UL_CLK_OSC>;
92 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
93 "secondary_sel", "step", "pll1_sw",
94 "pll1_sys", "pll1_bypass", "pll1",
95 "pll1_bypass_src", "osc";
96 arm-supply = <®_arm>;
97 soc-supply = <®_soc>;
98 };
99 };
100
101 intc: interrupt-controller@00a01000 {
102 compatible = "arm,cortex-a7-gic";
103 #interrupt-cells = <3>;
104 interrupt-controller;
105 reg = <0x00a01000 0x1000>,
106 <0x00a02000 0x1000>,
107 <0x00a04000 0x2000>,
108 <0x00a06000 0x2000>;
109 };
110
111 ckil: clock-cli {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <32768>;
115 clock-output-names = "ckil";
116 };
117
118 osc: clock-osc {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <24000000>;
122 clock-output-names = "osc";
123 };
124
125 ipp_di0: clock-di0 {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <0>;
129 clock-output-names = "ipp_di0";
130 };
131
132 ipp_di1: clock-di1 {
133 compatible = "fixed-clock";
134 #clock-cells = <0>;
135 clock-frequency = <0>;
136 clock-output-names = "ipp_di1";
137 };
138
139 soc {
140 #address-cells = <1>;
141 #size-cells = <1>;
142 compatible = "simple-bus";
143 interrupt-parent = <&gpc>;
144 ranges;
145
146 pmu {
147 compatible = "arm,cortex-a7-pmu";
148 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
149 status = "disabled";
150 };
151
152 ocram: sram@00900000 {
153 compatible = "mmio-sram";
154 reg = <0x00900000 0x20000>;
155 };
156
157 dma_apbh: dma-apbh@01804000 {
158 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
159 reg = <0x01804000 0x2000>;
160 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
161 <0 13 IRQ_TYPE_LEVEL_HIGH>,
162 <0 13 IRQ_TYPE_LEVEL_HIGH>,
163 <0 13 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
165 #dma-cells = <1>;
166 dma-channels = <4>;
167 clocks = <&clks IMX6UL_CLK_APBHDMA>;
168 };
169
170 gpmi: gpmi-nand@01806000 {
171 compatible = "fsl,imx6q-gpmi-nand";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
175 reg-names = "gpmi-nand", "bch";
176 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-names = "bch";
178 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
179 <&clks IMX6UL_CLK_GPMI_APB>,
180 <&clks IMX6UL_CLK_GPMI_BCH>,
181 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
182 <&clks IMX6UL_CLK_PER_BCH>;
183 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
184 "gpmi_bch_apb", "per1_bch";
185 dmas = <&dma_apbh 0>;
186 dma-names = "rx-tx";
187 status = "disabled";
188 };
189
190 aips1: aips-bus@02000000 {
191 compatible = "fsl,aips-bus", "simple-bus";
192 #address-cells = <1>;
193 #size-cells = <1>;
194 reg = <0x02000000 0x100000>;
195 ranges;
196
197 spba-bus@02000000 {
198 compatible = "fsl,spba-bus", "simple-bus";
199 #address-cells = <1>;
200 #size-cells = <1>;
201 reg = <0x02000000 0x40000>;
202 ranges;
203
204 ecspi1: ecspi@02008000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
208 reg = <0x02008000 0x4000>;
209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks IMX6UL_CLK_ECSPI1>,
211 <&clks IMX6UL_CLK_ECSPI1>;
212 clock-names = "ipg", "per";
213 status = "disabled";
214 };
215
216 ecspi2: ecspi@0200c000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
220 reg = <0x0200c000 0x4000>;
221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&clks IMX6UL_CLK_ECSPI2>,
223 <&clks IMX6UL_CLK_ECSPI2>;
224 clock-names = "ipg", "per";
225 status = "disabled";
226 };
227
228 ecspi3: ecspi@02010000 {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
232 reg = <0x02010000 0x4000>;
233 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clks IMX6UL_CLK_ECSPI3>,
235 <&clks IMX6UL_CLK_ECSPI3>;
236 clock-names = "ipg", "per";
237 status = "disabled";
238 };
239
240 ecspi4: ecspi@02014000 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
244 reg = <0x02014000 0x4000>;
245 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&clks IMX6UL_CLK_ECSPI4>,
247 <&clks IMX6UL_CLK_ECSPI4>;
248 clock-names = "ipg", "per";
249 status = "disabled";
250 };
251
252 uart7: serial@02018000 {
253 compatible = "fsl,imx6ul-uart",
254 "fsl,imx6q-uart";
255 reg = <0x02018000 0x4000>;
256 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
258 <&clks IMX6UL_CLK_UART7_SERIAL>;
259 clock-names = "ipg", "per";
260 status = "disabled";
261 };
262
263 uart1: serial@02020000 {
264 compatible = "fsl,imx6ul-uart",
265 "fsl,imx6q-uart";
266 reg = <0x02020000 0x4000>;
267 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
269 <&clks IMX6UL_CLK_UART1_SERIAL>;
270 clock-names = "ipg", "per";
271 status = "disabled";
272 };
273
274 uart8: serial@02024000 {
275 compatible = "fsl,imx6ul-uart",
276 "fsl,imx6q-uart";
277 reg = <0x02024000 0x4000>;
278 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
280 <&clks IMX6UL_CLK_UART8_SERIAL>;
281 clock-names = "ipg", "per";
282 status = "disabled";
283 };
284
285 sai1: sai@02028000 {
286 #sound-dai-cells = <0>;
287 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
288 reg = <0x02028000 0x4000>;
289 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
291 <&clks IMX6UL_CLK_SAI1>,
292 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
293 clock-names = "bus", "mclk1", "mclk2", "mclk3";
294 dmas = <&sdma 35 24 0>,
295 <&sdma 36 24 0>;
296 dma-names = "rx", "tx";
297 status = "disabled";
298 };
299
300 sai2: sai@0202c000 {
301 #sound-dai-cells = <0>;
302 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
303 reg = <0x0202c000 0x4000>;
304 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
306 <&clks IMX6UL_CLK_SAI2>,
307 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
308 clock-names = "bus", "mclk1", "mclk2", "mclk3";
309 dmas = <&sdma 37 24 0>,
310 <&sdma 38 24 0>;
311 dma-names = "rx", "tx";
312 status = "disabled";
313 };
314
315 sai3: sai@02030000 {
316 #sound-dai-cells = <0>;
317 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
318 reg = <0x02030000 0x4000>;
319 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
321 <&clks IMX6UL_CLK_SAI3>,
322 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
323 clock-names = "bus", "mclk1", "mclk2", "mclk3";
324 dmas = <&sdma 39 24 0>,
325 <&sdma 40 24 0>;
326 dma-names = "rx", "tx";
327 status = "disabled";
328 };
329 };
330
331 tsc: tsc@02040000 {
332 compatible = "fsl,imx6ul-tsc";
333 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&clks IMX6UL_CLK_IPG>,
337 <&clks IMX6UL_CLK_ADC2>;
338 clock-names = "tsc", "adc";
339 status = "disabled";
340 };
341
342 pwm1: pwm@02080000 {
343 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
344 reg = <0x02080000 0x4000>;
345 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clks IMX6UL_CLK_PWM1>,
347 <&clks IMX6UL_CLK_PWM1>;
348 clock-names = "ipg", "per";
349 #pwm-cells = <2>;
350 status = "disabled";
351 };
352
353 pwm2: pwm@02084000 {
354 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
355 reg = <0x02084000 0x4000>;
356 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6UL_CLK_PWM2>,
358 <&clks IMX6UL_CLK_PWM2>;
359 clock-names = "ipg", "per";
360 #pwm-cells = <2>;
361 status = "disabled";
362 };
363
364 pwm3: pwm@02088000 {
365 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
366 reg = <0x02088000 0x4000>;
367 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clks IMX6UL_CLK_PWM3>,
369 <&clks IMX6UL_CLK_PWM3>;
370 clock-names = "ipg", "per";
371 #pwm-cells = <2>;
372 status = "disabled";
373 };
374
375 pwm4: pwm@0208c000 {
376 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
377 reg = <0x0208c000 0x4000>;
378 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks IMX6UL_CLK_PWM4>,
380 <&clks IMX6UL_CLK_PWM4>;
381 clock-names = "ipg", "per";
382 #pwm-cells = <2>;
383 status = "disabled";
384 };
385
386 can1: flexcan@02090000 {
387 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
388 reg = <0x02090000 0x4000>;
389 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
391 <&clks IMX6UL_CLK_CAN1_SERIAL>;
392 clock-names = "ipg", "per";
393 status = "disabled";
394 };
395
396 can2: flexcan@02094000 {
397 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
398 reg = <0x02094000 0x4000>;
399 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
401 <&clks IMX6UL_CLK_CAN2_SERIAL>;
402 clock-names = "ipg", "per";
403 status = "disabled";
404 };
405
406 gpt1: gpt@02098000 {
407 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
408 reg = <0x02098000 0x4000>;
409 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
411 <&clks IMX6UL_CLK_GPT1_SERIAL>;
412 clock-names = "ipg", "per";
413 };
414
415 gpio1: gpio@0209c000 {
416 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
417 reg = <0x0209c000 0x4000>;
418 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
425 <&iomuxc 16 33 16>;
426 };
427
428 gpio2: gpio@020a0000 {
429 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
430 reg = <0x020a0000 0x4000>;
431 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
438 };
439
440 gpio3: gpio@020a4000 {
441 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
442 reg = <0x020a4000 0x4000>;
443 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
445 gpio-controller;
446 #gpio-cells = <2>;
447 interrupt-controller;
448 #interrupt-cells = <2>;
449 gpio-ranges = <&iomuxc 0 65 29>;
450 };
451
452 gpio4: gpio@020a8000 {
453 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
454 reg = <0x020a8000 0x4000>;
455 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
462 };
463
464 gpio5: gpio@020ac000 {
465 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
466 reg = <0x020ac000 0x4000>;
467 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
474 };
475
476 fec2: ethernet@020b4000 {
477 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
478 reg = <0x020b4000 0x4000>;
479 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clks IMX6UL_CLK_ENET>,
482 <&clks IMX6UL_CLK_ENET_AHB>,
483 <&clks IMX6UL_CLK_ENET_PTP>,
484 <&clks IMX6UL_CLK_ENET2_REF_125M>,
485 <&clks IMX6UL_CLK_ENET2_REF_125M>;
486 clock-names = "ipg", "ahb", "ptp",
487 "enet_clk_ref", "enet_out";
488 fsl,num-tx-queues=<1>;
489 fsl,num-rx-queues=<1>;
490 status = "disabled";
491 };
492
493 kpp: kpp@020b8000 {
494 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
495 reg = <0x020b8000 0x4000>;
496 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&clks IMX6UL_CLK_KPP>;
498 status = "disabled";
499 };
500
501 wdog1: wdog@020bc000 {
502 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
503 reg = <0x020bc000 0x4000>;
504 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clks IMX6UL_CLK_WDOG1>;
506 };
507
508 wdog2: wdog@020c0000 {
509 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
510 reg = <0x020c0000 0x4000>;
511 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clks IMX6UL_CLK_WDOG2>;
513 status = "disabled";
514 };
515
516 clks: ccm@020c4000 {
517 compatible = "fsl,imx6ul-ccm";
518 reg = <0x020c4000 0x4000>;
519 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
521 #clock-cells = <1>;
522 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
523 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
524 };
525
526 anatop: anatop@020c8000 {
527 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
528 "syscon", "simple-bus";
529 reg = <0x020c8000 0x1000>;
530 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
533
534 reg_3p0: regulator-3p0 {
535 compatible = "fsl,anatop-regulator";
536 regulator-name = "vdd3p0";
537 regulator-min-microvolt = <2625000>;
538 regulator-max-microvolt = <3400000>;
539 anatop-reg-offset = <0x120>;
540 anatop-vol-bit-shift = <8>;
541 anatop-vol-bit-width = <5>;
542 anatop-min-bit-val = <0>;
543 anatop-min-voltage = <2625000>;
544 anatop-max-voltage = <3400000>;
545 anatop-enable-bit = <0>;
546 };
547
548 reg_arm: regulator-vddcore {
549 compatible = "fsl,anatop-regulator";
550 regulator-name = "cpu";
551 regulator-min-microvolt = <725000>;
552 regulator-max-microvolt = <1450000>;
553 regulator-always-on;
554 anatop-reg-offset = <0x140>;
555 anatop-vol-bit-shift = <0>;
556 anatop-vol-bit-width = <5>;
557 anatop-delay-reg-offset = <0x170>;
558 anatop-delay-bit-shift = <24>;
559 anatop-delay-bit-width = <2>;
560 anatop-min-bit-val = <1>;
561 anatop-min-voltage = <725000>;
562 anatop-max-voltage = <1450000>;
563 };
564
565 reg_soc: regulator-vddsoc {
566 compatible = "fsl,anatop-regulator";
567 regulator-name = "vddsoc";
568 regulator-min-microvolt = <725000>;
569 regulator-max-microvolt = <1450000>;
570 regulator-always-on;
571 anatop-reg-offset = <0x140>;
572 anatop-vol-bit-shift = <18>;
573 anatop-vol-bit-width = <5>;
574 anatop-delay-reg-offset = <0x170>;
575 anatop-delay-bit-shift = <28>;
576 anatop-delay-bit-width = <2>;
577 anatop-min-bit-val = <1>;
578 anatop-min-voltage = <725000>;
579 anatop-max-voltage = <1450000>;
580 };
581 };
582
583 usbphy1: usbphy@020c9000 {
584 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
585 reg = <0x020c9000 0x1000>;
586 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&clks IMX6UL_CLK_USBPHY1>;
588 phy-3p0-supply = <®_3p0>;
589 fsl,anatop = <&anatop>;
590 };
591
592 usbphy2: usbphy@020ca000 {
593 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
594 reg = <0x020ca000 0x1000>;
595 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&clks IMX6UL_CLK_USBPHY2>;
597 phy-3p0-supply = <®_3p0>;
598 fsl,anatop = <&anatop>;
599 };
600
601 snvs: snvs@020cc000 {
602 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
603 reg = <0x020cc000 0x4000>;
604
605 snvs_rtc: snvs-rtc-lp {
606 compatible = "fsl,sec-v4.0-mon-rtc-lp";
607 regmap = <&snvs>;
608 offset = <0x34>;
609 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
611 };
612
613 snvs_poweroff: snvs-poweroff {
614 compatible = "syscon-poweroff";
615 regmap = <&snvs>;
616 offset = <0x38>;
617 mask = <0x60>;
618 status = "disabled";
619 };
620
621 snvs_pwrkey: snvs-powerkey {
622 compatible = "fsl,sec-v4.0-pwrkey";
623 regmap = <&snvs>;
624 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
625 linux,keycode = <KEY_POWER>;
626 wakeup-source;
627 };
628 };
629
630 epit1: epit@020d0000 {
631 reg = <0x020d0000 0x4000>;
632 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
633 };
634
635 epit2: epit@020d4000 {
636 reg = <0x020d4000 0x4000>;
637 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
638 };
639
640 src: src@020d8000 {
641 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
642 reg = <0x020d8000 0x4000>;
643 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
645 #reset-cells = <1>;
646 };
647
648 gpc: gpc@020dc000 {
649 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
650 reg = <0x020dc000 0x4000>;
651 interrupt-controller;
652 #interrupt-cells = <3>;
653 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
654 interrupt-parent = <&intc>;
655 };
656
657 iomuxc: iomuxc@020e0000 {
658 compatible = "fsl,imx6ul-iomuxc";
659 reg = <0x020e0000 0x4000>;
660 };
661
662 gpr: iomuxc-gpr@020e4000 {
663 compatible = "fsl,imx6ul-iomuxc-gpr",
664 "fsl,imx6q-iomuxc-gpr", "syscon";
665 reg = <0x020e4000 0x4000>;
666 };
667
668 gpt2: gpt@020e8000 {
669 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
670 reg = <0x020e8000 0x4000>;
671 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
673 <&clks IMX6UL_CLK_GPT2_SERIAL>;
674 clock-names = "ipg", "per";
675 };
676
677 sdma: sdma@020ec000 {
678 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
679 "fsl,imx35-sdma";
680 reg = <0x020ec000 0x4000>;
681 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clks IMX6UL_CLK_SDMA>,
683 <&clks IMX6UL_CLK_SDMA>;
684 clock-names = "ipg", "ahb";
685 #dma-cells = <3>;
686 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
687 };
688
689 pwm5: pwm@020f0000 {
690 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
691 reg = <0x020f0000 0x4000>;
692 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clks IMX6UL_CLK_PWM5>,
694 <&clks IMX6UL_CLK_PWM5>;
695 clock-names = "ipg", "per";
696 #pwm-cells = <2>;
697 status = "disabled";
698 };
699
700 pwm6: pwm@020f4000 {
701 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
702 reg = <0x020f4000 0x4000>;
703 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clks IMX6UL_CLK_PWM6>,
705 <&clks IMX6UL_CLK_PWM6>;
706 clock-names = "ipg", "per";
707 #pwm-cells = <2>;
708 status = "disabled";
709 };
710
711 pwm7: pwm@020f8000 {
712 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
713 reg = <0x020f8000 0x4000>;
714 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clks IMX6UL_CLK_PWM7>,
716 <&clks IMX6UL_CLK_PWM7>;
717 clock-names = "ipg", "per";
718 #pwm-cells = <2>;
719 status = "disabled";
720 };
721
722 pwm8: pwm@020fc000 {
723 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
724 reg = <0x020fc000 0x4000>;
725 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clks IMX6UL_CLK_PWM8>,
727 <&clks IMX6UL_CLK_PWM8>;
728 clock-names = "ipg", "per";
729 #pwm-cells = <2>;
730 status = "disabled";
731 };
732 };
733
734 aips2: aips-bus@02100000 {
735 compatible = "fsl,aips-bus", "simple-bus";
736 #address-cells = <1>;
737 #size-cells = <1>;
738 reg = <0x02100000 0x100000>;
739 ranges;
740
741 usbotg1: usb@02184000 {
742 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
743 reg = <0x02184000 0x200>;
744 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clks IMX6UL_CLK_USBOH3>;
746 fsl,usbphy = <&usbphy1>;
747 fsl,usbmisc = <&usbmisc 0>;
748 fsl,anatop = <&anatop>;
749 ahb-burst-config = <0x0>;
750 tx-burst-size-dword = <0x10>;
751 rx-burst-size-dword = <0x10>;
752 status = "disabled";
753 };
754
755 usbotg2: usb@02184200 {
756 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
757 reg = <0x02184200 0x200>;
758 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clks IMX6UL_CLK_USBOH3>;
760 fsl,usbphy = <&usbphy2>;
761 fsl,usbmisc = <&usbmisc 1>;
762 ahb-burst-config = <0x0>;
763 tx-burst-size-dword = <0x10>;
764 rx-burst-size-dword = <0x10>;
765 status = "disabled";
766 };
767
768 usbmisc: usbmisc@02184800 {
769 #index-cells = <1>;
770 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
771 reg = <0x02184800 0x200>;
772 };
773
774 fec1: ethernet@02188000 {
775 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
776 reg = <0x02188000 0x4000>;
777 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clks IMX6UL_CLK_ENET>,
780 <&clks IMX6UL_CLK_ENET_AHB>,
781 <&clks IMX6UL_CLK_ENET_PTP>,
782 <&clks IMX6UL_CLK_ENET_REF>,
783 <&clks IMX6UL_CLK_ENET_REF>;
784 clock-names = "ipg", "ahb", "ptp",
785 "enet_clk_ref", "enet_out";
786 fsl,num-tx-queues=<1>;
787 fsl,num-rx-queues=<1>;
788 status = "disabled";
789 };
790
791 usdhc1: usdhc@02190000 {
792 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
793 reg = <0x02190000 0x4000>;
794 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clks IMX6UL_CLK_USDHC1>,
796 <&clks IMX6UL_CLK_USDHC1>,
797 <&clks IMX6UL_CLK_USDHC1>;
798 clock-names = "ipg", "ahb", "per";
799 bus-width = <4>;
800 status = "disabled";
801 };
802
803 usdhc2: usdhc@02194000 {
804 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
805 reg = <0x02194000 0x4000>;
806 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clks IMX6UL_CLK_USDHC2>,
808 <&clks IMX6UL_CLK_USDHC2>,
809 <&clks IMX6UL_CLK_USDHC2>;
810 clock-names = "ipg", "ahb", "per";
811 bus-width = <4>;
812 status = "disabled";
813 };
814
815 adc1: adc@02198000 {
816 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
817 reg = <0x02198000 0x4000>;
818 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clks IMX6UL_CLK_ADC1>;
820 num-channels = <2>;
821 clock-names = "adc";
822 fsl,adck-max-frequency = <30000000>, <40000000>,
823 <20000000>;
824 status = "disabled";
825 };
826
827 i2c1: i2c@021a0000 {
828 #address-cells = <1>;
829 #size-cells = <0>;
830 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
831 reg = <0x021a0000 0x4000>;
832 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&clks IMX6UL_CLK_I2C1>;
834 status = "disabled";
835 };
836
837 i2c2: i2c@021a4000 {
838 #address-cells = <1>;
839 #size-cells = <0>;
840 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
841 reg = <0x021a4000 0x4000>;
842 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&clks IMX6UL_CLK_I2C2>;
844 status = "disabled";
845 };
846
847 i2c3: i2c@021a8000 {
848 #address-cells = <1>;
849 #size-cells = <0>;
850 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
851 reg = <0x021a8000 0x4000>;
852 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&clks IMX6UL_CLK_I2C3>;
854 status = "disabled";
855 };
856
857 mmdc: mmdc@021b0000 {
858 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
859 reg = <0x021b0000 0x4000>;
860 };
861
862 lcdif: lcdif@021c8000 {
863 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
864 reg = <0x021c8000 0x4000>;
865 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
867 <&clks IMX6UL_CLK_LCDIF_APB>,
868 <&clks IMX6UL_CLK_DUMMY>;
869 clock-names = "pix", "axi", "disp_axi";
870 status = "disabled";
871 };
872
873 qspi: qspi@021e0000 {
874 #address-cells = <1>;
875 #size-cells = <0>;
876 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
877 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
878 reg-names = "QuadSPI", "QuadSPI-memory";
879 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&clks IMX6UL_CLK_QSPI>,
881 <&clks IMX6UL_CLK_QSPI>;
882 clock-names = "qspi_en", "qspi";
883 status = "disabled";
884 };
885
886 uart2: serial@021e8000 {
887 compatible = "fsl,imx6ul-uart",
888 "fsl,imx6q-uart";
889 reg = <0x021e8000 0x4000>;
890 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
892 <&clks IMX6UL_CLK_UART2_SERIAL>;
893 clock-names = "ipg", "per";
894 status = "disabled";
895 };
896
897 uart3: serial@021ec000 {
898 compatible = "fsl,imx6ul-uart",
899 "fsl,imx6q-uart";
900 reg = <0x021ec000 0x4000>;
901 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
903 <&clks IMX6UL_CLK_UART3_SERIAL>;
904 clock-names = "ipg", "per";
905 status = "disabled";
906 };
907
908 uart4: serial@021f0000 {
909 compatible = "fsl,imx6ul-uart",
910 "fsl,imx6q-uart";
911 reg = <0x021f0000 0x4000>;
912 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
914 <&clks IMX6UL_CLK_UART4_SERIAL>;
915 clock-names = "ipg", "per";
916 status = "disabled";
917 };
918
919 uart5: serial@021f4000 {
920 compatible = "fsl,imx6ul-uart",
921 "fsl,imx6q-uart";
922 reg = <0x021f4000 0x4000>;
923 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
925 <&clks IMX6UL_CLK_UART5_SERIAL>;
926 clock-names = "ipg", "per";
927 status = "disabled";
928 };
929
930 i2c4: i2c@021f8000 {
931 #address-cells = <1>;
932 #size-cells = <0>;
933 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
934 reg = <0x021f8000 0x4000>;
935 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6UL_CLK_I2C4>;
937 status = "disabled";
938 };
939
940 uart6: serial@021fc000 {
941 compatible = "fsl,imx6ul-uart",
942 "fsl,imx6q-uart";
943 reg = <0x021fc000 0x4000>;
944 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
946 <&clks IMX6UL_CLK_UART6_SERIAL>;
947 clock-names = "ipg", "per";
948 status = "disabled";
949 };
950 };
951 };
952};