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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
4 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
5 */
6
7#include "imx53.dtsi"
8
9/ {
10 model = "TQ TQMa53";
11 compatible = "tq,tqma53", "fsl,imx53";
12
13 memory@70000000 {
14 device_type = "memory";
15 reg = <0x70000000 0x40000000>; /* Up to 1GiB */
16 };
17
18 regulators {
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 reg_3p3v: regulator@0 {
24 compatible = "regulator-fixed";
25 reg = <0>;
26 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-always-on;
30 };
31 };
32};
33
34&esdhc2 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_esdhc2>,
37 <&pinctrl_esdhc2_cdwp>;
38 vmmc-supply = <®_3p3v>;
39 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
40 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
41 status = "disabled";
42};
43
44&uart3 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_uart3>;
47 status = "disabled";
48};
49
50&ecspi1 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_ecspi1>;
53 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
54 <&gpio3 24 0>, <&gpio3 25 0>;
55 status = "disabled";
56};
57
58&esdhc3 { /* EMMC */
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_esdhc3>;
61 vmmc-supply = <®_3p3v>;
62 non-removable;
63 bus-width = <8>;
64 status = "okay";
65};
66
67&iomuxc {
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_hog>;
70
71 imx53-tqma53 {
72 pinctrl_hog: hoggrp {
73 fsl,pins = <
74 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
75 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
76 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
77 MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
78 MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */
79 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */
80 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */
81 MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */
82 MX53_PAD_GPIO_3__GPIO1_3 0x80000000
83 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
84 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
85 >;
86 };
87
88 pinctrl_audmux: audmuxgrp {
89 fsl,pins = <
90 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
91 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
92 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
93 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
94 >;
95 };
96
97 pinctrl_can1: can1grp {
98 fsl,pins = <
99 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
100 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
101 >;
102 };
103
104 pinctrl_can2: can2grp {
105 fsl,pins = <
106 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
107 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
108 >;
109 };
110
111 pinctrl_cspi: cspigrp {
112 fsl,pins = <
113 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
114 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
115 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
116 >;
117 };
118
119 pinctrl_ecspi1: ecspi1grp {
120 fsl,pins = <
121 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
122 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
123 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
124 >;
125 };
126
127 pinctrl_esdhc2: esdhc2grp {
128 fsl,pins = <
129 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
130 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
131 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
132 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
133 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
134 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
135 >;
136 };
137
138 pinctrl_esdhc2_cdwp: esdhc2cdwp {
139 fsl,pins = <
140 MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
141 MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
142 >;
143 };
144
145 pinctrl_esdhc3: esdhc3grp {
146 fsl,pins = <
147 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
148 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
149 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
150 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
151 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
152 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
153 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
154 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
155 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
156 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
157 >;
158 };
159
160 pinctrl_fec: fecgrp {
161 fsl,pins = <
162 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
163 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
164 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
165 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
166 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
167 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
168 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
169 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
170 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
171 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
172 >;
173 };
174
175 pinctrl_i2c2: i2c2grp {
176 fsl,pins = <
177 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
178 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
179 >;
180 };
181
182 pinctrl_i2c3: i2c3grp {
183 fsl,pins = <
184 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
185 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
186 >;
187 };
188
189 pinctrl_uart1: uart1grp {
190 fsl,pins = <
191 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
192 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
193 >;
194 };
195
196 pinctrl_uart2: uart2grp {
197 fsl,pins = <
198 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
199 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
200 >;
201 };
202
203 pinctrl_uart3: uart3grp {
204 fsl,pins = <
205 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
206 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
207 >;
208 };
209 };
210};
211
212&uart1 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_uart1>;
215 uart-has-rtscts;
216 status = "disabled";
217};
218
219&uart2 {
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_uart2>;
222 status = "disabled";
223};
224
225&can1 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_can1>;
228 status = "disabled";
229};
230
231&can2 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_can2>;
234 status = "disabled";
235};
236
237&i2c3 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_i2c3>;
240 status = "disabled";
241};
242
243&cspi {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_cspi>;
246 cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
247 <&gpio1 21 0>;
248 status = "disabled";
249};
250
251&i2c2 {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_i2c2>;
254 status = "okay";
255
256 pmic: mc34708@8 {
257 compatible = "fsl,mc34708";
258 reg = <0x8>;
259 fsl,mc13xxx-uses-rtc;
260 interrupt-parent = <&gpio2>;
261 interrupts = <6 4>; /* PATA_DATA6, active high */
262 };
263
264 sensor1: lm75@48 {
265 compatible = "lm75";
266 reg = <0x48>;
267 };
268
269 eeprom: 24c64@50 {
270 compatible = "atmel,24c64";
271 pagesize = <32>;
272 reg = <0x50>;
273 };
274};
275
276&fec {
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_fec>;
279 phy-mode = "rmii";
280 status = "disabled";
281};
1/*
2 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include "imx53.dtsi"
14
15/ {
16 model = "TQ TQMa53";
17 compatible = "tq,tqma53", "fsl,imx53";
18
19 memory {
20 reg = <0x70000000 0x40000000>; /* Up to 1GiB */
21 };
22
23 regulators {
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 reg_3p3v: regulator@0 {
29 compatible = "regulator-fixed";
30 reg = <0>;
31 regulator-name = "3P3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 regulator-always-on;
35 };
36 };
37};
38
39&esdhc2 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_esdhc2>,
42 <&pinctrl_esdhc2_cdwp>;
43 vmmc-supply = <®_3p3v>;
44 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
45 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
46 status = "disabled";
47};
48
49&uart3 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_uart3>;
52 status = "disabled";
53};
54
55&ecspi1 {
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_ecspi1>;
58 fsl,spi-num-chipselects = <4>;
59 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
60 <&gpio3 24 0>, <&gpio3 25 0>;
61 status = "disabled";
62};
63
64&esdhc3 { /* EMMC */
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_esdhc3>;
67 vmmc-supply = <®_3p3v>;
68 non-removable;
69 bus-width = <8>;
70 status = "okay";
71};
72
73&iomuxc {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_hog>;
76
77 imx53-tqma53 {
78 pinctrl_hog: hoggrp {
79 fsl,pins = <
80 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
81 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
82 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
83 MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
84 MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */
85 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */
86 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */
87 MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */
88 MX53_PAD_GPIO_3__GPIO1_3 0x80000000
89 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
90 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
91 >;
92 };
93
94 pinctrl_audmux: audmuxgrp {
95 fsl,pins = <
96 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
97 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
98 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
99 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
100 >;
101 };
102
103 pinctrl_can1: can1grp {
104 fsl,pins = <
105 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
106 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
107 >;
108 };
109
110 pinctrl_can2: can2grp {
111 fsl,pins = <
112 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
113 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
114 >;
115 };
116
117 pinctrl_cspi: cspigrp {
118 fsl,pins = <
119 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
120 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
121 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
122 >;
123 };
124
125 pinctrl_ecspi1: ecspi1grp {
126 fsl,pins = <
127 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
128 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
129 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
130 >;
131 };
132
133 pinctrl_esdhc2: esdhc2grp {
134 fsl,pins = <
135 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
136 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
137 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
138 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
139 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
140 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
141 >;
142 };
143
144 pinctrl_esdhc2_cdwp: esdhc2cdwp {
145 fsl,pins = <
146 MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
147 MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
148 >;
149 };
150
151 pinctrl_esdhc3: esdhc3grp {
152 fsl,pins = <
153 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
154 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
155 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
156 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
157 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
158 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
159 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
160 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
161 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
162 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
163 >;
164 };
165
166 pinctrl_fec: fecgrp {
167 fsl,pins = <
168 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
169 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
170 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
171 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
172 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
173 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
174 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
175 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
176 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
177 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
178 >;
179 };
180
181 pinctrl_i2c2: i2c2grp {
182 fsl,pins = <
183 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
184 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
185 >;
186 };
187
188 pinctrl_i2c3: i2c3grp {
189 fsl,pins = <
190 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
191 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
192 >;
193 };
194
195 pinctrl_uart1: uart1grp {
196 fsl,pins = <
197 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
198 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
199 >;
200 };
201
202 pinctrl_uart2: uart2grp {
203 fsl,pins = <
204 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
205 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
206 >;
207 };
208
209 pinctrl_uart3: uart3grp {
210 fsl,pins = <
211 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
212 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
213 >;
214 };
215 };
216};
217
218&uart1 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_uart1>;
221 uart-has-rtscts;
222 status = "disabled";
223};
224
225&uart2 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_uart2>;
228 status = "disabled";
229};
230
231&can1 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_can1>;
234 status = "disabled";
235};
236
237&can2 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_can2>;
240 status = "disabled";
241};
242
243&i2c3 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_i2c3>;
246 status = "disabled";
247};
248
249&cspi {
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_cspi>;
252 fsl,spi-num-chipselects = <3>;
253 cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
254 <&gpio1 21 0>;
255 status = "disabled";
256};
257
258&i2c2 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_i2c2>;
261 status = "okay";
262
263 pmic: mc34708@8 {
264 compatible = "fsl,mc34708";
265 reg = <0x8>;
266 fsl,mc13xxx-uses-rtc;
267 interrupt-parent = <&gpio2>;
268 interrupts = <6 4>; /* PATA_DATA6, active high */
269 };
270
271 sensor1: lm75@48 {
272 compatible = "lm75";
273 reg = <0x48>;
274 };
275
276 eeprom: 24c64@50 {
277 compatible = "at,24c64";
278 pagesize = <32>;
279 reg = <0x50>;
280 };
281};
282
283&fec {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_fec>;
286 phy-mode = "rmii";
287 status = "disabled";
288};