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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2011-2012 Calxeda, Inc.
4 */
5
6/dts-v1/;
7
8/* First 4KB has pen for secondary cores. */
9/memreserve/ 0x00000000 0x0001000;
10
11/ {
12 model = "Calxeda Highbank";
13 compatible = "calxeda,highbank";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 clock-ranges;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@900 {
23 compatible = "arm,cortex-a9";
24 device_type = "cpu";
25 reg = <0x900>;
26 next-level-cache = <&L2>;
27 clocks = <&a9pll>;
28 clock-names = "cpu";
29 operating-points = <
30 /* kHz ignored */
31 1300000 1000000
32 1200000 1000000
33 1100000 1000000
34 800000 1000000
35 400000 1000000
36 200000 1000000
37 >;
38 clock-latency = <100000>;
39 };
40
41 cpu@901 {
42 compatible = "arm,cortex-a9";
43 device_type = "cpu";
44 reg = <0x901>;
45 next-level-cache = <&L2>;
46 clocks = <&a9pll>;
47 clock-names = "cpu";
48 operating-points = <
49 /* kHz ignored */
50 1300000 1000000
51 1200000 1000000
52 1100000 1000000
53 800000 1000000
54 400000 1000000
55 200000 1000000
56 >;
57 clock-latency = <100000>;
58 };
59
60 cpu@902 {
61 compatible = "arm,cortex-a9";
62 device_type = "cpu";
63 reg = <0x902>;
64 next-level-cache = <&L2>;
65 clocks = <&a9pll>;
66 clock-names = "cpu";
67 operating-points = <
68 /* kHz ignored */
69 1300000 1000000
70 1200000 1000000
71 1100000 1000000
72 800000 1000000
73 400000 1000000
74 200000 1000000
75 >;
76 clock-latency = <100000>;
77 };
78
79 cpu@903 {
80 compatible = "arm,cortex-a9";
81 device_type = "cpu";
82 reg = <0x903>;
83 next-level-cache = <&L2>;
84 clocks = <&a9pll>;
85 clock-names = "cpu";
86 operating-points = <
87 /* kHz ignored */
88 1300000 1000000
89 1200000 1000000
90 1100000 1000000
91 800000 1000000
92 400000 1000000
93 200000 1000000
94 >;
95 clock-latency = <100000>;
96 };
97 };
98
99 memory {
100 name = "memory";
101 device_type = "memory";
102 reg = <0x00000000 0xff900000>;
103 };
104
105 soc {
106 ranges = <0x00000000 0x00000000 0xffffffff>;
107
108 memory-controller@fff00000 {
109 compatible = "calxeda,hb-ddr-ctrl";
110 reg = <0xfff00000 0x1000>;
111 interrupts = <0 91 4>;
112 };
113
114 timer@fff10600 {
115 compatible = "arm,cortex-a9-twd-timer";
116 reg = <0xfff10600 0x20>;
117 interrupts = <1 13 0xf01>;
118 clocks = <&a9periphclk>;
119 };
120
121 watchdog@fff10620 {
122 compatible = "arm,cortex-a9-twd-wdt";
123 reg = <0xfff10620 0x20>;
124 interrupts = <1 14 0xf01>;
125 clocks = <&a9periphclk>;
126 };
127
128 intc: interrupt-controller@fff11000 {
129 compatible = "arm,cortex-a9-gic";
130 #interrupt-cells = <3>;
131 #size-cells = <0>;
132 #address-cells = <1>;
133 interrupt-controller;
134 reg = <0xfff11000 0x1000>,
135 <0xfff10100 0x100>;
136 };
137
138 L2: l2-cache {
139 compatible = "arm,pl310-cache";
140 reg = <0xfff12000 0x1000>;
141 interrupts = <0 70 4>;
142 cache-unified;
143 cache-level = <2>;
144 };
145
146 pmu {
147 compatible = "arm,cortex-a9-pmu";
148 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
149 };
150
151
152 sregs@fff3c200 {
153 compatible = "calxeda,hb-sregs-l2-ecc";
154 reg = <0xfff3c200 0x100>;
155 interrupts = <0 71 4 0 72 4>;
156 };
157
158 };
159};
160
161/include/ "ecx-common.dtsi"
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18
19/* First 4KB has pen for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
21
22/ {
23 model = "Calxeda Highbank";
24 compatible = "calxeda,highbank";
25 #address-cells = <1>;
26 #size-cells = <1>;
27 clock-ranges;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@900 {
34 compatible = "arm,cortex-a9";
35 device_type = "cpu";
36 reg = <0x900>;
37 next-level-cache = <&L2>;
38 clocks = <&a9pll>;
39 clock-names = "cpu";
40 operating-points = <
41 /* kHz ignored */
42 1300000 1000000
43 1200000 1000000
44 1100000 1000000
45 800000 1000000
46 400000 1000000
47 200000 1000000
48 >;
49 clock-latency = <100000>;
50 };
51
52 cpu@901 {
53 compatible = "arm,cortex-a9";
54 device_type = "cpu";
55 reg = <0x901>;
56 next-level-cache = <&L2>;
57 clocks = <&a9pll>;
58 clock-names = "cpu";
59 };
60
61 cpu@902 {
62 compatible = "arm,cortex-a9";
63 device_type = "cpu";
64 reg = <0x902>;
65 next-level-cache = <&L2>;
66 clocks = <&a9pll>;
67 clock-names = "cpu";
68 };
69
70 cpu@903 {
71 compatible = "arm,cortex-a9";
72 device_type = "cpu";
73 reg = <0x903>;
74 next-level-cache = <&L2>;
75 clocks = <&a9pll>;
76 clock-names = "cpu";
77 };
78 };
79
80 memory {
81 name = "memory";
82 device_type = "memory";
83 reg = <0x00000000 0xff900000>;
84 };
85
86 soc {
87 ranges = <0x00000000 0x00000000 0xffffffff>;
88
89 memory-controller@fff00000 {
90 compatible = "calxeda,hb-ddr-ctrl";
91 reg = <0xfff00000 0x1000>;
92 interrupts = <0 91 4>;
93 };
94
95 timer@fff10600 {
96 compatible = "arm,cortex-a9-twd-timer";
97 reg = <0xfff10600 0x20>;
98 interrupts = <1 13 0xf01>;
99 clocks = <&a9periphclk>;
100 };
101
102 watchdog@fff10620 {
103 compatible = "arm,cortex-a9-twd-wdt";
104 reg = <0xfff10620 0x20>;
105 interrupts = <1 14 0xf01>;
106 clocks = <&a9periphclk>;
107 };
108
109 intc: interrupt-controller@fff11000 {
110 compatible = "arm,cortex-a9-gic";
111 #interrupt-cells = <3>;
112 #size-cells = <0>;
113 #address-cells = <1>;
114 interrupt-controller;
115 reg = <0xfff11000 0x1000>,
116 <0xfff10100 0x100>;
117 };
118
119 L2: l2-cache {
120 compatible = "arm,pl310-cache";
121 reg = <0xfff12000 0x1000>;
122 interrupts = <0 70 4>;
123 cache-unified;
124 cache-level = <2>;
125 };
126
127 pmu {
128 compatible = "arm,cortex-a9-pmu";
129 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
130 };
131
132
133 sregs@fff3c200 {
134 compatible = "calxeda,hb-sregs-l2-ecc";
135 reg = <0xfff3c200 0x100>;
136 interrupts = <0 71 4 0 72 4>;
137 };
138
139 };
140};
141
142/include/ "ecx-common.dtsi"