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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SAMSUNG EXYNOS5420 SoC cpu device tree source
4 *
5 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * This file provides desired ordering for Exynos5420 and Exynos5800
9 * boards: CPU[0123] being the A15.
10 *
11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
12 * but particular boards choose different booting order.
13 *
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * booting cluster (big or LITTLE) is chosen by IROM code by reading
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
18 */
19
20/ {
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a15";
28 reg = <0x0>;
29 clocks = <&clock CLK_ARM_CLK>;
30 clock-frequency = <1800000000>;
31 cci-control-port = <&cci_control1>;
32 operating-points-v2 = <&cluster_a15_opp_table>;
33 #cooling-cells = <2>; /* min followed by max */
34 capacity-dmips-mhz = <1024>;
35 };
36
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a15";
40 reg = <0x1>;
41 clocks = <&clock CLK_ARM_CLK>;
42 clock-frequency = <1800000000>;
43 cci-control-port = <&cci_control1>;
44 operating-points-v2 = <&cluster_a15_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
46 capacity-dmips-mhz = <1024>;
47 };
48
49 cpu2: cpu@2 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a15";
52 reg = <0x2>;
53 clocks = <&clock CLK_ARM_CLK>;
54 clock-frequency = <1800000000>;
55 cci-control-port = <&cci_control1>;
56 operating-points-v2 = <&cluster_a15_opp_table>;
57 #cooling-cells = <2>; /* min followed by max */
58 capacity-dmips-mhz = <1024>;
59 };
60
61 cpu3: cpu@3 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a15";
64 reg = <0x3>;
65 clocks = <&clock CLK_ARM_CLK>;
66 clock-frequency = <1800000000>;
67 cci-control-port = <&cci_control1>;
68 operating-points-v2 = <&cluster_a15_opp_table>;
69 #cooling-cells = <2>; /* min followed by max */
70 capacity-dmips-mhz = <1024>;
71 };
72
73 cpu4: cpu@100 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a7";
76 reg = <0x100>;
77 clocks = <&clock CLK_KFC_CLK>;
78 clock-frequency = <1000000000>;
79 cci-control-port = <&cci_control0>;
80 operating-points-v2 = <&cluster_a7_opp_table>;
81 #cooling-cells = <2>; /* min followed by max */
82 capacity-dmips-mhz = <539>;
83 };
84
85 cpu5: cpu@101 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a7";
88 reg = <0x101>;
89 clocks = <&clock CLK_KFC_CLK>;
90 clock-frequency = <1000000000>;
91 cci-control-port = <&cci_control0>;
92 operating-points-v2 = <&cluster_a7_opp_table>;
93 #cooling-cells = <2>; /* min followed by max */
94 capacity-dmips-mhz = <539>;
95 };
96
97 cpu6: cpu@102 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a7";
100 reg = <0x102>;
101 clocks = <&clock CLK_KFC_CLK>;
102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
104 operating-points-v2 = <&cluster_a7_opp_table>;
105 #cooling-cells = <2>; /* min followed by max */
106 capacity-dmips-mhz = <539>;
107 };
108
109 cpu7: cpu@103 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a7";
112 reg = <0x103>;
113 clocks = <&clock CLK_KFC_CLK>;
114 clock-frequency = <1000000000>;
115 cci-control-port = <&cci_control0>;
116 operating-points-v2 = <&cluster_a7_opp_table>;
117 #cooling-cells = <2>; /* min followed by max */
118 capacity-dmips-mhz = <539>;
119 };
120 };
121};
122
123&arm_a7_pmu {
124 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
125 status = "okay";
126};
127
128&arm_a15_pmu {
129 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
130 status = "okay";
131};
1/*
2 * SAMSUNG EXYNOS5420 SoC cpu device tree source
3 *
4 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This file provides desired ordering for Exynos5420 and Exynos5800
8 * boards: CPU[0123] being the A15.
9 *
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
11 * but particular boards choose different booting order.
12 *
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
14 * booting cluster (big or LITTLE) is chosen by IROM code by reading
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23/ {
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu0: cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a15";
31 reg = <0x0>;
32 clocks = <&clock CLK_ARM_CLK>;
33 clock-frequency = <1800000000>;
34 cci-control-port = <&cci_control1>;
35 operating-points-v2 = <&cluster_a15_opp_table>;
36 cooling-min-level = <0>;
37 cooling-max-level = <11>;
38 #cooling-cells = <2>; /* min followed by max */
39 };
40
41 cpu1: cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <0x1>;
45 clock-frequency = <1800000000>;
46 cci-control-port = <&cci_control1>;
47 operating-points-v2 = <&cluster_a15_opp_table>;
48 cooling-min-level = <0>;
49 cooling-max-level = <11>;
50 #cooling-cells = <2>; /* min followed by max */
51 };
52
53 cpu2: cpu@2 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a15";
56 reg = <0x2>;
57 clock-frequency = <1800000000>;
58 cci-control-port = <&cci_control1>;
59 operating-points-v2 = <&cluster_a15_opp_table>;
60 cooling-min-level = <0>;
61 cooling-max-level = <11>;
62 #cooling-cells = <2>; /* min followed by max */
63 };
64
65 cpu3: cpu@3 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <0x3>;
69 clock-frequency = <1800000000>;
70 cci-control-port = <&cci_control1>;
71 operating-points-v2 = <&cluster_a15_opp_table>;
72 cooling-min-level = <0>;
73 cooling-max-level = <11>;
74 #cooling-cells = <2>; /* min followed by max */
75 };
76
77 cpu4: cpu@100 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a7";
80 reg = <0x100>;
81 clocks = <&clock CLK_KFC_CLK>;
82 clock-frequency = <1000000000>;
83 cci-control-port = <&cci_control0>;
84 operating-points-v2 = <&cluster_a7_opp_table>;
85 cooling-min-level = <0>;
86 cooling-max-level = <7>;
87 #cooling-cells = <2>; /* min followed by max */
88 };
89
90 cpu5: cpu@101 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0x101>;
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
96 operating-points-v2 = <&cluster_a7_opp_table>;
97 cooling-min-level = <0>;
98 cooling-max-level = <7>;
99 #cooling-cells = <2>; /* min followed by max */
100 };
101
102 cpu6: cpu@102 {
103 device_type = "cpu";
104 compatible = "arm,cortex-a7";
105 reg = <0x102>;
106 clock-frequency = <1000000000>;
107 cci-control-port = <&cci_control0>;
108 operating-points-v2 = <&cluster_a7_opp_table>;
109 cooling-min-level = <0>;
110 cooling-max-level = <7>;
111 #cooling-cells = <2>; /* min followed by max */
112 };
113
114 cpu7: cpu@103 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x103>;
118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
120 operating-points-v2 = <&cluster_a7_opp_table>;
121 cooling-min-level = <0>;
122 cooling-max-level = <7>;
123 #cooling-cells = <2>; /* min followed by max */
124 };
125 };
126};