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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 */
11
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 model = "Marvell Armada 38x family SoC";
22 compatible = "marvell,armada380";
23
24 aliases {
25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 };
30
31 pmu {
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
34 };
35
36 soc {
37 compatible = "marvell,armada380-mbus", "simple-bus";
38 #address-cells = <2>;
39 #size-cells = <1>;
40 controller = <&mbusc>;
41 interrupt-parent = <&gic>;
42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
44
45 bootrom {
46 compatible = "marvell,bootrom";
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
48 };
49
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56 clocks = <&coreclk 0>;
57 status = "disabled";
58 };
59
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 clocks = <&coreclk 0>;
67 status = "disabled";
68 };
69
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
74 #address-cells = <1>;
75 #size-cells = <1>;
76 clocks = <&coreclk 0>;
77 status = "disabled";
78 };
79
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 clocks = <&coreclk 0>;
87 status = "disabled";
88 };
89
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 clocks = <&coreclk 0>;
97 status = "disabled";
98 };
99
100 internal-regs {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
105
106 L2: cache-controller@8000 {
107 compatible = "arm,pl310-cache";
108 reg = <0x8000 0x1000>;
109 cache-unified;
110 cache-level = <2>;
111 arm,double-linefill-incr = <0>;
112 arm,double-linefill-wrap = <0>;
113 arm,double-linefill = <0>;
114 prefetch-data = <1>;
115 };
116
117 scu@c000 {
118 compatible = "arm,cortex-a9-scu";
119 reg = <0xc000 0x58>;
120 };
121
122 timer@c200 {
123 compatible = "arm,cortex-a9-global-timer";
124 reg = <0xc200 0x20>;
125 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
126 clocks = <&coreclk 2>;
127 };
128
129 timer@c600 {
130 compatible = "arm,cortex-a9-twd-timer";
131 reg = <0xc600 0x20>;
132 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
133 clocks = <&coreclk 2>;
134 };
135
136 gic: interrupt-controller@d000 {
137 compatible = "arm,cortex-a9-gic";
138 #interrupt-cells = <3>;
139 #size-cells = <0>;
140 interrupt-controller;
141 reg = <0xd000 0x1000>,
142 <0xc100 0x100>;
143 };
144
145 i2c0: i2c@11000 {
146 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
147 reg = <0x11000 0x20>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
151 timeout-ms = <1000>;
152 clocks = <&coreclk 0>;
153 status = "disabled";
154 };
155
156 i2c1: i2c@11100 {
157 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
158 reg = <0x11100 0x20>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
162 timeout-ms = <1000>;
163 clocks = <&coreclk 0>;
164 status = "disabled";
165 };
166
167 uart0: serial@12000 {
168 compatible = "marvell,armada-38x-uart";
169 reg = <0x12000 0x100>;
170 reg-shift = <2>;
171 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
172 reg-io-width = <1>;
173 clocks = <&coreclk 0>;
174 status = "disabled";
175 };
176
177 uart1: serial@12100 {
178 compatible = "marvell,armada-38x-uart";
179 reg = <0x12100 0x100>;
180 reg-shift = <2>;
181 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
182 reg-io-width = <1>;
183 clocks = <&coreclk 0>;
184 status = "disabled";
185 };
186
187 pinctrl: pinctrl@18000 {
188 reg = <0x18000 0x20>;
189
190 ge0_rgmii_pins: ge-rgmii-pins-0 {
191 marvell,pins = "mpp6", "mpp7", "mpp8",
192 "mpp9", "mpp10", "mpp11",
193 "mpp12", "mpp13", "mpp14",
194 "mpp15", "mpp16", "mpp17";
195 marvell,function = "ge0";
196 };
197
198 ge1_rgmii_pins: ge-rgmii-pins-1 {
199 marvell,pins = "mpp21", "mpp27", "mpp28",
200 "mpp29", "mpp30", "mpp31",
201 "mpp32", "mpp37", "mpp38",
202 "mpp39", "mpp40", "mpp41";
203 marvell,function = "ge1";
204 };
205
206 i2c0_pins: i2c-pins-0 {
207 marvell,pins = "mpp2", "mpp3";
208 marvell,function = "i2c0";
209 };
210
211 mdio_pins: mdio-pins {
212 marvell,pins = "mpp4", "mpp5";
213 marvell,function = "ge";
214 };
215
216 ref_clk0_pins: ref-clk-pins-0 {
217 marvell,pins = "mpp45";
218 marvell,function = "ref";
219 };
220
221 ref_clk1_pins: ref-clk-pins-1 {
222 marvell,pins = "mpp46";
223 marvell,function = "ref";
224 };
225
226 spi0_pins: spi-pins-0 {
227 marvell,pins = "mpp22", "mpp23", "mpp24",
228 "mpp25";
229 marvell,function = "spi0";
230 };
231
232 spi1_pins: spi-pins-1 {
233 marvell,pins = "mpp56", "mpp57", "mpp58",
234 "mpp59";
235 marvell,function = "spi1";
236 };
237
238 nand_pins: nand-pins {
239 marvell,pins = "mpp22", "mpp34", "mpp23",
240 "mpp33", "mpp38", "mpp28",
241 "mpp40", "mpp42", "mpp35",
242 "mpp36", "mpp25", "mpp30",
243 "mpp32";
244 marvell,function = "dev";
245 };
246
247 nand_rb: nand-rb {
248 marvell,pins = "mpp41";
249 marvell,function = "nand";
250 };
251
252 uart0_pins: uart-pins-0 {
253 marvell,pins = "mpp0", "mpp1";
254 marvell,function = "ua0";
255 };
256
257 uart1_pins: uart-pins-1 {
258 marvell,pins = "mpp19", "mpp20";
259 marvell,function = "ua1";
260 };
261
262 sdhci_pins: sdhci-pins {
263 marvell,pins = "mpp48", "mpp49", "mpp50",
264 "mpp52", "mpp53", "mpp54",
265 "mpp55", "mpp57", "mpp58",
266 "mpp59";
267 marvell,function = "sd0";
268 };
269
270 sata0_pins: sata-pins-0 {
271 marvell,pins = "mpp20";
272 marvell,function = "sata0";
273 };
274
275 sata1_pins: sata-pins-1 {
276 marvell,pins = "mpp19";
277 marvell,function = "sata1";
278 };
279
280 sata2_pins: sata-pins-2 {
281 marvell,pins = "mpp47";
282 marvell,function = "sata2";
283 };
284
285 sata3_pins: sata-pins-3 {
286 marvell,pins = "mpp44";
287 marvell,function = "sata3";
288 };
289 };
290
291 gpio0: gpio@18100 {
292 compatible = "marvell,armada-370-gpio",
293 "marvell,orion-gpio";
294 reg = <0x18100 0x40>, <0x181c0 0x08>;
295 reg-names = "gpio", "pwm";
296 ngpios = <32>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 #pwm-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&coreclk 0>;
307 };
308
309 gpio1: gpio@18140 {
310 compatible = "marvell,armada-370-gpio",
311 "marvell,orion-gpio";
312 reg = <0x18140 0x40>, <0x181c8 0x08>;
313 reg-names = "gpio", "pwm";
314 ngpios = <28>;
315 gpio-controller;
316 #gpio-cells = <2>;
317 #pwm-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&coreclk 0>;
325 };
326
327 systemc: system-controller@18200 {
328 compatible = "marvell,armada-380-system-controller",
329 "marvell,armada-370-xp-system-controller";
330 reg = <0x18200 0x100>;
331 };
332
333 gateclk: clock-gating-control@18220 {
334 compatible = "marvell,armada-380-gating-clock";
335 reg = <0x18220 0x4>;
336 clocks = <&coreclk 0>;
337 #clock-cells = <1>;
338 };
339
340 comphy: phy@18300 {
341 compatible = "marvell,armada-380-comphy";
342 reg = <0x18300 0x100>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345
346 comphy0: phy@0 {
347 reg = <0>;
348 #phy-cells = <1>;
349 };
350
351 comphy1: phy@1 {
352 reg = <1>;
353 #phy-cells = <1>;
354 };
355
356 comphy2: phy@2 {
357 reg = <2>;
358 #phy-cells = <1>;
359 };
360
361 comphy3: phy@3 {
362 reg = <3>;
363 #phy-cells = <1>;
364 };
365
366 comphy4: phy@4 {
367 reg = <4>;
368 #phy-cells = <1>;
369 };
370
371 comphy5: phy@5 {
372 reg = <5>;
373 #phy-cells = <1>;
374 };
375 };
376
377 coreclk: mvebu-sar@18600 {
378 compatible = "marvell,armada-380-core-clock";
379 reg = <0x18600 0x04>;
380 #clock-cells = <1>;
381 };
382
383 mbusc: mbus-controller@20000 {
384 compatible = "marvell,mbus-controller";
385 reg = <0x20000 0x100>, <0x20180 0x20>,
386 <0x20250 0x8>;
387 };
388
389 mpic: interrupt-controller@20a00 {
390 compatible = "marvell,mpic";
391 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
392 #interrupt-cells = <1>;
393 #size-cells = <1>;
394 interrupt-controller;
395 msi-controller;
396 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
397 };
398
399 timer: timer@20300 {
400 compatible = "marvell,armada-380-timer",
401 "marvell,armada-xp-timer";
402 reg = <0x20300 0x30>, <0x21040 0x30>;
403 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
404 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
405 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
406 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
407 <&mpic 5>,
408 <&mpic 6>;
409 clocks = <&coreclk 2>, <&refclk>;
410 clock-names = "nbclk", "fixed";
411 };
412
413 watchdog: watchdog@20300 {
414 compatible = "marvell,armada-380-wdt";
415 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
416 clocks = <&coreclk 2>, <&refclk>;
417 clock-names = "nbclk", "fixed";
418 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
419 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
420 };
421
422 cpurst: cpurst@20800 {
423 compatible = "marvell,armada-370-cpu-reset";
424 reg = <0x20800 0x10>;
425 };
426
427 mpcore-soc-ctrl@20d20 {
428 compatible = "marvell,armada-380-mpcore-soc-ctrl";
429 reg = <0x20d20 0x6c>;
430 };
431
432 coherencyfab: coherency-fabric@21010 {
433 compatible = "marvell,armada-380-coherency-fabric";
434 reg = <0x21010 0x1c>;
435 };
436
437 pmsu: pmsu@22000 {
438 compatible = "marvell,armada-380-pmsu";
439 reg = <0x22000 0x1000>;
440 };
441
442 /*
443 * As a special exception to the "order by
444 * register address" rule, the eth0 node is
445 * placed here to ensure that it gets
446 * registered as the first interface, since
447 * the network subsystem doesn't allow naming
448 * interfaces using DT aliases. Without this,
449 * the ordering of interfaces is different
450 * from the one used in U-Boot and the
451 * labeling of interfaces on the boards, which
452 * is very confusing for users.
453 */
454 eth0: ethernet@70000 {
455 compatible = "marvell,armada-370-neta";
456 reg = <0x70000 0x4000>;
457 interrupts-extended = <&mpic 8>;
458 clocks = <&gateclk 4>;
459 tx-csum-limit = <9800>;
460 status = "disabled";
461 };
462
463 eth1: ethernet@30000 {
464 compatible = "marvell,armada-370-neta";
465 reg = <0x30000 0x4000>;
466 interrupts-extended = <&mpic 10>;
467 clocks = <&gateclk 3>;
468 status = "disabled";
469 };
470
471 eth2: ethernet@34000 {
472 compatible = "marvell,armada-370-neta";
473 reg = <0x34000 0x4000>;
474 interrupts-extended = <&mpic 12>;
475 clocks = <&gateclk 2>;
476 status = "disabled";
477 };
478
479 usb0: usb@58000 {
480 compatible = "marvell,orion-ehci";
481 reg = <0x58000 0x500>;
482 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&gateclk 18>;
484 status = "disabled";
485 };
486
487 xor0: xor@60800 {
488 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
489 reg = <0x60800 0x100
490 0x60a00 0x100>;
491 clocks = <&gateclk 22>;
492 status = "okay";
493
494 xor00 {
495 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
496 dmacap,memcpy;
497 dmacap,xor;
498 };
499 xor01 {
500 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
501 dmacap,memcpy;
502 dmacap,xor;
503 dmacap,memset;
504 };
505 };
506
507 xor1: xor@60900 {
508 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
509 reg = <0x60900 0x100
510 0x60b00 0x100>;
511 clocks = <&gateclk 28>;
512 status = "okay";
513
514 xor10 {
515 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
516 dmacap,memcpy;
517 dmacap,xor;
518 };
519 xor11 {
520 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
521 dmacap,memcpy;
522 dmacap,xor;
523 dmacap,memset;
524 };
525 };
526
527 mdio: mdio@72004 {
528 #address-cells = <1>;
529 #size-cells = <0>;
530 compatible = "marvell,orion-mdio";
531 reg = <0x72004 0x4>;
532 clocks = <&gateclk 4>;
533 };
534
535 cesa: crypto@90000 {
536 compatible = "marvell,armada-38x-crypto";
537 reg = <0x90000 0x10000>;
538 reg-names = "regs";
539 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&gateclk 23>, <&gateclk 21>,
542 <&gateclk 14>, <&gateclk 16>;
543 clock-names = "cesa0", "cesa1",
544 "cesaz0", "cesaz1";
545 marvell,crypto-srams = <&crypto_sram0>,
546 <&crypto_sram1>;
547 marvell,crypto-sram-size = <0x800>;
548 };
549
550 rtc: rtc@a3800 {
551 compatible = "marvell,armada-380-rtc";
552 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
553 reg-names = "rtc", "rtc-soc";
554 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
555 };
556
557 ahci0: sata@a8000 {
558 compatible = "marvell,armada-380-ahci";
559 reg = <0xa8000 0x2000>;
560 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gateclk 15>;
562 status = "disabled";
563 };
564
565 bm: bm@c8000 {
566 compatible = "marvell,armada-380-neta-bm";
567 reg = <0xc8000 0xac>;
568 clocks = <&gateclk 13>;
569 internal-mem = <&bm_bppi>;
570 status = "disabled";
571 };
572
573 ahci1: sata@e0000 {
574 compatible = "marvell,armada-380-ahci";
575 reg = <0xe0000 0x2000>;
576 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&gateclk 30>;
578 status = "disabled";
579 };
580
581 coredivclk: clock@e4250 {
582 compatible = "marvell,armada-380-corediv-clock";
583 reg = <0xe4250 0xc>;
584 #clock-cells = <1>;
585 clocks = <&mainpll>;
586 clock-output-names = "nand";
587 };
588
589 thermal: thermal@e8078 {
590 compatible = "marvell,armada380-thermal";
591 reg = <0xe4078 0x4>, <0xe4070 0x8>;
592 status = "okay";
593 };
594
595 nand_controller: nand-controller@d0000 {
596 compatible = "marvell,armada370-nand-controller";
597 reg = <0xd0000 0x54>;
598 #address-cells = <1>;
599 #size-cells = <0>;
600 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&coredivclk 0>;
602 status = "disabled";
603 };
604
605 sdhci: sdhci@d8000 {
606 compatible = "marvell,armada-380-sdhci";
607 reg-names = "sdhci", "mbus", "conf-sdio3";
608 reg = <0xd8000 0x1000>,
609 <0xdc000 0x100>,
610 <0x18454 0x4>;
611 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&gateclk 17>;
613 mrvl,clk-delay-cycles = <0x1F>;
614 status = "disabled";
615 };
616
617 usb3_0: usb3@f0000 {
618 compatible = "marvell,armada-380-xhci";
619 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
620 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&gateclk 9>;
622 status = "disabled";
623 };
624
625 usb3_1: usb3@f8000 {
626 compatible = "marvell,armada-380-xhci";
627 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
628 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&gateclk 10>;
630 status = "disabled";
631 };
632 };
633
634 crypto_sram0: sa-sram0 {
635 compatible = "mmio-sram";
636 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
637 clocks = <&gateclk 23>;
638 #address-cells = <1>;
639 #size-cells = <1>;
640 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
641 };
642
643 crypto_sram1: sa-sram1 {
644 compatible = "mmio-sram";
645 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
646 clocks = <&gateclk 21>;
647 #address-cells = <1>;
648 #size-cells = <1>;
649 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
650 };
651
652 bm_bppi: bm-bppi {
653 compatible = "mmio-sram";
654 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
655 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
656 #address-cells = <1>;
657 #size-cells = <1>;
658 clocks = <&gateclk 13>;
659 no-memory-wc;
660 status = "disabled";
661 };
662
663 spi0: spi@10600 {
664 compatible = "marvell,armada-380-spi",
665 "marvell,orion-spi";
666 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
667 #address-cells = <1>;
668 #size-cells = <0>;
669 cell-index = <0>;
670 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&coreclk 0>;
672 status = "disabled";
673 };
674
675 spi1: spi@10680 {
676 compatible = "marvell,armada-380-spi",
677 "marvell,orion-spi";
678 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
679 #address-cells = <1>;
680 #size-cells = <0>;
681 cell-index = <1>;
682 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&coreclk 0>;
684 status = "disabled";
685 };
686 };
687
688 clocks {
689 /* 1 GHz fixed main PLL */
690 mainpll: mainpll {
691 compatible = "fixed-clock";
692 #clock-cells = <0>;
693 clock-frequency = <1000000000>;
694 };
695
696 /* 25 MHz reference crystal */
697 refclk: oscillator {
698 compatible = "fixed-clock";
699 #clock-cells = <0>;
700 clock-frequency = <25000000>;
701 };
702 };
703};
1/*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49#include "skeleton.dtsi"
50#include <dt-bindings/interrupt-controller/arm-gic.h>
51#include <dt-bindings/interrupt-controller/irq.h>
52
53#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
54
55/ {
56 model = "Marvell Armada 38x family SoC";
57 compatible = "marvell,armada380";
58
59 aliases {
60 gpio0 = &gpio0;
61 gpio1 = &gpio1;
62 serial0 = &uart0;
63 serial1 = &uart1;
64 };
65
66 pmu {
67 compatible = "arm,cortex-a9-pmu";
68 interrupts-extended = <&mpic 3>;
69 };
70
71 soc {
72 compatible = "marvell,armada380-mbus", "simple-bus";
73 #address-cells = <2>;
74 #size-cells = <1>;
75 controller = <&mbusc>;
76 interrupt-parent = <&gic>;
77 pcie-mem-aperture = <0xe0000000 0x8000000>;
78 pcie-io-aperture = <0xe8000000 0x100000>;
79
80 bootrom {
81 compatible = "marvell,bootrom";
82 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
83 };
84
85 devbus-bootcs {
86 compatible = "marvell,mvebu-devbus";
87 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
88 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 clocks = <&coreclk 0>;
92 status = "disabled";
93 };
94
95 devbus-cs0 {
96 compatible = "marvell,mvebu-devbus";
97 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
98 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 clocks = <&coreclk 0>;
102 status = "disabled";
103 };
104
105 devbus-cs1 {
106 compatible = "marvell,mvebu-devbus";
107 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
108 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
109 #address-cells = <1>;
110 #size-cells = <1>;
111 clocks = <&coreclk 0>;
112 status = "disabled";
113 };
114
115 devbus-cs2 {
116 compatible = "marvell,mvebu-devbus";
117 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
118 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
119 #address-cells = <1>;
120 #size-cells = <1>;
121 clocks = <&coreclk 0>;
122 status = "disabled";
123 };
124
125 devbus-cs3 {
126 compatible = "marvell,mvebu-devbus";
127 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
128 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131 clocks = <&coreclk 0>;
132 status = "disabled";
133 };
134
135 internal-regs {
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
140
141 L2: cache-controller@8000 {
142 compatible = "arm,pl310-cache";
143 reg = <0x8000 0x1000>;
144 cache-unified;
145 cache-level = <2>;
146 arm,double-linefill-incr = <1>;
147 arm,double-linefill-wrap = <0>;
148 arm,double-linefill = <1>;
149 prefetch-data = <1>;
150 };
151
152 scu@c000 {
153 compatible = "arm,cortex-a9-scu";
154 reg = <0xc000 0x58>;
155 };
156
157 timer@c600 {
158 compatible = "arm,cortex-a9-twd-timer";
159 reg = <0xc600 0x20>;
160 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
161 clocks = <&coreclk 2>;
162 };
163
164 gic: interrupt-controller@d000 {
165 compatible = "arm,cortex-a9-gic";
166 #interrupt-cells = <3>;
167 #size-cells = <0>;
168 interrupt-controller;
169 reg = <0xd000 0x1000>,
170 <0xc100 0x100>;
171 };
172
173 i2c0: i2c@11000 {
174 compatible = "marvell,mv64xxx-i2c";
175 reg = <0x11000 0x20>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
179 timeout-ms = <1000>;
180 clocks = <&coreclk 0>;
181 status = "disabled";
182 };
183
184 i2c1: i2c@11100 {
185 compatible = "marvell,mv64xxx-i2c";
186 reg = <0x11100 0x20>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
190 timeout-ms = <1000>;
191 clocks = <&coreclk 0>;
192 status = "disabled";
193 };
194
195 uart0: serial@12000 {
196 compatible = "snps,dw-apb-uart";
197 reg = <0x12000 0x100>;
198 reg-shift = <2>;
199 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
200 reg-io-width = <1>;
201 clocks = <&coreclk 0>;
202 status = "disabled";
203 };
204
205 uart1: serial@12100 {
206 compatible = "snps,dw-apb-uart";
207 reg = <0x12100 0x100>;
208 reg-shift = <2>;
209 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
210 reg-io-width = <1>;
211 clocks = <&coreclk 0>;
212 status = "disabled";
213 };
214
215 pinctrl: pinctrl@18000 {
216 reg = <0x18000 0x20>;
217
218 ge0_rgmii_pins: ge-rgmii-pins-0 {
219 marvell,pins = "mpp6", "mpp7", "mpp8",
220 "mpp9", "mpp10", "mpp11",
221 "mpp12", "mpp13", "mpp14",
222 "mpp15", "mpp16", "mpp17";
223 marvell,function = "ge0";
224 };
225
226 ge1_rgmii_pins: ge-rgmii-pins-1 {
227 marvell,pins = "mpp21", "mpp27", "mpp28",
228 "mpp29", "mpp30", "mpp31",
229 "mpp32", "mpp37", "mpp38",
230 "mpp39", "mpp40", "mpp41";
231 marvell,function = "ge1";
232 };
233
234 i2c0_pins: i2c-pins-0 {
235 marvell,pins = "mpp2", "mpp3";
236 marvell,function = "i2c0";
237 };
238
239 mdio_pins: mdio-pins {
240 marvell,pins = "mpp4", "mpp5";
241 marvell,function = "ge";
242 };
243
244 ref_clk0_pins: ref-clk-pins-0 {
245 marvell,pins = "mpp45";
246 marvell,function = "ref";
247 };
248
249 ref_clk1_pins: ref-clk-pins-1 {
250 marvell,pins = "mpp46";
251 marvell,function = "ref";
252 };
253
254 spi0_pins: spi-pins-0 {
255 marvell,pins = "mpp22", "mpp23", "mpp24",
256 "mpp25";
257 marvell,function = "spi0";
258 };
259
260 spi1_pins: spi-pins-1 {
261 marvell,pins = "mpp56", "mpp57", "mpp58",
262 "mpp59";
263 marvell,function = "spi1";
264 };
265
266 nand_pins: nand-pins {
267 marvell,pins = "mpp22", "mpp34", "mpp23",
268 "mpp33", "mpp38", "mpp28",
269 "mpp40", "mpp42", "mpp35",
270 "mpp36", "mpp25", "mpp30",
271 "mpp32";
272 marvell,function = "dev";
273 };
274
275 uart0_pins: uart-pins-0 {
276 marvell,pins = "mpp0", "mpp1";
277 marvell,function = "ua0";
278 };
279
280 uart1_pins: uart-pins-1 {
281 marvell,pins = "mpp19", "mpp20";
282 marvell,function = "ua1";
283 };
284
285 sdhci_pins: sdhci-pins {
286 marvell,pins = "mpp48", "mpp49", "mpp50",
287 "mpp52", "mpp53", "mpp54",
288 "mpp55", "mpp57", "mpp58",
289 "mpp59";
290 marvell,function = "sd0";
291 };
292
293 sata0_pins: sata-pins-0 {
294 marvell,pins = "mpp20";
295 marvell,function = "sata0";
296 };
297
298 sata1_pins: sata-pins-1 {
299 marvell,pins = "mpp19";
300 marvell,function = "sata1";
301 };
302
303 sata2_pins: sata-pins-2 {
304 marvell,pins = "mpp47";
305 marvell,function = "sata2";
306 };
307
308 sata3_pins: sata-pins-3 {
309 marvell,pins = "mpp44";
310 marvell,function = "sata3";
311 };
312 };
313
314 gpio0: gpio@18100 {
315 compatible = "marvell,orion-gpio";
316 reg = <0x18100 0x40>;
317 ngpios = <32>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
326 };
327
328 gpio1: gpio@18140 {
329 compatible = "marvell,orion-gpio";
330 reg = <0x18140 0x40>;
331 ngpios = <28>;
332 gpio-controller;
333 #gpio-cells = <2>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
340 };
341
342 system-controller@18200 {
343 compatible = "marvell,armada-380-system-controller",
344 "marvell,armada-370-xp-system-controller";
345 reg = <0x18200 0x100>;
346 };
347
348 gateclk: clock-gating-control@18220 {
349 compatible = "marvell,armada-380-gating-clock";
350 reg = <0x18220 0x4>;
351 clocks = <&coreclk 0>;
352 #clock-cells = <1>;
353 };
354
355 coreclk: mvebu-sar@18600 {
356 compatible = "marvell,armada-380-core-clock";
357 reg = <0x18600 0x04>;
358 #clock-cells = <1>;
359 };
360
361 mbusc: mbus-controller@20000 {
362 compatible = "marvell,mbus-controller";
363 reg = <0x20000 0x100>, <0x20180 0x20>;
364 };
365
366 mpic: interrupt-controller@20a00 {
367 compatible = "marvell,mpic";
368 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
369 #interrupt-cells = <1>;
370 #size-cells = <1>;
371 interrupt-controller;
372 msi-controller;
373 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
374 };
375
376 timer@20300 {
377 compatible = "marvell,armada-380-timer",
378 "marvell,armada-xp-timer";
379 reg = <0x20300 0x30>, <0x21040 0x30>;
380 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
381 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
382 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
383 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
384 <&mpic 5>,
385 <&mpic 6>;
386 clocks = <&coreclk 2>, <&refclk>;
387 clock-names = "nbclk", "fixed";
388 };
389
390 watchdog@20300 {
391 compatible = "marvell,armada-380-wdt";
392 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
393 clocks = <&coreclk 2>, <&refclk>;
394 clock-names = "nbclk", "fixed";
395 };
396
397 cpurst@20800 {
398 compatible = "marvell,armada-370-cpu-reset";
399 reg = <0x20800 0x10>;
400 };
401
402 mpcore-soc-ctrl@20d20 {
403 compatible = "marvell,armada-380-mpcore-soc-ctrl";
404 reg = <0x20d20 0x6c>;
405 };
406
407 coherency-fabric@21010 {
408 compatible = "marvell,armada-380-coherency-fabric";
409 reg = <0x21010 0x1c>;
410 };
411
412 pmsu@22000 {
413 compatible = "marvell,armada-380-pmsu";
414 reg = <0x22000 0x1000>;
415 };
416
417 /*
418 * As a special exception to the "order by
419 * register address" rule, the eth0 node is
420 * placed here to ensure that it gets
421 * registered as the first interface, since
422 * the network subsystem doesn't allow naming
423 * interfaces using DT aliases. Without this,
424 * the ordering of interfaces is different
425 * from the one used in U-Boot and the
426 * labeling of interfaces on the boards, which
427 * is very confusing for users.
428 */
429 eth0: ethernet@70000 {
430 compatible = "marvell,armada-370-neta";
431 reg = <0x70000 0x4000>;
432 interrupts-extended = <&mpic 8>;
433 clocks = <&gateclk 4>;
434 tx-csum-limit = <9800>;
435 status = "disabled";
436 };
437
438 eth1: ethernet@30000 {
439 compatible = "marvell,armada-370-neta";
440 reg = <0x30000 0x4000>;
441 interrupts-extended = <&mpic 10>;
442 clocks = <&gateclk 3>;
443 status = "disabled";
444 };
445
446 eth2: ethernet@34000 {
447 compatible = "marvell,armada-370-neta";
448 reg = <0x34000 0x4000>;
449 interrupts-extended = <&mpic 12>;
450 clocks = <&gateclk 2>;
451 status = "disabled";
452 };
453
454 usb@58000 {
455 compatible = "marvell,orion-ehci";
456 reg = <0x58000 0x500>;
457 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gateclk 18>;
459 status = "disabled";
460 };
461
462 xor@60800 {
463 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
464 reg = <0x60800 0x100
465 0x60a00 0x100>;
466 clocks = <&gateclk 22>;
467 status = "okay";
468
469 xor00 {
470 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
471 dmacap,memcpy;
472 dmacap,xor;
473 };
474 xor01 {
475 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
476 dmacap,memcpy;
477 dmacap,xor;
478 dmacap,memset;
479 };
480 };
481
482 xor@60900 {
483 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
484 reg = <0x60900 0x100
485 0x60b00 0x100>;
486 clocks = <&gateclk 28>;
487 status = "okay";
488
489 xor10 {
490 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
491 dmacap,memcpy;
492 dmacap,xor;
493 };
494 xor11 {
495 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
496 dmacap,memcpy;
497 dmacap,xor;
498 dmacap,memset;
499 };
500 };
501
502 mdio: mdio@72004 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "marvell,orion-mdio";
506 reg = <0x72004 0x4>;
507 clocks = <&gateclk 4>;
508 };
509
510 crypto@90000 {
511 compatible = "marvell,armada-38x-crypto";
512 reg = <0x90000 0x10000>;
513 reg-names = "regs";
514 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&gateclk 23>, <&gateclk 21>,
517 <&gateclk 14>, <&gateclk 16>;
518 clock-names = "cesa0", "cesa1",
519 "cesaz0", "cesaz1";
520 marvell,crypto-srams = <&crypto_sram0>,
521 <&crypto_sram1>;
522 marvell,crypto-sram-size = <0x800>;
523 };
524
525 rtc@a3800 {
526 compatible = "marvell,armada-380-rtc";
527 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
528 reg-names = "rtc", "rtc-soc";
529 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
530 };
531
532 sata@a8000 {
533 compatible = "marvell,armada-380-ahci";
534 reg = <0xa8000 0x2000>;
535 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&gateclk 15>;
537 status = "disabled";
538 };
539
540 bm: bm@c8000 {
541 compatible = "marvell,armada-380-neta-bm";
542 reg = <0xc8000 0xac>;
543 clocks = <&gateclk 13>;
544 internal-mem = <&bm_bppi>;
545 status = "disabled";
546 };
547
548 sata@e0000 {
549 compatible = "marvell,armada-380-ahci";
550 reg = <0xe0000 0x2000>;
551 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&gateclk 30>;
553 status = "disabled";
554 };
555
556 coredivclk: clock@e4250 {
557 compatible = "marvell,armada-380-corediv-clock";
558 reg = <0xe4250 0xc>;
559 #clock-cells = <1>;
560 clocks = <&mainpll>;
561 clock-output-names = "nand";
562 };
563
564 thermal@e8078 {
565 compatible = "marvell,armada380-thermal";
566 reg = <0xe4078 0x4>, <0xe4074 0x4>;
567 status = "okay";
568 };
569
570 flash@d0000 {
571 compatible = "marvell,armada370-nand";
572 reg = <0xd0000 0x54>;
573 #address-cells = <1>;
574 #size-cells = <1>;
575 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&coredivclk 0>;
577 status = "disabled";
578 };
579
580 sdhci@d8000 {
581 compatible = "marvell,armada-380-sdhci";
582 reg-names = "sdhci", "mbus", "conf-sdio3";
583 reg = <0xd8000 0x1000>,
584 <0xdc000 0x100>,
585 <0x18454 0x4>;
586 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&gateclk 17>;
588 mrvl,clk-delay-cycles = <0x1F>;
589 status = "disabled";
590 };
591
592 usb3@f0000 {
593 compatible = "marvell,armada-380-xhci";
594 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
595 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&gateclk 9>;
597 status = "disabled";
598 };
599
600 usb3@f8000 {
601 compatible = "marvell,armada-380-xhci";
602 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
603 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&gateclk 10>;
605 status = "disabled";
606 };
607 };
608
609 crypto_sram0: sa-sram0 {
610 compatible = "mmio-sram";
611 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
612 clocks = <&gateclk 23>;
613 #address-cells = <1>;
614 #size-cells = <1>;
615 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
616 };
617
618 crypto_sram1: sa-sram1 {
619 compatible = "mmio-sram";
620 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
621 clocks = <&gateclk 21>;
622 #address-cells = <1>;
623 #size-cells = <1>;
624 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
625 };
626
627 bm_bppi: bm-bppi {
628 compatible = "mmio-sram";
629 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
630 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
631 #address-cells = <1>;
632 #size-cells = <1>;
633 clocks = <&gateclk 13>;
634 no-memory-wc;
635 status = "disabled";
636 };
637
638 spi0: spi@10600 {
639 compatible = "marvell,armada-380-spi",
640 "marvell,orion-spi";
641 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
642 #address-cells = <1>;
643 #size-cells = <0>;
644 cell-index = <0>;
645 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&coreclk 0>;
647 status = "disabled";
648 };
649
650 spi1: spi@10680 {
651 compatible = "marvell,armada-380-spi",
652 "marvell,orion-spi";
653 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
654 #address-cells = <1>;
655 #size-cells = <0>;
656 cell-index = <1>;
657 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&coreclk 0>;
659 status = "disabled";
660 };
661 };
662
663 clocks {
664 /* 1 GHz fixed main PLL */
665 mainpll: mainpll {
666 compatible = "fixed-clock";
667 #clock-cells = <0>;
668 clock-frequency = <1000000000>;
669 };
670
671 /* 25 MHz reference crystal */
672 refclk: oscillator {
673 compatible = "fixed-clock";
674 #clock-cells = <0>;
675 clock-frequency = <25000000>;
676 };
677 };
678};