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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Marvell Armada 388 evaluation board
4 * (DB-88F6820)
5 *
6 * Copyright (C) 2014 Marvell
7 *
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 */
10
11/dts-v1/;
12#include "armada-388.dtsi"
13
14/ {
15 model = "Marvell Armada 385 Development Board";
16 compatible = "marvell,a385-db", "marvell,armada388",
17 "marvell,armada385", "marvell,armada380";
18
19 chosen {
20 stdout-path = "serial0:115200n8";
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x00000000 0x10000000>; /* 256 MB */
26 };
27
28 soc {
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
33 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
34
35 internal-regs {
36 i2c@11000 {
37 status = "okay";
38 clock-frequency = <100000>;
39 };
40
41 i2c@11100 {
42 status = "okay";
43 clock-frequency = <100000>;
44 };
45
46 serial@12000 {
47 status = "okay";
48 };
49
50 ethernet@30000 {
51 status = "okay";
52 phy = <&phy1>;
53 phy-mode = "rgmii-id";
54 buffer-manager = <&bm>;
55 bm,pool-long = <2>;
56 bm,pool-short = <3>;
57 };
58
59 usb@58000 {
60 status = "ok";
61 };
62
63 ethernet@70000 {
64 status = "okay";
65 phy = <&phy0>;
66 phy-mode = "rgmii-id";
67 buffer-manager = <&bm>;
68 bm,pool-long = <0>;
69 bm,pool-short = <1>;
70 };
71
72 mdio@72004 {
73 phy0: ethernet-phy@0 {
74 reg = <0>;
75 };
76
77 phy1: ethernet-phy@1 {
78 reg = <1>;
79 };
80 };
81
82 sata@a8000 {
83 status = "okay";
84 };
85
86 sata@e0000 {
87 status = "okay";
88 };
89
90 bm@c8000 {
91 status = "okay";
92 };
93
94 sdhci@d8000 {
95 broken-cd;
96 wp-inverted;
97 bus-width = <8>;
98 status = "okay";
99 no-1-8-v;
100 };
101
102 usb3@f0000 {
103 status = "okay";
104 };
105
106 usb3@f8000 {
107 status = "okay";
108 };
109 };
110
111 bm-bppi {
112 status = "okay";
113 };
114
115 pcie {
116 status = "okay";
117 /*
118 * The two PCIe units are accessible through
119 * standard PCIe slots on the board.
120 */
121 pcie@1,0 {
122 /* Port 0, Lane 0 */
123 status = "okay";
124 };
125 pcie@2,0 {
126 /* Port 1, Lane 0 */
127 status = "okay";
128 };
129 };
130 };
131};
132
133&spi0 {
134 status = "okay";
135
136 spi-flash@0 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 compatible = "w25q32", "jedec,spi-nor";
140 reg = <0>; /* Chip select 0 */
141 spi-max-frequency = <108000000>;
142 };
143};
144
145&nand_controller {
146 status = "okay";
147
148 nand@0 {
149 reg = <0>;
150 label = "pxa3xx_nand-0";
151 nand-rb = <0>;
152 marvell,nand-keep-config;
153 nand-on-flash-bbt;
154 nand-ecc-strength = <4>;
155 nand-ecc-step-size = <512>;
156
157 partitions {
158 compatible = "fixed-partitions";
159 #address-cells = <1>;
160 #size-cells = <1>;
161
162 partition@0 {
163 label = "U-Boot";
164 reg = <0 0x800000>;
165 };
166 partition@800000 {
167 label = "Linux";
168 reg = <0x800000 0x800000>;
169 };
170 partition@1000000 {
171 label = "Filesystem";
172 reg = <0x1000000 0x3f000000>;
173 };
174 };
175 };
176};
1/*
2 * Device Tree file for Marvell Armada 388 evaluation board
3 * (DB-88F6820)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
18 *
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * Or, alternatively
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "armada-388.dtsi"
50
51/ {
52 model = "Marvell Armada 385 Development Board";
53 compatible = "marvell,a385-db", "marvell,armada388",
54 "marvell,armada385", "marvell,armada380";
55
56 chosen {
57 stdout-path = "serial0:115200n8";
58 };
59
60 memory {
61 device_type = "memory";
62 reg = <0x00000000 0x10000000>; /* 256 MB */
63 };
64
65 soc {
66 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
67 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
68 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
69 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
70 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
71
72 internal-regs {
73 i2c@11000 {
74 status = "okay";
75 clock-frequency = <100000>;
76 };
77
78 i2c@11100 {
79 status = "okay";
80 clock-frequency = <100000>;
81 };
82
83 serial@12000 {
84 status = "okay";
85 };
86
87 ethernet@30000 {
88 status = "okay";
89 phy = <&phy1>;
90 phy-mode = "rgmii-id";
91 buffer-manager = <&bm>;
92 bm,pool-long = <2>;
93 bm,pool-short = <3>;
94 };
95
96 usb@58000 {
97 status = "ok";
98 };
99
100 ethernet@70000 {
101 status = "okay";
102 phy = <&phy0>;
103 phy-mode = "rgmii-id";
104 buffer-manager = <&bm>;
105 bm,pool-long = <0>;
106 bm,pool-short = <1>;
107 };
108
109 mdio@72004 {
110 phy0: ethernet-phy@0 {
111 reg = <0>;
112 };
113
114 phy1: ethernet-phy@1 {
115 reg = <1>;
116 };
117 };
118
119 sata@a8000 {
120 status = "okay";
121 };
122
123 sata@e0000 {
124 status = "okay";
125 };
126
127 bm@c8000 {
128 status = "okay";
129 };
130
131 flash@d0000 {
132 status = "okay";
133 num-cs = <1>;
134 marvell,nand-keep-config;
135 marvell,nand-enable-arbiter;
136 nand-on-flash-bbt;
137 nand-ecc-strength = <4>;
138 nand-ecc-step-size = <512>;
139
140 partition@0 {
141 label = "U-Boot";
142 reg = <0 0x800000>;
143 };
144 partition@800000 {
145 label = "Linux";
146 reg = <0x800000 0x800000>;
147 };
148 partition@1000000 {
149 label = "Filesystem";
150 reg = <0x1000000 0x3f000000>;
151 };
152 };
153
154 sdhci@d8000 {
155 broken-cd;
156 wp-inverted;
157 bus-width = <8>;
158 status = "okay";
159 no-1-8-v;
160 };
161
162 usb3@f0000 {
163 status = "okay";
164 };
165
166 usb3@f8000 {
167 status = "okay";
168 };
169 };
170
171 bm-bppi {
172 status = "okay";
173 };
174
175 pcie-controller {
176 status = "okay";
177 /*
178 * The two PCIe units are accessible through
179 * standard PCIe slots on the board.
180 */
181 pcie@1,0 {
182 /* Port 0, Lane 0 */
183 status = "okay";
184 };
185 pcie@2,0 {
186 /* Port 1, Lane 0 */
187 status = "okay";
188 };
189 };
190 };
191};
192
193&spi0 {
194 status = "okay";
195
196 spi-flash@0 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 compatible = "w25q32", "jedec,spi-nor";
200 reg = <0>; /* Chip select 0 */
201 spi-max-frequency = <108000000>;
202 };
203};
204