Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
4 *
5 * Based on msm_serial.c, which is:
6 * Copyright (C) 2007 Google, Inc.
7 * Author: Robert Love <rlove@google.com>
8 */
9
10#if defined(CONFIG_SERIAL_VT8500_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11# define SUPPORT_SYSRQ
12#endif
13
14#include <linux/hrtimer.h>
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/irq.h>
19#include <linux/init.h>
20#include <linux/console.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24#include <linux/serial.h>
25#include <linux/slab.h>
26#include <linux/clk.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/err.h>
30
31/*
32 * UART Register offsets
33 */
34
35#define VT8500_URTDR 0x0000 /* Transmit data */
36#define VT8500_URRDR 0x0004 /* Receive data */
37#define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
38#define VT8500_URLCR 0x000C /* Line control */
39#define VT8500_URICR 0x0010 /* IrDA control */
40#define VT8500_URIER 0x0014 /* Interrupt enable */
41#define VT8500_URISR 0x0018 /* Interrupt status */
42#define VT8500_URUSR 0x001c /* UART status */
43#define VT8500_URFCR 0x0020 /* FIFO control */
44#define VT8500_URFIDX 0x0024 /* FIFO index */
45#define VT8500_URBKR 0x0028 /* Break signal count */
46#define VT8500_URTOD 0x002c /* Time out divisor */
47#define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
48#define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
49
50/*
51 * Interrupt enable and status bits
52 */
53
54#define TXDE (1 << 0) /* Tx Data empty */
55#define RXDF (1 << 1) /* Rx Data full */
56#define TXFAE (1 << 2) /* Tx FIFO almost empty */
57#define TXFE (1 << 3) /* Tx FIFO empty */
58#define RXFAF (1 << 4) /* Rx FIFO almost full */
59#define RXFF (1 << 5) /* Rx FIFO full */
60#define TXUDR (1 << 6) /* Tx underrun */
61#define RXOVER (1 << 7) /* Rx overrun */
62#define PER (1 << 8) /* Parity error */
63#define FER (1 << 9) /* Frame error */
64#define TCTS (1 << 10) /* Toggle of CTS */
65#define RXTOUT (1 << 11) /* Rx timeout */
66#define BKDONE (1 << 12) /* Break signal done */
67#define ERR (1 << 13) /* AHB error response */
68
69#define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
70#define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
71
72/*
73 * Line control bits
74 */
75
76#define VT8500_TXEN (1 << 0) /* Enable transmit logic */
77#define VT8500_RXEN (1 << 1) /* Enable receive logic */
78#define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
79#define VT8500_CSTOPB (1 << 3) /* 2 stop bits (vs. 1) */
80#define VT8500_PARENB (1 << 4) /* Enable parity */
81#define VT8500_PARODD (1 << 5) /* Odd parity (vs. even) */
82#define VT8500_RTS (1 << 6) /* Ready to send */
83#define VT8500_LOOPBK (1 << 7) /* Enable internal loopback */
84#define VT8500_DMA (1 << 8) /* Enable DMA mode (needs FIFO) */
85#define VT8500_BREAK (1 << 9) /* Initiate break signal */
86#define VT8500_PSLVERR (1 << 10) /* APB error upon empty RX FIFO read */
87#define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
88
89/*
90 * Capability flags (driver-internal)
91 */
92
93#define VT8500_HAS_SWRTSCTS_SWITCH (1 << 1)
94
95#define VT8500_RECOMMENDED_CLK 12000000
96#define VT8500_OVERSAMPLING_DIVISOR 13
97#define VT8500_MAX_PORTS 6
98
99struct vt8500_port {
100 struct uart_port uart;
101 char name[16];
102 struct clk *clk;
103 unsigned int clk_predivisor;
104 unsigned int ier;
105 unsigned int vt8500_uart_flags;
106};
107
108/*
109 * we use this variable to keep track of which ports
110 * have been allocated as we can't use pdev->id in
111 * devicetree
112 */
113static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
114
115static inline void vt8500_write(struct uart_port *port, unsigned int val,
116 unsigned int off)
117{
118 writel(val, port->membase + off);
119}
120
121static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
122{
123 return readl(port->membase + off);
124}
125
126static void vt8500_stop_tx(struct uart_port *port)
127{
128 struct vt8500_port *vt8500_port = container_of(port,
129 struct vt8500_port,
130 uart);
131
132 vt8500_port->ier &= ~TX_FIFO_INTS;
133 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
134}
135
136static void vt8500_stop_rx(struct uart_port *port)
137{
138 struct vt8500_port *vt8500_port = container_of(port,
139 struct vt8500_port,
140 uart);
141
142 vt8500_port->ier &= ~RX_FIFO_INTS;
143 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
144}
145
146static void vt8500_enable_ms(struct uart_port *port)
147{
148 struct vt8500_port *vt8500_port = container_of(port,
149 struct vt8500_port,
150 uart);
151
152 vt8500_port->ier |= TCTS;
153 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
154}
155
156static void handle_rx(struct uart_port *port)
157{
158 struct tty_port *tport = &port->state->port;
159
160 /*
161 * Handle overrun
162 */
163 if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
164 port->icount.overrun++;
165 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
166 }
167
168 /* and now the main RX loop */
169 while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
170 unsigned int c;
171 char flag = TTY_NORMAL;
172
173 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
174
175 /* Mask conditions we're ignorning. */
176 c &= ~port->read_status_mask;
177
178 if (c & FER) {
179 port->icount.frame++;
180 flag = TTY_FRAME;
181 } else if (c & PER) {
182 port->icount.parity++;
183 flag = TTY_PARITY;
184 }
185 port->icount.rx++;
186
187 if (!uart_handle_sysrq_char(port, c))
188 tty_insert_flip_char(tport, c, flag);
189 }
190
191 spin_unlock(&port->lock);
192 tty_flip_buffer_push(tport);
193 spin_lock(&port->lock);
194}
195
196static void handle_tx(struct uart_port *port)
197{
198 struct circ_buf *xmit = &port->state->xmit;
199
200 if (port->x_char) {
201 writeb(port->x_char, port->membase + VT8500_TXFIFO);
202 port->icount.tx++;
203 port->x_char = 0;
204 }
205 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
206 vt8500_stop_tx(port);
207 return;
208 }
209
210 while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
211 if (uart_circ_empty(xmit))
212 break;
213
214 writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
215
216 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
217 port->icount.tx++;
218 }
219
220 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
221 uart_write_wakeup(port);
222
223 if (uart_circ_empty(xmit))
224 vt8500_stop_tx(port);
225}
226
227static void vt8500_start_tx(struct uart_port *port)
228{
229 struct vt8500_port *vt8500_port = container_of(port,
230 struct vt8500_port,
231 uart);
232
233 vt8500_port->ier &= ~TX_FIFO_INTS;
234 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
235 handle_tx(port);
236 vt8500_port->ier |= TX_FIFO_INTS;
237 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
238}
239
240static void handle_delta_cts(struct uart_port *port)
241{
242 port->icount.cts++;
243 wake_up_interruptible(&port->state->port.delta_msr_wait);
244}
245
246static irqreturn_t vt8500_irq(int irq, void *dev_id)
247{
248 struct uart_port *port = dev_id;
249 unsigned long isr;
250
251 spin_lock(&port->lock);
252 isr = vt8500_read(port, VT8500_URISR);
253
254 /* Acknowledge active status bits */
255 vt8500_write(port, isr, VT8500_URISR);
256
257 if (isr & RX_FIFO_INTS)
258 handle_rx(port);
259 if (isr & TX_FIFO_INTS)
260 handle_tx(port);
261 if (isr & TCTS)
262 handle_delta_cts(port);
263
264 spin_unlock(&port->lock);
265
266 return IRQ_HANDLED;
267}
268
269static unsigned int vt8500_tx_empty(struct uart_port *port)
270{
271 return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
272 TIOCSER_TEMT : 0;
273}
274
275static unsigned int vt8500_get_mctrl(struct uart_port *port)
276{
277 unsigned int usr;
278
279 usr = vt8500_read(port, VT8500_URUSR);
280 if (usr & (1 << 4))
281 return TIOCM_CTS;
282 else
283 return 0;
284}
285
286static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
287{
288 unsigned int lcr = vt8500_read(port, VT8500_URLCR);
289
290 if (mctrl & TIOCM_RTS)
291 lcr |= VT8500_RTS;
292 else
293 lcr &= ~VT8500_RTS;
294
295 vt8500_write(port, lcr, VT8500_URLCR);
296}
297
298static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
299{
300 if (break_ctl)
301 vt8500_write(port,
302 vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
303 VT8500_URLCR);
304}
305
306static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
307{
308 struct vt8500_port *vt8500_port =
309 container_of(port, struct vt8500_port, uart);
310 unsigned long div;
311 unsigned int loops = 1000;
312
313 div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
314 div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
315
316 /* Effective baud rate */
317 baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
318
319 while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
320 cpu_relax();
321
322 vt8500_write(port, div, VT8500_URDIV);
323
324 /* Break signal timing depends on baud rate, update accordingly */
325 vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
326
327 return baud;
328}
329
330static int vt8500_startup(struct uart_port *port)
331{
332 struct vt8500_port *vt8500_port =
333 container_of(port, struct vt8500_port, uart);
334 int ret;
335
336 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
337 "vt8500_serial%d", port->line);
338
339 ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
340 vt8500_port->name, port);
341 if (unlikely(ret))
342 return ret;
343
344 vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
345
346 return 0;
347}
348
349static void vt8500_shutdown(struct uart_port *port)
350{
351 struct vt8500_port *vt8500_port =
352 container_of(port, struct vt8500_port, uart);
353
354 vt8500_port->ier = 0;
355
356 /* disable interrupts and FIFOs */
357 vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
358 vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
359 free_irq(port->irq, port);
360}
361
362static void vt8500_set_termios(struct uart_port *port,
363 struct ktermios *termios,
364 struct ktermios *old)
365{
366 struct vt8500_port *vt8500_port =
367 container_of(port, struct vt8500_port, uart);
368 unsigned long flags;
369 unsigned int baud, lcr;
370 unsigned int loops = 1000;
371
372 spin_lock_irqsave(&port->lock, flags);
373
374 /* calculate and set baud rate */
375 baud = uart_get_baud_rate(port, termios, old, 900, 921600);
376 baud = vt8500_set_baud_rate(port, baud);
377 if (tty_termios_baud_rate(termios))
378 tty_termios_encode_baud_rate(termios, baud, baud);
379
380 /* calculate parity */
381 lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
382 lcr &= ~(VT8500_PARENB | VT8500_PARODD);
383 if (termios->c_cflag & PARENB) {
384 lcr |= VT8500_PARENB;
385 termios->c_cflag &= ~CMSPAR;
386 if (termios->c_cflag & PARODD)
387 lcr |= VT8500_PARODD;
388 }
389
390 /* calculate bits per char */
391 lcr &= ~VT8500_CS8;
392 switch (termios->c_cflag & CSIZE) {
393 case CS7:
394 break;
395 case CS8:
396 default:
397 lcr |= VT8500_CS8;
398 termios->c_cflag &= ~CSIZE;
399 termios->c_cflag |= CS8;
400 break;
401 }
402
403 /* calculate stop bits */
404 lcr &= ~VT8500_CSTOPB;
405 if (termios->c_cflag & CSTOPB)
406 lcr |= VT8500_CSTOPB;
407
408 lcr &= ~VT8500_SWRTSCTS;
409 if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
410 lcr |= VT8500_SWRTSCTS;
411
412 /* set parity, bits per char, and stop bit */
413 vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
414
415 /* Configure status bits to ignore based on termio flags. */
416 port->read_status_mask = 0;
417 if (termios->c_iflag & IGNPAR)
418 port->read_status_mask = FER | PER;
419
420 uart_update_timeout(port, termios->c_cflag, baud);
421
422 /* Reset FIFOs */
423 vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
424 while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
425 && --loops)
426 cpu_relax();
427
428 /* Every possible FIFO-related interrupt */
429 vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
430
431 /*
432 * CTS flow control
433 */
434 if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
435 vt8500_port->ier |= TCTS;
436
437 vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
438 vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
439
440 spin_unlock_irqrestore(&port->lock, flags);
441}
442
443static const char *vt8500_type(struct uart_port *port)
444{
445 struct vt8500_port *vt8500_port =
446 container_of(port, struct vt8500_port, uart);
447 return vt8500_port->name;
448}
449
450static void vt8500_release_port(struct uart_port *port)
451{
452}
453
454static int vt8500_request_port(struct uart_port *port)
455{
456 return 0;
457}
458
459static void vt8500_config_port(struct uart_port *port, int flags)
460{
461 port->type = PORT_VT8500;
462}
463
464static int vt8500_verify_port(struct uart_port *port,
465 struct serial_struct *ser)
466{
467 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
468 return -EINVAL;
469 if (unlikely(port->irq != ser->irq))
470 return -EINVAL;
471 return 0;
472}
473
474static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
475static struct uart_driver vt8500_uart_driver;
476
477#ifdef CONFIG_SERIAL_VT8500_CONSOLE
478
479static void wait_for_xmitr(struct uart_port *port)
480{
481 unsigned int status, tmout = 10000;
482
483 /* Wait up to 10ms for the character(s) to be sent. */
484 do {
485 status = vt8500_read(port, VT8500_URFIDX);
486
487 if (--tmout == 0)
488 break;
489 udelay(1);
490 } while (status & 0x10);
491}
492
493static void vt8500_console_putchar(struct uart_port *port, int c)
494{
495 wait_for_xmitr(port);
496 writeb(c, port->membase + VT8500_TXFIFO);
497}
498
499static void vt8500_console_write(struct console *co, const char *s,
500 unsigned int count)
501{
502 struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
503 unsigned long ier;
504
505 BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
506
507 ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
508 vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
509
510 uart_console_write(&vt8500_port->uart, s, count,
511 vt8500_console_putchar);
512
513 /*
514 * Finally, wait for transmitter to become empty
515 * and switch back to FIFO
516 */
517 wait_for_xmitr(&vt8500_port->uart);
518 vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
519}
520
521static int __init vt8500_console_setup(struct console *co, char *options)
522{
523 struct vt8500_port *vt8500_port;
524 int baud = 9600;
525 int bits = 8;
526 int parity = 'n';
527 int flow = 'n';
528
529 if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
530 return -ENXIO;
531
532 vt8500_port = vt8500_uart_ports[co->index];
533
534 if (!vt8500_port)
535 return -ENODEV;
536
537 if (options)
538 uart_parse_options(options, &baud, &parity, &bits, &flow);
539
540 return uart_set_options(&vt8500_port->uart,
541 co, baud, parity, bits, flow);
542}
543
544static struct console vt8500_console = {
545 .name = "ttyWMT",
546 .write = vt8500_console_write,
547 .device = uart_console_device,
548 .setup = vt8500_console_setup,
549 .flags = CON_PRINTBUFFER,
550 .index = -1,
551 .data = &vt8500_uart_driver,
552};
553
554#define VT8500_CONSOLE (&vt8500_console)
555
556#else
557#define VT8500_CONSOLE NULL
558#endif
559
560#ifdef CONFIG_CONSOLE_POLL
561static int vt8500_get_poll_char(struct uart_port *port)
562{
563 unsigned int status = vt8500_read(port, VT8500_URFIDX);
564
565 if (!(status & 0x1f00))
566 return NO_POLL_CHAR;
567
568 return vt8500_read(port, VT8500_RXFIFO) & 0xff;
569}
570
571static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
572{
573 unsigned int status, tmout = 10000;
574
575 do {
576 status = vt8500_read(port, VT8500_URFIDX);
577
578 if (--tmout == 0)
579 break;
580 udelay(1);
581 } while (status & 0x10);
582
583 vt8500_write(port, c, VT8500_TXFIFO);
584}
585#endif
586
587static const struct uart_ops vt8500_uart_pops = {
588 .tx_empty = vt8500_tx_empty,
589 .set_mctrl = vt8500_set_mctrl,
590 .get_mctrl = vt8500_get_mctrl,
591 .stop_tx = vt8500_stop_tx,
592 .start_tx = vt8500_start_tx,
593 .stop_rx = vt8500_stop_rx,
594 .enable_ms = vt8500_enable_ms,
595 .break_ctl = vt8500_break_ctl,
596 .startup = vt8500_startup,
597 .shutdown = vt8500_shutdown,
598 .set_termios = vt8500_set_termios,
599 .type = vt8500_type,
600 .release_port = vt8500_release_port,
601 .request_port = vt8500_request_port,
602 .config_port = vt8500_config_port,
603 .verify_port = vt8500_verify_port,
604#ifdef CONFIG_CONSOLE_POLL
605 .poll_get_char = vt8500_get_poll_char,
606 .poll_put_char = vt8500_put_poll_char,
607#endif
608};
609
610static struct uart_driver vt8500_uart_driver = {
611 .owner = THIS_MODULE,
612 .driver_name = "vt8500_serial",
613 .dev_name = "ttyWMT",
614 .nr = 6,
615 .cons = VT8500_CONSOLE,
616};
617
618static unsigned int vt8500_flags; /* none required so far */
619static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
620
621static const struct of_device_id wmt_dt_ids[] = {
622 { .compatible = "via,vt8500-uart", .data = &vt8500_flags},
623 { .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
624 {}
625};
626
627static int vt8500_serial_probe(struct platform_device *pdev)
628{
629 struct vt8500_port *vt8500_port;
630 struct resource *mmres, *irqres;
631 struct device_node *np = pdev->dev.of_node;
632 const struct of_device_id *match;
633 const unsigned int *flags;
634 int ret;
635 int port;
636
637 match = of_match_device(wmt_dt_ids, &pdev->dev);
638 if (!match)
639 return -EINVAL;
640
641 flags = match->data;
642
643 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
644 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
645 if (!mmres || !irqres)
646 return -ENODEV;
647
648 if (np) {
649 port = of_alias_get_id(np, "serial");
650 if (port >= VT8500_MAX_PORTS)
651 port = -1;
652 } else {
653 port = -1;
654 }
655
656 if (port < 0) {
657 /* calculate the port id */
658 port = find_first_zero_bit(vt8500_ports_in_use,
659 VT8500_MAX_PORTS);
660 }
661
662 if (port >= VT8500_MAX_PORTS)
663 return -ENODEV;
664
665 /* reserve the port id */
666 if (test_and_set_bit(port, vt8500_ports_in_use)) {
667 /* port already in use - shouldn't really happen */
668 return -EBUSY;
669 }
670
671 vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
672 GFP_KERNEL);
673 if (!vt8500_port)
674 return -ENOMEM;
675
676 vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
677 if (IS_ERR(vt8500_port->uart.membase))
678 return PTR_ERR(vt8500_port->uart.membase);
679
680 vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
681 if (IS_ERR(vt8500_port->clk)) {
682 dev_err(&pdev->dev, "failed to get clock\n");
683 return -EINVAL;
684 }
685
686 ret = clk_prepare_enable(vt8500_port->clk);
687 if (ret) {
688 dev_err(&pdev->dev, "failed to enable clock\n");
689 return ret;
690 }
691
692 vt8500_port->vt8500_uart_flags = *flags;
693 vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
694 clk_get_rate(vt8500_port->clk),
695 VT8500_RECOMMENDED_CLK
696 );
697 vt8500_port->uart.type = PORT_VT8500;
698 vt8500_port->uart.iotype = UPIO_MEM;
699 vt8500_port->uart.mapbase = mmres->start;
700 vt8500_port->uart.irq = irqres->start;
701 vt8500_port->uart.fifosize = 16;
702 vt8500_port->uart.ops = &vt8500_uart_pops;
703 vt8500_port->uart.line = port;
704 vt8500_port->uart.dev = &pdev->dev;
705 vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
706
707 /* Serial core uses the magic "16" everywhere - adjust for it */
708 vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
709 vt8500_port->clk_predivisor /
710 VT8500_OVERSAMPLING_DIVISOR;
711
712 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
713 "VT8500 UART%d", pdev->id);
714
715 vt8500_uart_ports[port] = vt8500_port;
716
717 uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
718
719 platform_set_drvdata(pdev, vt8500_port);
720
721 return 0;
722}
723
724static struct platform_driver vt8500_platform_driver = {
725 .probe = vt8500_serial_probe,
726 .driver = {
727 .name = "vt8500_serial",
728 .of_match_table = wmt_dt_ids,
729 .suppress_bind_attrs = true,
730 },
731};
732
733static int __init vt8500_serial_init(void)
734{
735 int ret;
736
737 ret = uart_register_driver(&vt8500_uart_driver);
738 if (unlikely(ret))
739 return ret;
740
741 ret = platform_driver_register(&vt8500_platform_driver);
742
743 if (unlikely(ret))
744 uart_unregister_driver(&vt8500_uart_driver);
745
746 return ret;
747}
748device_initcall(vt8500_serial_init);
1/*
2 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
3 *
4 * Based on msm_serial.c, which is:
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#if defined(CONFIG_SERIAL_VT8500_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19# define SUPPORT_SYSRQ
20#endif
21
22#include <linux/hrtimer.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/ioport.h>
26#include <linux/irq.h>
27#include <linux/init.h>
28#include <linux/console.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/serial_core.h>
32#include <linux/serial.h>
33#include <linux/slab.h>
34#include <linux/clk.h>
35#include <linux/of.h>
36#include <linux/of_device.h>
37#include <linux/err.h>
38
39/*
40 * UART Register offsets
41 */
42
43#define VT8500_URTDR 0x0000 /* Transmit data */
44#define VT8500_URRDR 0x0004 /* Receive data */
45#define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
46#define VT8500_URLCR 0x000C /* Line control */
47#define VT8500_URICR 0x0010 /* IrDA control */
48#define VT8500_URIER 0x0014 /* Interrupt enable */
49#define VT8500_URISR 0x0018 /* Interrupt status */
50#define VT8500_URUSR 0x001c /* UART status */
51#define VT8500_URFCR 0x0020 /* FIFO control */
52#define VT8500_URFIDX 0x0024 /* FIFO index */
53#define VT8500_URBKR 0x0028 /* Break signal count */
54#define VT8500_URTOD 0x002c /* Time out divisor */
55#define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
56#define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
57
58/*
59 * Interrupt enable and status bits
60 */
61
62#define TXDE (1 << 0) /* Tx Data empty */
63#define RXDF (1 << 1) /* Rx Data full */
64#define TXFAE (1 << 2) /* Tx FIFO almost empty */
65#define TXFE (1 << 3) /* Tx FIFO empty */
66#define RXFAF (1 << 4) /* Rx FIFO almost full */
67#define RXFF (1 << 5) /* Rx FIFO full */
68#define TXUDR (1 << 6) /* Tx underrun */
69#define RXOVER (1 << 7) /* Rx overrun */
70#define PER (1 << 8) /* Parity error */
71#define FER (1 << 9) /* Frame error */
72#define TCTS (1 << 10) /* Toggle of CTS */
73#define RXTOUT (1 << 11) /* Rx timeout */
74#define BKDONE (1 << 12) /* Break signal done */
75#define ERR (1 << 13) /* AHB error response */
76
77#define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
78#define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
79
80/*
81 * Line control bits
82 */
83
84#define VT8500_TXEN (1 << 0) /* Enable transmit logic */
85#define VT8500_RXEN (1 << 1) /* Enable receive logic */
86#define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
87#define VT8500_CSTOPB (1 << 3) /* 2 stop bits (vs. 1) */
88#define VT8500_PARENB (1 << 4) /* Enable parity */
89#define VT8500_PARODD (1 << 5) /* Odd parity (vs. even) */
90#define VT8500_RTS (1 << 6) /* Ready to send */
91#define VT8500_LOOPBK (1 << 7) /* Enable internal loopback */
92#define VT8500_DMA (1 << 8) /* Enable DMA mode (needs FIFO) */
93#define VT8500_BREAK (1 << 9) /* Initiate break signal */
94#define VT8500_PSLVERR (1 << 10) /* APB error upon empty RX FIFO read */
95#define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
96
97/*
98 * Capability flags (driver-internal)
99 */
100
101#define VT8500_HAS_SWRTSCTS_SWITCH (1 << 1)
102
103#define VT8500_RECOMMENDED_CLK 12000000
104#define VT8500_OVERSAMPLING_DIVISOR 13
105#define VT8500_MAX_PORTS 6
106
107struct vt8500_port {
108 struct uart_port uart;
109 char name[16];
110 struct clk *clk;
111 unsigned int clk_predivisor;
112 unsigned int ier;
113 unsigned int vt8500_uart_flags;
114};
115
116/*
117 * we use this variable to keep track of which ports
118 * have been allocated as we can't use pdev->id in
119 * devicetree
120 */
121static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
122
123static inline void vt8500_write(struct uart_port *port, unsigned int val,
124 unsigned int off)
125{
126 writel(val, port->membase + off);
127}
128
129static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
130{
131 return readl(port->membase + off);
132}
133
134static void vt8500_stop_tx(struct uart_port *port)
135{
136 struct vt8500_port *vt8500_port = container_of(port,
137 struct vt8500_port,
138 uart);
139
140 vt8500_port->ier &= ~TX_FIFO_INTS;
141 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
142}
143
144static void vt8500_stop_rx(struct uart_port *port)
145{
146 struct vt8500_port *vt8500_port = container_of(port,
147 struct vt8500_port,
148 uart);
149
150 vt8500_port->ier &= ~RX_FIFO_INTS;
151 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
152}
153
154static void vt8500_enable_ms(struct uart_port *port)
155{
156 struct vt8500_port *vt8500_port = container_of(port,
157 struct vt8500_port,
158 uart);
159
160 vt8500_port->ier |= TCTS;
161 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
162}
163
164static void handle_rx(struct uart_port *port)
165{
166 struct tty_port *tport = &port->state->port;
167
168 /*
169 * Handle overrun
170 */
171 if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
172 port->icount.overrun++;
173 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
174 }
175
176 /* and now the main RX loop */
177 while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
178 unsigned int c;
179 char flag = TTY_NORMAL;
180
181 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
182
183 /* Mask conditions we're ignorning. */
184 c &= ~port->read_status_mask;
185
186 if (c & FER) {
187 port->icount.frame++;
188 flag = TTY_FRAME;
189 } else if (c & PER) {
190 port->icount.parity++;
191 flag = TTY_PARITY;
192 }
193 port->icount.rx++;
194
195 if (!uart_handle_sysrq_char(port, c))
196 tty_insert_flip_char(tport, c, flag);
197 }
198
199 spin_unlock(&port->lock);
200 tty_flip_buffer_push(tport);
201 spin_lock(&port->lock);
202}
203
204static void handle_tx(struct uart_port *port)
205{
206 struct circ_buf *xmit = &port->state->xmit;
207
208 if (port->x_char) {
209 writeb(port->x_char, port->membase + VT8500_TXFIFO);
210 port->icount.tx++;
211 port->x_char = 0;
212 }
213 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
214 vt8500_stop_tx(port);
215 return;
216 }
217
218 while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
219 if (uart_circ_empty(xmit))
220 break;
221
222 writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
223
224 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
225 port->icount.tx++;
226 }
227
228 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
229 uart_write_wakeup(port);
230
231 if (uart_circ_empty(xmit))
232 vt8500_stop_tx(port);
233}
234
235static void vt8500_start_tx(struct uart_port *port)
236{
237 struct vt8500_port *vt8500_port = container_of(port,
238 struct vt8500_port,
239 uart);
240
241 vt8500_port->ier &= ~TX_FIFO_INTS;
242 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
243 handle_tx(port);
244 vt8500_port->ier |= TX_FIFO_INTS;
245 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
246}
247
248static void handle_delta_cts(struct uart_port *port)
249{
250 port->icount.cts++;
251 wake_up_interruptible(&port->state->port.delta_msr_wait);
252}
253
254static irqreturn_t vt8500_irq(int irq, void *dev_id)
255{
256 struct uart_port *port = dev_id;
257 unsigned long isr;
258
259 spin_lock(&port->lock);
260 isr = vt8500_read(port, VT8500_URISR);
261
262 /* Acknowledge active status bits */
263 vt8500_write(port, isr, VT8500_URISR);
264
265 if (isr & RX_FIFO_INTS)
266 handle_rx(port);
267 if (isr & TX_FIFO_INTS)
268 handle_tx(port);
269 if (isr & TCTS)
270 handle_delta_cts(port);
271
272 spin_unlock(&port->lock);
273
274 return IRQ_HANDLED;
275}
276
277static unsigned int vt8500_tx_empty(struct uart_port *port)
278{
279 return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
280 TIOCSER_TEMT : 0;
281}
282
283static unsigned int vt8500_get_mctrl(struct uart_port *port)
284{
285 unsigned int usr;
286
287 usr = vt8500_read(port, VT8500_URUSR);
288 if (usr & (1 << 4))
289 return TIOCM_CTS;
290 else
291 return 0;
292}
293
294static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
295{
296 unsigned int lcr = vt8500_read(port, VT8500_URLCR);
297
298 if (mctrl & TIOCM_RTS)
299 lcr |= VT8500_RTS;
300 else
301 lcr &= ~VT8500_RTS;
302
303 vt8500_write(port, lcr, VT8500_URLCR);
304}
305
306static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
307{
308 if (break_ctl)
309 vt8500_write(port,
310 vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
311 VT8500_URLCR);
312}
313
314static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
315{
316 struct vt8500_port *vt8500_port =
317 container_of(port, struct vt8500_port, uart);
318 unsigned long div;
319 unsigned int loops = 1000;
320
321 div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
322 div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
323
324 /* Effective baud rate */
325 baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
326
327 while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
328 cpu_relax();
329
330 vt8500_write(port, div, VT8500_URDIV);
331
332 /* Break signal timing depends on baud rate, update accordingly */
333 vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
334
335 return baud;
336}
337
338static int vt8500_startup(struct uart_port *port)
339{
340 struct vt8500_port *vt8500_port =
341 container_of(port, struct vt8500_port, uart);
342 int ret;
343
344 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
345 "vt8500_serial%d", port->line);
346
347 ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
348 vt8500_port->name, port);
349 if (unlikely(ret))
350 return ret;
351
352 vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
353
354 return 0;
355}
356
357static void vt8500_shutdown(struct uart_port *port)
358{
359 struct vt8500_port *vt8500_port =
360 container_of(port, struct vt8500_port, uart);
361
362 vt8500_port->ier = 0;
363
364 /* disable interrupts and FIFOs */
365 vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
366 vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
367 free_irq(port->irq, port);
368}
369
370static void vt8500_set_termios(struct uart_port *port,
371 struct ktermios *termios,
372 struct ktermios *old)
373{
374 struct vt8500_port *vt8500_port =
375 container_of(port, struct vt8500_port, uart);
376 unsigned long flags;
377 unsigned int baud, lcr;
378 unsigned int loops = 1000;
379
380 spin_lock_irqsave(&port->lock, flags);
381
382 /* calculate and set baud rate */
383 baud = uart_get_baud_rate(port, termios, old, 900, 921600);
384 baud = vt8500_set_baud_rate(port, baud);
385 if (tty_termios_baud_rate(termios))
386 tty_termios_encode_baud_rate(termios, baud, baud);
387
388 /* calculate parity */
389 lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
390 lcr &= ~(VT8500_PARENB | VT8500_PARODD);
391 if (termios->c_cflag & PARENB) {
392 lcr |= VT8500_PARENB;
393 termios->c_cflag &= ~CMSPAR;
394 if (termios->c_cflag & PARODD)
395 lcr |= VT8500_PARODD;
396 }
397
398 /* calculate bits per char */
399 lcr &= ~VT8500_CS8;
400 switch (termios->c_cflag & CSIZE) {
401 case CS7:
402 break;
403 case CS8:
404 default:
405 lcr |= VT8500_CS8;
406 termios->c_cflag &= ~CSIZE;
407 termios->c_cflag |= CS8;
408 break;
409 }
410
411 /* calculate stop bits */
412 lcr &= ~VT8500_CSTOPB;
413 if (termios->c_cflag & CSTOPB)
414 lcr |= VT8500_CSTOPB;
415
416 lcr &= ~VT8500_SWRTSCTS;
417 if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
418 lcr |= VT8500_SWRTSCTS;
419
420 /* set parity, bits per char, and stop bit */
421 vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
422
423 /* Configure status bits to ignore based on termio flags. */
424 port->read_status_mask = 0;
425 if (termios->c_iflag & IGNPAR)
426 port->read_status_mask = FER | PER;
427
428 uart_update_timeout(port, termios->c_cflag, baud);
429
430 /* Reset FIFOs */
431 vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
432 while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
433 && --loops)
434 cpu_relax();
435
436 /* Every possible FIFO-related interrupt */
437 vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
438
439 /*
440 * CTS flow control
441 */
442 if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
443 vt8500_port->ier |= TCTS;
444
445 vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
446 vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
447
448 spin_unlock_irqrestore(&port->lock, flags);
449}
450
451static const char *vt8500_type(struct uart_port *port)
452{
453 struct vt8500_port *vt8500_port =
454 container_of(port, struct vt8500_port, uart);
455 return vt8500_port->name;
456}
457
458static void vt8500_release_port(struct uart_port *port)
459{
460}
461
462static int vt8500_request_port(struct uart_port *port)
463{
464 return 0;
465}
466
467static void vt8500_config_port(struct uart_port *port, int flags)
468{
469 port->type = PORT_VT8500;
470}
471
472static int vt8500_verify_port(struct uart_port *port,
473 struct serial_struct *ser)
474{
475 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
476 return -EINVAL;
477 if (unlikely(port->irq != ser->irq))
478 return -EINVAL;
479 return 0;
480}
481
482static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
483static struct uart_driver vt8500_uart_driver;
484
485#ifdef CONFIG_SERIAL_VT8500_CONSOLE
486
487static void wait_for_xmitr(struct uart_port *port)
488{
489 unsigned int status, tmout = 10000;
490
491 /* Wait up to 10ms for the character(s) to be sent. */
492 do {
493 status = vt8500_read(port, VT8500_URFIDX);
494
495 if (--tmout == 0)
496 break;
497 udelay(1);
498 } while (status & 0x10);
499}
500
501static void vt8500_console_putchar(struct uart_port *port, int c)
502{
503 wait_for_xmitr(port);
504 writeb(c, port->membase + VT8500_TXFIFO);
505}
506
507static void vt8500_console_write(struct console *co, const char *s,
508 unsigned int count)
509{
510 struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
511 unsigned long ier;
512
513 BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
514
515 ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
516 vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
517
518 uart_console_write(&vt8500_port->uart, s, count,
519 vt8500_console_putchar);
520
521 /*
522 * Finally, wait for transmitter to become empty
523 * and switch back to FIFO
524 */
525 wait_for_xmitr(&vt8500_port->uart);
526 vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
527}
528
529static int __init vt8500_console_setup(struct console *co, char *options)
530{
531 struct vt8500_port *vt8500_port;
532 int baud = 9600;
533 int bits = 8;
534 int parity = 'n';
535 int flow = 'n';
536
537 if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
538 return -ENXIO;
539
540 vt8500_port = vt8500_uart_ports[co->index];
541
542 if (!vt8500_port)
543 return -ENODEV;
544
545 if (options)
546 uart_parse_options(options, &baud, &parity, &bits, &flow);
547
548 return uart_set_options(&vt8500_port->uart,
549 co, baud, parity, bits, flow);
550}
551
552static struct console vt8500_console = {
553 .name = "ttyWMT",
554 .write = vt8500_console_write,
555 .device = uart_console_device,
556 .setup = vt8500_console_setup,
557 .flags = CON_PRINTBUFFER,
558 .index = -1,
559 .data = &vt8500_uart_driver,
560};
561
562#define VT8500_CONSOLE (&vt8500_console)
563
564#else
565#define VT8500_CONSOLE NULL
566#endif
567
568#ifdef CONFIG_CONSOLE_POLL
569static int vt8500_get_poll_char(struct uart_port *port)
570{
571 unsigned int status = vt8500_read(port, VT8500_URFIDX);
572
573 if (!(status & 0x1f00))
574 return NO_POLL_CHAR;
575
576 return vt8500_read(port, VT8500_RXFIFO) & 0xff;
577}
578
579static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
580{
581 unsigned int status, tmout = 10000;
582
583 do {
584 status = vt8500_read(port, VT8500_URFIDX);
585
586 if (--tmout == 0)
587 break;
588 udelay(1);
589 } while (status & 0x10);
590
591 vt8500_write(port, c, VT8500_TXFIFO);
592}
593#endif
594
595static struct uart_ops vt8500_uart_pops = {
596 .tx_empty = vt8500_tx_empty,
597 .set_mctrl = vt8500_set_mctrl,
598 .get_mctrl = vt8500_get_mctrl,
599 .stop_tx = vt8500_stop_tx,
600 .start_tx = vt8500_start_tx,
601 .stop_rx = vt8500_stop_rx,
602 .enable_ms = vt8500_enable_ms,
603 .break_ctl = vt8500_break_ctl,
604 .startup = vt8500_startup,
605 .shutdown = vt8500_shutdown,
606 .set_termios = vt8500_set_termios,
607 .type = vt8500_type,
608 .release_port = vt8500_release_port,
609 .request_port = vt8500_request_port,
610 .config_port = vt8500_config_port,
611 .verify_port = vt8500_verify_port,
612#ifdef CONFIG_CONSOLE_POLL
613 .poll_get_char = vt8500_get_poll_char,
614 .poll_put_char = vt8500_put_poll_char,
615#endif
616};
617
618static struct uart_driver vt8500_uart_driver = {
619 .owner = THIS_MODULE,
620 .driver_name = "vt8500_serial",
621 .dev_name = "ttyWMT",
622 .nr = 6,
623 .cons = VT8500_CONSOLE,
624};
625
626static unsigned int vt8500_flags; /* none required so far */
627static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
628
629static const struct of_device_id wmt_dt_ids[] = {
630 { .compatible = "via,vt8500-uart", .data = &vt8500_flags},
631 { .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
632 {}
633};
634
635static int vt8500_serial_probe(struct platform_device *pdev)
636{
637 struct vt8500_port *vt8500_port;
638 struct resource *mmres, *irqres;
639 struct device_node *np = pdev->dev.of_node;
640 const struct of_device_id *match;
641 const unsigned int *flags;
642 int ret;
643 int port;
644
645 match = of_match_device(wmt_dt_ids, &pdev->dev);
646 if (!match)
647 return -EINVAL;
648
649 flags = match->data;
650
651 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
652 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
653 if (!mmres || !irqres)
654 return -ENODEV;
655
656 if (np) {
657 port = of_alias_get_id(np, "serial");
658 if (port >= VT8500_MAX_PORTS)
659 port = -1;
660 } else {
661 port = -1;
662 }
663
664 if (port < 0) {
665 /* calculate the port id */
666 port = find_first_zero_bit(vt8500_ports_in_use,
667 VT8500_MAX_PORTS);
668 }
669
670 if (port >= VT8500_MAX_PORTS)
671 return -ENODEV;
672
673 /* reserve the port id */
674 if (test_and_set_bit(port, vt8500_ports_in_use)) {
675 /* port already in use - shouldn't really happen */
676 return -EBUSY;
677 }
678
679 vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
680 GFP_KERNEL);
681 if (!vt8500_port)
682 return -ENOMEM;
683
684 vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
685 if (IS_ERR(vt8500_port->uart.membase))
686 return PTR_ERR(vt8500_port->uart.membase);
687
688 vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
689 if (IS_ERR(vt8500_port->clk)) {
690 dev_err(&pdev->dev, "failed to get clock\n");
691 return -EINVAL;
692 }
693
694 ret = clk_prepare_enable(vt8500_port->clk);
695 if (ret) {
696 dev_err(&pdev->dev, "failed to enable clock\n");
697 return ret;
698 }
699
700 vt8500_port->vt8500_uart_flags = *flags;
701 vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
702 clk_get_rate(vt8500_port->clk),
703 VT8500_RECOMMENDED_CLK
704 );
705 vt8500_port->uart.type = PORT_VT8500;
706 vt8500_port->uart.iotype = UPIO_MEM;
707 vt8500_port->uart.mapbase = mmres->start;
708 vt8500_port->uart.irq = irqres->start;
709 vt8500_port->uart.fifosize = 16;
710 vt8500_port->uart.ops = &vt8500_uart_pops;
711 vt8500_port->uart.line = port;
712 vt8500_port->uart.dev = &pdev->dev;
713 vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
714
715 /* Serial core uses the magic "16" everywhere - adjust for it */
716 vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
717 vt8500_port->clk_predivisor /
718 VT8500_OVERSAMPLING_DIVISOR;
719
720 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
721 "VT8500 UART%d", pdev->id);
722
723 vt8500_uart_ports[port] = vt8500_port;
724
725 uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
726
727 platform_set_drvdata(pdev, vt8500_port);
728
729 return 0;
730}
731
732static struct platform_driver vt8500_platform_driver = {
733 .probe = vt8500_serial_probe,
734 .driver = {
735 .name = "vt8500_serial",
736 .of_match_table = wmt_dt_ids,
737 .suppress_bind_attrs = true,
738 },
739};
740
741static int __init vt8500_serial_init(void)
742{
743 int ret;
744
745 ret = uart_register_driver(&vt8500_uart_driver);
746 if (unlikely(ret))
747 return ret;
748
749 ret = platform_driver_register(&vt8500_platform_driver);
750
751 if (unlikely(ret))
752 uart_unregister_driver(&vt8500_uart_driver);
753
754 return ret;
755}
756device_initcall(vt8500_serial_init);