Loading...
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/drm_cache.h>
29#include "amdgpu.h"
30#include "gmc_v6_0.h"
31#include "amdgpu_ucode.h"
32#include "amdgpu_gem.h"
33
34#include "bif/bif_3_0_d.h"
35#include "bif/bif_3_0_sh_mask.h"
36#include "oss/oss_1_0_d.h"
37#include "oss/oss_1_0_sh_mask.h"
38#include "gmc/gmc_6_0_d.h"
39#include "gmc/gmc_6_0_sh_mask.h"
40#include "dce/dce_6_0_d.h"
41#include "dce/dce_6_0_sh_mask.h"
42#include "si_enums.h"
43
44static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
45static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
46static int gmc_v6_0_wait_for_idle(void *handle);
47
48MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
49MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
50MODULE_FIRMWARE("amdgpu/verde_mc.bin");
51MODULE_FIRMWARE("amdgpu/oland_mc.bin");
52MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
53MODULE_FIRMWARE("amdgpu/si58_mc.bin");
54
55#define MC_SEQ_MISC0__MT__MASK 0xf0000000
56#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
57#define MC_SEQ_MISC0__MT__DDR2 0x20000000
58#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
59#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
60#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
61#define MC_SEQ_MISC0__MT__HBM 0x60000000
62#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
63
64
65static const u32 crtc_offsets[6] =
66{
67 SI_CRTC0_REGISTER_OFFSET,
68 SI_CRTC1_REGISTER_OFFSET,
69 SI_CRTC2_REGISTER_OFFSET,
70 SI_CRTC3_REGISTER_OFFSET,
71 SI_CRTC4_REGISTER_OFFSET,
72 SI_CRTC5_REGISTER_OFFSET
73};
74
75static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
76{
77 u32 blackout;
78
79 gmc_v6_0_wait_for_idle((void *)adev);
80
81 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
82 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
83 /* Block CPU access */
84 WREG32(mmBIF_FB_EN, 0);
85 /* blackout the MC */
86 blackout = REG_SET_FIELD(blackout,
87 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
88 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
89 }
90 /* wait for the MC to settle */
91 udelay(100);
92
93}
94
95static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
96{
97 u32 tmp;
98
99 /* unblackout the MC */
100 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
101 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
102 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
103 /* allow CPU access */
104 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
105 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
106 WREG32(mmBIF_FB_EN, tmp);
107}
108
109static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
110{
111 const char *chip_name;
112 char fw_name[30];
113 int err;
114 bool is_58_fw = false;
115
116 DRM_DEBUG("\n");
117
118 switch (adev->asic_type) {
119 case CHIP_TAHITI:
120 chip_name = "tahiti";
121 break;
122 case CHIP_PITCAIRN:
123 chip_name = "pitcairn";
124 break;
125 case CHIP_VERDE:
126 chip_name = "verde";
127 break;
128 case CHIP_OLAND:
129 chip_name = "oland";
130 break;
131 case CHIP_HAINAN:
132 chip_name = "hainan";
133 break;
134 default: BUG();
135 }
136
137 /* this memory configuration requires special firmware */
138 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
139 is_58_fw = true;
140
141 if (is_58_fw)
142 snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin");
143 else
144 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
145 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
146 if (err)
147 goto out;
148
149 err = amdgpu_ucode_validate(adev->gmc.fw);
150
151out:
152 if (err) {
153 dev_err(adev->dev,
154 "si_mc: Failed to load firmware \"%s\"\n",
155 fw_name);
156 release_firmware(adev->gmc.fw);
157 adev->gmc.fw = NULL;
158 }
159 return err;
160}
161
162static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
163{
164 const __le32 *new_fw_data = NULL;
165 u32 running;
166 const __le32 *new_io_mc_regs = NULL;
167 int i, regs_size, ucode_size;
168 const struct mc_firmware_header_v1_0 *hdr;
169
170 if (!adev->gmc.fw)
171 return -EINVAL;
172
173 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
174
175 amdgpu_ucode_print_mc_hdr(&hdr->header);
176
177 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
178 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
179 new_io_mc_regs = (const __le32 *)
180 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
181 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
182 new_fw_data = (const __le32 *)
183 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
184
185 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
186
187 if (running == 0) {
188
189 /* reset the engine and set to writable */
190 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
191 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
192
193 /* load mc io regs */
194 for (i = 0; i < regs_size; i++) {
195 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
196 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
197 }
198 /* load the MC ucode */
199 for (i = 0; i < ucode_size; i++) {
200 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
201 }
202
203 /* put the engine back into the active state */
204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
205 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
206 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
207
208 /* wait for training to complete */
209 for (i = 0; i < adev->usec_timeout; i++) {
210 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
211 break;
212 udelay(1);
213 }
214 for (i = 0; i < adev->usec_timeout; i++) {
215 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
216 break;
217 udelay(1);
218 }
219
220 }
221
222 return 0;
223}
224
225static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
226 struct amdgpu_gmc *mc)
227{
228 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
229 base <<= 24;
230
231 amdgpu_gmc_vram_location(adev, mc, base);
232 amdgpu_gmc_gart_location(adev, mc);
233}
234
235static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
236{
237 int i, j;
238
239 /* Initialize HDP */
240 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
241 WREG32((0xb05 + j), 0x00000000);
242 WREG32((0xb06 + j), 0x00000000);
243 WREG32((0xb07 + j), 0x00000000);
244 WREG32((0xb08 + j), 0x00000000);
245 WREG32((0xb09 + j), 0x00000000);
246 }
247 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
248
249 if (gmc_v6_0_wait_for_idle((void *)adev)) {
250 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
251 }
252
253 if (adev->mode_info.num_crtc) {
254 u32 tmp;
255
256 /* Lockout access through VGA aperture*/
257 tmp = RREG32(mmVGA_HDP_CONTROL);
258 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
259 WREG32(mmVGA_HDP_CONTROL, tmp);
260
261 /* disable VGA render */
262 tmp = RREG32(mmVGA_RENDER_CONTROL);
263 tmp &= ~VGA_VSTATUS_CNTL;
264 WREG32(mmVGA_RENDER_CONTROL, tmp);
265 }
266 /* Update configuration */
267 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
268 adev->gmc.vram_start >> 12);
269 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
270 adev->gmc.vram_end >> 12);
271 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
272 adev->vram_scratch.gpu_addr >> 12);
273 WREG32(mmMC_VM_AGP_BASE, 0);
274 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
275 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
276
277 if (gmc_v6_0_wait_for_idle((void *)adev)) {
278 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
279 }
280}
281
282static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
283{
284
285 u32 tmp;
286 int chansize, numchan;
287 int r;
288
289 tmp = RREG32(mmMC_ARB_RAMCFG);
290 if (tmp & (1 << 11)) {
291 chansize = 16;
292 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
293 chansize = 64;
294 } else {
295 chansize = 32;
296 }
297 tmp = RREG32(mmMC_SHARED_CHMAP);
298 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
299 case 0:
300 default:
301 numchan = 1;
302 break;
303 case 1:
304 numchan = 2;
305 break;
306 case 2:
307 numchan = 4;
308 break;
309 case 3:
310 numchan = 8;
311 break;
312 case 4:
313 numchan = 3;
314 break;
315 case 5:
316 numchan = 6;
317 break;
318 case 6:
319 numchan = 10;
320 break;
321 case 7:
322 numchan = 12;
323 break;
324 case 8:
325 numchan = 16;
326 break;
327 }
328 adev->gmc.vram_width = numchan * chansize;
329 /* size in MB on si */
330 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
331 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
332
333 if (!(adev->flags & AMD_IS_APU)) {
334 r = amdgpu_device_resize_fb_bar(adev);
335 if (r)
336 return r;
337 }
338 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
339 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
340 adev->gmc.visible_vram_size = adev->gmc.aper_size;
341
342 /* set the gart size */
343 if (amdgpu_gart_size == -1) {
344 switch (adev->asic_type) {
345 case CHIP_HAINAN: /* no MM engines */
346 default:
347 adev->gmc.gart_size = 256ULL << 20;
348 break;
349 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
350 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
351 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
352 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
353 adev->gmc.gart_size = 1024ULL << 20;
354 break;
355 }
356 } else {
357 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
358 }
359
360 gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
361
362 return 0;
363}
364
365static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
366 uint32_t vmhub, uint32_t flush_type)
367{
368 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
369}
370
371static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
372 unsigned vmid, uint64_t pd_addr)
373{
374 uint32_t reg;
375
376 /* write new base address */
377 if (vmid < 8)
378 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
379 else
380 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
381 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
382
383 /* bits 0-15 are the VM contexts0-15 */
384 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
385
386 return pd_addr;
387}
388
389static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
390 uint32_t flags)
391{
392 uint64_t pte_flag = 0;
393
394 if (flags & AMDGPU_VM_PAGE_READABLE)
395 pte_flag |= AMDGPU_PTE_READABLE;
396 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
397 pte_flag |= AMDGPU_PTE_WRITEABLE;
398 if (flags & AMDGPU_VM_PAGE_PRT)
399 pte_flag |= AMDGPU_PTE_PRT;
400
401 return pte_flag;
402}
403
404static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
405 uint64_t *addr, uint64_t *flags)
406{
407 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
408}
409
410static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
411 bool value)
412{
413 u32 tmp;
414
415 tmp = RREG32(mmVM_CONTEXT1_CNTL);
416 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
417 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
418 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
419 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
420 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
421 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
422 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
423 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
424 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
425 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
426 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
427 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
428 WREG32(mmVM_CONTEXT1_CNTL, tmp);
429}
430
431 /**
432 + * gmc_v8_0_set_prt - set PRT VM fault
433 + *
434 + * @adev: amdgpu_device pointer
435 + * @enable: enable/disable VM fault handling for PRT
436 +*/
437static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
438{
439 u32 tmp;
440
441 if (enable && !adev->gmc.prt_warning) {
442 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
443 adev->gmc.prt_warning = true;
444 }
445
446 tmp = RREG32(mmVM_PRT_CNTL);
447 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
448 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
449 enable);
450 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
451 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
452 enable);
453 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
454 L2_CACHE_STORE_INVALID_ENTRIES,
455 enable);
456 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
457 L1_TLB_STORE_INVALID_ENTRIES,
458 enable);
459 WREG32(mmVM_PRT_CNTL, tmp);
460
461 if (enable) {
462 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
463 uint32_t high = adev->vm_manager.max_pfn -
464 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
465
466 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
467 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
468 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
469 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
470 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
471 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
472 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
473 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
474 } else {
475 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
476 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
477 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
478 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
479 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
480 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
481 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
482 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
483 }
484}
485
486static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
487{
488 uint64_t table_addr;
489 int r, i;
490 u32 field;
491
492 if (adev->gart.bo == NULL) {
493 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
494 return -EINVAL;
495 }
496 r = amdgpu_gart_table_vram_pin(adev);
497 if (r)
498 return r;
499
500 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
501
502 /* Setup TLB control */
503 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
504 (0xA << 7) |
505 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
506 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
507 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
508 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
509 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
510 /* Setup L2 cache */
511 WREG32(mmVM_L2_CNTL,
512 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
513 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
514 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
515 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
516 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
517 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
518 WREG32(mmVM_L2_CNTL2,
519 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
520 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
521
522 field = adev->vm_manager.fragment_size;
523 WREG32(mmVM_L2_CNTL3,
524 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
525 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
526 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
527 /* setup context0 */
528 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
529 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
530 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
531 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
532 (u32)(adev->dummy_page_addr >> 12));
533 WREG32(mmVM_CONTEXT0_CNTL2, 0);
534 WREG32(mmVM_CONTEXT0_CNTL,
535 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
536 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
537 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
538
539 WREG32(0x575, 0);
540 WREG32(0x576, 0);
541 WREG32(0x577, 0);
542
543 /* empty context1-15 */
544 /* set vm size, must be a multiple of 4 */
545 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
546 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
547 /* Assign the pt base to something valid for now; the pts used for
548 * the VMs are determined by the application and setup and assigned
549 * on the fly in the vm part of radeon_gart.c
550 */
551 for (i = 1; i < 16; i++) {
552 if (i < 8)
553 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
554 table_addr >> 12);
555 else
556 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
557 table_addr >> 12);
558 }
559
560 /* enable context1-15 */
561 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
562 (u32)(adev->dummy_page_addr >> 12));
563 WREG32(mmVM_CONTEXT1_CNTL2, 4);
564 WREG32(mmVM_CONTEXT1_CNTL,
565 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
566 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
567 ((adev->vm_manager.block_size - 9)
568 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
569 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
570 gmc_v6_0_set_fault_enable_default(adev, false);
571 else
572 gmc_v6_0_set_fault_enable_default(adev, true);
573
574 gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0);
575 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
576 (unsigned)(adev->gmc.gart_size >> 20),
577 (unsigned long long)table_addr);
578 adev->gart.ready = true;
579 return 0;
580}
581
582static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
583{
584 int r;
585
586 if (adev->gart.bo) {
587 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
588 return 0;
589 }
590 r = amdgpu_gart_init(adev);
591 if (r)
592 return r;
593 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
594 adev->gart.gart_pte_flags = 0;
595 return amdgpu_gart_table_vram_alloc(adev);
596}
597
598static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
599{
600 /*unsigned i;
601
602 for (i = 1; i < 16; ++i) {
603 uint32_t reg;
604 if (i < 8)
605 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
606 else
607 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
608 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
609 }*/
610
611 /* Disable all tables */
612 WREG32(mmVM_CONTEXT0_CNTL, 0);
613 WREG32(mmVM_CONTEXT1_CNTL, 0);
614 /* Setup TLB control */
615 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
616 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
617 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
618 /* Setup L2 cache */
619 WREG32(mmVM_L2_CNTL,
620 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
621 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
622 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
623 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
624 WREG32(mmVM_L2_CNTL2, 0);
625 WREG32(mmVM_L2_CNTL3,
626 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
627 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
628 amdgpu_gart_table_vram_unpin(adev);
629}
630
631static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
632 u32 status, u32 addr, u32 mc_client)
633{
634 u32 mc_id;
635 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
636 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
637 PROTECTIONS);
638 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
639 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
640
641 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
642 MEMORY_CLIENT_ID);
643
644 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
645 protections, vmid, addr,
646 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
647 MEMORY_CLIENT_RW) ?
648 "write" : "read", block, mc_client, mc_id);
649}
650
651/*
652static const u32 mc_cg_registers[] = {
653 MC_HUB_MISC_HUB_CG,
654 MC_HUB_MISC_SIP_CG,
655 MC_HUB_MISC_VM_CG,
656 MC_XPB_CLK_GAT,
657 ATC_MISC_CG,
658 MC_CITF_MISC_WR_CG,
659 MC_CITF_MISC_RD_CG,
660 MC_CITF_MISC_VM_CG,
661 VM_L2_CG,
662};
663
664static const u32 mc_cg_ls_en[] = {
665 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
666 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
667 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
668 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
669 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
670 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
671 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
672 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
673 VM_L2_CG__MEM_LS_ENABLE_MASK,
674};
675
676static const u32 mc_cg_en[] = {
677 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
678 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
679 MC_HUB_MISC_VM_CG__ENABLE_MASK,
680 MC_XPB_CLK_GAT__ENABLE_MASK,
681 ATC_MISC_CG__ENABLE_MASK,
682 MC_CITF_MISC_WR_CG__ENABLE_MASK,
683 MC_CITF_MISC_RD_CG__ENABLE_MASK,
684 MC_CITF_MISC_VM_CG__ENABLE_MASK,
685 VM_L2_CG__ENABLE_MASK,
686};
687
688static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
689 bool enable)
690{
691 int i;
692 u32 orig, data;
693
694 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
695 orig = data = RREG32(mc_cg_registers[i]);
696 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
697 data |= mc_cg_ls_en[i];
698 else
699 data &= ~mc_cg_ls_en[i];
700 if (data != orig)
701 WREG32(mc_cg_registers[i], data);
702 }
703}
704
705static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
706 bool enable)
707{
708 int i;
709 u32 orig, data;
710
711 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
712 orig = data = RREG32(mc_cg_registers[i]);
713 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
714 data |= mc_cg_en[i];
715 else
716 data &= ~mc_cg_en[i];
717 if (data != orig)
718 WREG32(mc_cg_registers[i], data);
719 }
720}
721
722static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
723 bool enable)
724{
725 u32 orig, data;
726
727 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
728
729 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
730 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
731 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
732 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
733 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
734 } else {
735 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
736 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
737 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
738 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
739 }
740
741 if (orig != data)
742 WREG32_PCIE(ixPCIE_CNTL2, data);
743}
744
745static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
746 bool enable)
747{
748 u32 orig, data;
749
750 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
751
752 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
753 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
754 else
755 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
756
757 if (orig != data)
758 WREG32(mmHDP_HOST_PATH_CNTL, data);
759}
760
761static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
762 bool enable)
763{
764 u32 orig, data;
765
766 orig = data = RREG32(mmHDP_MEM_POWER_LS);
767
768 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
769 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
770 else
771 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
772
773 if (orig != data)
774 WREG32(mmHDP_MEM_POWER_LS, data);
775}
776*/
777
778static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
779{
780 switch (mc_seq_vram_type) {
781 case MC_SEQ_MISC0__MT__GDDR1:
782 return AMDGPU_VRAM_TYPE_GDDR1;
783 case MC_SEQ_MISC0__MT__DDR2:
784 return AMDGPU_VRAM_TYPE_DDR2;
785 case MC_SEQ_MISC0__MT__GDDR3:
786 return AMDGPU_VRAM_TYPE_GDDR3;
787 case MC_SEQ_MISC0__MT__GDDR4:
788 return AMDGPU_VRAM_TYPE_GDDR4;
789 case MC_SEQ_MISC0__MT__GDDR5:
790 return AMDGPU_VRAM_TYPE_GDDR5;
791 case MC_SEQ_MISC0__MT__DDR3:
792 return AMDGPU_VRAM_TYPE_DDR3;
793 default:
794 return AMDGPU_VRAM_TYPE_UNKNOWN;
795 }
796}
797
798static int gmc_v6_0_early_init(void *handle)
799{
800 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
801
802 gmc_v6_0_set_gmc_funcs(adev);
803 gmc_v6_0_set_irq_funcs(adev);
804
805 return 0;
806}
807
808static int gmc_v6_0_late_init(void *handle)
809{
810 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
811
812 amdgpu_bo_late_init(adev);
813
814 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
815 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
816 else
817 return 0;
818}
819
820static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
821{
822 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
823 unsigned size;
824
825 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
826 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
827 } else {
828 u32 viewport = RREG32(mmVIEWPORT_SIZE);
829 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
830 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
831 4);
832 }
833 /* return 0 if the pre-OS buffer uses up most of vram */
834 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
835 return 0;
836 return size;
837}
838
839static int gmc_v6_0_sw_init(void *handle)
840{
841 int r;
842 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
843
844 adev->num_vmhubs = 1;
845
846 if (adev->flags & AMD_IS_APU) {
847 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
848 } else {
849 u32 tmp = RREG32(mmMC_SEQ_MISC0);
850 tmp &= MC_SEQ_MISC0__MT__MASK;
851 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
852 }
853
854 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
855 if (r)
856 return r;
857
858 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
859 if (r)
860 return r;
861
862 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
863
864 adev->gmc.mc_mask = 0xffffffffffULL;
865
866 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
867 if (r) {
868 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
869 return r;
870 }
871 adev->need_swiotlb = drm_need_swiotlb(44);
872
873 r = gmc_v6_0_init_microcode(adev);
874 if (r) {
875 dev_err(adev->dev, "Failed to load mc firmware!\n");
876 return r;
877 }
878
879 r = gmc_v6_0_mc_init(adev);
880 if (r)
881 return r;
882
883 adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);
884
885 r = amdgpu_bo_init(adev);
886 if (r)
887 return r;
888
889 r = gmc_v6_0_gart_init(adev);
890 if (r)
891 return r;
892
893 /*
894 * number of VMs
895 * VMID 0 is reserved for System
896 * amdgpu graphics/compute will use VMIDs 1-7
897 * amdkfd will use VMIDs 8-15
898 */
899 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
900 amdgpu_vm_manager_init(adev);
901
902 /* base offset of vram pages */
903 if (adev->flags & AMD_IS_APU) {
904 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
905
906 tmp <<= 22;
907 adev->vm_manager.vram_base_offset = tmp;
908 } else {
909 adev->vm_manager.vram_base_offset = 0;
910 }
911
912 return 0;
913}
914
915static int gmc_v6_0_sw_fini(void *handle)
916{
917 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
918
919 amdgpu_gem_force_release(adev);
920 amdgpu_vm_manager_fini(adev);
921 amdgpu_gart_table_vram_free(adev);
922 amdgpu_bo_fini(adev);
923 amdgpu_gart_fini(adev);
924 release_firmware(adev->gmc.fw);
925 adev->gmc.fw = NULL;
926
927 return 0;
928}
929
930static int gmc_v6_0_hw_init(void *handle)
931{
932 int r;
933 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
934
935 gmc_v6_0_mc_program(adev);
936
937 if (!(adev->flags & AMD_IS_APU)) {
938 r = gmc_v6_0_mc_load_microcode(adev);
939 if (r) {
940 dev_err(adev->dev, "Failed to load MC firmware!\n");
941 return r;
942 }
943 }
944
945 r = gmc_v6_0_gart_enable(adev);
946 if (r)
947 return r;
948
949 return r;
950}
951
952static int gmc_v6_0_hw_fini(void *handle)
953{
954 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
955
956 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
957 gmc_v6_0_gart_disable(adev);
958
959 return 0;
960}
961
962static int gmc_v6_0_suspend(void *handle)
963{
964 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
965
966 gmc_v6_0_hw_fini(adev);
967
968 return 0;
969}
970
971static int gmc_v6_0_resume(void *handle)
972{
973 int r;
974 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
975
976 r = gmc_v6_0_hw_init(adev);
977 if (r)
978 return r;
979
980 amdgpu_vmid_reset_all(adev);
981
982 return 0;
983}
984
985static bool gmc_v6_0_is_idle(void *handle)
986{
987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
988 u32 tmp = RREG32(mmSRBM_STATUS);
989
990 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
991 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
992 return false;
993
994 return true;
995}
996
997static int gmc_v6_0_wait_for_idle(void *handle)
998{
999 unsigned i;
1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002 for (i = 0; i < adev->usec_timeout; i++) {
1003 if (gmc_v6_0_is_idle(handle))
1004 return 0;
1005 udelay(1);
1006 }
1007 return -ETIMEDOUT;
1008
1009}
1010
1011static int gmc_v6_0_soft_reset(void *handle)
1012{
1013 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1014 u32 srbm_soft_reset = 0;
1015 u32 tmp = RREG32(mmSRBM_STATUS);
1016
1017 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1018 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1019 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1020
1021 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1022 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1023 if (!(adev->flags & AMD_IS_APU))
1024 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1025 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1026 }
1027
1028 if (srbm_soft_reset) {
1029 gmc_v6_0_mc_stop(adev);
1030 if (gmc_v6_0_wait_for_idle(adev)) {
1031 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1032 }
1033
1034
1035 tmp = RREG32(mmSRBM_SOFT_RESET);
1036 tmp |= srbm_soft_reset;
1037 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1038 WREG32(mmSRBM_SOFT_RESET, tmp);
1039 tmp = RREG32(mmSRBM_SOFT_RESET);
1040
1041 udelay(50);
1042
1043 tmp &= ~srbm_soft_reset;
1044 WREG32(mmSRBM_SOFT_RESET, tmp);
1045 tmp = RREG32(mmSRBM_SOFT_RESET);
1046
1047 udelay(50);
1048
1049 gmc_v6_0_mc_resume(adev);
1050 udelay(50);
1051 }
1052
1053 return 0;
1054}
1055
1056static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1057 struct amdgpu_irq_src *src,
1058 unsigned type,
1059 enum amdgpu_interrupt_state state)
1060{
1061 u32 tmp;
1062 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1063 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1064 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1065 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1066 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1067 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1068
1069 switch (state) {
1070 case AMDGPU_IRQ_STATE_DISABLE:
1071 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1072 tmp &= ~bits;
1073 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1074 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1075 tmp &= ~bits;
1076 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1077 break;
1078 case AMDGPU_IRQ_STATE_ENABLE:
1079 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1080 tmp |= bits;
1081 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1082 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1083 tmp |= bits;
1084 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1085 break;
1086 default:
1087 break;
1088 }
1089
1090 return 0;
1091}
1092
1093static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1094 struct amdgpu_irq_src *source,
1095 struct amdgpu_iv_entry *entry)
1096{
1097 u32 addr, status;
1098
1099 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1100 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1101 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1102
1103 if (!addr && !status)
1104 return 0;
1105
1106 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1107 gmc_v6_0_set_fault_enable_default(adev, false);
1108
1109 if (printk_ratelimit()) {
1110 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1111 entry->src_id, entry->src_data[0]);
1112 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1113 addr);
1114 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1115 status);
1116 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1117 }
1118
1119 return 0;
1120}
1121
1122static int gmc_v6_0_set_clockgating_state(void *handle,
1123 enum amd_clockgating_state state)
1124{
1125 return 0;
1126}
1127
1128static int gmc_v6_0_set_powergating_state(void *handle,
1129 enum amd_powergating_state state)
1130{
1131 return 0;
1132}
1133
1134static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1135 .name = "gmc_v6_0",
1136 .early_init = gmc_v6_0_early_init,
1137 .late_init = gmc_v6_0_late_init,
1138 .sw_init = gmc_v6_0_sw_init,
1139 .sw_fini = gmc_v6_0_sw_fini,
1140 .hw_init = gmc_v6_0_hw_init,
1141 .hw_fini = gmc_v6_0_hw_fini,
1142 .suspend = gmc_v6_0_suspend,
1143 .resume = gmc_v6_0_resume,
1144 .is_idle = gmc_v6_0_is_idle,
1145 .wait_for_idle = gmc_v6_0_wait_for_idle,
1146 .soft_reset = gmc_v6_0_soft_reset,
1147 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1148 .set_powergating_state = gmc_v6_0_set_powergating_state,
1149};
1150
1151static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1152 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1153 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1154 .set_prt = gmc_v6_0_set_prt,
1155 .get_vm_pde = gmc_v6_0_get_vm_pde,
1156 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1157};
1158
1159static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1160 .set = gmc_v6_0_vm_fault_interrupt_state,
1161 .process = gmc_v6_0_process_interrupt,
1162};
1163
1164static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1165{
1166 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1167}
1168
1169static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1170{
1171 adev->gmc.vm_fault.num_types = 1;
1172 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1173}
1174
1175const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1176{
1177 .type = AMD_IP_BLOCK_TYPE_GMC,
1178 .major = 6,
1179 .minor = 0,
1180 .rev = 0,
1181 .funcs = &gmc_v6_0_ip_funcs,
1182};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "gmc_v6_0.h"
27#include "amdgpu_ucode.h"
28
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gmc/gmc_6_0_d.h"
34#include "gmc/gmc_6_0_sh_mask.h"
35#include "dce/dce_6_0_d.h"
36#include "dce/dce_6_0_sh_mask.h"
37#include "si_enums.h"
38
39static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
40static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41static int gmc_v6_0_wait_for_idle(void *handle);
42
43MODULE_FIRMWARE("radeon/tahiti_mc.bin");
44MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
45MODULE_FIRMWARE("radeon/verde_mc.bin");
46MODULE_FIRMWARE("radeon/oland_mc.bin");
47MODULE_FIRMWARE("radeon/si58_mc.bin");
48
49#define MC_SEQ_MISC0__MT__MASK 0xf0000000
50#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
51#define MC_SEQ_MISC0__MT__DDR2 0x20000000
52#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
53#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
54#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
55#define MC_SEQ_MISC0__MT__HBM 0x60000000
56#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
57
58
59static const u32 crtc_offsets[6] =
60{
61 SI_CRTC0_REGISTER_OFFSET,
62 SI_CRTC1_REGISTER_OFFSET,
63 SI_CRTC2_REGISTER_OFFSET,
64 SI_CRTC3_REGISTER_OFFSET,
65 SI_CRTC4_REGISTER_OFFSET,
66 SI_CRTC5_REGISTER_OFFSET
67};
68
69static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
70 struct amdgpu_mode_mc_save *save)
71{
72 u32 blackout;
73
74 if (adev->mode_info.num_crtc)
75 amdgpu_display_stop_mc_access(adev, save);
76
77 gmc_v6_0_wait_for_idle((void *)adev);
78
79 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
80 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
81 /* Block CPU access */
82 WREG32(mmBIF_FB_EN, 0);
83 /* blackout the MC */
84 blackout = REG_SET_FIELD(blackout,
85 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
86 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
87 }
88 /* wait for the MC to settle */
89 udelay(100);
90
91}
92
93static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
94 struct amdgpu_mode_mc_save *save)
95{
96 u32 tmp;
97
98 /* unblackout the MC */
99 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
100 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
101 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
102 /* allow CPU access */
103 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
104 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
105 WREG32(mmBIF_FB_EN, tmp);
106
107 if (adev->mode_info.num_crtc)
108 amdgpu_display_resume_mc_access(adev, save);
109
110}
111
112static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
113{
114 const char *chip_name;
115 char fw_name[30];
116 int err;
117 bool is_58_fw = false;
118
119 DRM_DEBUG("\n");
120
121 switch (adev->asic_type) {
122 case CHIP_TAHITI:
123 chip_name = "tahiti";
124 break;
125 case CHIP_PITCAIRN:
126 chip_name = "pitcairn";
127 break;
128 case CHIP_VERDE:
129 chip_name = "verde";
130 break;
131 case CHIP_OLAND:
132 chip_name = "oland";
133 break;
134 case CHIP_HAINAN:
135 chip_name = "hainan";
136 break;
137 default: BUG();
138 }
139
140 /* this memory configuration requires special firmware */
141 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
142 is_58_fw = true;
143
144 if (is_58_fw)
145 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
146 else
147 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
148 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
149 if (err)
150 goto out;
151
152 err = amdgpu_ucode_validate(adev->mc.fw);
153
154out:
155 if (err) {
156 dev_err(adev->dev,
157 "si_mc: Failed to load firmware \"%s\"\n",
158 fw_name);
159 release_firmware(adev->mc.fw);
160 adev->mc.fw = NULL;
161 }
162 return err;
163}
164
165static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
166{
167 const __le32 *new_fw_data = NULL;
168 u32 running;
169 const __le32 *new_io_mc_regs = NULL;
170 int i, regs_size, ucode_size;
171 const struct mc_firmware_header_v1_0 *hdr;
172
173 if (!adev->mc.fw)
174 return -EINVAL;
175
176 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
177
178 amdgpu_ucode_print_mc_hdr(&hdr->header);
179
180 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
181 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
182 new_io_mc_regs = (const __le32 *)
183 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
184 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
185 new_fw_data = (const __le32 *)
186 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
187
188 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
189
190 if (running == 0) {
191
192 /* reset the engine and set to writable */
193 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
194 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
195
196 /* load mc io regs */
197 for (i = 0; i < regs_size; i++) {
198 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
199 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
200 }
201 /* load the MC ucode */
202 for (i = 0; i < ucode_size; i++) {
203 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
204 }
205
206 /* put the engine back into the active state */
207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
209 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
210
211 /* wait for training to complete */
212 for (i = 0; i < adev->usec_timeout; i++) {
213 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
214 break;
215 udelay(1);
216 }
217 for (i = 0; i < adev->usec_timeout; i++) {
218 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
219 break;
220 udelay(1);
221 }
222
223 }
224
225 return 0;
226}
227
228static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
229 struct amdgpu_mc *mc)
230{
231 if (mc->mc_vram_size > 0xFFC0000000ULL) {
232 dev_warn(adev->dev, "limiting VRAM\n");
233 mc->real_vram_size = 0xFFC0000000ULL;
234 mc->mc_vram_size = 0xFFC0000000ULL;
235 }
236 amdgpu_vram_location(adev, &adev->mc, 0);
237 adev->mc.gtt_base_align = 0;
238 amdgpu_gtt_location(adev, mc);
239}
240
241static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
242{
243 struct amdgpu_mode_mc_save save;
244 u32 tmp;
245 int i, j;
246
247 /* Initialize HDP */
248 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
249 WREG32((0xb05 + j), 0x00000000);
250 WREG32((0xb06 + j), 0x00000000);
251 WREG32((0xb07 + j), 0x00000000);
252 WREG32((0xb08 + j), 0x00000000);
253 WREG32((0xb09 + j), 0x00000000);
254 }
255 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
256
257 if (adev->mode_info.num_crtc)
258 amdgpu_display_set_vga_render_state(adev, false);
259
260 gmc_v6_0_mc_stop(adev, &save);
261
262 if (gmc_v6_0_wait_for_idle((void *)adev)) {
263 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
264 }
265
266 WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
267 /* Update configuration */
268 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
269 adev->mc.vram_start >> 12);
270 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
271 adev->mc.vram_end >> 12);
272 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
273 adev->vram_scratch.gpu_addr >> 12);
274 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
275 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
276 WREG32(mmMC_VM_FB_LOCATION, tmp);
277 /* XXX double check these! */
278 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
279 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
280 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
281 WREG32(mmMC_VM_AGP_BASE, 0);
282 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
283 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
284
285 if (gmc_v6_0_wait_for_idle((void *)adev)) {
286 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
287 }
288 gmc_v6_0_mc_resume(adev, &save);
289}
290
291static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
292{
293
294 u32 tmp;
295 int chansize, numchan;
296
297 tmp = RREG32(mmMC_ARB_RAMCFG);
298 if (tmp & (1 << 11)) {
299 chansize = 16;
300 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
301 chansize = 64;
302 } else {
303 chansize = 32;
304 }
305 tmp = RREG32(mmMC_SHARED_CHMAP);
306 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
307 case 0:
308 default:
309 numchan = 1;
310 break;
311 case 1:
312 numchan = 2;
313 break;
314 case 2:
315 numchan = 4;
316 break;
317 case 3:
318 numchan = 8;
319 break;
320 case 4:
321 numchan = 3;
322 break;
323 case 5:
324 numchan = 6;
325 break;
326 case 6:
327 numchan = 10;
328 break;
329 case 7:
330 numchan = 12;
331 break;
332 case 8:
333 numchan = 16;
334 break;
335 }
336 adev->mc.vram_width = numchan * chansize;
337 /* Could aper size report 0 ? */
338 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
339 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
340 /* size in MB on si */
341 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
342 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
343 adev->mc.visible_vram_size = adev->mc.aper_size;
344
345 /* unless the user had overridden it, set the gart
346 * size equal to the 1024 or vram, whichever is larger.
347 */
348 if (amdgpu_gart_size == -1)
349 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
350 else
351 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
352
353 gmc_v6_0_vram_gtt_location(adev, &adev->mc);
354
355 return 0;
356}
357
358static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
359 uint32_t vmid)
360{
361 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
362
363 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
364}
365
366static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
367 void *cpu_pt_addr,
368 uint32_t gpu_page_idx,
369 uint64_t addr,
370 uint32_t flags)
371{
372 void __iomem *ptr = (void *)cpu_pt_addr;
373 uint64_t value;
374
375 value = addr & 0xFFFFFFFFFFFFF000ULL;
376 value |= flags;
377 writeq(value, ptr + (gpu_page_idx * 8));
378
379 return 0;
380}
381
382static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
383 bool value)
384{
385 u32 tmp;
386
387 tmp = RREG32(mmVM_CONTEXT1_CNTL);
388 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
389 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
390 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
391 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
392 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
393 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
394 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
395 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
396 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
397 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
398 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
399 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
400 WREG32(mmVM_CONTEXT1_CNTL, tmp);
401}
402
403static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
404{
405 int r, i;
406
407 if (adev->gart.robj == NULL) {
408 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
409 return -EINVAL;
410 }
411 r = amdgpu_gart_table_vram_pin(adev);
412 if (r)
413 return r;
414 /* Setup TLB control */
415 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
416 (0xA << 7) |
417 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
418 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
419 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
420 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
421 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
422 /* Setup L2 cache */
423 WREG32(mmVM_L2_CNTL,
424 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
425 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
426 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
427 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
428 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
429 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
430 WREG32(mmVM_L2_CNTL2,
431 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
432 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
433 WREG32(mmVM_L2_CNTL3,
434 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
435 (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
436 (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
437 /* setup context0 */
438 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
439 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
440 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
441 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
442 (u32)(adev->dummy_page.addr >> 12));
443 WREG32(mmVM_CONTEXT0_CNTL2, 0);
444 WREG32(mmVM_CONTEXT0_CNTL,
445 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
446 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
447 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
448
449 WREG32(0x575, 0);
450 WREG32(0x576, 0);
451 WREG32(0x577, 0);
452
453 /* empty context1-15 */
454 /* set vm size, must be a multiple of 4 */
455 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
456 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
457 /* Assign the pt base to something valid for now; the pts used for
458 * the VMs are determined by the application and setup and assigned
459 * on the fly in the vm part of radeon_gart.c
460 */
461 for (i = 1; i < 16; i++) {
462 if (i < 8)
463 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
464 adev->gart.table_addr >> 12);
465 else
466 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
467 adev->gart.table_addr >> 12);
468 }
469
470 /* enable context1-15 */
471 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
472 (u32)(adev->dummy_page.addr >> 12));
473 WREG32(mmVM_CONTEXT1_CNTL2, 4);
474 WREG32(mmVM_CONTEXT1_CNTL,
475 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
476 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
477 ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
478 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
479 gmc_v6_0_set_fault_enable_default(adev, false);
480 else
481 gmc_v6_0_set_fault_enable_default(adev, true);
482
483 gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
484 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
485 (unsigned)(adev->mc.gtt_size >> 20),
486 (unsigned long long)adev->gart.table_addr);
487 adev->gart.ready = true;
488 return 0;
489}
490
491static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
492{
493 int r;
494
495 if (adev->gart.robj) {
496 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
497 return 0;
498 }
499 r = amdgpu_gart_init(adev);
500 if (r)
501 return r;
502 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
503 return amdgpu_gart_table_vram_alloc(adev);
504}
505
506static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
507{
508 /*unsigned i;
509
510 for (i = 1; i < 16; ++i) {
511 uint32_t reg;
512 if (i < 8)
513 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
514 else
515 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
516 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
517 }*/
518
519 /* Disable all tables */
520 WREG32(mmVM_CONTEXT0_CNTL, 0);
521 WREG32(mmVM_CONTEXT1_CNTL, 0);
522 /* Setup TLB control */
523 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
524 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
525 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
526 /* Setup L2 cache */
527 WREG32(mmVM_L2_CNTL,
528 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
529 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
530 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
531 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
532 WREG32(mmVM_L2_CNTL2, 0);
533 WREG32(mmVM_L2_CNTL3,
534 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
535 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
536 amdgpu_gart_table_vram_unpin(adev);
537}
538
539static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
540{
541 amdgpu_gart_table_vram_free(adev);
542 amdgpu_gart_fini(adev);
543}
544
545static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
546{
547 /*
548 * number of VMs
549 * VMID 0 is reserved for System
550 * amdgpu graphics/compute will use VMIDs 1-7
551 * amdkfd will use VMIDs 8-15
552 */
553 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
554 amdgpu_vm_manager_init(adev);
555
556 /* base offset of vram pages */
557 if (adev->flags & AMD_IS_APU) {
558 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
559 tmp <<= 22;
560 adev->vm_manager.vram_base_offset = tmp;
561 } else
562 adev->vm_manager.vram_base_offset = 0;
563
564 return 0;
565}
566
567static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
568{
569}
570
571static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
572 u32 status, u32 addr, u32 mc_client)
573{
574 u32 mc_id;
575 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
576 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
577 PROTECTIONS);
578 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
579 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
580
581 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
582 MEMORY_CLIENT_ID);
583
584 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
585 protections, vmid, addr,
586 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
587 MEMORY_CLIENT_RW) ?
588 "write" : "read", block, mc_client, mc_id);
589}
590
591/*
592static const u32 mc_cg_registers[] = {
593 MC_HUB_MISC_HUB_CG,
594 MC_HUB_MISC_SIP_CG,
595 MC_HUB_MISC_VM_CG,
596 MC_XPB_CLK_GAT,
597 ATC_MISC_CG,
598 MC_CITF_MISC_WR_CG,
599 MC_CITF_MISC_RD_CG,
600 MC_CITF_MISC_VM_CG,
601 VM_L2_CG,
602};
603
604static const u32 mc_cg_ls_en[] = {
605 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
606 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
607 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
608 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
609 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
610 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
611 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
612 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
613 VM_L2_CG__MEM_LS_ENABLE_MASK,
614};
615
616static const u32 mc_cg_en[] = {
617 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
618 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
619 MC_HUB_MISC_VM_CG__ENABLE_MASK,
620 MC_XPB_CLK_GAT__ENABLE_MASK,
621 ATC_MISC_CG__ENABLE_MASK,
622 MC_CITF_MISC_WR_CG__ENABLE_MASK,
623 MC_CITF_MISC_RD_CG__ENABLE_MASK,
624 MC_CITF_MISC_VM_CG__ENABLE_MASK,
625 VM_L2_CG__ENABLE_MASK,
626};
627
628static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
629 bool enable)
630{
631 int i;
632 u32 orig, data;
633
634 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
635 orig = data = RREG32(mc_cg_registers[i]);
636 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
637 data |= mc_cg_ls_en[i];
638 else
639 data &= ~mc_cg_ls_en[i];
640 if (data != orig)
641 WREG32(mc_cg_registers[i], data);
642 }
643}
644
645static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
646 bool enable)
647{
648 int i;
649 u32 orig, data;
650
651 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
652 orig = data = RREG32(mc_cg_registers[i]);
653 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
654 data |= mc_cg_en[i];
655 else
656 data &= ~mc_cg_en[i];
657 if (data != orig)
658 WREG32(mc_cg_registers[i], data);
659 }
660}
661
662static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
663 bool enable)
664{
665 u32 orig, data;
666
667 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
668
669 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
670 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
671 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
672 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
673 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
674 } else {
675 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
676 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
677 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
678 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
679 }
680
681 if (orig != data)
682 WREG32_PCIE(ixPCIE_CNTL2, data);
683}
684
685static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
686 bool enable)
687{
688 u32 orig, data;
689
690 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
691
692 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
693 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
694 else
695 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
696
697 if (orig != data)
698 WREG32(mmHDP_HOST_PATH_CNTL, data);
699}
700
701static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
702 bool enable)
703{
704 u32 orig, data;
705
706 orig = data = RREG32(mmHDP_MEM_POWER_LS);
707
708 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
709 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
710 else
711 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
712
713 if (orig != data)
714 WREG32(mmHDP_MEM_POWER_LS, data);
715}
716*/
717
718static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
719{
720 switch (mc_seq_vram_type) {
721 case MC_SEQ_MISC0__MT__GDDR1:
722 return AMDGPU_VRAM_TYPE_GDDR1;
723 case MC_SEQ_MISC0__MT__DDR2:
724 return AMDGPU_VRAM_TYPE_DDR2;
725 case MC_SEQ_MISC0__MT__GDDR3:
726 return AMDGPU_VRAM_TYPE_GDDR3;
727 case MC_SEQ_MISC0__MT__GDDR4:
728 return AMDGPU_VRAM_TYPE_GDDR4;
729 case MC_SEQ_MISC0__MT__GDDR5:
730 return AMDGPU_VRAM_TYPE_GDDR5;
731 case MC_SEQ_MISC0__MT__DDR3:
732 return AMDGPU_VRAM_TYPE_DDR3;
733 default:
734 return AMDGPU_VRAM_TYPE_UNKNOWN;
735 }
736}
737
738static int gmc_v6_0_early_init(void *handle)
739{
740 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
741
742 gmc_v6_0_set_gart_funcs(adev);
743 gmc_v6_0_set_irq_funcs(adev);
744
745 if (adev->flags & AMD_IS_APU) {
746 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
747 } else {
748 u32 tmp = RREG32(mmMC_SEQ_MISC0);
749 tmp &= MC_SEQ_MISC0__MT__MASK;
750 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
751 }
752
753 return 0;
754}
755
756static int gmc_v6_0_late_init(void *handle)
757{
758 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
759
760 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
761 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
762 else
763 return 0;
764}
765
766static int gmc_v6_0_sw_init(void *handle)
767{
768 int r;
769 int dma_bits;
770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771
772 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
773 if (r)
774 return r;
775
776 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
777 if (r)
778 return r;
779
780 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
781
782 adev->mc.mc_mask = 0xffffffffffULL;
783
784 adev->need_dma32 = false;
785 dma_bits = adev->need_dma32 ? 32 : 40;
786 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
787 if (r) {
788 adev->need_dma32 = true;
789 dma_bits = 32;
790 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
791 }
792 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
793 if (r) {
794 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
795 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
796 }
797
798 r = gmc_v6_0_init_microcode(adev);
799 if (r) {
800 dev_err(adev->dev, "Failed to load mc firmware!\n");
801 return r;
802 }
803
804 r = gmc_v6_0_mc_init(adev);
805 if (r)
806 return r;
807
808 r = amdgpu_bo_init(adev);
809 if (r)
810 return r;
811
812 r = gmc_v6_0_gart_init(adev);
813 if (r)
814 return r;
815
816 if (!adev->vm_manager.enabled) {
817 r = gmc_v6_0_vm_init(adev);
818 if (r) {
819 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
820 return r;
821 }
822 adev->vm_manager.enabled = true;
823 }
824
825 return r;
826}
827
828static int gmc_v6_0_sw_fini(void *handle)
829{
830 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
831
832 if (adev->vm_manager.enabled) {
833 gmc_v6_0_vm_fini(adev);
834 adev->vm_manager.enabled = false;
835 }
836 gmc_v6_0_gart_fini(adev);
837 amdgpu_gem_force_release(adev);
838 amdgpu_bo_fini(adev);
839
840 return 0;
841}
842
843static int gmc_v6_0_hw_init(void *handle)
844{
845 int r;
846 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
847
848 gmc_v6_0_mc_program(adev);
849
850 if (!(adev->flags & AMD_IS_APU)) {
851 r = gmc_v6_0_mc_load_microcode(adev);
852 if (r) {
853 dev_err(adev->dev, "Failed to load MC firmware!\n");
854 return r;
855 }
856 }
857
858 r = gmc_v6_0_gart_enable(adev);
859 if (r)
860 return r;
861
862 return r;
863}
864
865static int gmc_v6_0_hw_fini(void *handle)
866{
867 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
868
869 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
870 gmc_v6_0_gart_disable(adev);
871
872 return 0;
873}
874
875static int gmc_v6_0_suspend(void *handle)
876{
877 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
878
879 if (adev->vm_manager.enabled) {
880 gmc_v6_0_vm_fini(adev);
881 adev->vm_manager.enabled = false;
882 }
883 gmc_v6_0_hw_fini(adev);
884
885 return 0;
886}
887
888static int gmc_v6_0_resume(void *handle)
889{
890 int r;
891 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
892
893 r = gmc_v6_0_hw_init(adev);
894 if (r)
895 return r;
896
897 if (!adev->vm_manager.enabled) {
898 r = gmc_v6_0_vm_init(adev);
899 if (r) {
900 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
901 return r;
902 }
903 adev->vm_manager.enabled = true;
904 }
905
906 return r;
907}
908
909static bool gmc_v6_0_is_idle(void *handle)
910{
911 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
912 u32 tmp = RREG32(mmSRBM_STATUS);
913
914 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
915 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
916 return false;
917
918 return true;
919}
920
921static int gmc_v6_0_wait_for_idle(void *handle)
922{
923 unsigned i;
924 u32 tmp;
925 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
926
927 for (i = 0; i < adev->usec_timeout; i++) {
928 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
929 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
930 SRBM_STATUS__MCC_BUSY_MASK |
931 SRBM_STATUS__MCD_BUSY_MASK |
932 SRBM_STATUS__VMC_BUSY_MASK);
933 if (!tmp)
934 return 0;
935 udelay(1);
936 }
937 return -ETIMEDOUT;
938
939}
940
941static int gmc_v6_0_soft_reset(void *handle)
942{
943 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
944 struct amdgpu_mode_mc_save save;
945 u32 srbm_soft_reset = 0;
946 u32 tmp = RREG32(mmSRBM_STATUS);
947
948 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
949 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
950 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
951
952 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
953 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
954 if (!(adev->flags & AMD_IS_APU))
955 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
956 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
957 }
958
959 if (srbm_soft_reset) {
960 gmc_v6_0_mc_stop(adev, &save);
961 if (gmc_v6_0_wait_for_idle(adev)) {
962 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
963 }
964
965
966 tmp = RREG32(mmSRBM_SOFT_RESET);
967 tmp |= srbm_soft_reset;
968 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
969 WREG32(mmSRBM_SOFT_RESET, tmp);
970 tmp = RREG32(mmSRBM_SOFT_RESET);
971
972 udelay(50);
973
974 tmp &= ~srbm_soft_reset;
975 WREG32(mmSRBM_SOFT_RESET, tmp);
976 tmp = RREG32(mmSRBM_SOFT_RESET);
977
978 udelay(50);
979
980 gmc_v6_0_mc_resume(adev, &save);
981 udelay(50);
982 }
983
984 return 0;
985}
986
987static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
988 struct amdgpu_irq_src *src,
989 unsigned type,
990 enum amdgpu_interrupt_state state)
991{
992 u32 tmp;
993 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
994 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
995 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
996 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
997 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
998 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
999
1000 switch (state) {
1001 case AMDGPU_IRQ_STATE_DISABLE:
1002 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1003 tmp &= ~bits;
1004 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1005 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1006 tmp &= ~bits;
1007 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1008 break;
1009 case AMDGPU_IRQ_STATE_ENABLE:
1010 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1011 tmp |= bits;
1012 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1013 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1014 tmp |= bits;
1015 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1016 break;
1017 default:
1018 break;
1019 }
1020
1021 return 0;
1022}
1023
1024static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1025 struct amdgpu_irq_src *source,
1026 struct amdgpu_iv_entry *entry)
1027{
1028 u32 addr, status;
1029
1030 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1031 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1032 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1033
1034 if (!addr && !status)
1035 return 0;
1036
1037 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1038 gmc_v6_0_set_fault_enable_default(adev, false);
1039
1040 if (printk_ratelimit()) {
1041 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1042 entry->src_id, entry->src_data);
1043 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1044 addr);
1045 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1046 status);
1047 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1048 }
1049
1050 return 0;
1051}
1052
1053static int gmc_v6_0_set_clockgating_state(void *handle,
1054 enum amd_clockgating_state state)
1055{
1056 return 0;
1057}
1058
1059static int gmc_v6_0_set_powergating_state(void *handle,
1060 enum amd_powergating_state state)
1061{
1062 return 0;
1063}
1064
1065static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1066 .name = "gmc_v6_0",
1067 .early_init = gmc_v6_0_early_init,
1068 .late_init = gmc_v6_0_late_init,
1069 .sw_init = gmc_v6_0_sw_init,
1070 .sw_fini = gmc_v6_0_sw_fini,
1071 .hw_init = gmc_v6_0_hw_init,
1072 .hw_fini = gmc_v6_0_hw_fini,
1073 .suspend = gmc_v6_0_suspend,
1074 .resume = gmc_v6_0_resume,
1075 .is_idle = gmc_v6_0_is_idle,
1076 .wait_for_idle = gmc_v6_0_wait_for_idle,
1077 .soft_reset = gmc_v6_0_soft_reset,
1078 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1079 .set_powergating_state = gmc_v6_0_set_powergating_state,
1080};
1081
1082static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1083 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1084 .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
1085};
1086
1087static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1088 .set = gmc_v6_0_vm_fault_interrupt_state,
1089 .process = gmc_v6_0_process_interrupt,
1090};
1091
1092static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1093{
1094 if (adev->gart.gart_funcs == NULL)
1095 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1096}
1097
1098static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1099{
1100 adev->mc.vm_fault.num_types = 1;
1101 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1102}
1103
1104const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1105{
1106 .type = AMD_IP_BLOCK_TYPE_GMC,
1107 .major = 6,
1108 .minor = 0,
1109 .rev = 0,
1110 .funcs = &gmc_v6_0_ip_funcs,
1111};