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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Local APIC related interfaces to support IOAPIC, MSI, etc.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * Jiang Liu <jiang.liu@linux.intel.com>
8 * Enable support of hierarchical irqdomains
9 */
10#include <linux/interrupt.h>
11#include <linux/irq.h>
12#include <linux/seq_file.h>
13#include <linux/init.h>
14#include <linux/compiler.h>
15#include <linux/slab.h>
16#include <asm/irqdomain.h>
17#include <asm/hw_irq.h>
18#include <asm/traps.h>
19#include <asm/apic.h>
20#include <asm/i8259.h>
21#include <asm/desc.h>
22#include <asm/irq_remapping.h>
23
24#include <asm/trace/irq_vectors.h>
25
26struct apic_chip_data {
27 struct irq_cfg hw_irq_cfg;
28 unsigned int vector;
29 unsigned int prev_vector;
30 unsigned int cpu;
31 unsigned int prev_cpu;
32 unsigned int irq;
33 struct hlist_node clist;
34 unsigned int move_in_progress : 1,
35 is_managed : 1,
36 can_reserve : 1,
37 has_reserved : 1;
38};
39
40struct irq_domain *x86_vector_domain;
41EXPORT_SYMBOL_GPL(x86_vector_domain);
42static DEFINE_RAW_SPINLOCK(vector_lock);
43static cpumask_var_t vector_searchmask;
44static struct irq_chip lapic_controller;
45static struct irq_matrix *vector_matrix;
46#ifdef CONFIG_SMP
47static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
48#endif
49
50void lock_vector_lock(void)
51{
52 /* Used to the online set of cpus does not change
53 * during assign_irq_vector.
54 */
55 raw_spin_lock(&vector_lock);
56}
57
58void unlock_vector_lock(void)
59{
60 raw_spin_unlock(&vector_lock);
61}
62
63void init_irq_alloc_info(struct irq_alloc_info *info,
64 const struct cpumask *mask)
65{
66 memset(info, 0, sizeof(*info));
67 info->mask = mask;
68}
69
70void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
71{
72 if (src)
73 *dst = *src;
74 else
75 memset(dst, 0, sizeof(*dst));
76}
77
78static struct apic_chip_data *apic_chip_data(struct irq_data *irqd)
79{
80 if (!irqd)
81 return NULL;
82
83 while (irqd->parent_data)
84 irqd = irqd->parent_data;
85
86 return irqd->chip_data;
87}
88
89struct irq_cfg *irqd_cfg(struct irq_data *irqd)
90{
91 struct apic_chip_data *apicd = apic_chip_data(irqd);
92
93 return apicd ? &apicd->hw_irq_cfg : NULL;
94}
95EXPORT_SYMBOL_GPL(irqd_cfg);
96
97struct irq_cfg *irq_cfg(unsigned int irq)
98{
99 return irqd_cfg(irq_get_irq_data(irq));
100}
101
102static struct apic_chip_data *alloc_apic_chip_data(int node)
103{
104 struct apic_chip_data *apicd;
105
106 apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node);
107 if (apicd)
108 INIT_HLIST_NODE(&apicd->clist);
109 return apicd;
110}
111
112static void free_apic_chip_data(struct apic_chip_data *apicd)
113{
114 kfree(apicd);
115}
116
117static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector,
118 unsigned int cpu)
119{
120 struct apic_chip_data *apicd = apic_chip_data(irqd);
121
122 lockdep_assert_held(&vector_lock);
123
124 apicd->hw_irq_cfg.vector = vector;
125 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);
126 irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
127 trace_vector_config(irqd->irq, vector, cpu,
128 apicd->hw_irq_cfg.dest_apicid);
129}
130
131static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
132 unsigned int newcpu)
133{
134 struct apic_chip_data *apicd = apic_chip_data(irqd);
135 struct irq_desc *desc = irq_data_to_desc(irqd);
136 bool managed = irqd_affinity_is_managed(irqd);
137
138 lockdep_assert_held(&vector_lock);
139
140 trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
141 apicd->cpu);
142
143 /*
144 * If there is no vector associated or if the associated vector is
145 * the shutdown vector, which is associated to make PCI/MSI
146 * shutdown mode work, then there is nothing to release. Clear out
147 * prev_vector for this and the offlined target case.
148 */
149 apicd->prev_vector = 0;
150 if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR)
151 goto setnew;
152 /*
153 * If the target CPU of the previous vector is online, then mark
154 * the vector as move in progress and store it for cleanup when the
155 * first interrupt on the new vector arrives. If the target CPU is
156 * offline then the regular release mechanism via the cleanup
157 * vector is not possible and the vector can be immediately freed
158 * in the underlying matrix allocator.
159 */
160 if (cpu_online(apicd->cpu)) {
161 apicd->move_in_progress = true;
162 apicd->prev_vector = apicd->vector;
163 apicd->prev_cpu = apicd->cpu;
164 } else {
165 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
166 managed);
167 }
168
169setnew:
170 apicd->vector = newvec;
171 apicd->cpu = newcpu;
172 BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
173 per_cpu(vector_irq, newcpu)[newvec] = desc;
174}
175
176static void vector_assign_managed_shutdown(struct irq_data *irqd)
177{
178 unsigned int cpu = cpumask_first(cpu_online_mask);
179
180 apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu);
181}
182
183static int reserve_managed_vector(struct irq_data *irqd)
184{
185 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
186 struct apic_chip_data *apicd = apic_chip_data(irqd);
187 unsigned long flags;
188 int ret;
189
190 raw_spin_lock_irqsave(&vector_lock, flags);
191 apicd->is_managed = true;
192 ret = irq_matrix_reserve_managed(vector_matrix, affmsk);
193 raw_spin_unlock_irqrestore(&vector_lock, flags);
194 trace_vector_reserve_managed(irqd->irq, ret);
195 return ret;
196}
197
198static void reserve_irq_vector_locked(struct irq_data *irqd)
199{
200 struct apic_chip_data *apicd = apic_chip_data(irqd);
201
202 irq_matrix_reserve(vector_matrix);
203 apicd->can_reserve = true;
204 apicd->has_reserved = true;
205 irqd_set_can_reserve(irqd);
206 trace_vector_reserve(irqd->irq, 0);
207 vector_assign_managed_shutdown(irqd);
208}
209
210static int reserve_irq_vector(struct irq_data *irqd)
211{
212 unsigned long flags;
213
214 raw_spin_lock_irqsave(&vector_lock, flags);
215 reserve_irq_vector_locked(irqd);
216 raw_spin_unlock_irqrestore(&vector_lock, flags);
217 return 0;
218}
219
220static int
221assign_vector_locked(struct irq_data *irqd, const struct cpumask *dest)
222{
223 struct apic_chip_data *apicd = apic_chip_data(irqd);
224 bool resvd = apicd->has_reserved;
225 unsigned int cpu = apicd->cpu;
226 int vector = apicd->vector;
227
228 lockdep_assert_held(&vector_lock);
229
230 /*
231 * If the current target CPU is online and in the new requested
232 * affinity mask, there is no point in moving the interrupt from
233 * one CPU to another.
234 */
235 if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest))
236 return 0;
237
238 /*
239 * Careful here. @apicd might either have move_in_progress set or
240 * be enqueued for cleanup. Assigning a new vector would either
241 * leave a stale vector on some CPU around or in case of a pending
242 * cleanup corrupt the hlist.
243 */
244 if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist))
245 return -EBUSY;
246
247 vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu);
248 trace_vector_alloc(irqd->irq, vector, resvd, vector);
249 if (vector < 0)
250 return vector;
251 apic_update_vector(irqd, vector, cpu);
252 apic_update_irq_cfg(irqd, vector, cpu);
253
254 return 0;
255}
256
257static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest)
258{
259 unsigned long flags;
260 int ret;
261
262 raw_spin_lock_irqsave(&vector_lock, flags);
263 cpumask_and(vector_searchmask, dest, cpu_online_mask);
264 ret = assign_vector_locked(irqd, vector_searchmask);
265 raw_spin_unlock_irqrestore(&vector_lock, flags);
266 return ret;
267}
268
269static int assign_irq_vector_any_locked(struct irq_data *irqd)
270{
271 /* Get the affinity mask - either irq_default_affinity or (user) set */
272 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
273 int node = irq_data_get_node(irqd);
274
275 if (node == NUMA_NO_NODE)
276 goto all;
277 /* Try the intersection of @affmsk and node mask */
278 cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);
279 if (!assign_vector_locked(irqd, vector_searchmask))
280 return 0;
281 /* Try the node mask */
282 if (!assign_vector_locked(irqd, cpumask_of_node(node)))
283 return 0;
284all:
285 /* Try the full affinity mask */
286 cpumask_and(vector_searchmask, affmsk, cpu_online_mask);
287 if (!assign_vector_locked(irqd, vector_searchmask))
288 return 0;
289 /* Try the full online mask */
290 return assign_vector_locked(irqd, cpu_online_mask);
291}
292
293static int
294assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
295{
296 if (irqd_affinity_is_managed(irqd))
297 return reserve_managed_vector(irqd);
298 if (info->mask)
299 return assign_irq_vector(irqd, info->mask);
300 /*
301 * Make only a global reservation with no guarantee. A real vector
302 * is associated at activation time.
303 */
304 return reserve_irq_vector(irqd);
305}
306
307static int
308assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest)
309{
310 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
311 struct apic_chip_data *apicd = apic_chip_data(irqd);
312 int vector, cpu;
313
314 cpumask_and(vector_searchmask, dest, affmsk);
315
316 /* set_affinity might call here for nothing */
317 if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask))
318 return 0;
319 vector = irq_matrix_alloc_managed(vector_matrix, vector_searchmask,
320 &cpu);
321 trace_vector_alloc_managed(irqd->irq, vector, vector);
322 if (vector < 0)
323 return vector;
324 apic_update_vector(irqd, vector, cpu);
325 apic_update_irq_cfg(irqd, vector, cpu);
326 return 0;
327}
328
329static void clear_irq_vector(struct irq_data *irqd)
330{
331 struct apic_chip_data *apicd = apic_chip_data(irqd);
332 bool managed = irqd_affinity_is_managed(irqd);
333 unsigned int vector = apicd->vector;
334
335 lockdep_assert_held(&vector_lock);
336
337 if (!vector)
338 return;
339
340 trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector,
341 apicd->prev_cpu);
342
343 per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_SHUTDOWN;
344 irq_matrix_free(vector_matrix, apicd->cpu, vector, managed);
345 apicd->vector = 0;
346
347 /* Clean up move in progress */
348 vector = apicd->prev_vector;
349 if (!vector)
350 return;
351
352 per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_SHUTDOWN;
353 irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed);
354 apicd->prev_vector = 0;
355 apicd->move_in_progress = 0;
356 hlist_del_init(&apicd->clist);
357}
358
359static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd)
360{
361 struct apic_chip_data *apicd = apic_chip_data(irqd);
362 unsigned long flags;
363
364 trace_vector_deactivate(irqd->irq, apicd->is_managed,
365 apicd->can_reserve, false);
366
367 /* Regular fixed assigned interrupt */
368 if (!apicd->is_managed && !apicd->can_reserve)
369 return;
370 /* If the interrupt has a global reservation, nothing to do */
371 if (apicd->has_reserved)
372 return;
373
374 raw_spin_lock_irqsave(&vector_lock, flags);
375 clear_irq_vector(irqd);
376 if (apicd->can_reserve)
377 reserve_irq_vector_locked(irqd);
378 else
379 vector_assign_managed_shutdown(irqd);
380 raw_spin_unlock_irqrestore(&vector_lock, flags);
381}
382
383static int activate_reserved(struct irq_data *irqd)
384{
385 struct apic_chip_data *apicd = apic_chip_data(irqd);
386 int ret;
387
388 ret = assign_irq_vector_any_locked(irqd);
389 if (!ret) {
390 apicd->has_reserved = false;
391 /*
392 * Core might have disabled reservation mode after
393 * allocating the irq descriptor. Ideally this should
394 * happen before allocation time, but that would require
395 * completely convoluted ways of transporting that
396 * information.
397 */
398 if (!irqd_can_reserve(irqd))
399 apicd->can_reserve = false;
400 }
401
402 /*
403 * Check to ensure that the effective affinity mask is a subset
404 * the user supplied affinity mask, and warn the user if it is not
405 */
406 if (!cpumask_subset(irq_data_get_effective_affinity_mask(irqd),
407 irq_data_get_affinity_mask(irqd))) {
408 pr_warn("irq %u: Affinity broken due to vector space exhaustion.\n",
409 irqd->irq);
410 }
411
412 return ret;
413}
414
415static int activate_managed(struct irq_data *irqd)
416{
417 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
418 int ret;
419
420 cpumask_and(vector_searchmask, dest, cpu_online_mask);
421 if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) {
422 /* Something in the core code broke! Survive gracefully */
423 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq);
424 return -EINVAL;
425 }
426
427 ret = assign_managed_vector(irqd, vector_searchmask);
428 /*
429 * This should not happen. The vector reservation got buggered. Handle
430 * it gracefully.
431 */
432 if (WARN_ON_ONCE(ret < 0)) {
433 pr_err("Managed startup irq %u, no vector available\n",
434 irqd->irq);
435 }
436 return ret;
437}
438
439static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd,
440 bool reserve)
441{
442 struct apic_chip_data *apicd = apic_chip_data(irqd);
443 unsigned long flags;
444 int ret = 0;
445
446 trace_vector_activate(irqd->irq, apicd->is_managed,
447 apicd->can_reserve, reserve);
448
449 /* Nothing to do for fixed assigned vectors */
450 if (!apicd->can_reserve && !apicd->is_managed)
451 return 0;
452
453 raw_spin_lock_irqsave(&vector_lock, flags);
454 if (reserve || irqd_is_managed_and_shutdown(irqd))
455 vector_assign_managed_shutdown(irqd);
456 else if (apicd->is_managed)
457 ret = activate_managed(irqd);
458 else if (apicd->has_reserved)
459 ret = activate_reserved(irqd);
460 raw_spin_unlock_irqrestore(&vector_lock, flags);
461 return ret;
462}
463
464static void vector_free_reserved_and_managed(struct irq_data *irqd)
465{
466 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
467 struct apic_chip_data *apicd = apic_chip_data(irqd);
468
469 trace_vector_teardown(irqd->irq, apicd->is_managed,
470 apicd->has_reserved);
471
472 if (apicd->has_reserved)
473 irq_matrix_remove_reserved(vector_matrix);
474 if (apicd->is_managed)
475 irq_matrix_remove_managed(vector_matrix, dest);
476}
477
478static void x86_vector_free_irqs(struct irq_domain *domain,
479 unsigned int virq, unsigned int nr_irqs)
480{
481 struct apic_chip_data *apicd;
482 struct irq_data *irqd;
483 unsigned long flags;
484 int i;
485
486 for (i = 0; i < nr_irqs; i++) {
487 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i);
488 if (irqd && irqd->chip_data) {
489 raw_spin_lock_irqsave(&vector_lock, flags);
490 clear_irq_vector(irqd);
491 vector_free_reserved_and_managed(irqd);
492 apicd = irqd->chip_data;
493 irq_domain_reset_irq_data(irqd);
494 raw_spin_unlock_irqrestore(&vector_lock, flags);
495 free_apic_chip_data(apicd);
496 }
497 }
498}
499
500static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
501 struct apic_chip_data *apicd)
502{
503 unsigned long flags;
504 bool realloc = false;
505
506 apicd->vector = ISA_IRQ_VECTOR(virq);
507 apicd->cpu = 0;
508
509 raw_spin_lock_irqsave(&vector_lock, flags);
510 /*
511 * If the interrupt is activated, then it must stay at this vector
512 * position. That's usually the timer interrupt (0).
513 */
514 if (irqd_is_activated(irqd)) {
515 trace_vector_setup(virq, true, 0);
516 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
517 } else {
518 /* Release the vector */
519 apicd->can_reserve = true;
520 irqd_set_can_reserve(irqd);
521 clear_irq_vector(irqd);
522 realloc = true;
523 }
524 raw_spin_unlock_irqrestore(&vector_lock, flags);
525 return realloc;
526}
527
528static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
529 unsigned int nr_irqs, void *arg)
530{
531 struct irq_alloc_info *info = arg;
532 struct apic_chip_data *apicd;
533 struct irq_data *irqd;
534 int i, err, node;
535
536 if (disable_apic)
537 return -ENXIO;
538
539 /* Currently vector allocator can't guarantee contiguous allocations */
540 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
541 return -ENOSYS;
542
543 for (i = 0; i < nr_irqs; i++) {
544 irqd = irq_domain_get_irq_data(domain, virq + i);
545 BUG_ON(!irqd);
546 node = irq_data_get_node(irqd);
547 WARN_ON_ONCE(irqd->chip_data);
548 apicd = alloc_apic_chip_data(node);
549 if (!apicd) {
550 err = -ENOMEM;
551 goto error;
552 }
553
554 apicd->irq = virq + i;
555 irqd->chip = &lapic_controller;
556 irqd->chip_data = apicd;
557 irqd->hwirq = virq + i;
558 irqd_set_single_target(irqd);
559 /*
560 * Legacy vectors are already assigned when the IOAPIC
561 * takes them over. They stay on the same vector. This is
562 * required for check_timer() to work correctly as it might
563 * switch back to legacy mode. Only update the hardware
564 * config.
565 */
566 if (info->flags & X86_IRQ_ALLOC_LEGACY) {
567 if (!vector_configure_legacy(virq + i, irqd, apicd))
568 continue;
569 }
570
571 err = assign_irq_vector_policy(irqd, info);
572 trace_vector_setup(virq + i, false, err);
573 if (err) {
574 irqd->chip_data = NULL;
575 free_apic_chip_data(apicd);
576 goto error;
577 }
578 }
579
580 return 0;
581
582error:
583 x86_vector_free_irqs(domain, virq, i);
584 return err;
585}
586
587#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
588static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,
589 struct irq_data *irqd, int ind)
590{
591 struct apic_chip_data apicd;
592 unsigned long flags;
593 int irq;
594
595 if (!irqd) {
596 irq_matrix_debug_show(m, vector_matrix, ind);
597 return;
598 }
599
600 irq = irqd->irq;
601 if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) {
602 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq));
603 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, "");
604 return;
605 }
606
607 if (!irqd->chip_data) {
608 seq_printf(m, "%*sVector: Not assigned\n", ind, "");
609 return;
610 }
611
612 raw_spin_lock_irqsave(&vector_lock, flags);
613 memcpy(&apicd, irqd->chip_data, sizeof(apicd));
614 raw_spin_unlock_irqrestore(&vector_lock, flags);
615
616 seq_printf(m, "%*sVector: %5u\n", ind, "", apicd.vector);
617 seq_printf(m, "%*sTarget: %5u\n", ind, "", apicd.cpu);
618 if (apicd.prev_vector) {
619 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", apicd.prev_vector);
620 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", apicd.prev_cpu);
621 }
622 seq_printf(m, "%*smove_in_progress: %u\n", ind, "", apicd.move_in_progress ? 1 : 0);
623 seq_printf(m, "%*sis_managed: %u\n", ind, "", apicd.is_managed ? 1 : 0);
624 seq_printf(m, "%*scan_reserve: %u\n", ind, "", apicd.can_reserve ? 1 : 0);
625 seq_printf(m, "%*shas_reserved: %u\n", ind, "", apicd.has_reserved ? 1 : 0);
626 seq_printf(m, "%*scleanup_pending: %u\n", ind, "", !hlist_unhashed(&apicd.clist));
627}
628#endif
629
630static const struct irq_domain_ops x86_vector_domain_ops = {
631 .alloc = x86_vector_alloc_irqs,
632 .free = x86_vector_free_irqs,
633 .activate = x86_vector_activate,
634 .deactivate = x86_vector_deactivate,
635#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
636 .debug_show = x86_vector_debug_show,
637#endif
638};
639
640int __init arch_probe_nr_irqs(void)
641{
642 int nr;
643
644 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
645 nr_irqs = NR_VECTORS * nr_cpu_ids;
646
647 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
648#if defined(CONFIG_PCI_MSI)
649 /*
650 * for MSI and HT dyn irq
651 */
652 if (gsi_top <= NR_IRQS_LEGACY)
653 nr += 8 * nr_cpu_ids;
654 else
655 nr += gsi_top * 16;
656#endif
657 if (nr < nr_irqs)
658 nr_irqs = nr;
659
660 /*
661 * We don't know if PIC is present at this point so we need to do
662 * probe() to get the right number of legacy IRQs.
663 */
664 return legacy_pic->probe();
665}
666
667void lapic_assign_legacy_vector(unsigned int irq, bool replace)
668{
669 /*
670 * Use assign system here so it wont get accounted as allocated
671 * and moveable in the cpu hotplug check and it prevents managed
672 * irq reservation from touching it.
673 */
674 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
675}
676
677void __init lapic_assign_system_vectors(void)
678{
679 unsigned int i, vector = 0;
680
681 for_each_set_bit_from(vector, system_vectors, NR_VECTORS)
682 irq_matrix_assign_system(vector_matrix, vector, false);
683
684 if (nr_legacy_irqs() > 1)
685 lapic_assign_legacy_vector(PIC_CASCADE_IR, false);
686
687 /* System vectors are reserved, online it */
688 irq_matrix_online(vector_matrix);
689
690 /* Mark the preallocated legacy interrupts */
691 for (i = 0; i < nr_legacy_irqs(); i++) {
692 if (i != PIC_CASCADE_IR)
693 irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
694 }
695}
696
697int __init arch_early_irq_init(void)
698{
699 struct fwnode_handle *fn;
700
701 fn = irq_domain_alloc_named_fwnode("VECTOR");
702 BUG_ON(!fn);
703 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops,
704 NULL);
705 BUG_ON(x86_vector_domain == NULL);
706 irq_domain_free_fwnode(fn);
707 irq_set_default_host(x86_vector_domain);
708
709 arch_init_msi_domain(x86_vector_domain);
710
711 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
712
713 /*
714 * Allocate the vector matrix allocator data structure and limit the
715 * search area.
716 */
717 vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
718 FIRST_SYSTEM_VECTOR);
719 BUG_ON(!vector_matrix);
720
721 return arch_early_ioapic_init();
722}
723
724#ifdef CONFIG_SMP
725
726static struct irq_desc *__setup_vector_irq(int vector)
727{
728 int isairq = vector - ISA_IRQ_VECTOR(0);
729
730 /* Check whether the irq is in the legacy space */
731 if (isairq < 0 || isairq >= nr_legacy_irqs())
732 return VECTOR_UNUSED;
733 /* Check whether the irq is handled by the IOAPIC */
734 if (test_bit(isairq, &io_apic_irqs))
735 return VECTOR_UNUSED;
736 return irq_to_desc(isairq);
737}
738
739/* Online the local APIC infrastructure and initialize the vectors */
740void lapic_online(void)
741{
742 unsigned int vector;
743
744 lockdep_assert_held(&vector_lock);
745
746 /* Online the vector matrix array for this CPU */
747 irq_matrix_online(vector_matrix);
748
749 /*
750 * The interrupt affinity logic never targets interrupts to offline
751 * CPUs. The exception are the legacy PIC interrupts. In general
752 * they are only targeted to CPU0, but depending on the platform
753 * they can be distributed to any online CPU in hardware. The
754 * kernel has no influence on that. So all active legacy vectors
755 * must be installed on all CPUs. All non legacy interrupts can be
756 * cleared.
757 */
758 for (vector = 0; vector < NR_VECTORS; vector++)
759 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector));
760}
761
762void lapic_offline(void)
763{
764 lock_vector_lock();
765 irq_matrix_offline(vector_matrix);
766 unlock_vector_lock();
767}
768
769static int apic_set_affinity(struct irq_data *irqd,
770 const struct cpumask *dest, bool force)
771{
772 struct apic_chip_data *apicd = apic_chip_data(irqd);
773 int err;
774
775 /*
776 * Core code can call here for inactive interrupts. For inactive
777 * interrupts which use managed or reservation mode there is no
778 * point in going through the vector assignment right now as the
779 * activation will assign a vector which fits the destination
780 * cpumask. Let the core code store the destination mask and be
781 * done with it.
782 */
783 if (!irqd_is_activated(irqd) &&
784 (apicd->is_managed || apicd->can_reserve))
785 return IRQ_SET_MASK_OK;
786
787 raw_spin_lock(&vector_lock);
788 cpumask_and(vector_searchmask, dest, cpu_online_mask);
789 if (irqd_affinity_is_managed(irqd))
790 err = assign_managed_vector(irqd, vector_searchmask);
791 else
792 err = assign_vector_locked(irqd, vector_searchmask);
793 raw_spin_unlock(&vector_lock);
794 return err ? err : IRQ_SET_MASK_OK;
795}
796
797#else
798# define apic_set_affinity NULL
799#endif
800
801static int apic_retrigger_irq(struct irq_data *irqd)
802{
803 struct apic_chip_data *apicd = apic_chip_data(irqd);
804 unsigned long flags;
805
806 raw_spin_lock_irqsave(&vector_lock, flags);
807 apic->send_IPI(apicd->cpu, apicd->vector);
808 raw_spin_unlock_irqrestore(&vector_lock, flags);
809
810 return 1;
811}
812
813void apic_ack_irq(struct irq_data *irqd)
814{
815 irq_move_irq(irqd);
816 ack_APIC_irq();
817}
818
819void apic_ack_edge(struct irq_data *irqd)
820{
821 irq_complete_move(irqd_cfg(irqd));
822 apic_ack_irq(irqd);
823}
824
825static struct irq_chip lapic_controller = {
826 .name = "APIC",
827 .irq_ack = apic_ack_edge,
828 .irq_set_affinity = apic_set_affinity,
829 .irq_retrigger = apic_retrigger_irq,
830};
831
832#ifdef CONFIG_SMP
833
834static void free_moved_vector(struct apic_chip_data *apicd)
835{
836 unsigned int vector = apicd->prev_vector;
837 unsigned int cpu = apicd->prev_cpu;
838 bool managed = apicd->is_managed;
839
840 /*
841 * This should never happen. Managed interrupts are not
842 * migrated except on CPU down, which does not involve the
843 * cleanup vector. But try to keep the accounting correct
844 * nevertheless.
845 */
846 WARN_ON_ONCE(managed);
847
848 trace_vector_free_moved(apicd->irq, cpu, vector, managed);
849 irq_matrix_free(vector_matrix, cpu, vector, managed);
850 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
851 hlist_del_init(&apicd->clist);
852 apicd->prev_vector = 0;
853 apicd->move_in_progress = 0;
854}
855
856asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void)
857{
858 struct hlist_head *clhead = this_cpu_ptr(&cleanup_list);
859 struct apic_chip_data *apicd;
860 struct hlist_node *tmp;
861
862 entering_ack_irq();
863 /* Prevent vectors vanishing under us */
864 raw_spin_lock(&vector_lock);
865
866 hlist_for_each_entry_safe(apicd, tmp, clhead, clist) {
867 unsigned int irr, vector = apicd->prev_vector;
868
869 /*
870 * Paranoia: Check if the vector that needs to be cleaned
871 * up is registered at the APICs IRR. If so, then this is
872 * not the best time to clean it up. Clean it up in the
873 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
874 * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest
875 * priority external vector, so on return from this
876 * interrupt the device interrupt will happen first.
877 */
878 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
879 if (irr & (1U << (vector % 32))) {
880 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
881 continue;
882 }
883 free_moved_vector(apicd);
884 }
885
886 raw_spin_unlock(&vector_lock);
887 exiting_irq();
888}
889
890static void __send_cleanup_vector(struct apic_chip_data *apicd)
891{
892 unsigned int cpu;
893
894 raw_spin_lock(&vector_lock);
895 apicd->move_in_progress = 0;
896 cpu = apicd->prev_cpu;
897 if (cpu_online(cpu)) {
898 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu));
899 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR);
900 } else {
901 apicd->prev_vector = 0;
902 }
903 raw_spin_unlock(&vector_lock);
904}
905
906void send_cleanup_vector(struct irq_cfg *cfg)
907{
908 struct apic_chip_data *apicd;
909
910 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
911 if (apicd->move_in_progress)
912 __send_cleanup_vector(apicd);
913}
914
915static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
916{
917 struct apic_chip_data *apicd;
918
919 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
920 if (likely(!apicd->move_in_progress))
921 return;
922
923 if (vector == apicd->vector && apicd->cpu == smp_processor_id())
924 __send_cleanup_vector(apicd);
925}
926
927void irq_complete_move(struct irq_cfg *cfg)
928{
929 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
930}
931
932/*
933 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
934 */
935void irq_force_complete_move(struct irq_desc *desc)
936{
937 struct apic_chip_data *apicd;
938 struct irq_data *irqd;
939 unsigned int vector;
940
941 /*
942 * The function is called for all descriptors regardless of which
943 * irqdomain they belong to. For example if an IRQ is provided by
944 * an irq_chip as part of a GPIO driver, the chip data for that
945 * descriptor is specific to the irq_chip in question.
946 *
947 * Check first that the chip_data is what we expect
948 * (apic_chip_data) before touching it any further.
949 */
950 irqd = irq_domain_get_irq_data(x86_vector_domain,
951 irq_desc_get_irq(desc));
952 if (!irqd)
953 return;
954
955 raw_spin_lock(&vector_lock);
956 apicd = apic_chip_data(irqd);
957 if (!apicd)
958 goto unlock;
959
960 /*
961 * If prev_vector is empty, no action required.
962 */
963 vector = apicd->prev_vector;
964 if (!vector)
965 goto unlock;
966
967 /*
968 * This is tricky. If the cleanup of the old vector has not been
969 * done yet, then the following setaffinity call will fail with
970 * -EBUSY. This can leave the interrupt in a stale state.
971 *
972 * All CPUs are stuck in stop machine with interrupts disabled so
973 * calling __irq_complete_move() would be completely pointless.
974 *
975 * 1) The interrupt is in move_in_progress state. That means that we
976 * have not seen an interrupt since the io_apic was reprogrammed to
977 * the new vector.
978 *
979 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
980 * have not been processed yet.
981 */
982 if (apicd->move_in_progress) {
983 /*
984 * In theory there is a race:
985 *
986 * set_ioapic(new_vector) <-- Interrupt is raised before update
987 * is effective, i.e. it's raised on
988 * the old vector.
989 *
990 * So if the target cpu cannot handle that interrupt before
991 * the old vector is cleaned up, we get a spurious interrupt
992 * and in the worst case the ioapic irq line becomes stale.
993 *
994 * But in case of cpu hotplug this should be a non issue
995 * because if the affinity update happens right before all
996 * cpus rendevouz in stop machine, there is no way that the
997 * interrupt can be blocked on the target cpu because all cpus
998 * loops first with interrupts enabled in stop machine, so the
999 * old vector is not yet cleaned up when the interrupt fires.
1000 *
1001 * So the only way to run into this issue is if the delivery
1002 * of the interrupt on the apic/system bus would be delayed
1003 * beyond the point where the target cpu disables interrupts
1004 * in stop machine. I doubt that it can happen, but at least
1005 * there is a theroretical chance. Virtualization might be
1006 * able to expose this, but AFAICT the IOAPIC emulation is not
1007 * as stupid as the real hardware.
1008 *
1009 * Anyway, there is nothing we can do about that at this point
1010 * w/o refactoring the whole fixup_irq() business completely.
1011 * We print at least the irq number and the old vector number,
1012 * so we have the necessary information when a problem in that
1013 * area arises.
1014 */
1015 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
1016 irqd->irq, vector);
1017 }
1018 free_moved_vector(apicd);
1019unlock:
1020 raw_spin_unlock(&vector_lock);
1021}
1022
1023#ifdef CONFIG_HOTPLUG_CPU
1024/*
1025 * Note, this is not accurate accounting, but at least good enough to
1026 * prevent that the actual interrupt move will run out of vectors.
1027 */
1028int lapic_can_unplug_cpu(void)
1029{
1030 unsigned int rsvd, avl, tomove, cpu = smp_processor_id();
1031 int ret = 0;
1032
1033 raw_spin_lock(&vector_lock);
1034 tomove = irq_matrix_allocated(vector_matrix);
1035 avl = irq_matrix_available(vector_matrix, true);
1036 if (avl < tomove) {
1037 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n",
1038 cpu, tomove, avl);
1039 ret = -ENOSPC;
1040 goto out;
1041 }
1042 rsvd = irq_matrix_reserved(vector_matrix);
1043 if (avl < rsvd) {
1044 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n",
1045 rsvd, avl);
1046 }
1047out:
1048 raw_spin_unlock(&vector_lock);
1049 return ret;
1050}
1051#endif /* HOTPLUG_CPU */
1052#endif /* SMP */
1053
1054static void __init print_APIC_field(int base)
1055{
1056 int i;
1057
1058 printk(KERN_DEBUG);
1059
1060 for (i = 0; i < 8; i++)
1061 pr_cont("%08x", apic_read(base + i*0x10));
1062
1063 pr_cont("\n");
1064}
1065
1066static void __init print_local_APIC(void *dummy)
1067{
1068 unsigned int i, v, ver, maxlvt;
1069 u64 icr;
1070
1071 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
1072 smp_processor_id(), hard_smp_processor_id());
1073 v = apic_read(APIC_ID);
1074 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
1075 v = apic_read(APIC_LVR);
1076 pr_info("... APIC VERSION: %08x\n", v);
1077 ver = GET_APIC_VERSION(v);
1078 maxlvt = lapic_get_maxlvt();
1079
1080 v = apic_read(APIC_TASKPRI);
1081 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1082
1083 /* !82489DX */
1084 if (APIC_INTEGRATED(ver)) {
1085 if (!APIC_XAPIC(ver)) {
1086 v = apic_read(APIC_ARBPRI);
1087 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
1088 v, v & APIC_ARBPRI_MASK);
1089 }
1090 v = apic_read(APIC_PROCPRI);
1091 pr_debug("... APIC PROCPRI: %08x\n", v);
1092 }
1093
1094 /*
1095 * Remote read supported only in the 82489DX and local APIC for
1096 * Pentium processors.
1097 */
1098 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1099 v = apic_read(APIC_RRR);
1100 pr_debug("... APIC RRR: %08x\n", v);
1101 }
1102
1103 v = apic_read(APIC_LDR);
1104 pr_debug("... APIC LDR: %08x\n", v);
1105 if (!x2apic_enabled()) {
1106 v = apic_read(APIC_DFR);
1107 pr_debug("... APIC DFR: %08x\n", v);
1108 }
1109 v = apic_read(APIC_SPIV);
1110 pr_debug("... APIC SPIV: %08x\n", v);
1111
1112 pr_debug("... APIC ISR field:\n");
1113 print_APIC_field(APIC_ISR);
1114 pr_debug("... APIC TMR field:\n");
1115 print_APIC_field(APIC_TMR);
1116 pr_debug("... APIC IRR field:\n");
1117 print_APIC_field(APIC_IRR);
1118
1119 /* !82489DX */
1120 if (APIC_INTEGRATED(ver)) {
1121 /* Due to the Pentium erratum 3AP. */
1122 if (maxlvt > 3)
1123 apic_write(APIC_ESR, 0);
1124
1125 v = apic_read(APIC_ESR);
1126 pr_debug("... APIC ESR: %08x\n", v);
1127 }
1128
1129 icr = apic_icr_read();
1130 pr_debug("... APIC ICR: %08x\n", (u32)icr);
1131 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
1132
1133 v = apic_read(APIC_LVTT);
1134 pr_debug("... APIC LVTT: %08x\n", v);
1135
1136 if (maxlvt > 3) {
1137 /* PC is LVT#4. */
1138 v = apic_read(APIC_LVTPC);
1139 pr_debug("... APIC LVTPC: %08x\n", v);
1140 }
1141 v = apic_read(APIC_LVT0);
1142 pr_debug("... APIC LVT0: %08x\n", v);
1143 v = apic_read(APIC_LVT1);
1144 pr_debug("... APIC LVT1: %08x\n", v);
1145
1146 if (maxlvt > 2) {
1147 /* ERR is LVT#3. */
1148 v = apic_read(APIC_LVTERR);
1149 pr_debug("... APIC LVTERR: %08x\n", v);
1150 }
1151
1152 v = apic_read(APIC_TMICT);
1153 pr_debug("... APIC TMICT: %08x\n", v);
1154 v = apic_read(APIC_TMCCT);
1155 pr_debug("... APIC TMCCT: %08x\n", v);
1156 v = apic_read(APIC_TDCR);
1157 pr_debug("... APIC TDCR: %08x\n", v);
1158
1159 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1160 v = apic_read(APIC_EFEAT);
1161 maxlvt = (v >> 16) & 0xff;
1162 pr_debug("... APIC EFEAT: %08x\n", v);
1163 v = apic_read(APIC_ECTRL);
1164 pr_debug("... APIC ECTRL: %08x\n", v);
1165 for (i = 0; i < maxlvt; i++) {
1166 v = apic_read(APIC_EILVTn(i));
1167 pr_debug("... APIC EILVT%d: %08x\n", i, v);
1168 }
1169 }
1170 pr_cont("\n");
1171}
1172
1173static void __init print_local_APICs(int maxcpu)
1174{
1175 int cpu;
1176
1177 if (!maxcpu)
1178 return;
1179
1180 preempt_disable();
1181 for_each_online_cpu(cpu) {
1182 if (cpu >= maxcpu)
1183 break;
1184 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1185 }
1186 preempt_enable();
1187}
1188
1189static void __init print_PIC(void)
1190{
1191 unsigned int v;
1192 unsigned long flags;
1193
1194 if (!nr_legacy_irqs())
1195 return;
1196
1197 pr_debug("\nprinting PIC contents\n");
1198
1199 raw_spin_lock_irqsave(&i8259A_lock, flags);
1200
1201 v = inb(0xa1) << 8 | inb(0x21);
1202 pr_debug("... PIC IMR: %04x\n", v);
1203
1204 v = inb(0xa0) << 8 | inb(0x20);
1205 pr_debug("... PIC IRR: %04x\n", v);
1206
1207 outb(0x0b, 0xa0);
1208 outb(0x0b, 0x20);
1209 v = inb(0xa0) << 8 | inb(0x20);
1210 outb(0x0a, 0xa0);
1211 outb(0x0a, 0x20);
1212
1213 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1214
1215 pr_debug("... PIC ISR: %04x\n", v);
1216
1217 v = inb(0x4d1) << 8 | inb(0x4d0);
1218 pr_debug("... PIC ELCR: %04x\n", v);
1219}
1220
1221static int show_lapic __initdata = 1;
1222static __init int setup_show_lapic(char *arg)
1223{
1224 int num = -1;
1225
1226 if (strcmp(arg, "all") == 0) {
1227 show_lapic = CONFIG_NR_CPUS;
1228 } else {
1229 get_option(&arg, &num);
1230 if (num >= 0)
1231 show_lapic = num;
1232 }
1233
1234 return 1;
1235}
1236__setup("show_lapic=", setup_show_lapic);
1237
1238static int __init print_ICs(void)
1239{
1240 if (apic_verbosity == APIC_QUIET)
1241 return 0;
1242
1243 print_PIC();
1244
1245 /* don't print out if apic is not there */
1246 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1247 return 0;
1248
1249 print_local_APICs(show_lapic);
1250 print_IO_APICs();
1251
1252 return 0;
1253}
1254
1255late_initcall(print_ICs);
1/*
2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/interrupt.h>
14#include <linux/init.h>
15#include <linux/compiler.h>
16#include <linux/slab.h>
17#include <asm/irqdomain.h>
18#include <asm/hw_irq.h>
19#include <asm/apic.h>
20#include <asm/i8259.h>
21#include <asm/desc.h>
22#include <asm/irq_remapping.h>
23
24struct apic_chip_data {
25 struct irq_cfg cfg;
26 cpumask_var_t domain;
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
29};
30
31struct irq_domain *x86_vector_domain;
32EXPORT_SYMBOL_GPL(x86_vector_domain);
33static DEFINE_RAW_SPINLOCK(vector_lock);
34static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask;
35static struct irq_chip lapic_controller;
36#ifdef CONFIG_X86_IO_APIC
37static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
38#endif
39
40void lock_vector_lock(void)
41{
42 /* Used to the online set of cpus does not change
43 * during assign_irq_vector.
44 */
45 raw_spin_lock(&vector_lock);
46}
47
48void unlock_vector_lock(void)
49{
50 raw_spin_unlock(&vector_lock);
51}
52
53static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
54{
55 if (!irq_data)
56 return NULL;
57
58 while (irq_data->parent_data)
59 irq_data = irq_data->parent_data;
60
61 return irq_data->chip_data;
62}
63
64struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
65{
66 struct apic_chip_data *data = apic_chip_data(irq_data);
67
68 return data ? &data->cfg : NULL;
69}
70EXPORT_SYMBOL_GPL(irqd_cfg);
71
72struct irq_cfg *irq_cfg(unsigned int irq)
73{
74 return irqd_cfg(irq_get_irq_data(irq));
75}
76
77static struct apic_chip_data *alloc_apic_chip_data(int node)
78{
79 struct apic_chip_data *data;
80
81 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
82 if (!data)
83 return NULL;
84 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
85 goto out_data;
86 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
87 goto out_domain;
88 return data;
89out_domain:
90 free_cpumask_var(data->domain);
91out_data:
92 kfree(data);
93 return NULL;
94}
95
96static void free_apic_chip_data(struct apic_chip_data *data)
97{
98 if (data) {
99 free_cpumask_var(data->domain);
100 free_cpumask_var(data->old_domain);
101 kfree(data);
102 }
103}
104
105static int __assign_irq_vector(int irq, struct apic_chip_data *d,
106 const struct cpumask *mask)
107{
108 /*
109 * NOTE! The local APIC isn't very good at handling
110 * multiple interrupts at the same interrupt level.
111 * As the interrupt level is determined by taking the
112 * vector number and shifting that right by 4, we
113 * want to spread these out a bit so that they don't
114 * all fall in the same interrupt level.
115 *
116 * Also, we've got to be careful not to trash gate
117 * 0x80, because int 0x80 is hm, kind of importantish. ;)
118 */
119 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
120 static int current_offset = VECTOR_OFFSET_START % 16;
121 int cpu, vector;
122
123 /*
124 * If there is still a move in progress or the previous move has not
125 * been cleaned up completely, tell the caller to come back later.
126 */
127 if (d->move_in_progress ||
128 cpumask_intersects(d->old_domain, cpu_online_mask))
129 return -EBUSY;
130
131 /* Only try and allocate irqs on cpus that are present */
132 cpumask_clear(d->old_domain);
133 cpumask_clear(searched_cpumask);
134 cpu = cpumask_first_and(mask, cpu_online_mask);
135 while (cpu < nr_cpu_ids) {
136 int new_cpu, offset;
137
138 /* Get the possible target cpus for @mask/@cpu from the apic */
139 apic->vector_allocation_domain(cpu, vector_cpumask, mask);
140
141 /*
142 * Clear the offline cpus from @vector_cpumask for searching
143 * and verify whether the result overlaps with @mask. If true,
144 * then the call to apic->cpu_mask_to_apicid_and() will
145 * succeed as well. If not, no point in trying to find a
146 * vector in this mask.
147 */
148 cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask);
149 if (!cpumask_intersects(vector_searchmask, mask))
150 goto next_cpu;
151
152 if (cpumask_subset(vector_cpumask, d->domain)) {
153 if (cpumask_equal(vector_cpumask, d->domain))
154 goto success;
155 /*
156 * Mark the cpus which are not longer in the mask for
157 * cleanup.
158 */
159 cpumask_andnot(d->old_domain, d->domain, vector_cpumask);
160 vector = d->cfg.vector;
161 goto update;
162 }
163
164 vector = current_vector;
165 offset = current_offset;
166next:
167 vector += 16;
168 if (vector >= first_system_vector) {
169 offset = (offset + 1) % 16;
170 vector = FIRST_EXTERNAL_VECTOR + offset;
171 }
172
173 /* If the search wrapped around, try the next cpu */
174 if (unlikely(current_vector == vector))
175 goto next_cpu;
176
177 if (test_bit(vector, used_vectors))
178 goto next;
179
180 for_each_cpu(new_cpu, vector_searchmask) {
181 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
182 goto next;
183 }
184 /* Found one! */
185 current_vector = vector;
186 current_offset = offset;
187 /* Schedule the old vector for cleanup on all cpus */
188 if (d->cfg.vector)
189 cpumask_copy(d->old_domain, d->domain);
190 for_each_cpu(new_cpu, vector_searchmask)
191 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
192 goto update;
193
194next_cpu:
195 /*
196 * We exclude the current @vector_cpumask from the requested
197 * @mask and try again with the next online cpu in the
198 * result. We cannot modify @mask, so we use @vector_cpumask
199 * as a temporary buffer here as it will be reassigned when
200 * calling apic->vector_allocation_domain() above.
201 */
202 cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask);
203 cpumask_andnot(vector_cpumask, mask, searched_cpumask);
204 cpu = cpumask_first_and(vector_cpumask, cpu_online_mask);
205 continue;
206 }
207 return -ENOSPC;
208
209update:
210 /*
211 * Exclude offline cpus from the cleanup mask and set the
212 * move_in_progress flag when the result is not empty.
213 */
214 cpumask_and(d->old_domain, d->old_domain, cpu_online_mask);
215 d->move_in_progress = !cpumask_empty(d->old_domain);
216 d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0;
217 d->cfg.vector = vector;
218 cpumask_copy(d->domain, vector_cpumask);
219success:
220 /*
221 * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail
222 * as we already established, that mask & d->domain & cpu_online_mask
223 * is not empty.
224 */
225 BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain,
226 &d->cfg.dest_apicid));
227 return 0;
228}
229
230static int assign_irq_vector(int irq, struct apic_chip_data *data,
231 const struct cpumask *mask)
232{
233 int err;
234 unsigned long flags;
235
236 raw_spin_lock_irqsave(&vector_lock, flags);
237 err = __assign_irq_vector(irq, data, mask);
238 raw_spin_unlock_irqrestore(&vector_lock, flags);
239 return err;
240}
241
242static int assign_irq_vector_policy(int irq, int node,
243 struct apic_chip_data *data,
244 struct irq_alloc_info *info)
245{
246 if (info && info->mask)
247 return assign_irq_vector(irq, data, info->mask);
248 if (node != NUMA_NO_NODE &&
249 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
250 return 0;
251 return assign_irq_vector(irq, data, apic->target_cpus());
252}
253
254static void clear_irq_vector(int irq, struct apic_chip_data *data)
255{
256 struct irq_desc *desc;
257 int cpu, vector;
258
259 if (!data->cfg.vector)
260 return;
261
262 vector = data->cfg.vector;
263 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
264 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
265
266 data->cfg.vector = 0;
267 cpumask_clear(data->domain);
268
269 /*
270 * If move is in progress or the old_domain mask is not empty,
271 * i.e. the cleanup IPI has not been processed yet, we need to remove
272 * the old references to desc from all cpus vector tables.
273 */
274 if (!data->move_in_progress && cpumask_empty(data->old_domain))
275 return;
276
277 desc = irq_to_desc(irq);
278 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
279 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
280 vector++) {
281 if (per_cpu(vector_irq, cpu)[vector] != desc)
282 continue;
283 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
284 break;
285 }
286 }
287 data->move_in_progress = 0;
288}
289
290void init_irq_alloc_info(struct irq_alloc_info *info,
291 const struct cpumask *mask)
292{
293 memset(info, 0, sizeof(*info));
294 info->mask = mask;
295}
296
297void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
298{
299 if (src)
300 *dst = *src;
301 else
302 memset(dst, 0, sizeof(*dst));
303}
304
305static void x86_vector_free_irqs(struct irq_domain *domain,
306 unsigned int virq, unsigned int nr_irqs)
307{
308 struct apic_chip_data *apic_data;
309 struct irq_data *irq_data;
310 unsigned long flags;
311 int i;
312
313 for (i = 0; i < nr_irqs; i++) {
314 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
315 if (irq_data && irq_data->chip_data) {
316 raw_spin_lock_irqsave(&vector_lock, flags);
317 clear_irq_vector(virq + i, irq_data->chip_data);
318 apic_data = irq_data->chip_data;
319 irq_domain_reset_irq_data(irq_data);
320 raw_spin_unlock_irqrestore(&vector_lock, flags);
321 free_apic_chip_data(apic_data);
322#ifdef CONFIG_X86_IO_APIC
323 if (virq + i < nr_legacy_irqs())
324 legacy_irq_data[virq + i] = NULL;
325#endif
326 }
327 }
328}
329
330static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
331 unsigned int nr_irqs, void *arg)
332{
333 struct irq_alloc_info *info = arg;
334 struct apic_chip_data *data;
335 struct irq_data *irq_data;
336 int i, err, node;
337
338 if (disable_apic)
339 return -ENXIO;
340
341 /* Currently vector allocator can't guarantee contiguous allocations */
342 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
343 return -ENOSYS;
344
345 for (i = 0; i < nr_irqs; i++) {
346 irq_data = irq_domain_get_irq_data(domain, virq + i);
347 BUG_ON(!irq_data);
348 node = irq_data_get_node(irq_data);
349#ifdef CONFIG_X86_IO_APIC
350 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
351 data = legacy_irq_data[virq + i];
352 else
353#endif
354 data = alloc_apic_chip_data(node);
355 if (!data) {
356 err = -ENOMEM;
357 goto error;
358 }
359
360 irq_data->chip = &lapic_controller;
361 irq_data->chip_data = data;
362 irq_data->hwirq = virq + i;
363 err = assign_irq_vector_policy(virq + i, node, data, info);
364 if (err)
365 goto error;
366 }
367
368 return 0;
369
370error:
371 x86_vector_free_irqs(domain, virq, i + 1);
372 return err;
373}
374
375static const struct irq_domain_ops x86_vector_domain_ops = {
376 .alloc = x86_vector_alloc_irqs,
377 .free = x86_vector_free_irqs,
378};
379
380int __init arch_probe_nr_irqs(void)
381{
382 int nr;
383
384 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
385 nr_irqs = NR_VECTORS * nr_cpu_ids;
386
387 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
388#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
389 /*
390 * for MSI and HT dyn irq
391 */
392 if (gsi_top <= NR_IRQS_LEGACY)
393 nr += 8 * nr_cpu_ids;
394 else
395 nr += gsi_top * 16;
396#endif
397 if (nr < nr_irqs)
398 nr_irqs = nr;
399
400 /*
401 * We don't know if PIC is present at this point so we need to do
402 * probe() to get the right number of legacy IRQs.
403 */
404 return legacy_pic->probe();
405}
406
407#ifdef CONFIG_X86_IO_APIC
408static void init_legacy_irqs(void)
409{
410 int i, node = cpu_to_node(0);
411 struct apic_chip_data *data;
412
413 /*
414 * For legacy IRQ's, start with assigning irq0 to irq15 to
415 * ISA_IRQ_VECTOR(i) for all cpu's.
416 */
417 for (i = 0; i < nr_legacy_irqs(); i++) {
418 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
419 BUG_ON(!data);
420
421 data->cfg.vector = ISA_IRQ_VECTOR(i);
422 cpumask_setall(data->domain);
423 irq_set_chip_data(i, data);
424 }
425}
426#else
427static void init_legacy_irqs(void) { }
428#endif
429
430int __init arch_early_irq_init(void)
431{
432 init_legacy_irqs();
433
434 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
435 NULL);
436 BUG_ON(x86_vector_domain == NULL);
437 irq_set_default_host(x86_vector_domain);
438
439 arch_init_msi_domain(x86_vector_domain);
440 arch_init_htirq_domain(x86_vector_domain);
441
442 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
443 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
444 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
445
446 return arch_early_ioapic_init();
447}
448
449/* Initialize vector_irq on a new cpu */
450static void __setup_vector_irq(int cpu)
451{
452 struct apic_chip_data *data;
453 struct irq_desc *desc;
454 int irq, vector;
455
456 /* Mark the inuse vectors */
457 for_each_irq_desc(irq, desc) {
458 struct irq_data *idata = irq_desc_get_irq_data(desc);
459
460 data = apic_chip_data(idata);
461 if (!data || !cpumask_test_cpu(cpu, data->domain))
462 continue;
463 vector = data->cfg.vector;
464 per_cpu(vector_irq, cpu)[vector] = desc;
465 }
466 /* Mark the free vectors */
467 for (vector = 0; vector < NR_VECTORS; ++vector) {
468 desc = per_cpu(vector_irq, cpu)[vector];
469 if (IS_ERR_OR_NULL(desc))
470 continue;
471
472 data = apic_chip_data(irq_desc_get_irq_data(desc));
473 if (!cpumask_test_cpu(cpu, data->domain))
474 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
475 }
476}
477
478/*
479 * Setup the vector to irq mappings. Must be called with vector_lock held.
480 */
481void setup_vector_irq(int cpu)
482{
483 int irq;
484
485 lockdep_assert_held(&vector_lock);
486 /*
487 * On most of the platforms, legacy PIC delivers the interrupts on the
488 * boot cpu. But there are certain platforms where PIC interrupts are
489 * delivered to multiple cpu's. If the legacy IRQ is handled by the
490 * legacy PIC, for the new cpu that is coming online, setup the static
491 * legacy vector to irq mapping:
492 */
493 for (irq = 0; irq < nr_legacy_irqs(); irq++)
494 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
495
496 __setup_vector_irq(cpu);
497}
498
499static int apic_retrigger_irq(struct irq_data *irq_data)
500{
501 struct apic_chip_data *data = apic_chip_data(irq_data);
502 unsigned long flags;
503 int cpu;
504
505 raw_spin_lock_irqsave(&vector_lock, flags);
506 cpu = cpumask_first_and(data->domain, cpu_online_mask);
507 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
508 raw_spin_unlock_irqrestore(&vector_lock, flags);
509
510 return 1;
511}
512
513void apic_ack_edge(struct irq_data *data)
514{
515 irq_complete_move(irqd_cfg(data));
516 irq_move_irq(data);
517 ack_APIC_irq();
518}
519
520static int apic_set_affinity(struct irq_data *irq_data,
521 const struct cpumask *dest, bool force)
522{
523 struct apic_chip_data *data = irq_data->chip_data;
524 int err, irq = irq_data->irq;
525
526 if (!IS_ENABLED(CONFIG_SMP))
527 return -EPERM;
528
529 if (!cpumask_intersects(dest, cpu_online_mask))
530 return -EINVAL;
531
532 err = assign_irq_vector(irq, data, dest);
533 return err ? err : IRQ_SET_MASK_OK;
534}
535
536static struct irq_chip lapic_controller = {
537 .irq_ack = apic_ack_edge,
538 .irq_set_affinity = apic_set_affinity,
539 .irq_retrigger = apic_retrigger_irq,
540};
541
542#ifdef CONFIG_SMP
543static void __send_cleanup_vector(struct apic_chip_data *data)
544{
545 raw_spin_lock(&vector_lock);
546 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
547 data->move_in_progress = 0;
548 if (!cpumask_empty(data->old_domain))
549 apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR);
550 raw_spin_unlock(&vector_lock);
551}
552
553void send_cleanup_vector(struct irq_cfg *cfg)
554{
555 struct apic_chip_data *data;
556
557 data = container_of(cfg, struct apic_chip_data, cfg);
558 if (data->move_in_progress)
559 __send_cleanup_vector(data);
560}
561
562asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
563{
564 unsigned vector, me;
565
566 entering_ack_irq();
567
568 /* Prevent vectors vanishing under us */
569 raw_spin_lock(&vector_lock);
570
571 me = smp_processor_id();
572 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
573 struct apic_chip_data *data;
574 struct irq_desc *desc;
575 unsigned int irr;
576
577 retry:
578 desc = __this_cpu_read(vector_irq[vector]);
579 if (IS_ERR_OR_NULL(desc))
580 continue;
581
582 if (!raw_spin_trylock(&desc->lock)) {
583 raw_spin_unlock(&vector_lock);
584 cpu_relax();
585 raw_spin_lock(&vector_lock);
586 goto retry;
587 }
588
589 data = apic_chip_data(irq_desc_get_irq_data(desc));
590 if (!data)
591 goto unlock;
592
593 /*
594 * Nothing to cleanup if irq migration is in progress
595 * or this cpu is not set in the cleanup mask.
596 */
597 if (data->move_in_progress ||
598 !cpumask_test_cpu(me, data->old_domain))
599 goto unlock;
600
601 /*
602 * We have two cases to handle here:
603 * 1) vector is unchanged but the target mask got reduced
604 * 2) vector and the target mask has changed
605 *
606 * #1 is obvious, but in #2 we have two vectors with the same
607 * irq descriptor: the old and the new vector. So we need to
608 * make sure that we only cleanup the old vector. The new
609 * vector has the current @vector number in the config and
610 * this cpu is part of the target mask. We better leave that
611 * one alone.
612 */
613 if (vector == data->cfg.vector &&
614 cpumask_test_cpu(me, data->domain))
615 goto unlock;
616
617 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
618 /*
619 * Check if the vector that needs to be cleanedup is
620 * registered at the cpu's IRR. If so, then this is not
621 * the best time to clean it up. Lets clean it up in the
622 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
623 * to myself.
624 */
625 if (irr & (1 << (vector % 32))) {
626 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
627 goto unlock;
628 }
629 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
630 cpumask_clear_cpu(me, data->old_domain);
631unlock:
632 raw_spin_unlock(&desc->lock);
633 }
634
635 raw_spin_unlock(&vector_lock);
636
637 exiting_irq();
638}
639
640static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
641{
642 unsigned me;
643 struct apic_chip_data *data;
644
645 data = container_of(cfg, struct apic_chip_data, cfg);
646 if (likely(!data->move_in_progress))
647 return;
648
649 me = smp_processor_id();
650 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
651 __send_cleanup_vector(data);
652}
653
654void irq_complete_move(struct irq_cfg *cfg)
655{
656 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
657}
658
659/*
660 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
661 */
662void irq_force_complete_move(struct irq_desc *desc)
663{
664 struct irq_data *irqdata;
665 struct apic_chip_data *data;
666 struct irq_cfg *cfg;
667 unsigned int cpu;
668
669 /*
670 * The function is called for all descriptors regardless of which
671 * irqdomain they belong to. For example if an IRQ is provided by
672 * an irq_chip as part of a GPIO driver, the chip data for that
673 * descriptor is specific to the irq_chip in question.
674 *
675 * Check first that the chip_data is what we expect
676 * (apic_chip_data) before touching it any further.
677 */
678 irqdata = irq_domain_get_irq_data(x86_vector_domain,
679 irq_desc_get_irq(desc));
680 if (!irqdata)
681 return;
682
683 data = apic_chip_data(irqdata);
684 cfg = data ? &data->cfg : NULL;
685
686 if (!cfg)
687 return;
688
689 /*
690 * This is tricky. If the cleanup of @data->old_domain has not been
691 * done yet, then the following setaffinity call will fail with
692 * -EBUSY. This can leave the interrupt in a stale state.
693 *
694 * All CPUs are stuck in stop machine with interrupts disabled so
695 * calling __irq_complete_move() would be completely pointless.
696 */
697 raw_spin_lock(&vector_lock);
698 /*
699 * Clean out all offline cpus (including the outgoing one) from the
700 * old_domain mask.
701 */
702 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
703
704 /*
705 * If move_in_progress is cleared and the old_domain mask is empty,
706 * then there is nothing to cleanup. fixup_irqs() will take care of
707 * the stale vectors on the outgoing cpu.
708 */
709 if (!data->move_in_progress && cpumask_empty(data->old_domain)) {
710 raw_spin_unlock(&vector_lock);
711 return;
712 }
713
714 /*
715 * 1) The interrupt is in move_in_progress state. That means that we
716 * have not seen an interrupt since the io_apic was reprogrammed to
717 * the new vector.
718 *
719 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
720 * have not been processed yet.
721 */
722 if (data->move_in_progress) {
723 /*
724 * In theory there is a race:
725 *
726 * set_ioapic(new_vector) <-- Interrupt is raised before update
727 * is effective, i.e. it's raised on
728 * the old vector.
729 *
730 * So if the target cpu cannot handle that interrupt before
731 * the old vector is cleaned up, we get a spurious interrupt
732 * and in the worst case the ioapic irq line becomes stale.
733 *
734 * But in case of cpu hotplug this should be a non issue
735 * because if the affinity update happens right before all
736 * cpus rendevouz in stop machine, there is no way that the
737 * interrupt can be blocked on the target cpu because all cpus
738 * loops first with interrupts enabled in stop machine, so the
739 * old vector is not yet cleaned up when the interrupt fires.
740 *
741 * So the only way to run into this issue is if the delivery
742 * of the interrupt on the apic/system bus would be delayed
743 * beyond the point where the target cpu disables interrupts
744 * in stop machine. I doubt that it can happen, but at least
745 * there is a theroretical chance. Virtualization might be
746 * able to expose this, but AFAICT the IOAPIC emulation is not
747 * as stupid as the real hardware.
748 *
749 * Anyway, there is nothing we can do about that at this point
750 * w/o refactoring the whole fixup_irq() business completely.
751 * We print at least the irq number and the old vector number,
752 * so we have the necessary information when a problem in that
753 * area arises.
754 */
755 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
756 irqdata->irq, cfg->old_vector);
757 }
758 /*
759 * If old_domain is not empty, then other cpus still have the irq
760 * descriptor set in their vector array. Clean it up.
761 */
762 for_each_cpu(cpu, data->old_domain)
763 per_cpu(vector_irq, cpu)[cfg->old_vector] = VECTOR_UNUSED;
764
765 /* Cleanup the left overs of the (half finished) move */
766 cpumask_clear(data->old_domain);
767 data->move_in_progress = 0;
768 raw_spin_unlock(&vector_lock);
769}
770#endif
771
772static void __init print_APIC_field(int base)
773{
774 int i;
775
776 printk(KERN_DEBUG);
777
778 for (i = 0; i < 8; i++)
779 pr_cont("%08x", apic_read(base + i*0x10));
780
781 pr_cont("\n");
782}
783
784static void __init print_local_APIC(void *dummy)
785{
786 unsigned int i, v, ver, maxlvt;
787 u64 icr;
788
789 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
790 smp_processor_id(), hard_smp_processor_id());
791 v = apic_read(APIC_ID);
792 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
793 v = apic_read(APIC_LVR);
794 pr_info("... APIC VERSION: %08x\n", v);
795 ver = GET_APIC_VERSION(v);
796 maxlvt = lapic_get_maxlvt();
797
798 v = apic_read(APIC_TASKPRI);
799 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
800
801 /* !82489DX */
802 if (APIC_INTEGRATED(ver)) {
803 if (!APIC_XAPIC(ver)) {
804 v = apic_read(APIC_ARBPRI);
805 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
806 v, v & APIC_ARBPRI_MASK);
807 }
808 v = apic_read(APIC_PROCPRI);
809 pr_debug("... APIC PROCPRI: %08x\n", v);
810 }
811
812 /*
813 * Remote read supported only in the 82489DX and local APIC for
814 * Pentium processors.
815 */
816 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
817 v = apic_read(APIC_RRR);
818 pr_debug("... APIC RRR: %08x\n", v);
819 }
820
821 v = apic_read(APIC_LDR);
822 pr_debug("... APIC LDR: %08x\n", v);
823 if (!x2apic_enabled()) {
824 v = apic_read(APIC_DFR);
825 pr_debug("... APIC DFR: %08x\n", v);
826 }
827 v = apic_read(APIC_SPIV);
828 pr_debug("... APIC SPIV: %08x\n", v);
829
830 pr_debug("... APIC ISR field:\n");
831 print_APIC_field(APIC_ISR);
832 pr_debug("... APIC TMR field:\n");
833 print_APIC_field(APIC_TMR);
834 pr_debug("... APIC IRR field:\n");
835 print_APIC_field(APIC_IRR);
836
837 /* !82489DX */
838 if (APIC_INTEGRATED(ver)) {
839 /* Due to the Pentium erratum 3AP. */
840 if (maxlvt > 3)
841 apic_write(APIC_ESR, 0);
842
843 v = apic_read(APIC_ESR);
844 pr_debug("... APIC ESR: %08x\n", v);
845 }
846
847 icr = apic_icr_read();
848 pr_debug("... APIC ICR: %08x\n", (u32)icr);
849 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
850
851 v = apic_read(APIC_LVTT);
852 pr_debug("... APIC LVTT: %08x\n", v);
853
854 if (maxlvt > 3) {
855 /* PC is LVT#4. */
856 v = apic_read(APIC_LVTPC);
857 pr_debug("... APIC LVTPC: %08x\n", v);
858 }
859 v = apic_read(APIC_LVT0);
860 pr_debug("... APIC LVT0: %08x\n", v);
861 v = apic_read(APIC_LVT1);
862 pr_debug("... APIC LVT1: %08x\n", v);
863
864 if (maxlvt > 2) {
865 /* ERR is LVT#3. */
866 v = apic_read(APIC_LVTERR);
867 pr_debug("... APIC LVTERR: %08x\n", v);
868 }
869
870 v = apic_read(APIC_TMICT);
871 pr_debug("... APIC TMICT: %08x\n", v);
872 v = apic_read(APIC_TMCCT);
873 pr_debug("... APIC TMCCT: %08x\n", v);
874 v = apic_read(APIC_TDCR);
875 pr_debug("... APIC TDCR: %08x\n", v);
876
877 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
878 v = apic_read(APIC_EFEAT);
879 maxlvt = (v >> 16) & 0xff;
880 pr_debug("... APIC EFEAT: %08x\n", v);
881 v = apic_read(APIC_ECTRL);
882 pr_debug("... APIC ECTRL: %08x\n", v);
883 for (i = 0; i < maxlvt; i++) {
884 v = apic_read(APIC_EILVTn(i));
885 pr_debug("... APIC EILVT%d: %08x\n", i, v);
886 }
887 }
888 pr_cont("\n");
889}
890
891static void __init print_local_APICs(int maxcpu)
892{
893 int cpu;
894
895 if (!maxcpu)
896 return;
897
898 preempt_disable();
899 for_each_online_cpu(cpu) {
900 if (cpu >= maxcpu)
901 break;
902 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
903 }
904 preempt_enable();
905}
906
907static void __init print_PIC(void)
908{
909 unsigned int v;
910 unsigned long flags;
911
912 if (!nr_legacy_irqs())
913 return;
914
915 pr_debug("\nprinting PIC contents\n");
916
917 raw_spin_lock_irqsave(&i8259A_lock, flags);
918
919 v = inb(0xa1) << 8 | inb(0x21);
920 pr_debug("... PIC IMR: %04x\n", v);
921
922 v = inb(0xa0) << 8 | inb(0x20);
923 pr_debug("... PIC IRR: %04x\n", v);
924
925 outb(0x0b, 0xa0);
926 outb(0x0b, 0x20);
927 v = inb(0xa0) << 8 | inb(0x20);
928 outb(0x0a, 0xa0);
929 outb(0x0a, 0x20);
930
931 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
932
933 pr_debug("... PIC ISR: %04x\n", v);
934
935 v = inb(0x4d1) << 8 | inb(0x4d0);
936 pr_debug("... PIC ELCR: %04x\n", v);
937}
938
939static int show_lapic __initdata = 1;
940static __init int setup_show_lapic(char *arg)
941{
942 int num = -1;
943
944 if (strcmp(arg, "all") == 0) {
945 show_lapic = CONFIG_NR_CPUS;
946 } else {
947 get_option(&arg, &num);
948 if (num >= 0)
949 show_lapic = num;
950 }
951
952 return 1;
953}
954__setup("show_lapic=", setup_show_lapic);
955
956static int __init print_ICs(void)
957{
958 if (apic_verbosity == APIC_QUIET)
959 return 0;
960
961 print_PIC();
962
963 /* don't print out if apic is not there */
964 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
965 return 0;
966
967 print_local_APICs(show_lapic);
968 print_IO_APICs();
969
970 return 0;
971}
972
973late_initcall(print_ICs);