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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Local APIC handling, local APIC timers
4 *
5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 *
7 * Fixes
8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
9 * thanks to Eric Gilmore
10 * and Rolf G. Tews
11 * for testing these extensively.
12 * Maciej W. Rozycki : Various updates and fixes.
13 * Mikael Pettersson : Power Management for UP-APIC.
14 * Pavel Machek and
15 * Mikael Pettersson : PM converted to driver model.
16 */
17
18#include <linux/perf_event.h>
19#include <linux/kernel_stat.h>
20#include <linux/mc146818rtc.h>
21#include <linux/acpi_pmtmr.h>
22#include <linux/clockchips.h>
23#include <linux/interrupt.h>
24#include <linux/memblock.h>
25#include <linux/ftrace.h>
26#include <linux/ioport.h>
27#include <linux/export.h>
28#include <linux/syscore_ops.h>
29#include <linux/delay.h>
30#include <linux/timex.h>
31#include <linux/i8253.h>
32#include <linux/dmar.h>
33#include <linux/init.h>
34#include <linux/cpu.h>
35#include <linux/dmi.h>
36#include <linux/smp.h>
37#include <linux/mm.h>
38
39#include <asm/trace/irq_vectors.h>
40#include <asm/irq_remapping.h>
41#include <asm/perf_event.h>
42#include <asm/x86_init.h>
43#include <asm/pgalloc.h>
44#include <linux/atomic.h>
45#include <asm/mpspec.h>
46#include <asm/i8259.h>
47#include <asm/proto.h>
48#include <asm/traps.h>
49#include <asm/apic.h>
50#include <asm/io_apic.h>
51#include <asm/desc.h>
52#include <asm/hpet.h>
53#include <asm/mtrr.h>
54#include <asm/time.h>
55#include <asm/smp.h>
56#include <asm/mce.h>
57#include <asm/tsc.h>
58#include <asm/hypervisor.h>
59#include <asm/cpu_device_id.h>
60#include <asm/intel-family.h>
61#include <asm/irq_regs.h>
62
63unsigned int num_processors;
64
65unsigned disabled_cpus;
66
67/* Processor that is doing the boot up */
68unsigned int boot_cpu_physical_apicid __ro_after_init = -1U;
69EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
70
71u8 boot_cpu_apic_version __ro_after_init;
72
73/*
74 * The highest APIC ID seen during enumeration.
75 */
76static unsigned int max_physical_apicid;
77
78/*
79 * Bitmask of physically existing CPUs:
80 */
81physid_mask_t phys_cpu_present_map;
82
83/*
84 * Processor to be disabled specified by kernel parameter
85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
86 * avoid undefined behaviour caused by sending INIT from AP to BSP.
87 */
88static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID;
89
90/*
91 * This variable controls which CPUs receive external NMIs. By default,
92 * external NMIs are delivered only to the BSP.
93 */
94static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP;
95
96/*
97 * Map cpu index to physical APIC ID
98 */
99DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
100DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
101DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
102EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
103EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
104EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
105
106#ifdef CONFIG_X86_32
107
108/*
109 * On x86_32, the mapping between cpu and logical apicid may vary
110 * depending on apic in use. The following early percpu variable is
111 * used for the mapping. This is where the behaviors of x86_64 and 32
112 * actually diverge. Let's keep it ugly for now.
113 */
114DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
115
116/* Local APIC was disabled by the BIOS and enabled by the kernel */
117static int enabled_via_apicbase __ro_after_init;
118
119/*
120 * Handle interrupt mode configuration register (IMCR).
121 * This register controls whether the interrupt signals
122 * that reach the BSP come from the master PIC or from the
123 * local APIC. Before entering Symmetric I/O Mode, either
124 * the BIOS or the operating system must switch out of
125 * PIC Mode by changing the IMCR.
126 */
127static inline void imcr_pic_to_apic(void)
128{
129 /* select IMCR register */
130 outb(0x70, 0x22);
131 /* NMI and 8259 INTR go through APIC */
132 outb(0x01, 0x23);
133}
134
135static inline void imcr_apic_to_pic(void)
136{
137 /* select IMCR register */
138 outb(0x70, 0x22);
139 /* NMI and 8259 INTR go directly to BSP */
140 outb(0x00, 0x23);
141}
142#endif
143
144/*
145 * Knob to control our willingness to enable the local APIC.
146 *
147 * +1=force-enable
148 */
149static int force_enable_local_apic __initdata;
150
151/*
152 * APIC command line parameters
153 */
154static int __init parse_lapic(char *arg)
155{
156 if (IS_ENABLED(CONFIG_X86_32) && !arg)
157 force_enable_local_apic = 1;
158 else if (arg && !strncmp(arg, "notscdeadline", 13))
159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
160 return 0;
161}
162early_param("lapic", parse_lapic);
163
164#ifdef CONFIG_X86_64
165static int apic_calibrate_pmtmr __initdata;
166static __init int setup_apicpmtimer(char *s)
167{
168 apic_calibrate_pmtmr = 1;
169 notsc_setup(NULL);
170 return 0;
171}
172__setup("apicpmtimer", setup_apicpmtimer);
173#endif
174
175unsigned long mp_lapic_addr __ro_after_init;
176int disable_apic __ro_after_init;
177/* Disable local APIC timer from the kernel commandline or via dmi quirk */
178static int disable_apic_timer __initdata;
179/* Local APIC timer works in C2 */
180int local_apic_timer_c2_ok __ro_after_init;
181EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
182
183/*
184 * Debug level, exported for io_apic.c
185 */
186int apic_verbosity __ro_after_init;
187
188int pic_mode __ro_after_init;
189
190/* Have we found an MP table */
191int smp_found_config __ro_after_init;
192
193static struct resource lapic_resource = {
194 .name = "Local APIC",
195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
196};
197
198unsigned int lapic_timer_period = 0;
199
200static void apic_pm_activate(void);
201
202static unsigned long apic_phys __ro_after_init;
203
204/*
205 * Get the LAPIC version
206 */
207static inline int lapic_get_version(void)
208{
209 return GET_APIC_VERSION(apic_read(APIC_LVR));
210}
211
212/*
213 * Check, if the APIC is integrated or a separate chip
214 */
215static inline int lapic_is_integrated(void)
216{
217 return APIC_INTEGRATED(lapic_get_version());
218}
219
220/*
221 * Check, whether this is a modern or a first generation APIC
222 */
223static int modern_apic(void)
224{
225 /* AMD systems use old APIC versions, so check the CPU */
226 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
227 boot_cpu_data.x86 >= 0xf)
228 return 1;
229
230 /* Hygon systems use modern APIC */
231 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
232 return 1;
233
234 return lapic_get_version() >= 0x14;
235}
236
237/*
238 * right after this call apic become NOOP driven
239 * so apic->write/read doesn't do anything
240 */
241static void __init apic_disable(void)
242{
243 pr_info("APIC: switched to apic NOOP\n");
244 apic = &apic_noop;
245}
246
247void native_apic_wait_icr_idle(void)
248{
249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
250 cpu_relax();
251}
252
253u32 native_safe_apic_wait_icr_idle(void)
254{
255 u32 send_status;
256 int timeout;
257
258 timeout = 0;
259 do {
260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
261 if (!send_status)
262 break;
263 inc_irq_stat(icr_read_retry_count);
264 udelay(100);
265 } while (timeout++ < 1000);
266
267 return send_status;
268}
269
270void native_apic_icr_write(u32 low, u32 id)
271{
272 unsigned long flags;
273
274 local_irq_save(flags);
275 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
276 apic_write(APIC_ICR, low);
277 local_irq_restore(flags);
278}
279
280u64 native_apic_icr_read(void)
281{
282 u32 icr1, icr2;
283
284 icr2 = apic_read(APIC_ICR2);
285 icr1 = apic_read(APIC_ICR);
286
287 return icr1 | ((u64)icr2 << 32);
288}
289
290#ifdef CONFIG_X86_32
291/**
292 * get_physical_broadcast - Get number of physical broadcast IDs
293 */
294int get_physical_broadcast(void)
295{
296 return modern_apic() ? 0xff : 0xf;
297}
298#endif
299
300/**
301 * lapic_get_maxlvt - get the maximum number of local vector table entries
302 */
303int lapic_get_maxlvt(void)
304{
305 /*
306 * - we always have APIC integrated on 64bit mode
307 * - 82489DXs do not report # of LVT entries
308 */
309 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
310}
311
312/*
313 * Local APIC timer
314 */
315
316/* Clock divisor */
317#define APIC_DIVISOR 16
318#define TSC_DIVISOR 8
319
320/*
321 * This function sets up the local APIC timer, with a timeout of
322 * 'clocks' APIC bus clock. During calibration we actually call
323 * this function twice on the boot CPU, once with a bogus timeout
324 * value, second time for real. The other (noncalibrating) CPUs
325 * call this function only once, with the real, calibrated value.
326 *
327 * We do reads before writes even if unnecessary, to get around the
328 * P5 APIC double write bug.
329 */
330static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
331{
332 unsigned int lvtt_value, tmp_value;
333
334 lvtt_value = LOCAL_TIMER_VECTOR;
335 if (!oneshot)
336 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
337 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
338 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
339
340 if (!lapic_is_integrated())
341 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
342
343 if (!irqen)
344 lvtt_value |= APIC_LVT_MASKED;
345
346 apic_write(APIC_LVTT, lvtt_value);
347
348 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
349 /*
350 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
351 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
352 * According to Intel, MFENCE can do the serialization here.
353 */
354 asm volatile("mfence" : : : "memory");
355
356 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
357 return;
358 }
359
360 /*
361 * Divide PICLK by 16
362 */
363 tmp_value = apic_read(APIC_TDCR);
364 apic_write(APIC_TDCR,
365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
366 APIC_TDR_DIV_16);
367
368 if (!oneshot)
369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
370}
371
372/*
373 * Setup extended LVT, AMD specific
374 *
375 * Software should use the LVT offsets the BIOS provides. The offsets
376 * are determined by the subsystems using it like those for MCE
377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
378 * are supported. Beginning with family 10h at least 4 offsets are
379 * available.
380 *
381 * Since the offsets must be consistent for all cores, we keep track
382 * of the LVT offsets in software and reserve the offset for the same
383 * vector also to be used on other cores. An offset is freed by
384 * setting the entry to APIC_EILVT_MASKED.
385 *
386 * If the BIOS is right, there should be no conflicts. Otherwise a
387 * "[Firmware Bug]: ..." error message is generated. However, if
388 * software does not properly determines the offsets, it is not
389 * necessarily a BIOS bug.
390 */
391
392static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
393
394static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
395{
396 return (old & APIC_EILVT_MASKED)
397 || (new == APIC_EILVT_MASKED)
398 || ((new & ~APIC_EILVT_MASKED) == old);
399}
400
401static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
402{
403 unsigned int rsvd, vector;
404
405 if (offset >= APIC_EILVT_NR_MAX)
406 return ~0;
407
408 rsvd = atomic_read(&eilvt_offsets[offset]);
409 do {
410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
411 if (vector && !eilvt_entry_is_changeable(vector, new))
412 /* may not change if vectors are different */
413 return rsvd;
414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
415 } while (rsvd != new);
416
417 rsvd &= ~APIC_EILVT_MASKED;
418 if (rsvd && rsvd != vector)
419 pr_info("LVT offset %d assigned for vector 0x%02x\n",
420 offset, rsvd);
421
422 return new;
423}
424
425/*
426 * If mask=1, the LVT entry does not generate interrupts while mask=0
427 * enables the vector. See also the BKDGs. Must be called with
428 * preemption disabled.
429 */
430
431int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
432{
433 unsigned long reg = APIC_EILVTn(offset);
434 unsigned int new, old, reserved;
435
436 new = (mask << 16) | (msg_type << 8) | vector;
437 old = apic_read(reg);
438 reserved = reserve_eilvt_offset(offset, new);
439
440 if (reserved != new) {
441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442 "vector 0x%x, but the register is already in use for "
443 "vector 0x%x on another cpu\n",
444 smp_processor_id(), reg, offset, new, reserved);
445 return -EINVAL;
446 }
447
448 if (!eilvt_entry_is_changeable(old, new)) {
449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
450 "vector 0x%x, but the register is already in use for "
451 "vector 0x%x on this cpu\n",
452 smp_processor_id(), reg, offset, new, old);
453 return -EBUSY;
454 }
455
456 apic_write(reg, new);
457
458 return 0;
459}
460EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
461
462/*
463 * Program the next event, relative to now
464 */
465static int lapic_next_event(unsigned long delta,
466 struct clock_event_device *evt)
467{
468 apic_write(APIC_TMICT, delta);
469 return 0;
470}
471
472static int lapic_next_deadline(unsigned long delta,
473 struct clock_event_device *evt)
474{
475 u64 tsc;
476
477 tsc = rdtsc();
478 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
479 return 0;
480}
481
482static int lapic_timer_shutdown(struct clock_event_device *evt)
483{
484 unsigned int v;
485
486 /* Lapic used as dummy for broadcast ? */
487 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
488 return 0;
489
490 v = apic_read(APIC_LVTT);
491 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
492 apic_write(APIC_LVTT, v);
493 apic_write(APIC_TMICT, 0);
494 return 0;
495}
496
497static inline int
498lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
499{
500 /* Lapic used as dummy for broadcast ? */
501 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
502 return 0;
503
504 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1);
505 return 0;
506}
507
508static int lapic_timer_set_periodic(struct clock_event_device *evt)
509{
510 return lapic_timer_set_periodic_oneshot(evt, false);
511}
512
513static int lapic_timer_set_oneshot(struct clock_event_device *evt)
514{
515 return lapic_timer_set_periodic_oneshot(evt, true);
516}
517
518/*
519 * Local APIC timer broadcast function
520 */
521static void lapic_timer_broadcast(const struct cpumask *mask)
522{
523#ifdef CONFIG_SMP
524 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
525#endif
526}
527
528
529/*
530 * The local apic timer can be used for any function which is CPU local.
531 */
532static struct clock_event_device lapic_clockevent = {
533 .name = "lapic",
534 .features = CLOCK_EVT_FEAT_PERIODIC |
535 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
536 | CLOCK_EVT_FEAT_DUMMY,
537 .shift = 32,
538 .set_state_shutdown = lapic_timer_shutdown,
539 .set_state_periodic = lapic_timer_set_periodic,
540 .set_state_oneshot = lapic_timer_set_oneshot,
541 .set_state_oneshot_stopped = lapic_timer_shutdown,
542 .set_next_event = lapic_next_event,
543 .broadcast = lapic_timer_broadcast,
544 .rating = 100,
545 .irq = -1,
546};
547static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
548
549#define DEADLINE_MODEL_MATCH_FUNC(model, func) \
550 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
551
552#define DEADLINE_MODEL_MATCH_REV(model, rev) \
553 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
554
555static u32 hsx_deadline_rev(void)
556{
557 switch (boot_cpu_data.x86_stepping) {
558 case 0x02: return 0x3a; /* EP */
559 case 0x04: return 0x0f; /* EX */
560 }
561
562 return ~0U;
563}
564
565static u32 bdx_deadline_rev(void)
566{
567 switch (boot_cpu_data.x86_stepping) {
568 case 0x02: return 0x00000011;
569 case 0x03: return 0x0700000e;
570 case 0x04: return 0x0f00000c;
571 case 0x05: return 0x0e000003;
572 }
573
574 return ~0U;
575}
576
577static u32 skx_deadline_rev(void)
578{
579 switch (boot_cpu_data.x86_stepping) {
580 case 0x03: return 0x01000136;
581 case 0x04: return 0x02000014;
582 }
583
584 if (boot_cpu_data.x86_stepping > 4)
585 return 0;
586
587 return ~0U;
588}
589
590static const struct x86_cpu_id deadline_match[] = {
591 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_D, bdx_deadline_rev),
594 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
595
596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL, 0x22),
597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_L, 0x20),
598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_G, 0x17),
599
600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL, 0x25),
601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_G, 0x17),
602
603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_L, 0xb2),
604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE, 0xb2),
605
606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_L, 0x52),
607 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE, 0x52),
608
609 {},
610};
611
612static void apic_check_deadline_errata(void)
613{
614 const struct x86_cpu_id *m;
615 u32 rev;
616
617 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) ||
618 boot_cpu_has(X86_FEATURE_HYPERVISOR))
619 return;
620
621 m = x86_match_cpu(deadline_match);
622 if (!m)
623 return;
624
625 /*
626 * Function pointers will have the MSB set due to address layout,
627 * immediate revisions will not.
628 */
629 if ((long)m->driver_data < 0)
630 rev = ((u32 (*)(void))(m->driver_data))();
631 else
632 rev = (u32)m->driver_data;
633
634 if (boot_cpu_data.microcode >= rev)
635 return;
636
637 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
638 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
639 "please update microcode to version: 0x%x (or later)\n", rev);
640}
641
642/*
643 * Setup the local APIC timer for this CPU. Copy the initialized values
644 * of the boot CPU and register the clock event in the framework.
645 */
646static void setup_APIC_timer(void)
647{
648 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
649
650 if (this_cpu_has(X86_FEATURE_ARAT)) {
651 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
652 /* Make LAPIC timer preferrable over percpu HPET */
653 lapic_clockevent.rating = 150;
654 }
655
656 memcpy(levt, &lapic_clockevent, sizeof(*levt));
657 levt->cpumask = cpumask_of(smp_processor_id());
658
659 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
660 levt->name = "lapic-deadline";
661 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
662 CLOCK_EVT_FEAT_DUMMY);
663 levt->set_next_event = lapic_next_deadline;
664 clockevents_config_and_register(levt,
665 tsc_khz * (1000 / TSC_DIVISOR),
666 0xF, ~0UL);
667 } else
668 clockevents_register_device(levt);
669}
670
671/*
672 * Install the updated TSC frequency from recalibration at the TSC
673 * deadline clockevent devices.
674 */
675static void __lapic_update_tsc_freq(void *info)
676{
677 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
678
679 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
680 return;
681
682 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
683}
684
685void lapic_update_tsc_freq(void)
686{
687 /*
688 * The clockevent device's ->mult and ->shift can both be
689 * changed. In order to avoid races, schedule the frequency
690 * update code on each CPU.
691 */
692 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
693}
694
695/*
696 * In this functions we calibrate APIC bus clocks to the external timer.
697 *
698 * We want to do the calibration only once since we want to have local timer
699 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
700 * frequency.
701 *
702 * This was previously done by reading the PIT/HPET and waiting for a wrap
703 * around to find out, that a tick has elapsed. I have a box, where the PIT
704 * readout is broken, so it never gets out of the wait loop again. This was
705 * also reported by others.
706 *
707 * Monitoring the jiffies value is inaccurate and the clockevents
708 * infrastructure allows us to do a simple substitution of the interrupt
709 * handler.
710 *
711 * The calibration routine also uses the pm_timer when possible, as the PIT
712 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
713 * back to normal later in the boot process).
714 */
715
716#define LAPIC_CAL_LOOPS (HZ/10)
717
718static __initdata int lapic_cal_loops = -1;
719static __initdata long lapic_cal_t1, lapic_cal_t2;
720static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
721static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
722static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
723
724/*
725 * Temporary interrupt handler and polled calibration function.
726 */
727static void __init lapic_cal_handler(struct clock_event_device *dev)
728{
729 unsigned long long tsc = 0;
730 long tapic = apic_read(APIC_TMCCT);
731 unsigned long pm = acpi_pm_read_early();
732
733 if (boot_cpu_has(X86_FEATURE_TSC))
734 tsc = rdtsc();
735
736 switch (lapic_cal_loops++) {
737 case 0:
738 lapic_cal_t1 = tapic;
739 lapic_cal_tsc1 = tsc;
740 lapic_cal_pm1 = pm;
741 lapic_cal_j1 = jiffies;
742 break;
743
744 case LAPIC_CAL_LOOPS:
745 lapic_cal_t2 = tapic;
746 lapic_cal_tsc2 = tsc;
747 if (pm < lapic_cal_pm1)
748 pm += ACPI_PM_OVRRUN;
749 lapic_cal_pm2 = pm;
750 lapic_cal_j2 = jiffies;
751 break;
752 }
753}
754
755static int __init
756calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
757{
758 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
759 const long pm_thresh = pm_100ms / 100;
760 unsigned long mult;
761 u64 res;
762
763#ifndef CONFIG_X86_PM_TIMER
764 return -1;
765#endif
766
767 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
768
769 /* Check, if the PM timer is available */
770 if (!deltapm)
771 return -1;
772
773 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
774
775 if (deltapm > (pm_100ms - pm_thresh) &&
776 deltapm < (pm_100ms + pm_thresh)) {
777 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
778 return 0;
779 }
780
781 res = (((u64)deltapm) * mult) >> 22;
782 do_div(res, 1000000);
783 pr_warning("APIC calibration not consistent "
784 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
785
786 /* Correct the lapic counter value */
787 res = (((u64)(*delta)) * pm_100ms);
788 do_div(res, deltapm);
789 pr_info("APIC delta adjusted to PM-Timer: "
790 "%lu (%ld)\n", (unsigned long)res, *delta);
791 *delta = (long)res;
792
793 /* Correct the tsc counter value */
794 if (boot_cpu_has(X86_FEATURE_TSC)) {
795 res = (((u64)(*deltatsc)) * pm_100ms);
796 do_div(res, deltapm);
797 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
798 "PM-Timer: %lu (%ld)\n",
799 (unsigned long)res, *deltatsc);
800 *deltatsc = (long)res;
801 }
802
803 return 0;
804}
805
806static int __init lapic_init_clockevent(void)
807{
808 if (!lapic_timer_period)
809 return -1;
810
811 /* Calculate the scaled math multiplication factor */
812 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR,
813 TICK_NSEC, lapic_clockevent.shift);
814 lapic_clockevent.max_delta_ns =
815 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
816 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
817 lapic_clockevent.min_delta_ns =
818 clockevent_delta2ns(0xF, &lapic_clockevent);
819 lapic_clockevent.min_delta_ticks = 0xF;
820
821 return 0;
822}
823
824bool __init apic_needs_pit(void)
825{
826 /*
827 * If the frequencies are not known, PIT is required for both TSC
828 * and apic timer calibration.
829 */
830 if (!tsc_khz || !cpu_khz)
831 return true;
832
833 /* Is there an APIC at all? */
834 if (!boot_cpu_has(X86_FEATURE_APIC))
835 return true;
836
837 /* Virt guests may lack ARAT, but still have DEADLINE */
838 if (!boot_cpu_has(X86_FEATURE_ARAT))
839 return true;
840
841 /* Deadline timer is based on TSC so no further PIT action required */
842 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
843 return false;
844
845 /* APIC timer disabled? */
846 if (disable_apic_timer)
847 return true;
848 /*
849 * The APIC timer frequency is known already, no PIT calibration
850 * required. If unknown, let the PIT be initialized.
851 */
852 return lapic_timer_period == 0;
853}
854
855static int __init calibrate_APIC_clock(void)
856{
857 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
858 u64 tsc_perj = 0, tsc_start = 0;
859 unsigned long jif_start;
860 unsigned long deltaj;
861 long delta, deltatsc;
862 int pm_referenced = 0;
863
864 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
865 return 0;
866
867 /*
868 * Check if lapic timer has already been calibrated by platform
869 * specific routine, such as tsc calibration code. If so just fill
870 * in the clockevent structure and return.
871 */
872 if (!lapic_init_clockevent()) {
873 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
874 lapic_timer_period);
875 /*
876 * Direct calibration methods must have an always running
877 * local APIC timer, no need for broadcast timer.
878 */
879 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
880 return 0;
881 }
882
883 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
884 "calibrating APIC timer ...\n");
885
886 /*
887 * There are platforms w/o global clockevent devices. Instead of
888 * making the calibration conditional on that, use a polling based
889 * approach everywhere.
890 */
891 local_irq_disable();
892
893 /*
894 * Setup the APIC counter to maximum. There is no way the lapic
895 * can underflow in the 100ms detection time frame
896 */
897 __setup_APIC_LVTT(0xffffffff, 0, 0);
898
899 /*
900 * Methods to terminate the calibration loop:
901 * 1) Global clockevent if available (jiffies)
902 * 2) TSC if available and frequency is known
903 */
904 jif_start = READ_ONCE(jiffies);
905
906 if (tsc_khz) {
907 tsc_start = rdtsc();
908 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
909 }
910
911 /*
912 * Enable interrupts so the tick can fire, if a global
913 * clockevent device is available
914 */
915 local_irq_enable();
916
917 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
918 /* Wait for a tick to elapse */
919 while (1) {
920 if (tsc_khz) {
921 u64 tsc_now = rdtsc();
922 if ((tsc_now - tsc_start) >= tsc_perj) {
923 tsc_start += tsc_perj;
924 break;
925 }
926 } else {
927 unsigned long jif_now = READ_ONCE(jiffies);
928
929 if (time_after(jif_now, jif_start)) {
930 jif_start = jif_now;
931 break;
932 }
933 }
934 cpu_relax();
935 }
936
937 /* Invoke the calibration routine */
938 local_irq_disable();
939 lapic_cal_handler(NULL);
940 local_irq_enable();
941 }
942
943 local_irq_disable();
944
945 /* Build delta t1-t2 as apic timer counts down */
946 delta = lapic_cal_t1 - lapic_cal_t2;
947 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
948
949 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
950
951 /* we trust the PM based calibration if possible */
952 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
953 &delta, &deltatsc);
954
955 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
956 lapic_init_clockevent();
957
958 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
959 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
960 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
961 lapic_timer_period);
962
963 if (boot_cpu_has(X86_FEATURE_TSC)) {
964 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
965 "%ld.%04ld MHz.\n",
966 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
967 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
968 }
969
970 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
971 "%u.%04u MHz.\n",
972 lapic_timer_period / (1000000 / HZ),
973 lapic_timer_period % (1000000 / HZ));
974
975 /*
976 * Do a sanity check on the APIC calibration result
977 */
978 if (lapic_timer_period < (1000000 / HZ)) {
979 local_irq_enable();
980 pr_warning("APIC frequency too slow, disabling apic timer\n");
981 return -1;
982 }
983
984 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
985
986 /*
987 * PM timer calibration failed or not turned on so lets try APIC
988 * timer based calibration, if a global clockevent device is
989 * available.
990 */
991 if (!pm_referenced && global_clock_event) {
992 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
993
994 /*
995 * Setup the apic timer manually
996 */
997 levt->event_handler = lapic_cal_handler;
998 lapic_timer_set_periodic(levt);
999 lapic_cal_loops = -1;
1000
1001 /* Let the interrupts run */
1002 local_irq_enable();
1003
1004 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
1005 cpu_relax();
1006
1007 /* Stop the lapic timer */
1008 local_irq_disable();
1009 lapic_timer_shutdown(levt);
1010
1011 /* Jiffies delta */
1012 deltaj = lapic_cal_j2 - lapic_cal_j1;
1013 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
1014
1015 /* Check, if the jiffies result is consistent */
1016 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
1017 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
1018 else
1019 levt->features |= CLOCK_EVT_FEAT_DUMMY;
1020 }
1021 local_irq_enable();
1022
1023 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
1024 pr_warning("APIC timer disabled due to verification failure\n");
1025 return -1;
1026 }
1027
1028 return 0;
1029}
1030
1031/*
1032 * Setup the boot APIC
1033 *
1034 * Calibrate and verify the result.
1035 */
1036void __init setup_boot_APIC_clock(void)
1037{
1038 /*
1039 * The local apic timer can be disabled via the kernel
1040 * commandline or from the CPU detection code. Register the lapic
1041 * timer as a dummy clock event source on SMP systems, so the
1042 * broadcast mechanism is used. On UP systems simply ignore it.
1043 */
1044 if (disable_apic_timer) {
1045 pr_info("Disabling APIC timer\n");
1046 /* No broadcast on UP ! */
1047 if (num_possible_cpus() > 1) {
1048 lapic_clockevent.mult = 1;
1049 setup_APIC_timer();
1050 }
1051 return;
1052 }
1053
1054 if (calibrate_APIC_clock()) {
1055 /* No broadcast on UP ! */
1056 if (num_possible_cpus() > 1)
1057 setup_APIC_timer();
1058 return;
1059 }
1060
1061 /*
1062 * If nmi_watchdog is set to IO_APIC, we need the
1063 * PIT/HPET going. Otherwise register lapic as a dummy
1064 * device.
1065 */
1066 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1067
1068 /* Setup the lapic or request the broadcast */
1069 setup_APIC_timer();
1070 amd_e400_c1e_apic_setup();
1071}
1072
1073void setup_secondary_APIC_clock(void)
1074{
1075 setup_APIC_timer();
1076 amd_e400_c1e_apic_setup();
1077}
1078
1079/*
1080 * The guts of the apic timer interrupt
1081 */
1082static void local_apic_timer_interrupt(void)
1083{
1084 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1085
1086 /*
1087 * Normally we should not be here till LAPIC has been initialized but
1088 * in some cases like kdump, its possible that there is a pending LAPIC
1089 * timer interrupt from previous kernel's context and is delivered in
1090 * new kernel the moment interrupts are enabled.
1091 *
1092 * Interrupts are enabled early and LAPIC is setup much later, hence
1093 * its possible that when we get here evt->event_handler is NULL.
1094 * Check for event_handler being NULL and discard the interrupt as
1095 * spurious.
1096 */
1097 if (!evt->event_handler) {
1098 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1099 smp_processor_id());
1100 /* Switch it off */
1101 lapic_timer_shutdown(evt);
1102 return;
1103 }
1104
1105 /*
1106 * the NMI deadlock-detector uses this.
1107 */
1108 inc_irq_stat(apic_timer_irqs);
1109
1110 evt->event_handler(evt);
1111}
1112
1113/*
1114 * Local APIC timer interrupt. This is the most natural way for doing
1115 * local interrupts, but local timer interrupts can be emulated by
1116 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1117 *
1118 * [ if a single-CPU system runs an SMP kernel then we call the local
1119 * interrupt as well. Thus we cannot inline the local irq ... ]
1120 */
1121__visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1122{
1123 struct pt_regs *old_regs = set_irq_regs(regs);
1124
1125 /*
1126 * NOTE! We'd better ACK the irq immediately,
1127 * because timer handling can be slow.
1128 *
1129 * update_process_times() expects us to have done irq_enter().
1130 * Besides, if we don't timer interrupts ignore the global
1131 * interrupt lock, which is the WrongThing (tm) to do.
1132 */
1133 entering_ack_irq();
1134 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1135 local_apic_timer_interrupt();
1136 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1137 exiting_irq();
1138
1139 set_irq_regs(old_regs);
1140}
1141
1142int setup_profiling_timer(unsigned int multiplier)
1143{
1144 return -EINVAL;
1145}
1146
1147/*
1148 * Local APIC start and shutdown
1149 */
1150
1151/**
1152 * clear_local_APIC - shutdown the local APIC
1153 *
1154 * This is called, when a CPU is disabled and before rebooting, so the state of
1155 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1156 * leftovers during boot.
1157 */
1158void clear_local_APIC(void)
1159{
1160 int maxlvt;
1161 u32 v;
1162
1163 /* APIC hasn't been mapped yet */
1164 if (!x2apic_mode && !apic_phys)
1165 return;
1166
1167 maxlvt = lapic_get_maxlvt();
1168 /*
1169 * Masking an LVT entry can trigger a local APIC error
1170 * if the vector is zero. Mask LVTERR first to prevent this.
1171 */
1172 if (maxlvt >= 3) {
1173 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1174 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1175 }
1176 /*
1177 * Careful: we have to set masks only first to deassert
1178 * any level-triggered sources.
1179 */
1180 v = apic_read(APIC_LVTT);
1181 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1182 v = apic_read(APIC_LVT0);
1183 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1184 v = apic_read(APIC_LVT1);
1185 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1186 if (maxlvt >= 4) {
1187 v = apic_read(APIC_LVTPC);
1188 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1189 }
1190
1191 /* lets not touch this if we didn't frob it */
1192#ifdef CONFIG_X86_THERMAL_VECTOR
1193 if (maxlvt >= 5) {
1194 v = apic_read(APIC_LVTTHMR);
1195 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1196 }
1197#endif
1198#ifdef CONFIG_X86_MCE_INTEL
1199 if (maxlvt >= 6) {
1200 v = apic_read(APIC_LVTCMCI);
1201 if (!(v & APIC_LVT_MASKED))
1202 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1203 }
1204#endif
1205
1206 /*
1207 * Clean APIC state for other OSs:
1208 */
1209 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1210 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1211 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1212 if (maxlvt >= 3)
1213 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1214 if (maxlvt >= 4)
1215 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1216
1217 /* Integrated APIC (!82489DX) ? */
1218 if (lapic_is_integrated()) {
1219 if (maxlvt > 3)
1220 /* Clear ESR due to Pentium errata 3AP and 11AP */
1221 apic_write(APIC_ESR, 0);
1222 apic_read(APIC_ESR);
1223 }
1224}
1225
1226/**
1227 * apic_soft_disable - Clears and software disables the local APIC on hotplug
1228 *
1229 * Contrary to disable_local_APIC() this does not touch the enable bit in
1230 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC
1231 * bus would require a hardware reset as the APIC would lose track of bus
1232 * arbitration. On systems with FSB delivery APICBASE could be disabled,
1233 * but it has to be guaranteed that no interrupt is sent to the APIC while
1234 * in that state and it's not clear from the SDM whether it still responds
1235 * to INIT/SIPI messages. Stay on the safe side and use software disable.
1236 */
1237void apic_soft_disable(void)
1238{
1239 u32 value;
1240
1241 clear_local_APIC();
1242
1243 /* Soft disable APIC (implies clearing of registers for 82489DX!). */
1244 value = apic_read(APIC_SPIV);
1245 value &= ~APIC_SPIV_APIC_ENABLED;
1246 apic_write(APIC_SPIV, value);
1247}
1248
1249/**
1250 * disable_local_APIC - clear and disable the local APIC
1251 */
1252void disable_local_APIC(void)
1253{
1254 /* APIC hasn't been mapped yet */
1255 if (!x2apic_mode && !apic_phys)
1256 return;
1257
1258 apic_soft_disable();
1259
1260#ifdef CONFIG_X86_32
1261 /*
1262 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1263 * restore the disabled state.
1264 */
1265 if (enabled_via_apicbase) {
1266 unsigned int l, h;
1267
1268 rdmsr(MSR_IA32_APICBASE, l, h);
1269 l &= ~MSR_IA32_APICBASE_ENABLE;
1270 wrmsr(MSR_IA32_APICBASE, l, h);
1271 }
1272#endif
1273}
1274
1275/*
1276 * If Linux enabled the LAPIC against the BIOS default disable it down before
1277 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1278 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1279 * for the case where Linux didn't enable the LAPIC.
1280 */
1281void lapic_shutdown(void)
1282{
1283 unsigned long flags;
1284
1285 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1286 return;
1287
1288 local_irq_save(flags);
1289
1290#ifdef CONFIG_X86_32
1291 if (!enabled_via_apicbase)
1292 clear_local_APIC();
1293 else
1294#endif
1295 disable_local_APIC();
1296
1297
1298 local_irq_restore(flags);
1299}
1300
1301/**
1302 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1303 */
1304void __init sync_Arb_IDs(void)
1305{
1306 /*
1307 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1308 * needed on AMD.
1309 */
1310 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1311 return;
1312
1313 /*
1314 * Wait for idle.
1315 */
1316 apic_wait_icr_idle();
1317
1318 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1319 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1320 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1321}
1322
1323enum apic_intr_mode_id apic_intr_mode __ro_after_init;
1324
1325static int __init apic_intr_mode_select(void)
1326{
1327 /* Check kernel option */
1328 if (disable_apic) {
1329 pr_info("APIC disabled via kernel command line\n");
1330 return APIC_PIC;
1331 }
1332
1333 /* Check BIOS */
1334#ifdef CONFIG_X86_64
1335 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1336 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1337 disable_apic = 1;
1338 pr_info("APIC disabled by BIOS\n");
1339 return APIC_PIC;
1340 }
1341#else
1342 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1343
1344 /* Neither 82489DX nor integrated APIC ? */
1345 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1346 disable_apic = 1;
1347 return APIC_PIC;
1348 }
1349
1350 /* If the BIOS pretends there is an integrated APIC ? */
1351 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1352 APIC_INTEGRATED(boot_cpu_apic_version)) {
1353 disable_apic = 1;
1354 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1355 boot_cpu_physical_apicid);
1356 return APIC_PIC;
1357 }
1358#endif
1359
1360 /* Check MP table or ACPI MADT configuration */
1361 if (!smp_found_config) {
1362 disable_ioapic_support();
1363 if (!acpi_lapic) {
1364 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1365 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1366 }
1367 return APIC_VIRTUAL_WIRE;
1368 }
1369
1370#ifdef CONFIG_SMP
1371 /* If SMP should be disabled, then really disable it! */
1372 if (!setup_max_cpus) {
1373 pr_info("APIC: SMP mode deactivated\n");
1374 return APIC_SYMMETRIC_IO_NO_ROUTING;
1375 }
1376
1377 if (read_apic_id() != boot_cpu_physical_apicid) {
1378 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1379 read_apic_id(), boot_cpu_physical_apicid);
1380 /* Or can we switch back to PIC here? */
1381 }
1382#endif
1383
1384 return APIC_SYMMETRIC_IO;
1385}
1386
1387/*
1388 * An initial setup of the virtual wire mode.
1389 */
1390void __init init_bsp_APIC(void)
1391{
1392 unsigned int value;
1393
1394 /*
1395 * Don't do the setup now if we have a SMP BIOS as the
1396 * through-I/O-APIC virtual wire mode might be active.
1397 */
1398 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1399 return;
1400
1401 /*
1402 * Do not trust the local APIC being empty at bootup.
1403 */
1404 clear_local_APIC();
1405
1406 /*
1407 * Enable APIC.
1408 */
1409 value = apic_read(APIC_SPIV);
1410 value &= ~APIC_VECTOR_MASK;
1411 value |= APIC_SPIV_APIC_ENABLED;
1412
1413#ifdef CONFIG_X86_32
1414 /* This bit is reserved on P4/Xeon and should be cleared */
1415 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1416 (boot_cpu_data.x86 == 15))
1417 value &= ~APIC_SPIV_FOCUS_DISABLED;
1418 else
1419#endif
1420 value |= APIC_SPIV_FOCUS_DISABLED;
1421 value |= SPURIOUS_APIC_VECTOR;
1422 apic_write(APIC_SPIV, value);
1423
1424 /*
1425 * Set up the virtual wire mode.
1426 */
1427 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1428 value = APIC_DM_NMI;
1429 if (!lapic_is_integrated()) /* 82489DX */
1430 value |= APIC_LVT_LEVEL_TRIGGER;
1431 if (apic_extnmi == APIC_EXTNMI_NONE)
1432 value |= APIC_LVT_MASKED;
1433 apic_write(APIC_LVT1, value);
1434}
1435
1436static void __init apic_bsp_setup(bool upmode);
1437
1438/* Init the interrupt delivery mode for the BSP */
1439void __init apic_intr_mode_init(void)
1440{
1441 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1442
1443 apic_intr_mode = apic_intr_mode_select();
1444
1445 switch (apic_intr_mode) {
1446 case APIC_PIC:
1447 pr_info("APIC: Keep in PIC mode(8259)\n");
1448 return;
1449 case APIC_VIRTUAL_WIRE:
1450 pr_info("APIC: Switch to virtual wire mode setup\n");
1451 default_setup_apic_routing();
1452 break;
1453 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1454 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1455 upmode = true;
1456 default_setup_apic_routing();
1457 break;
1458 case APIC_SYMMETRIC_IO:
1459 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1460 default_setup_apic_routing();
1461 break;
1462 case APIC_SYMMETRIC_IO_NO_ROUTING:
1463 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1464 break;
1465 }
1466
1467 apic_bsp_setup(upmode);
1468}
1469
1470static void lapic_setup_esr(void)
1471{
1472 unsigned int oldvalue, value, maxlvt;
1473
1474 if (!lapic_is_integrated()) {
1475 pr_info("No ESR for 82489DX.\n");
1476 return;
1477 }
1478
1479 if (apic->disable_esr) {
1480 /*
1481 * Something untraceable is creating bad interrupts on
1482 * secondary quads ... for the moment, just leave the
1483 * ESR disabled - we can't do anything useful with the
1484 * errors anyway - mbligh
1485 */
1486 pr_info("Leaving ESR disabled.\n");
1487 return;
1488 }
1489
1490 maxlvt = lapic_get_maxlvt();
1491 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1492 apic_write(APIC_ESR, 0);
1493 oldvalue = apic_read(APIC_ESR);
1494
1495 /* enables sending errors */
1496 value = ERROR_APIC_VECTOR;
1497 apic_write(APIC_LVTERR, value);
1498
1499 /*
1500 * spec says clear errors after enabling vector.
1501 */
1502 if (maxlvt > 3)
1503 apic_write(APIC_ESR, 0);
1504 value = apic_read(APIC_ESR);
1505 if (value != oldvalue)
1506 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1507 "vector: 0x%08x after: 0x%08x\n",
1508 oldvalue, value);
1509}
1510
1511#define APIC_IR_REGS APIC_ISR_NR
1512#define APIC_IR_BITS (APIC_IR_REGS * 32)
1513#define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG)
1514
1515union apic_ir {
1516 unsigned long map[APIC_IR_MAPSIZE];
1517 u32 regs[APIC_IR_REGS];
1518};
1519
1520static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1521{
1522 int i, bit;
1523
1524 /* Read the IRRs */
1525 for (i = 0; i < APIC_IR_REGS; i++)
1526 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1527
1528 /* Read the ISRs */
1529 for (i = 0; i < APIC_IR_REGS; i++)
1530 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1531
1532 /*
1533 * If the ISR map is not empty. ACK the APIC and run another round
1534 * to verify whether a pending IRR has been unblocked and turned
1535 * into a ISR.
1536 */
1537 if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1538 /*
1539 * There can be multiple ISR bits set when a high priority
1540 * interrupt preempted a lower priority one. Issue an ACK
1541 * per set bit.
1542 */
1543 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1544 ack_APIC_irq();
1545 return true;
1546 }
1547
1548 return !bitmap_empty(irr->map, APIC_IR_BITS);
1549}
1550
1551/*
1552 * After a crash, we no longer service the interrupts and a pending
1553 * interrupt from previous kernel might still have ISR bit set.
1554 *
1555 * Most probably by now the CPU has serviced that pending interrupt and it
1556 * might not have done the ack_APIC_irq() because it thought, interrupt
1557 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1558 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
1559 * a vector might get locked. It was noticed for timer irq (vector
1560 * 0x31). Issue an extra EOI to clear ISR.
1561 *
1562 * If there are pending IRR bits they turn into ISR bits after a higher
1563 * priority ISR bit has been acked.
1564 */
1565static void apic_pending_intr_clear(void)
1566{
1567 union apic_ir irr, isr;
1568 unsigned int i;
1569
1570 /* 512 loops are way oversized and give the APIC a chance to obey. */
1571 for (i = 0; i < 512; i++) {
1572 if (!apic_check_and_ack(&irr, &isr))
1573 return;
1574 }
1575 /* Dump the IRR/ISR content if that failed */
1576 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1577}
1578
1579/**
1580 * setup_local_APIC - setup the local APIC
1581 *
1582 * Used to setup local APIC while initializing BSP or bringing up APs.
1583 * Always called with preemption disabled.
1584 */
1585static void setup_local_APIC(void)
1586{
1587 int cpu = smp_processor_id();
1588 unsigned int value;
1589
1590 if (disable_apic) {
1591 disable_ioapic_support();
1592 return;
1593 }
1594
1595 /*
1596 * If this comes from kexec/kcrash the APIC might be enabled in
1597 * SPIV. Soft disable it before doing further initialization.
1598 */
1599 value = apic_read(APIC_SPIV);
1600 value &= ~APIC_SPIV_APIC_ENABLED;
1601 apic_write(APIC_SPIV, value);
1602
1603#ifdef CONFIG_X86_32
1604 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1605 if (lapic_is_integrated() && apic->disable_esr) {
1606 apic_write(APIC_ESR, 0);
1607 apic_write(APIC_ESR, 0);
1608 apic_write(APIC_ESR, 0);
1609 apic_write(APIC_ESR, 0);
1610 }
1611#endif
1612 /*
1613 * Double-check whether this APIC is really registered.
1614 * This is meaningless in clustered apic mode, so we skip it.
1615 */
1616 BUG_ON(!apic->apic_id_registered());
1617
1618 /*
1619 * Intel recommends to set DFR, LDR and TPR before enabling
1620 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1621 * document number 292116). So here it goes...
1622 */
1623 apic->init_apic_ldr();
1624
1625#ifdef CONFIG_X86_32
1626 if (apic->dest_logical) {
1627 int logical_apicid, ldr_apicid;
1628
1629 /*
1630 * APIC LDR is initialized. If logical_apicid mapping was
1631 * initialized during get_smp_config(), make sure it matches
1632 * the actual value.
1633 */
1634 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1635 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1636 if (logical_apicid != BAD_APICID)
1637 WARN_ON(logical_apicid != ldr_apicid);
1638 /* Always use the value from LDR. */
1639 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1640 }
1641#endif
1642
1643 /*
1644 * Set Task Priority to 'accept all except vectors 0-31'. An APIC
1645 * vector in the 16-31 range could be delivered if TPR == 0, but we
1646 * would think it's an exception and terrible things will happen. We
1647 * never change this later on.
1648 */
1649 value = apic_read(APIC_TASKPRI);
1650 value &= ~APIC_TPRI_MASK;
1651 value |= 0x10;
1652 apic_write(APIC_TASKPRI, value);
1653
1654 /* Clear eventually stale ISR/IRR bits */
1655 apic_pending_intr_clear();
1656
1657 /*
1658 * Now that we are all set up, enable the APIC
1659 */
1660 value = apic_read(APIC_SPIV);
1661 value &= ~APIC_VECTOR_MASK;
1662 /*
1663 * Enable APIC
1664 */
1665 value |= APIC_SPIV_APIC_ENABLED;
1666
1667#ifdef CONFIG_X86_32
1668 /*
1669 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1670 * certain networking cards. If high frequency interrupts are
1671 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1672 * entry is masked/unmasked at a high rate as well then sooner or
1673 * later IOAPIC line gets 'stuck', no more interrupts are received
1674 * from the device. If focus CPU is disabled then the hang goes
1675 * away, oh well :-(
1676 *
1677 * [ This bug can be reproduced easily with a level-triggered
1678 * PCI Ne2000 networking cards and PII/PIII processors, dual
1679 * BX chipset. ]
1680 */
1681 /*
1682 * Actually disabling the focus CPU check just makes the hang less
1683 * frequent as it makes the interrupt distributon model be more
1684 * like LRU than MRU (the short-term load is more even across CPUs).
1685 */
1686
1687 /*
1688 * - enable focus processor (bit==0)
1689 * - 64bit mode always use processor focus
1690 * so no need to set it
1691 */
1692 value &= ~APIC_SPIV_FOCUS_DISABLED;
1693#endif
1694
1695 /*
1696 * Set spurious IRQ vector
1697 */
1698 value |= SPURIOUS_APIC_VECTOR;
1699 apic_write(APIC_SPIV, value);
1700
1701 perf_events_lapic_init();
1702
1703 /*
1704 * Set up LVT0, LVT1:
1705 *
1706 * set up through-local-APIC on the boot CPU's LINT0. This is not
1707 * strictly necessary in pure symmetric-IO mode, but sometimes
1708 * we delegate interrupts to the 8259A.
1709 */
1710 /*
1711 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1712 */
1713 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1714 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1715 value = APIC_DM_EXTINT;
1716 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1717 } else {
1718 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1719 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1720 }
1721 apic_write(APIC_LVT0, value);
1722
1723 /*
1724 * Only the BSP sees the LINT1 NMI signal by default. This can be
1725 * modified by apic_extnmi= boot option.
1726 */
1727 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1728 apic_extnmi == APIC_EXTNMI_ALL)
1729 value = APIC_DM_NMI;
1730 else
1731 value = APIC_DM_NMI | APIC_LVT_MASKED;
1732
1733 /* Is 82489DX ? */
1734 if (!lapic_is_integrated())
1735 value |= APIC_LVT_LEVEL_TRIGGER;
1736 apic_write(APIC_LVT1, value);
1737
1738#ifdef CONFIG_X86_MCE_INTEL
1739 /* Recheck CMCI information after local APIC is up on CPU #0 */
1740 if (!cpu)
1741 cmci_recheck();
1742#endif
1743}
1744
1745static void end_local_APIC_setup(void)
1746{
1747 lapic_setup_esr();
1748
1749#ifdef CONFIG_X86_32
1750 {
1751 unsigned int value;
1752 /* Disable the local apic timer */
1753 value = apic_read(APIC_LVTT);
1754 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1755 apic_write(APIC_LVTT, value);
1756 }
1757#endif
1758
1759 apic_pm_activate();
1760}
1761
1762/*
1763 * APIC setup function for application processors. Called from smpboot.c
1764 */
1765void apic_ap_setup(void)
1766{
1767 setup_local_APIC();
1768 end_local_APIC_setup();
1769}
1770
1771#ifdef CONFIG_X86_X2APIC
1772int x2apic_mode;
1773
1774enum {
1775 X2APIC_OFF,
1776 X2APIC_ON,
1777 X2APIC_DISABLED,
1778};
1779static int x2apic_state;
1780
1781static void __x2apic_disable(void)
1782{
1783 u64 msr;
1784
1785 if (!boot_cpu_has(X86_FEATURE_APIC))
1786 return;
1787
1788 rdmsrl(MSR_IA32_APICBASE, msr);
1789 if (!(msr & X2APIC_ENABLE))
1790 return;
1791 /* Disable xapic and x2apic first and then reenable xapic mode */
1792 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1793 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1794 printk_once(KERN_INFO "x2apic disabled\n");
1795}
1796
1797static void __x2apic_enable(void)
1798{
1799 u64 msr;
1800
1801 rdmsrl(MSR_IA32_APICBASE, msr);
1802 if (msr & X2APIC_ENABLE)
1803 return;
1804 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1805 printk_once(KERN_INFO "x2apic enabled\n");
1806}
1807
1808static int __init setup_nox2apic(char *str)
1809{
1810 if (x2apic_enabled()) {
1811 int apicid = native_apic_msr_read(APIC_ID);
1812
1813 if (apicid >= 255) {
1814 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1815 apicid);
1816 return 0;
1817 }
1818 pr_warning("x2apic already enabled.\n");
1819 __x2apic_disable();
1820 }
1821 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1822 x2apic_state = X2APIC_DISABLED;
1823 x2apic_mode = 0;
1824 return 0;
1825}
1826early_param("nox2apic", setup_nox2apic);
1827
1828/* Called from cpu_init() to enable x2apic on (secondary) cpus */
1829void x2apic_setup(void)
1830{
1831 /*
1832 * If x2apic is not in ON state, disable it if already enabled
1833 * from BIOS.
1834 */
1835 if (x2apic_state != X2APIC_ON) {
1836 __x2apic_disable();
1837 return;
1838 }
1839 __x2apic_enable();
1840}
1841
1842static __init void x2apic_disable(void)
1843{
1844 u32 x2apic_id, state = x2apic_state;
1845
1846 x2apic_mode = 0;
1847 x2apic_state = X2APIC_DISABLED;
1848
1849 if (state != X2APIC_ON)
1850 return;
1851
1852 x2apic_id = read_apic_id();
1853 if (x2apic_id >= 255)
1854 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1855
1856 __x2apic_disable();
1857 register_lapic_address(mp_lapic_addr);
1858}
1859
1860static __init void x2apic_enable(void)
1861{
1862 if (x2apic_state != X2APIC_OFF)
1863 return;
1864
1865 x2apic_mode = 1;
1866 x2apic_state = X2APIC_ON;
1867 __x2apic_enable();
1868}
1869
1870static __init void try_to_enable_x2apic(int remap_mode)
1871{
1872 if (x2apic_state == X2APIC_DISABLED)
1873 return;
1874
1875 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1876 /* IR is required if there is APIC ID > 255 even when running
1877 * under KVM
1878 */
1879 if (max_physical_apicid > 255 ||
1880 !x86_init.hyper.x2apic_available()) {
1881 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1882 x2apic_disable();
1883 return;
1884 }
1885
1886 /*
1887 * without IR all CPUs can be addressed by IOAPIC/MSI
1888 * only in physical mode
1889 */
1890 x2apic_phys = 1;
1891 }
1892 x2apic_enable();
1893}
1894
1895void __init check_x2apic(void)
1896{
1897 if (x2apic_enabled()) {
1898 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1899 x2apic_mode = 1;
1900 x2apic_state = X2APIC_ON;
1901 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1902 x2apic_state = X2APIC_DISABLED;
1903 }
1904}
1905#else /* CONFIG_X86_X2APIC */
1906static int __init validate_x2apic(void)
1907{
1908 if (!apic_is_x2apic_enabled())
1909 return 0;
1910 /*
1911 * Checkme: Can we simply turn off x2apic here instead of panic?
1912 */
1913 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1914}
1915early_initcall(validate_x2apic);
1916
1917static inline void try_to_enable_x2apic(int remap_mode) { }
1918static inline void __x2apic_enable(void) { }
1919#endif /* !CONFIG_X86_X2APIC */
1920
1921void __init enable_IR_x2apic(void)
1922{
1923 unsigned long flags;
1924 int ret, ir_stat;
1925
1926 if (skip_ioapic_setup) {
1927 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1928 return;
1929 }
1930
1931 ir_stat = irq_remapping_prepare();
1932 if (ir_stat < 0 && !x2apic_supported())
1933 return;
1934
1935 ret = save_ioapic_entries();
1936 if (ret) {
1937 pr_info("Saving IO-APIC state failed: %d\n", ret);
1938 return;
1939 }
1940
1941 local_irq_save(flags);
1942 legacy_pic->mask_all();
1943 mask_ioapic_entries();
1944
1945 /* If irq_remapping_prepare() succeeded, try to enable it */
1946 if (ir_stat >= 0)
1947 ir_stat = irq_remapping_enable();
1948 /* ir_stat contains the remap mode or an error code */
1949 try_to_enable_x2apic(ir_stat);
1950
1951 if (ir_stat < 0)
1952 restore_ioapic_entries();
1953 legacy_pic->restore_mask();
1954 local_irq_restore(flags);
1955}
1956
1957#ifdef CONFIG_X86_64
1958/*
1959 * Detect and enable local APICs on non-SMP boards.
1960 * Original code written by Keir Fraser.
1961 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1962 * not correctly set up (usually the APIC timer won't work etc.)
1963 */
1964static int __init detect_init_APIC(void)
1965{
1966 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1967 pr_info("No local APIC present\n");
1968 return -1;
1969 }
1970
1971 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1972 return 0;
1973}
1974#else
1975
1976static int __init apic_verify(void)
1977{
1978 u32 features, h, l;
1979
1980 /*
1981 * The APIC feature bit should now be enabled
1982 * in `cpuid'
1983 */
1984 features = cpuid_edx(1);
1985 if (!(features & (1 << X86_FEATURE_APIC))) {
1986 pr_warning("Could not enable APIC!\n");
1987 return -1;
1988 }
1989 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1990 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1991
1992 /* The BIOS may have set up the APIC at some other address */
1993 if (boot_cpu_data.x86 >= 6) {
1994 rdmsr(MSR_IA32_APICBASE, l, h);
1995 if (l & MSR_IA32_APICBASE_ENABLE)
1996 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1997 }
1998
1999 pr_info("Found and enabled local APIC!\n");
2000 return 0;
2001}
2002
2003int __init apic_force_enable(unsigned long addr)
2004{
2005 u32 h, l;
2006
2007 if (disable_apic)
2008 return -1;
2009
2010 /*
2011 * Some BIOSes disable the local APIC in the APIC_BASE
2012 * MSR. This can only be done in software for Intel P6 or later
2013 * and AMD K7 (Model > 1) or later.
2014 */
2015 if (boot_cpu_data.x86 >= 6) {
2016 rdmsr(MSR_IA32_APICBASE, l, h);
2017 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
2018 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
2019 l &= ~MSR_IA32_APICBASE_BASE;
2020 l |= MSR_IA32_APICBASE_ENABLE | addr;
2021 wrmsr(MSR_IA32_APICBASE, l, h);
2022 enabled_via_apicbase = 1;
2023 }
2024 }
2025 return apic_verify();
2026}
2027
2028/*
2029 * Detect and initialize APIC
2030 */
2031static int __init detect_init_APIC(void)
2032{
2033 /* Disabled by kernel option? */
2034 if (disable_apic)
2035 return -1;
2036
2037 switch (boot_cpu_data.x86_vendor) {
2038 case X86_VENDOR_AMD:
2039 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
2040 (boot_cpu_data.x86 >= 15))
2041 break;
2042 goto no_apic;
2043 case X86_VENDOR_HYGON:
2044 break;
2045 case X86_VENDOR_INTEL:
2046 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
2047 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
2048 break;
2049 goto no_apic;
2050 default:
2051 goto no_apic;
2052 }
2053
2054 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2055 /*
2056 * Over-ride BIOS and try to enable the local APIC only if
2057 * "lapic" specified.
2058 */
2059 if (!force_enable_local_apic) {
2060 pr_info("Local APIC disabled by BIOS -- "
2061 "you can enable it with \"lapic\"\n");
2062 return -1;
2063 }
2064 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2065 return -1;
2066 } else {
2067 if (apic_verify())
2068 return -1;
2069 }
2070
2071 apic_pm_activate();
2072
2073 return 0;
2074
2075no_apic:
2076 pr_info("No local APIC present or hardware disabled\n");
2077 return -1;
2078}
2079#endif
2080
2081/**
2082 * init_apic_mappings - initialize APIC mappings
2083 */
2084void __init init_apic_mappings(void)
2085{
2086 unsigned int new_apicid;
2087
2088 apic_check_deadline_errata();
2089
2090 if (x2apic_mode) {
2091 boot_cpu_physical_apicid = read_apic_id();
2092 return;
2093 }
2094
2095 /* If no local APIC can be found return early */
2096 if (!smp_found_config && detect_init_APIC()) {
2097 /* lets NOP'ify apic operations */
2098 pr_info("APIC: disable apic facility\n");
2099 apic_disable();
2100 } else {
2101 apic_phys = mp_lapic_addr;
2102
2103 /*
2104 * If the system has ACPI MADT tables or MP info, the LAPIC
2105 * address is already registered.
2106 */
2107 if (!acpi_lapic && !smp_found_config)
2108 register_lapic_address(apic_phys);
2109 }
2110
2111 /*
2112 * Fetch the APIC ID of the BSP in case we have a
2113 * default configuration (or the MP table is broken).
2114 */
2115 new_apicid = read_apic_id();
2116 if (boot_cpu_physical_apicid != new_apicid) {
2117 boot_cpu_physical_apicid = new_apicid;
2118 /*
2119 * yeah -- we lie about apic_version
2120 * in case if apic was disabled via boot option
2121 * but it's not a problem for SMP compiled kernel
2122 * since apic_intr_mode_select is prepared for such
2123 * a case and disable smp mode
2124 */
2125 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2126 }
2127}
2128
2129void __init register_lapic_address(unsigned long address)
2130{
2131 mp_lapic_addr = address;
2132
2133 if (!x2apic_mode) {
2134 set_fixmap_nocache(FIX_APIC_BASE, address);
2135 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2136 APIC_BASE, address);
2137 }
2138 if (boot_cpu_physical_apicid == -1U) {
2139 boot_cpu_physical_apicid = read_apic_id();
2140 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2141 }
2142}
2143
2144/*
2145 * Local APIC interrupts
2146 */
2147
2148/*
2149 * This interrupt should _never_ happen with our APIC/SMP architecture
2150 */
2151__visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
2152{
2153 u8 vector = ~regs->orig_ax;
2154 u32 v;
2155
2156 entering_irq();
2157 trace_spurious_apic_entry(vector);
2158
2159 inc_irq_stat(irq_spurious_count);
2160
2161 /*
2162 * If this is a spurious interrupt then do not acknowledge
2163 */
2164 if (vector == SPURIOUS_APIC_VECTOR) {
2165 /* See SDM vol 3 */
2166 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2167 smp_processor_id());
2168 goto out;
2169 }
2170
2171 /*
2172 * If it is a vectored one, verify it's set in the ISR. If set,
2173 * acknowledge it.
2174 */
2175 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2176 if (v & (1 << (vector & 0x1f))) {
2177 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2178 vector, smp_processor_id());
2179 ack_APIC_irq();
2180 } else {
2181 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2182 vector, smp_processor_id());
2183 }
2184out:
2185 trace_spurious_apic_exit(vector);
2186 exiting_irq();
2187}
2188
2189/*
2190 * This interrupt should never happen with our APIC/SMP architecture
2191 */
2192__visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2193{
2194 static const char * const error_interrupt_reason[] = {
2195 "Send CS error", /* APIC Error Bit 0 */
2196 "Receive CS error", /* APIC Error Bit 1 */
2197 "Send accept error", /* APIC Error Bit 2 */
2198 "Receive accept error", /* APIC Error Bit 3 */
2199 "Redirectable IPI", /* APIC Error Bit 4 */
2200 "Send illegal vector", /* APIC Error Bit 5 */
2201 "Received illegal vector", /* APIC Error Bit 6 */
2202 "Illegal register address", /* APIC Error Bit 7 */
2203 };
2204 u32 v, i = 0;
2205
2206 entering_irq();
2207 trace_error_apic_entry(ERROR_APIC_VECTOR);
2208
2209 /* First tickle the hardware, only then report what went on. -- REW */
2210 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2211 apic_write(APIC_ESR, 0);
2212 v = apic_read(APIC_ESR);
2213 ack_APIC_irq();
2214 atomic_inc(&irq_err_count);
2215
2216 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2217 smp_processor_id(), v);
2218
2219 v &= 0xff;
2220 while (v) {
2221 if (v & 0x1)
2222 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2223 i++;
2224 v >>= 1;
2225 }
2226
2227 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2228
2229 trace_error_apic_exit(ERROR_APIC_VECTOR);
2230 exiting_irq();
2231}
2232
2233/**
2234 * connect_bsp_APIC - attach the APIC to the interrupt system
2235 */
2236static void __init connect_bsp_APIC(void)
2237{
2238#ifdef CONFIG_X86_32
2239 if (pic_mode) {
2240 /*
2241 * Do not trust the local APIC being empty at bootup.
2242 */
2243 clear_local_APIC();
2244 /*
2245 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2246 * local APIC to INT and NMI lines.
2247 */
2248 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2249 "enabling APIC mode.\n");
2250 imcr_pic_to_apic();
2251 }
2252#endif
2253}
2254
2255/**
2256 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2257 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2258 *
2259 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2260 * APIC is disabled.
2261 */
2262void disconnect_bsp_APIC(int virt_wire_setup)
2263{
2264 unsigned int value;
2265
2266#ifdef CONFIG_X86_32
2267 if (pic_mode) {
2268 /*
2269 * Put the board back into PIC mode (has an effect only on
2270 * certain older boards). Note that APIC interrupts, including
2271 * IPIs, won't work beyond this point! The only exception are
2272 * INIT IPIs.
2273 */
2274 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2275 "entering PIC mode.\n");
2276 imcr_apic_to_pic();
2277 return;
2278 }
2279#endif
2280
2281 /* Go back to Virtual Wire compatibility mode */
2282
2283 /* For the spurious interrupt use vector F, and enable it */
2284 value = apic_read(APIC_SPIV);
2285 value &= ~APIC_VECTOR_MASK;
2286 value |= APIC_SPIV_APIC_ENABLED;
2287 value |= 0xf;
2288 apic_write(APIC_SPIV, value);
2289
2290 if (!virt_wire_setup) {
2291 /*
2292 * For LVT0 make it edge triggered, active high,
2293 * external and enabled
2294 */
2295 value = apic_read(APIC_LVT0);
2296 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2297 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2298 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2299 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2300 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2301 apic_write(APIC_LVT0, value);
2302 } else {
2303 /* Disable LVT0 */
2304 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2305 }
2306
2307 /*
2308 * For LVT1 make it edge triggered, active high,
2309 * nmi and enabled
2310 */
2311 value = apic_read(APIC_LVT1);
2312 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2313 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2314 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2315 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2316 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2317 apic_write(APIC_LVT1, value);
2318}
2319
2320/*
2321 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2322 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2323 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2324 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2325 *
2326 * NOTE: Reserve 0 for BSP.
2327 */
2328static int nr_logical_cpuids = 1;
2329
2330/*
2331 * Used to store mapping between logical CPU IDs and APIC IDs.
2332 */
2333static int cpuid_to_apicid[] = {
2334 [0 ... NR_CPUS - 1] = -1,
2335};
2336
2337#ifdef CONFIG_SMP
2338/**
2339 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2340 * @id: APIC ID to check
2341 */
2342bool apic_id_is_primary_thread(unsigned int apicid)
2343{
2344 u32 mask;
2345
2346 if (smp_num_siblings == 1)
2347 return true;
2348 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2349 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2350 return !(apicid & mask);
2351}
2352#endif
2353
2354/*
2355 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2356 * and cpuid_to_apicid[] synchronized.
2357 */
2358static int allocate_logical_cpuid(int apicid)
2359{
2360 int i;
2361
2362 /*
2363 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2364 * check if the kernel has allocated a cpuid for it.
2365 */
2366 for (i = 0; i < nr_logical_cpuids; i++) {
2367 if (cpuid_to_apicid[i] == apicid)
2368 return i;
2369 }
2370
2371 /* Allocate a new cpuid. */
2372 if (nr_logical_cpuids >= nr_cpu_ids) {
2373 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2374 "Processor %d/0x%x and the rest are ignored.\n",
2375 nr_cpu_ids, nr_logical_cpuids, apicid);
2376 return -EINVAL;
2377 }
2378
2379 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2380 return nr_logical_cpuids++;
2381}
2382
2383int generic_processor_info(int apicid, int version)
2384{
2385 int cpu, max = nr_cpu_ids;
2386 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2387 phys_cpu_present_map);
2388
2389 /*
2390 * boot_cpu_physical_apicid is designed to have the apicid
2391 * returned by read_apic_id(), i.e, the apicid of the
2392 * currently booting-up processor. However, on some platforms,
2393 * it is temporarily modified by the apicid reported as BSP
2394 * through MP table. Concretely:
2395 *
2396 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2397 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2398 *
2399 * This function is executed with the modified
2400 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2401 * parameter doesn't work to disable APs on kdump 2nd kernel.
2402 *
2403 * Since fixing handling of boot_cpu_physical_apicid requires
2404 * another discussion and tests on each platform, we leave it
2405 * for now and here we use read_apic_id() directly in this
2406 * function, generic_processor_info().
2407 */
2408 if (disabled_cpu_apicid != BAD_APICID &&
2409 disabled_cpu_apicid != read_apic_id() &&
2410 disabled_cpu_apicid == apicid) {
2411 int thiscpu = num_processors + disabled_cpus;
2412
2413 pr_warning("APIC: Disabling requested cpu."
2414 " Processor %d/0x%x ignored.\n",
2415 thiscpu, apicid);
2416
2417 disabled_cpus++;
2418 return -ENODEV;
2419 }
2420
2421 /*
2422 * If boot cpu has not been detected yet, then only allow upto
2423 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2424 */
2425 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2426 apicid != boot_cpu_physical_apicid) {
2427 int thiscpu = max + disabled_cpus - 1;
2428
2429 pr_warning(
2430 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2431 " reached. Keeping one slot for boot cpu."
2432 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2433
2434 disabled_cpus++;
2435 return -ENODEV;
2436 }
2437
2438 if (num_processors >= nr_cpu_ids) {
2439 int thiscpu = max + disabled_cpus;
2440
2441 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2442 "reached. Processor %d/0x%x ignored.\n",
2443 max, thiscpu, apicid);
2444
2445 disabled_cpus++;
2446 return -EINVAL;
2447 }
2448
2449 if (apicid == boot_cpu_physical_apicid) {
2450 /*
2451 * x86_bios_cpu_apicid is required to have processors listed
2452 * in same order as logical cpu numbers. Hence the first
2453 * entry is BSP, and so on.
2454 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2455 * for BSP.
2456 */
2457 cpu = 0;
2458
2459 /* Logical cpuid 0 is reserved for BSP. */
2460 cpuid_to_apicid[0] = apicid;
2461 } else {
2462 cpu = allocate_logical_cpuid(apicid);
2463 if (cpu < 0) {
2464 disabled_cpus++;
2465 return -EINVAL;
2466 }
2467 }
2468
2469 /*
2470 * Validate version
2471 */
2472 if (version == 0x0) {
2473 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2474 cpu, apicid);
2475 version = 0x10;
2476 }
2477
2478 if (version != boot_cpu_apic_version) {
2479 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2480 boot_cpu_apic_version, cpu, version);
2481 }
2482
2483 if (apicid > max_physical_apicid)
2484 max_physical_apicid = apicid;
2485
2486#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2487 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2488 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2489#endif
2490#ifdef CONFIG_X86_32
2491 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2492 apic->x86_32_early_logical_apicid(cpu);
2493#endif
2494 set_cpu_possible(cpu, true);
2495 physid_set(apicid, phys_cpu_present_map);
2496 set_cpu_present(cpu, true);
2497 num_processors++;
2498
2499 return cpu;
2500}
2501
2502int hard_smp_processor_id(void)
2503{
2504 return read_apic_id();
2505}
2506
2507/*
2508 * Override the generic EOI implementation with an optimized version.
2509 * Only called during early boot when only one CPU is active and with
2510 * interrupts disabled, so we know this does not race with actual APIC driver
2511 * use.
2512 */
2513void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2514{
2515 struct apic **drv;
2516
2517 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2518 /* Should happen once for each apic */
2519 WARN_ON((*drv)->eoi_write == eoi_write);
2520 (*drv)->native_eoi_write = (*drv)->eoi_write;
2521 (*drv)->eoi_write = eoi_write;
2522 }
2523}
2524
2525static void __init apic_bsp_up_setup(void)
2526{
2527#ifdef CONFIG_X86_64
2528 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2529#else
2530 /*
2531 * Hack: In case of kdump, after a crash, kernel might be booting
2532 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2533 * might be zero if read from MP tables. Get it from LAPIC.
2534 */
2535# ifdef CONFIG_CRASH_DUMP
2536 boot_cpu_physical_apicid = read_apic_id();
2537# endif
2538#endif
2539 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2540}
2541
2542/**
2543 * apic_bsp_setup - Setup function for local apic and io-apic
2544 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2545 */
2546static void __init apic_bsp_setup(bool upmode)
2547{
2548 connect_bsp_APIC();
2549 if (upmode)
2550 apic_bsp_up_setup();
2551 setup_local_APIC();
2552
2553 enable_IO_APIC();
2554 end_local_APIC_setup();
2555 irq_remap_enable_fault_handling();
2556 setup_IO_APIC();
2557}
2558
2559#ifdef CONFIG_UP_LATE_INIT
2560void __init up_late_init(void)
2561{
2562 if (apic_intr_mode == APIC_PIC)
2563 return;
2564
2565 /* Setup local timer */
2566 x86_init.timers.setup_percpu_clockev();
2567}
2568#endif
2569
2570/*
2571 * Power management
2572 */
2573#ifdef CONFIG_PM
2574
2575static struct {
2576 /*
2577 * 'active' is true if the local APIC was enabled by us and
2578 * not the BIOS; this signifies that we are also responsible
2579 * for disabling it before entering apm/acpi suspend
2580 */
2581 int active;
2582 /* r/w apic fields */
2583 unsigned int apic_id;
2584 unsigned int apic_taskpri;
2585 unsigned int apic_ldr;
2586 unsigned int apic_dfr;
2587 unsigned int apic_spiv;
2588 unsigned int apic_lvtt;
2589 unsigned int apic_lvtpc;
2590 unsigned int apic_lvt0;
2591 unsigned int apic_lvt1;
2592 unsigned int apic_lvterr;
2593 unsigned int apic_tmict;
2594 unsigned int apic_tdcr;
2595 unsigned int apic_thmr;
2596 unsigned int apic_cmci;
2597} apic_pm_state;
2598
2599static int lapic_suspend(void)
2600{
2601 unsigned long flags;
2602 int maxlvt;
2603
2604 if (!apic_pm_state.active)
2605 return 0;
2606
2607 maxlvt = lapic_get_maxlvt();
2608
2609 apic_pm_state.apic_id = apic_read(APIC_ID);
2610 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2611 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2612 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2613 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2614 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2615 if (maxlvt >= 4)
2616 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2617 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2618 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2619 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2620 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2621 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2622#ifdef CONFIG_X86_THERMAL_VECTOR
2623 if (maxlvt >= 5)
2624 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2625#endif
2626#ifdef CONFIG_X86_MCE_INTEL
2627 if (maxlvt >= 6)
2628 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2629#endif
2630
2631 local_irq_save(flags);
2632 disable_local_APIC();
2633
2634 irq_remapping_disable();
2635
2636 local_irq_restore(flags);
2637 return 0;
2638}
2639
2640static void lapic_resume(void)
2641{
2642 unsigned int l, h;
2643 unsigned long flags;
2644 int maxlvt;
2645
2646 if (!apic_pm_state.active)
2647 return;
2648
2649 local_irq_save(flags);
2650
2651 /*
2652 * IO-APIC and PIC have their own resume routines.
2653 * We just mask them here to make sure the interrupt
2654 * subsystem is completely quiet while we enable x2apic
2655 * and interrupt-remapping.
2656 */
2657 mask_ioapic_entries();
2658 legacy_pic->mask_all();
2659
2660 if (x2apic_mode) {
2661 __x2apic_enable();
2662 } else {
2663 /*
2664 * Make sure the APICBASE points to the right address
2665 *
2666 * FIXME! This will be wrong if we ever support suspend on
2667 * SMP! We'll need to do this as part of the CPU restore!
2668 */
2669 if (boot_cpu_data.x86 >= 6) {
2670 rdmsr(MSR_IA32_APICBASE, l, h);
2671 l &= ~MSR_IA32_APICBASE_BASE;
2672 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2673 wrmsr(MSR_IA32_APICBASE, l, h);
2674 }
2675 }
2676
2677 maxlvt = lapic_get_maxlvt();
2678 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2679 apic_write(APIC_ID, apic_pm_state.apic_id);
2680 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2681 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2682 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2683 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2684 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2685 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2686#ifdef CONFIG_X86_THERMAL_VECTOR
2687 if (maxlvt >= 5)
2688 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2689#endif
2690#ifdef CONFIG_X86_MCE_INTEL
2691 if (maxlvt >= 6)
2692 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2693#endif
2694 if (maxlvt >= 4)
2695 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2696 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2697 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2698 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2699 apic_write(APIC_ESR, 0);
2700 apic_read(APIC_ESR);
2701 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2702 apic_write(APIC_ESR, 0);
2703 apic_read(APIC_ESR);
2704
2705 irq_remapping_reenable(x2apic_mode);
2706
2707 local_irq_restore(flags);
2708}
2709
2710/*
2711 * This device has no shutdown method - fully functioning local APICs
2712 * are needed on every CPU up until machine_halt/restart/poweroff.
2713 */
2714
2715static struct syscore_ops lapic_syscore_ops = {
2716 .resume = lapic_resume,
2717 .suspend = lapic_suspend,
2718};
2719
2720static void apic_pm_activate(void)
2721{
2722 apic_pm_state.active = 1;
2723}
2724
2725static int __init init_lapic_sysfs(void)
2726{
2727 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2728 if (boot_cpu_has(X86_FEATURE_APIC))
2729 register_syscore_ops(&lapic_syscore_ops);
2730
2731 return 0;
2732}
2733
2734/* local apic needs to resume before other devices access its registers. */
2735core_initcall(init_lapic_sysfs);
2736
2737#else /* CONFIG_PM */
2738
2739static void apic_pm_activate(void) { }
2740
2741#endif /* CONFIG_PM */
2742
2743#ifdef CONFIG_X86_64
2744
2745static int multi_checked;
2746static int multi;
2747
2748static int set_multi(const struct dmi_system_id *d)
2749{
2750 if (multi)
2751 return 0;
2752 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2753 multi = 1;
2754 return 0;
2755}
2756
2757static const struct dmi_system_id multi_dmi_table[] = {
2758 {
2759 .callback = set_multi,
2760 .ident = "IBM System Summit2",
2761 .matches = {
2762 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2763 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2764 },
2765 },
2766 {}
2767};
2768
2769static void dmi_check_multi(void)
2770{
2771 if (multi_checked)
2772 return;
2773
2774 dmi_check_system(multi_dmi_table);
2775 multi_checked = 1;
2776}
2777
2778/*
2779 * apic_is_clustered_box() -- Check if we can expect good TSC
2780 *
2781 * Thus far, the major user of this is IBM's Summit2 series:
2782 * Clustered boxes may have unsynced TSC problems if they are
2783 * multi-chassis.
2784 * Use DMI to check them
2785 */
2786int apic_is_clustered_box(void)
2787{
2788 dmi_check_multi();
2789 return multi;
2790}
2791#endif
2792
2793/*
2794 * APIC command line parameters
2795 */
2796static int __init setup_disableapic(char *arg)
2797{
2798 disable_apic = 1;
2799 setup_clear_cpu_cap(X86_FEATURE_APIC);
2800 return 0;
2801}
2802early_param("disableapic", setup_disableapic);
2803
2804/* same as disableapic, for compatibility */
2805static int __init setup_nolapic(char *arg)
2806{
2807 return setup_disableapic(arg);
2808}
2809early_param("nolapic", setup_nolapic);
2810
2811static int __init parse_lapic_timer_c2_ok(char *arg)
2812{
2813 local_apic_timer_c2_ok = 1;
2814 return 0;
2815}
2816early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2817
2818static int __init parse_disable_apic_timer(char *arg)
2819{
2820 disable_apic_timer = 1;
2821 return 0;
2822}
2823early_param("noapictimer", parse_disable_apic_timer);
2824
2825static int __init parse_nolapic_timer(char *arg)
2826{
2827 disable_apic_timer = 1;
2828 return 0;
2829}
2830early_param("nolapic_timer", parse_nolapic_timer);
2831
2832static int __init apic_set_verbosity(char *arg)
2833{
2834 if (!arg) {
2835#ifdef CONFIG_X86_64
2836 skip_ioapic_setup = 0;
2837 return 0;
2838#endif
2839 return -EINVAL;
2840 }
2841
2842 if (strcmp("debug", arg) == 0)
2843 apic_verbosity = APIC_DEBUG;
2844 else if (strcmp("verbose", arg) == 0)
2845 apic_verbosity = APIC_VERBOSE;
2846#ifdef CONFIG_X86_64
2847 else {
2848 pr_warning("APIC Verbosity level %s not recognised"
2849 " use apic=verbose or apic=debug\n", arg);
2850 return -EINVAL;
2851 }
2852#endif
2853
2854 return 0;
2855}
2856early_param("apic", apic_set_verbosity);
2857
2858static int __init lapic_insert_resource(void)
2859{
2860 if (!apic_phys)
2861 return -1;
2862
2863 /* Put local APIC into the resource map. */
2864 lapic_resource.start = apic_phys;
2865 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2866 insert_resource(&iomem_resource, &lapic_resource);
2867
2868 return 0;
2869}
2870
2871/*
2872 * need call insert after e820__reserve_resources()
2873 * that is using request_resource
2874 */
2875late_initcall(lapic_insert_resource);
2876
2877static int __init apic_set_disabled_cpu_apicid(char *arg)
2878{
2879 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2880 return -EINVAL;
2881
2882 return 0;
2883}
2884early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2885
2886static int __init apic_set_extnmi(char *arg)
2887{
2888 if (!arg)
2889 return -EINVAL;
2890
2891 if (!strncmp("all", arg, 3))
2892 apic_extnmi = APIC_EXTNMI_ALL;
2893 else if (!strncmp("none", arg, 4))
2894 apic_extnmi = APIC_EXTNMI_NONE;
2895 else if (!strncmp("bsp", arg, 3))
2896 apic_extnmi = APIC_EXTNMI_BSP;
2897 else {
2898 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2899 return -EINVAL;
2900 }
2901
2902 return 0;
2903}
2904early_param("apic_extnmi", apic_set_extnmi);
1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/perf_event.h>
18#include <linux/kernel_stat.h>
19#include <linux/mc146818rtc.h>
20#include <linux/acpi_pmtmr.h>
21#include <linux/clockchips.h>
22#include <linux/interrupt.h>
23#include <linux/bootmem.h>
24#include <linux/ftrace.h>
25#include <linux/ioport.h>
26#include <linux/export.h>
27#include <linux/syscore_ops.h>
28#include <linux/delay.h>
29#include <linux/timex.h>
30#include <linux/i8253.h>
31#include <linux/dmar.h>
32#include <linux/init.h>
33#include <linux/cpu.h>
34#include <linux/dmi.h>
35#include <linux/smp.h>
36#include <linux/mm.h>
37
38#include <asm/trace/irq_vectors.h>
39#include <asm/irq_remapping.h>
40#include <asm/perf_event.h>
41#include <asm/x86_init.h>
42#include <asm/pgalloc.h>
43#include <linux/atomic.h>
44#include <asm/mpspec.h>
45#include <asm/i8259.h>
46#include <asm/proto.h>
47#include <asm/apic.h>
48#include <asm/io_apic.h>
49#include <asm/desc.h>
50#include <asm/hpet.h>
51#include <asm/mtrr.h>
52#include <asm/time.h>
53#include <asm/smp.h>
54#include <asm/mce.h>
55#include <asm/tsc.h>
56#include <asm/hypervisor.h>
57
58unsigned int num_processors;
59
60unsigned disabled_cpus;
61
62/* Processor that is doing the boot up */
63unsigned int boot_cpu_physical_apicid = -1U;
64EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
65
66u8 boot_cpu_apic_version;
67
68/*
69 * The highest APIC ID seen during enumeration.
70 */
71static unsigned int max_physical_apicid;
72
73/*
74 * Bitmask of physically existing CPUs:
75 */
76physid_mask_t phys_cpu_present_map;
77
78/*
79 * Processor to be disabled specified by kernel parameter
80 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
81 * avoid undefined behaviour caused by sending INIT from AP to BSP.
82 */
83static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
84
85/*
86 * This variable controls which CPUs receive external NMIs. By default,
87 * external NMIs are delivered only to the BSP.
88 */
89static int apic_extnmi = APIC_EXTNMI_BSP;
90
91/*
92 * Map cpu index to physical APIC ID
93 */
94DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
95DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
96DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
97EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
98EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
99EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
100
101#ifdef CONFIG_X86_32
102
103/*
104 * On x86_32, the mapping between cpu and logical apicid may vary
105 * depending on apic in use. The following early percpu variable is
106 * used for the mapping. This is where the behaviors of x86_64 and 32
107 * actually diverge. Let's keep it ugly for now.
108 */
109DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
110
111/* Local APIC was disabled by the BIOS and enabled by the kernel */
112static int enabled_via_apicbase;
113
114/*
115 * Handle interrupt mode configuration register (IMCR).
116 * This register controls whether the interrupt signals
117 * that reach the BSP come from the master PIC or from the
118 * local APIC. Before entering Symmetric I/O Mode, either
119 * the BIOS or the operating system must switch out of
120 * PIC Mode by changing the IMCR.
121 */
122static inline void imcr_pic_to_apic(void)
123{
124 /* select IMCR register */
125 outb(0x70, 0x22);
126 /* NMI and 8259 INTR go through APIC */
127 outb(0x01, 0x23);
128}
129
130static inline void imcr_apic_to_pic(void)
131{
132 /* select IMCR register */
133 outb(0x70, 0x22);
134 /* NMI and 8259 INTR go directly to BSP */
135 outb(0x00, 0x23);
136}
137#endif
138
139/*
140 * Knob to control our willingness to enable the local APIC.
141 *
142 * +1=force-enable
143 */
144static int force_enable_local_apic __initdata;
145
146/*
147 * APIC command line parameters
148 */
149static int __init parse_lapic(char *arg)
150{
151 if (IS_ENABLED(CONFIG_X86_32) && !arg)
152 force_enable_local_apic = 1;
153 else if (arg && !strncmp(arg, "notscdeadline", 13))
154 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
155 return 0;
156}
157early_param("lapic", parse_lapic);
158
159#ifdef CONFIG_X86_64
160static int apic_calibrate_pmtmr __initdata;
161static __init int setup_apicpmtimer(char *s)
162{
163 apic_calibrate_pmtmr = 1;
164 notsc_setup(NULL);
165 return 0;
166}
167__setup("apicpmtimer", setup_apicpmtimer);
168#endif
169
170unsigned long mp_lapic_addr;
171int disable_apic;
172/* Disable local APIC timer from the kernel commandline or via dmi quirk */
173static int disable_apic_timer __initdata;
174/* Local APIC timer works in C2 */
175int local_apic_timer_c2_ok;
176EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
177
178int first_system_vector = FIRST_SYSTEM_VECTOR;
179
180/*
181 * Debug level, exported for io_apic.c
182 */
183unsigned int apic_verbosity;
184
185int pic_mode;
186
187/* Have we found an MP table */
188int smp_found_config;
189
190static struct resource lapic_resource = {
191 .name = "Local APIC",
192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
193};
194
195unsigned int lapic_timer_frequency = 0;
196
197static void apic_pm_activate(void);
198
199static unsigned long apic_phys;
200
201/*
202 * Get the LAPIC version
203 */
204static inline int lapic_get_version(void)
205{
206 return GET_APIC_VERSION(apic_read(APIC_LVR));
207}
208
209/*
210 * Check, if the APIC is integrated or a separate chip
211 */
212static inline int lapic_is_integrated(void)
213{
214#ifdef CONFIG_X86_64
215 return 1;
216#else
217 return APIC_INTEGRATED(lapic_get_version());
218#endif
219}
220
221/*
222 * Check, whether this is a modern or a first generation APIC
223 */
224static int modern_apic(void)
225{
226 /* AMD systems use old APIC versions, so check the CPU */
227 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
228 boot_cpu_data.x86 >= 0xf)
229 return 1;
230 return lapic_get_version() >= 0x14;
231}
232
233/*
234 * right after this call apic become NOOP driven
235 * so apic->write/read doesn't do anything
236 */
237static void __init apic_disable(void)
238{
239 pr_info("APIC: switched to apic NOOP\n");
240 apic = &apic_noop;
241}
242
243void native_apic_wait_icr_idle(void)
244{
245 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
246 cpu_relax();
247}
248
249u32 native_safe_apic_wait_icr_idle(void)
250{
251 u32 send_status;
252 int timeout;
253
254 timeout = 0;
255 do {
256 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
257 if (!send_status)
258 break;
259 inc_irq_stat(icr_read_retry_count);
260 udelay(100);
261 } while (timeout++ < 1000);
262
263 return send_status;
264}
265
266void native_apic_icr_write(u32 low, u32 id)
267{
268 unsigned long flags;
269
270 local_irq_save(flags);
271 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
272 apic_write(APIC_ICR, low);
273 local_irq_restore(flags);
274}
275
276u64 native_apic_icr_read(void)
277{
278 u32 icr1, icr2;
279
280 icr2 = apic_read(APIC_ICR2);
281 icr1 = apic_read(APIC_ICR);
282
283 return icr1 | ((u64)icr2 << 32);
284}
285
286#ifdef CONFIG_X86_32
287/**
288 * get_physical_broadcast - Get number of physical broadcast IDs
289 */
290int get_physical_broadcast(void)
291{
292 return modern_apic() ? 0xff : 0xf;
293}
294#endif
295
296/**
297 * lapic_get_maxlvt - get the maximum number of local vector table entries
298 */
299int lapic_get_maxlvt(void)
300{
301 unsigned int v;
302
303 v = apic_read(APIC_LVR);
304 /*
305 * - we always have APIC integrated on 64bit mode
306 * - 82489DXs do not report # of LVT entries
307 */
308 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
309}
310
311/*
312 * Local APIC timer
313 */
314
315/* Clock divisor */
316#define APIC_DIVISOR 16
317#define TSC_DIVISOR 8
318
319/*
320 * This function sets up the local APIC timer, with a timeout of
321 * 'clocks' APIC bus clock. During calibration we actually call
322 * this function twice on the boot CPU, once with a bogus timeout
323 * value, second time for real. The other (noncalibrating) CPUs
324 * call this function only once, with the real, calibrated value.
325 *
326 * We do reads before writes even if unnecessary, to get around the
327 * P5 APIC double write bug.
328 */
329static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
330{
331 unsigned int lvtt_value, tmp_value;
332
333 lvtt_value = LOCAL_TIMER_VECTOR;
334 if (!oneshot)
335 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
338
339 if (!lapic_is_integrated())
340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
341
342 if (!irqen)
343 lvtt_value |= APIC_LVT_MASKED;
344
345 apic_write(APIC_LVTT, lvtt_value);
346
347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
348 /*
349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
351 * According to Intel, MFENCE can do the serialization here.
352 */
353 asm volatile("mfence" : : : "memory");
354
355 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
356 return;
357 }
358
359 /*
360 * Divide PICLK by 16
361 */
362 tmp_value = apic_read(APIC_TDCR);
363 apic_write(APIC_TDCR,
364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
365 APIC_TDR_DIV_16);
366
367 if (!oneshot)
368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
369}
370
371/*
372 * Setup extended LVT, AMD specific
373 *
374 * Software should use the LVT offsets the BIOS provides. The offsets
375 * are determined by the subsystems using it like those for MCE
376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
377 * are supported. Beginning with family 10h at least 4 offsets are
378 * available.
379 *
380 * Since the offsets must be consistent for all cores, we keep track
381 * of the LVT offsets in software and reserve the offset for the same
382 * vector also to be used on other cores. An offset is freed by
383 * setting the entry to APIC_EILVT_MASKED.
384 *
385 * If the BIOS is right, there should be no conflicts. Otherwise a
386 * "[Firmware Bug]: ..." error message is generated. However, if
387 * software does not properly determines the offsets, it is not
388 * necessarily a BIOS bug.
389 */
390
391static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
392
393static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
394{
395 return (old & APIC_EILVT_MASKED)
396 || (new == APIC_EILVT_MASKED)
397 || ((new & ~APIC_EILVT_MASKED) == old);
398}
399
400static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
401{
402 unsigned int rsvd, vector;
403
404 if (offset >= APIC_EILVT_NR_MAX)
405 return ~0;
406
407 rsvd = atomic_read(&eilvt_offsets[offset]);
408 do {
409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
410 if (vector && !eilvt_entry_is_changeable(vector, new))
411 /* may not change if vectors are different */
412 return rsvd;
413 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
414 } while (rsvd != new);
415
416 rsvd &= ~APIC_EILVT_MASKED;
417 if (rsvd && rsvd != vector)
418 pr_info("LVT offset %d assigned for vector 0x%02x\n",
419 offset, rsvd);
420
421 return new;
422}
423
424/*
425 * If mask=1, the LVT entry does not generate interrupts while mask=0
426 * enables the vector. See also the BKDGs. Must be called with
427 * preemption disabled.
428 */
429
430int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
431{
432 unsigned long reg = APIC_EILVTn(offset);
433 unsigned int new, old, reserved;
434
435 new = (mask << 16) | (msg_type << 8) | vector;
436 old = apic_read(reg);
437 reserved = reserve_eilvt_offset(offset, new);
438
439 if (reserved != new) {
440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
441 "vector 0x%x, but the register is already in use for "
442 "vector 0x%x on another cpu\n",
443 smp_processor_id(), reg, offset, new, reserved);
444 return -EINVAL;
445 }
446
447 if (!eilvt_entry_is_changeable(old, new)) {
448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
449 "vector 0x%x, but the register is already in use for "
450 "vector 0x%x on this cpu\n",
451 smp_processor_id(), reg, offset, new, old);
452 return -EBUSY;
453 }
454
455 apic_write(reg, new);
456
457 return 0;
458}
459EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
460
461/*
462 * Program the next event, relative to now
463 */
464static int lapic_next_event(unsigned long delta,
465 struct clock_event_device *evt)
466{
467 apic_write(APIC_TMICT, delta);
468 return 0;
469}
470
471static int lapic_next_deadline(unsigned long delta,
472 struct clock_event_device *evt)
473{
474 u64 tsc;
475
476 tsc = rdtsc();
477 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
478 return 0;
479}
480
481static int lapic_timer_shutdown(struct clock_event_device *evt)
482{
483 unsigned int v;
484
485 /* Lapic used as dummy for broadcast ? */
486 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
487 return 0;
488
489 v = apic_read(APIC_LVTT);
490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
491 apic_write(APIC_LVTT, v);
492 apic_write(APIC_TMICT, 0);
493 return 0;
494}
495
496static inline int
497lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
498{
499 /* Lapic used as dummy for broadcast ? */
500 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
501 return 0;
502
503 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
504 return 0;
505}
506
507static int lapic_timer_set_periodic(struct clock_event_device *evt)
508{
509 return lapic_timer_set_periodic_oneshot(evt, false);
510}
511
512static int lapic_timer_set_oneshot(struct clock_event_device *evt)
513{
514 return lapic_timer_set_periodic_oneshot(evt, true);
515}
516
517/*
518 * Local APIC timer broadcast function
519 */
520static void lapic_timer_broadcast(const struct cpumask *mask)
521{
522#ifdef CONFIG_SMP
523 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
524#endif
525}
526
527
528/*
529 * The local apic timer can be used for any function which is CPU local.
530 */
531static struct clock_event_device lapic_clockevent = {
532 .name = "lapic",
533 .features = CLOCK_EVT_FEAT_PERIODIC |
534 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
535 | CLOCK_EVT_FEAT_DUMMY,
536 .shift = 32,
537 .set_state_shutdown = lapic_timer_shutdown,
538 .set_state_periodic = lapic_timer_set_periodic,
539 .set_state_oneshot = lapic_timer_set_oneshot,
540 .set_next_event = lapic_next_event,
541 .broadcast = lapic_timer_broadcast,
542 .rating = 100,
543 .irq = -1,
544};
545static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
546
547/*
548 * Setup the local APIC timer for this CPU. Copy the initialized values
549 * of the boot CPU and register the clock event in the framework.
550 */
551static void setup_APIC_timer(void)
552{
553 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
554
555 if (this_cpu_has(X86_FEATURE_ARAT)) {
556 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
557 /* Make LAPIC timer preferrable over percpu HPET */
558 lapic_clockevent.rating = 150;
559 }
560
561 memcpy(levt, &lapic_clockevent, sizeof(*levt));
562 levt->cpumask = cpumask_of(smp_processor_id());
563
564 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
565 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
566 CLOCK_EVT_FEAT_DUMMY);
567 levt->set_next_event = lapic_next_deadline;
568 clockevents_config_and_register(levt,
569 tsc_khz * (1000 / TSC_DIVISOR),
570 0xF, ~0UL);
571 } else
572 clockevents_register_device(levt);
573}
574
575/*
576 * Install the updated TSC frequency from recalibration at the TSC
577 * deadline clockevent devices.
578 */
579static void __lapic_update_tsc_freq(void *info)
580{
581 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
582
583 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
584 return;
585
586 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
587}
588
589void lapic_update_tsc_freq(void)
590{
591 /*
592 * The clockevent device's ->mult and ->shift can both be
593 * changed. In order to avoid races, schedule the frequency
594 * update code on each CPU.
595 */
596 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
597}
598
599/*
600 * In this functions we calibrate APIC bus clocks to the external timer.
601 *
602 * We want to do the calibration only once since we want to have local timer
603 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
604 * frequency.
605 *
606 * This was previously done by reading the PIT/HPET and waiting for a wrap
607 * around to find out, that a tick has elapsed. I have a box, where the PIT
608 * readout is broken, so it never gets out of the wait loop again. This was
609 * also reported by others.
610 *
611 * Monitoring the jiffies value is inaccurate and the clockevents
612 * infrastructure allows us to do a simple substitution of the interrupt
613 * handler.
614 *
615 * The calibration routine also uses the pm_timer when possible, as the PIT
616 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
617 * back to normal later in the boot process).
618 */
619
620#define LAPIC_CAL_LOOPS (HZ/10)
621
622static __initdata int lapic_cal_loops = -1;
623static __initdata long lapic_cal_t1, lapic_cal_t2;
624static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
625static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
626static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
627
628/*
629 * Temporary interrupt handler.
630 */
631static void __init lapic_cal_handler(struct clock_event_device *dev)
632{
633 unsigned long long tsc = 0;
634 long tapic = apic_read(APIC_TMCCT);
635 unsigned long pm = acpi_pm_read_early();
636
637 if (boot_cpu_has(X86_FEATURE_TSC))
638 tsc = rdtsc();
639
640 switch (lapic_cal_loops++) {
641 case 0:
642 lapic_cal_t1 = tapic;
643 lapic_cal_tsc1 = tsc;
644 lapic_cal_pm1 = pm;
645 lapic_cal_j1 = jiffies;
646 break;
647
648 case LAPIC_CAL_LOOPS:
649 lapic_cal_t2 = tapic;
650 lapic_cal_tsc2 = tsc;
651 if (pm < lapic_cal_pm1)
652 pm += ACPI_PM_OVRRUN;
653 lapic_cal_pm2 = pm;
654 lapic_cal_j2 = jiffies;
655 break;
656 }
657}
658
659static int __init
660calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
661{
662 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
663 const long pm_thresh = pm_100ms / 100;
664 unsigned long mult;
665 u64 res;
666
667#ifndef CONFIG_X86_PM_TIMER
668 return -1;
669#endif
670
671 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
672
673 /* Check, if the PM timer is available */
674 if (!deltapm)
675 return -1;
676
677 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
678
679 if (deltapm > (pm_100ms - pm_thresh) &&
680 deltapm < (pm_100ms + pm_thresh)) {
681 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
682 return 0;
683 }
684
685 res = (((u64)deltapm) * mult) >> 22;
686 do_div(res, 1000000);
687 pr_warning("APIC calibration not consistent "
688 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
689
690 /* Correct the lapic counter value */
691 res = (((u64)(*delta)) * pm_100ms);
692 do_div(res, deltapm);
693 pr_info("APIC delta adjusted to PM-Timer: "
694 "%lu (%ld)\n", (unsigned long)res, *delta);
695 *delta = (long)res;
696
697 /* Correct the tsc counter value */
698 if (boot_cpu_has(X86_FEATURE_TSC)) {
699 res = (((u64)(*deltatsc)) * pm_100ms);
700 do_div(res, deltapm);
701 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
702 "PM-Timer: %lu (%ld)\n",
703 (unsigned long)res, *deltatsc);
704 *deltatsc = (long)res;
705 }
706
707 return 0;
708}
709
710static int __init calibrate_APIC_clock(void)
711{
712 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
713 void (*real_handler)(struct clock_event_device *dev);
714 unsigned long deltaj;
715 long delta, deltatsc;
716 int pm_referenced = 0;
717
718 /**
719 * check if lapic timer has already been calibrated by platform
720 * specific routine, such as tsc calibration code. if so, we just fill
721 * in the clockevent structure and return.
722 */
723
724 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
725 return 0;
726 } else if (lapic_timer_frequency) {
727 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
728 lapic_timer_frequency);
729 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
730 TICK_NSEC, lapic_clockevent.shift);
731 lapic_clockevent.max_delta_ns =
732 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
733 lapic_clockevent.min_delta_ns =
734 clockevent_delta2ns(0xF, &lapic_clockevent);
735 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
736 return 0;
737 }
738
739 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
740 "calibrating APIC timer ...\n");
741
742 local_irq_disable();
743
744 /* Replace the global interrupt handler */
745 real_handler = global_clock_event->event_handler;
746 global_clock_event->event_handler = lapic_cal_handler;
747
748 /*
749 * Setup the APIC counter to maximum. There is no way the lapic
750 * can underflow in the 100ms detection time frame
751 */
752 __setup_APIC_LVTT(0xffffffff, 0, 0);
753
754 /* Let the interrupts run */
755 local_irq_enable();
756
757 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
758 cpu_relax();
759
760 local_irq_disable();
761
762 /* Restore the real event handler */
763 global_clock_event->event_handler = real_handler;
764
765 /* Build delta t1-t2 as apic timer counts down */
766 delta = lapic_cal_t1 - lapic_cal_t2;
767 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
768
769 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
770
771 /* we trust the PM based calibration if possible */
772 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
773 &delta, &deltatsc);
774
775 /* Calculate the scaled math multiplication factor */
776 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
777 lapic_clockevent.shift);
778 lapic_clockevent.max_delta_ns =
779 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
780 lapic_clockevent.min_delta_ns =
781 clockevent_delta2ns(0xF, &lapic_clockevent);
782
783 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
784
785 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
786 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
787 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
788 lapic_timer_frequency);
789
790 if (boot_cpu_has(X86_FEATURE_TSC)) {
791 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
792 "%ld.%04ld MHz.\n",
793 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
794 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
795 }
796
797 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
798 "%u.%04u MHz.\n",
799 lapic_timer_frequency / (1000000 / HZ),
800 lapic_timer_frequency % (1000000 / HZ));
801
802 /*
803 * Do a sanity check on the APIC calibration result
804 */
805 if (lapic_timer_frequency < (1000000 / HZ)) {
806 local_irq_enable();
807 pr_warning("APIC frequency too slow, disabling apic timer\n");
808 return -1;
809 }
810
811 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
812
813 /*
814 * PM timer calibration failed or not turned on
815 * so lets try APIC timer based calibration
816 */
817 if (!pm_referenced) {
818 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
819
820 /*
821 * Setup the apic timer manually
822 */
823 levt->event_handler = lapic_cal_handler;
824 lapic_timer_set_periodic(levt);
825 lapic_cal_loops = -1;
826
827 /* Let the interrupts run */
828 local_irq_enable();
829
830 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
831 cpu_relax();
832
833 /* Stop the lapic timer */
834 local_irq_disable();
835 lapic_timer_shutdown(levt);
836
837 /* Jiffies delta */
838 deltaj = lapic_cal_j2 - lapic_cal_j1;
839 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
840
841 /* Check, if the jiffies result is consistent */
842 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
843 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
844 else
845 levt->features |= CLOCK_EVT_FEAT_DUMMY;
846 }
847 local_irq_enable();
848
849 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
850 pr_warning("APIC timer disabled due to verification failure\n");
851 return -1;
852 }
853
854 return 0;
855}
856
857/*
858 * Setup the boot APIC
859 *
860 * Calibrate and verify the result.
861 */
862void __init setup_boot_APIC_clock(void)
863{
864 /*
865 * The local apic timer can be disabled via the kernel
866 * commandline or from the CPU detection code. Register the lapic
867 * timer as a dummy clock event source on SMP systems, so the
868 * broadcast mechanism is used. On UP systems simply ignore it.
869 */
870 if (disable_apic_timer) {
871 pr_info("Disabling APIC timer\n");
872 /* No broadcast on UP ! */
873 if (num_possible_cpus() > 1) {
874 lapic_clockevent.mult = 1;
875 setup_APIC_timer();
876 }
877 return;
878 }
879
880 if (calibrate_APIC_clock()) {
881 /* No broadcast on UP ! */
882 if (num_possible_cpus() > 1)
883 setup_APIC_timer();
884 return;
885 }
886
887 /*
888 * If nmi_watchdog is set to IO_APIC, we need the
889 * PIT/HPET going. Otherwise register lapic as a dummy
890 * device.
891 */
892 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
893
894 /* Setup the lapic or request the broadcast */
895 setup_APIC_timer();
896 amd_e400_c1e_apic_setup();
897}
898
899void setup_secondary_APIC_clock(void)
900{
901 setup_APIC_timer();
902 amd_e400_c1e_apic_setup();
903}
904
905/*
906 * The guts of the apic timer interrupt
907 */
908static void local_apic_timer_interrupt(void)
909{
910 int cpu = smp_processor_id();
911 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
912
913 /*
914 * Normally we should not be here till LAPIC has been initialized but
915 * in some cases like kdump, its possible that there is a pending LAPIC
916 * timer interrupt from previous kernel's context and is delivered in
917 * new kernel the moment interrupts are enabled.
918 *
919 * Interrupts are enabled early and LAPIC is setup much later, hence
920 * its possible that when we get here evt->event_handler is NULL.
921 * Check for event_handler being NULL and discard the interrupt as
922 * spurious.
923 */
924 if (!evt->event_handler) {
925 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
926 /* Switch it off */
927 lapic_timer_shutdown(evt);
928 return;
929 }
930
931 /*
932 * the NMI deadlock-detector uses this.
933 */
934 inc_irq_stat(apic_timer_irqs);
935
936 evt->event_handler(evt);
937}
938
939/*
940 * Local APIC timer interrupt. This is the most natural way for doing
941 * local interrupts, but local timer interrupts can be emulated by
942 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
943 *
944 * [ if a single-CPU system runs an SMP kernel then we call the local
945 * interrupt as well. Thus we cannot inline the local irq ... ]
946 */
947__visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
948{
949 struct pt_regs *old_regs = set_irq_regs(regs);
950
951 /*
952 * NOTE! We'd better ACK the irq immediately,
953 * because timer handling can be slow.
954 *
955 * update_process_times() expects us to have done irq_enter().
956 * Besides, if we don't timer interrupts ignore the global
957 * interrupt lock, which is the WrongThing (tm) to do.
958 */
959 entering_ack_irq();
960 local_apic_timer_interrupt();
961 exiting_irq();
962
963 set_irq_regs(old_regs);
964}
965
966__visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
967{
968 struct pt_regs *old_regs = set_irq_regs(regs);
969
970 /*
971 * NOTE! We'd better ACK the irq immediately,
972 * because timer handling can be slow.
973 *
974 * update_process_times() expects us to have done irq_enter().
975 * Besides, if we don't timer interrupts ignore the global
976 * interrupt lock, which is the WrongThing (tm) to do.
977 */
978 entering_ack_irq();
979 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
980 local_apic_timer_interrupt();
981 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
982 exiting_irq();
983
984 set_irq_regs(old_regs);
985}
986
987int setup_profiling_timer(unsigned int multiplier)
988{
989 return -EINVAL;
990}
991
992/*
993 * Local APIC start and shutdown
994 */
995
996/**
997 * clear_local_APIC - shutdown the local APIC
998 *
999 * This is called, when a CPU is disabled and before rebooting, so the state of
1000 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1001 * leftovers during boot.
1002 */
1003void clear_local_APIC(void)
1004{
1005 int maxlvt;
1006 u32 v;
1007
1008 /* APIC hasn't been mapped yet */
1009 if (!x2apic_mode && !apic_phys)
1010 return;
1011
1012 maxlvt = lapic_get_maxlvt();
1013 /*
1014 * Masking an LVT entry can trigger a local APIC error
1015 * if the vector is zero. Mask LVTERR first to prevent this.
1016 */
1017 if (maxlvt >= 3) {
1018 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1019 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1020 }
1021 /*
1022 * Careful: we have to set masks only first to deassert
1023 * any level-triggered sources.
1024 */
1025 v = apic_read(APIC_LVTT);
1026 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1027 v = apic_read(APIC_LVT0);
1028 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1029 v = apic_read(APIC_LVT1);
1030 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1031 if (maxlvt >= 4) {
1032 v = apic_read(APIC_LVTPC);
1033 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1034 }
1035
1036 /* lets not touch this if we didn't frob it */
1037#ifdef CONFIG_X86_THERMAL_VECTOR
1038 if (maxlvt >= 5) {
1039 v = apic_read(APIC_LVTTHMR);
1040 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1041 }
1042#endif
1043#ifdef CONFIG_X86_MCE_INTEL
1044 if (maxlvt >= 6) {
1045 v = apic_read(APIC_LVTCMCI);
1046 if (!(v & APIC_LVT_MASKED))
1047 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1048 }
1049#endif
1050
1051 /*
1052 * Clean APIC state for other OSs:
1053 */
1054 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1055 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1056 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1057 if (maxlvt >= 3)
1058 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1059 if (maxlvt >= 4)
1060 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1061
1062 /* Integrated APIC (!82489DX) ? */
1063 if (lapic_is_integrated()) {
1064 if (maxlvt > 3)
1065 /* Clear ESR due to Pentium errata 3AP and 11AP */
1066 apic_write(APIC_ESR, 0);
1067 apic_read(APIC_ESR);
1068 }
1069}
1070
1071/**
1072 * disable_local_APIC - clear and disable the local APIC
1073 */
1074void disable_local_APIC(void)
1075{
1076 unsigned int value;
1077
1078 /* APIC hasn't been mapped yet */
1079 if (!x2apic_mode && !apic_phys)
1080 return;
1081
1082 clear_local_APIC();
1083
1084 /*
1085 * Disable APIC (implies clearing of registers
1086 * for 82489DX!).
1087 */
1088 value = apic_read(APIC_SPIV);
1089 value &= ~APIC_SPIV_APIC_ENABLED;
1090 apic_write(APIC_SPIV, value);
1091
1092#ifdef CONFIG_X86_32
1093 /*
1094 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1095 * restore the disabled state.
1096 */
1097 if (enabled_via_apicbase) {
1098 unsigned int l, h;
1099
1100 rdmsr(MSR_IA32_APICBASE, l, h);
1101 l &= ~MSR_IA32_APICBASE_ENABLE;
1102 wrmsr(MSR_IA32_APICBASE, l, h);
1103 }
1104#endif
1105}
1106
1107/*
1108 * If Linux enabled the LAPIC against the BIOS default disable it down before
1109 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1110 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1111 * for the case where Linux didn't enable the LAPIC.
1112 */
1113void lapic_shutdown(void)
1114{
1115 unsigned long flags;
1116
1117 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1118 return;
1119
1120 local_irq_save(flags);
1121
1122#ifdef CONFIG_X86_32
1123 if (!enabled_via_apicbase)
1124 clear_local_APIC();
1125 else
1126#endif
1127 disable_local_APIC();
1128
1129
1130 local_irq_restore(flags);
1131}
1132
1133/**
1134 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1135 */
1136void __init sync_Arb_IDs(void)
1137{
1138 /*
1139 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1140 * needed on AMD.
1141 */
1142 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1143 return;
1144
1145 /*
1146 * Wait for idle.
1147 */
1148 apic_wait_icr_idle();
1149
1150 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1151 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1152 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1153}
1154
1155/*
1156 * An initial setup of the virtual wire mode.
1157 */
1158void __init init_bsp_APIC(void)
1159{
1160 unsigned int value;
1161
1162 /*
1163 * Don't do the setup now if we have a SMP BIOS as the
1164 * through-I/O-APIC virtual wire mode might be active.
1165 */
1166 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1167 return;
1168
1169 /*
1170 * Do not trust the local APIC being empty at bootup.
1171 */
1172 clear_local_APIC();
1173
1174 /*
1175 * Enable APIC.
1176 */
1177 value = apic_read(APIC_SPIV);
1178 value &= ~APIC_VECTOR_MASK;
1179 value |= APIC_SPIV_APIC_ENABLED;
1180
1181#ifdef CONFIG_X86_32
1182 /* This bit is reserved on P4/Xeon and should be cleared */
1183 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1184 (boot_cpu_data.x86 == 15))
1185 value &= ~APIC_SPIV_FOCUS_DISABLED;
1186 else
1187#endif
1188 value |= APIC_SPIV_FOCUS_DISABLED;
1189 value |= SPURIOUS_APIC_VECTOR;
1190 apic_write(APIC_SPIV, value);
1191
1192 /*
1193 * Set up the virtual wire mode.
1194 */
1195 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1196 value = APIC_DM_NMI;
1197 if (!lapic_is_integrated()) /* 82489DX */
1198 value |= APIC_LVT_LEVEL_TRIGGER;
1199 if (apic_extnmi == APIC_EXTNMI_NONE)
1200 value |= APIC_LVT_MASKED;
1201 apic_write(APIC_LVT1, value);
1202}
1203
1204static void lapic_setup_esr(void)
1205{
1206 unsigned int oldvalue, value, maxlvt;
1207
1208 if (!lapic_is_integrated()) {
1209 pr_info("No ESR for 82489DX.\n");
1210 return;
1211 }
1212
1213 if (apic->disable_esr) {
1214 /*
1215 * Something untraceable is creating bad interrupts on
1216 * secondary quads ... for the moment, just leave the
1217 * ESR disabled - we can't do anything useful with the
1218 * errors anyway - mbligh
1219 */
1220 pr_info("Leaving ESR disabled.\n");
1221 return;
1222 }
1223
1224 maxlvt = lapic_get_maxlvt();
1225 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1226 apic_write(APIC_ESR, 0);
1227 oldvalue = apic_read(APIC_ESR);
1228
1229 /* enables sending errors */
1230 value = ERROR_APIC_VECTOR;
1231 apic_write(APIC_LVTERR, value);
1232
1233 /*
1234 * spec says clear errors after enabling vector.
1235 */
1236 if (maxlvt > 3)
1237 apic_write(APIC_ESR, 0);
1238 value = apic_read(APIC_ESR);
1239 if (value != oldvalue)
1240 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1241 "vector: 0x%08x after: 0x%08x\n",
1242 oldvalue, value);
1243}
1244
1245/**
1246 * setup_local_APIC - setup the local APIC
1247 *
1248 * Used to setup local APIC while initializing BSP or bringin up APs.
1249 * Always called with preemption disabled.
1250 */
1251void setup_local_APIC(void)
1252{
1253 int cpu = smp_processor_id();
1254 unsigned int value, queued;
1255 int i, j, acked = 0;
1256 unsigned long long tsc = 0, ntsc;
1257 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1258
1259 if (boot_cpu_has(X86_FEATURE_TSC))
1260 tsc = rdtsc();
1261
1262 if (disable_apic) {
1263 disable_ioapic_support();
1264 return;
1265 }
1266
1267#ifdef CONFIG_X86_32
1268 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1269 if (lapic_is_integrated() && apic->disable_esr) {
1270 apic_write(APIC_ESR, 0);
1271 apic_write(APIC_ESR, 0);
1272 apic_write(APIC_ESR, 0);
1273 apic_write(APIC_ESR, 0);
1274 }
1275#endif
1276 perf_events_lapic_init();
1277
1278 /*
1279 * Double-check whether this APIC is really registered.
1280 * This is meaningless in clustered apic mode, so we skip it.
1281 */
1282 BUG_ON(!apic->apic_id_registered());
1283
1284 /*
1285 * Intel recommends to set DFR, LDR and TPR before enabling
1286 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1287 * document number 292116). So here it goes...
1288 */
1289 apic->init_apic_ldr();
1290
1291#ifdef CONFIG_X86_32
1292 /*
1293 * APIC LDR is initialized. If logical_apicid mapping was
1294 * initialized during get_smp_config(), make sure it matches the
1295 * actual value.
1296 */
1297 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1298 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1299 /* always use the value from LDR */
1300 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1301 logical_smp_processor_id();
1302#endif
1303
1304 /*
1305 * Set Task Priority to 'accept all'. We never change this
1306 * later on.
1307 */
1308 value = apic_read(APIC_TASKPRI);
1309 value &= ~APIC_TPRI_MASK;
1310 apic_write(APIC_TASKPRI, value);
1311
1312 /*
1313 * After a crash, we no longer service the interrupts and a pending
1314 * interrupt from previous kernel might still have ISR bit set.
1315 *
1316 * Most probably by now CPU has serviced that pending interrupt and
1317 * it might not have done the ack_APIC_irq() because it thought,
1318 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1319 * does not clear the ISR bit and cpu thinks it has already serivced
1320 * the interrupt. Hence a vector might get locked. It was noticed
1321 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1322 */
1323 do {
1324 queued = 0;
1325 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1326 queued |= apic_read(APIC_IRR + i*0x10);
1327
1328 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1329 value = apic_read(APIC_ISR + i*0x10);
1330 for (j = 31; j >= 0; j--) {
1331 if (value & (1<<j)) {
1332 ack_APIC_irq();
1333 acked++;
1334 }
1335 }
1336 }
1337 if (acked > 256) {
1338 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1339 acked);
1340 break;
1341 }
1342 if (queued) {
1343 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1344 ntsc = rdtsc();
1345 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1346 } else
1347 max_loops--;
1348 }
1349 } while (queued && max_loops > 0);
1350 WARN_ON(max_loops <= 0);
1351
1352 /*
1353 * Now that we are all set up, enable the APIC
1354 */
1355 value = apic_read(APIC_SPIV);
1356 value &= ~APIC_VECTOR_MASK;
1357 /*
1358 * Enable APIC
1359 */
1360 value |= APIC_SPIV_APIC_ENABLED;
1361
1362#ifdef CONFIG_X86_32
1363 /*
1364 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1365 * certain networking cards. If high frequency interrupts are
1366 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1367 * entry is masked/unmasked at a high rate as well then sooner or
1368 * later IOAPIC line gets 'stuck', no more interrupts are received
1369 * from the device. If focus CPU is disabled then the hang goes
1370 * away, oh well :-(
1371 *
1372 * [ This bug can be reproduced easily with a level-triggered
1373 * PCI Ne2000 networking cards and PII/PIII processors, dual
1374 * BX chipset. ]
1375 */
1376 /*
1377 * Actually disabling the focus CPU check just makes the hang less
1378 * frequent as it makes the interrupt distributon model be more
1379 * like LRU than MRU (the short-term load is more even across CPUs).
1380 */
1381
1382 /*
1383 * - enable focus processor (bit==0)
1384 * - 64bit mode always use processor focus
1385 * so no need to set it
1386 */
1387 value &= ~APIC_SPIV_FOCUS_DISABLED;
1388#endif
1389
1390 /*
1391 * Set spurious IRQ vector
1392 */
1393 value |= SPURIOUS_APIC_VECTOR;
1394 apic_write(APIC_SPIV, value);
1395
1396 /*
1397 * Set up LVT0, LVT1:
1398 *
1399 * set up through-local-APIC on the BP's LINT0. This is not
1400 * strictly necessary in pure symmetric-IO mode, but sometimes
1401 * we delegate interrupts to the 8259A.
1402 */
1403 /*
1404 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1405 */
1406 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1407 if (!cpu && (pic_mode || !value)) {
1408 value = APIC_DM_EXTINT;
1409 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1410 } else {
1411 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1412 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1413 }
1414 apic_write(APIC_LVT0, value);
1415
1416 /*
1417 * Only the BSP sees the LINT1 NMI signal by default. This can be
1418 * modified by apic_extnmi= boot option.
1419 */
1420 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1421 apic_extnmi == APIC_EXTNMI_ALL)
1422 value = APIC_DM_NMI;
1423 else
1424 value = APIC_DM_NMI | APIC_LVT_MASKED;
1425 if (!lapic_is_integrated()) /* 82489DX */
1426 value |= APIC_LVT_LEVEL_TRIGGER;
1427 apic_write(APIC_LVT1, value);
1428
1429#ifdef CONFIG_X86_MCE_INTEL
1430 /* Recheck CMCI information after local APIC is up on CPU #0 */
1431 if (!cpu)
1432 cmci_recheck();
1433#endif
1434}
1435
1436static void end_local_APIC_setup(void)
1437{
1438 lapic_setup_esr();
1439
1440#ifdef CONFIG_X86_32
1441 {
1442 unsigned int value;
1443 /* Disable the local apic timer */
1444 value = apic_read(APIC_LVTT);
1445 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1446 apic_write(APIC_LVTT, value);
1447 }
1448#endif
1449
1450 apic_pm_activate();
1451}
1452
1453/*
1454 * APIC setup function for application processors. Called from smpboot.c
1455 */
1456void apic_ap_setup(void)
1457{
1458 setup_local_APIC();
1459 end_local_APIC_setup();
1460}
1461
1462#ifdef CONFIG_X86_X2APIC
1463int x2apic_mode;
1464
1465enum {
1466 X2APIC_OFF,
1467 X2APIC_ON,
1468 X2APIC_DISABLED,
1469};
1470static int x2apic_state;
1471
1472static void __x2apic_disable(void)
1473{
1474 u64 msr;
1475
1476 if (!boot_cpu_has(X86_FEATURE_APIC))
1477 return;
1478
1479 rdmsrl(MSR_IA32_APICBASE, msr);
1480 if (!(msr & X2APIC_ENABLE))
1481 return;
1482 /* Disable xapic and x2apic first and then reenable xapic mode */
1483 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1484 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1485 printk_once(KERN_INFO "x2apic disabled\n");
1486}
1487
1488static void __x2apic_enable(void)
1489{
1490 u64 msr;
1491
1492 rdmsrl(MSR_IA32_APICBASE, msr);
1493 if (msr & X2APIC_ENABLE)
1494 return;
1495 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1496 printk_once(KERN_INFO "x2apic enabled\n");
1497}
1498
1499static int __init setup_nox2apic(char *str)
1500{
1501 if (x2apic_enabled()) {
1502 int apicid = native_apic_msr_read(APIC_ID);
1503
1504 if (apicid >= 255) {
1505 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1506 apicid);
1507 return 0;
1508 }
1509 pr_warning("x2apic already enabled.\n");
1510 __x2apic_disable();
1511 }
1512 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1513 x2apic_state = X2APIC_DISABLED;
1514 x2apic_mode = 0;
1515 return 0;
1516}
1517early_param("nox2apic", setup_nox2apic);
1518
1519/* Called from cpu_init() to enable x2apic on (secondary) cpus */
1520void x2apic_setup(void)
1521{
1522 /*
1523 * If x2apic is not in ON state, disable it if already enabled
1524 * from BIOS.
1525 */
1526 if (x2apic_state != X2APIC_ON) {
1527 __x2apic_disable();
1528 return;
1529 }
1530 __x2apic_enable();
1531}
1532
1533static __init void x2apic_disable(void)
1534{
1535 u32 x2apic_id, state = x2apic_state;
1536
1537 x2apic_mode = 0;
1538 x2apic_state = X2APIC_DISABLED;
1539
1540 if (state != X2APIC_ON)
1541 return;
1542
1543 x2apic_id = read_apic_id();
1544 if (x2apic_id >= 255)
1545 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1546
1547 __x2apic_disable();
1548 register_lapic_address(mp_lapic_addr);
1549}
1550
1551static __init void x2apic_enable(void)
1552{
1553 if (x2apic_state != X2APIC_OFF)
1554 return;
1555
1556 x2apic_mode = 1;
1557 x2apic_state = X2APIC_ON;
1558 __x2apic_enable();
1559}
1560
1561static __init void try_to_enable_x2apic(int remap_mode)
1562{
1563 if (x2apic_state == X2APIC_DISABLED)
1564 return;
1565
1566 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1567 /* IR is required if there is APIC ID > 255 even when running
1568 * under KVM
1569 */
1570 if (max_physical_apicid > 255 ||
1571 !hypervisor_x2apic_available()) {
1572 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1573 x2apic_disable();
1574 return;
1575 }
1576
1577 /*
1578 * without IR all CPUs can be addressed by IOAPIC/MSI
1579 * only in physical mode
1580 */
1581 x2apic_phys = 1;
1582 }
1583 x2apic_enable();
1584}
1585
1586void __init check_x2apic(void)
1587{
1588 if (x2apic_enabled()) {
1589 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1590 x2apic_mode = 1;
1591 x2apic_state = X2APIC_ON;
1592 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1593 x2apic_state = X2APIC_DISABLED;
1594 }
1595}
1596#else /* CONFIG_X86_X2APIC */
1597static int __init validate_x2apic(void)
1598{
1599 if (!apic_is_x2apic_enabled())
1600 return 0;
1601 /*
1602 * Checkme: Can we simply turn off x2apic here instead of panic?
1603 */
1604 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1605}
1606early_initcall(validate_x2apic);
1607
1608static inline void try_to_enable_x2apic(int remap_mode) { }
1609static inline void __x2apic_enable(void) { }
1610#endif /* !CONFIG_X86_X2APIC */
1611
1612static int __init try_to_enable_IR(void)
1613{
1614#ifdef CONFIG_X86_IO_APIC
1615 if (!x2apic_enabled() && skip_ioapic_setup) {
1616 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1617 return -1;
1618 }
1619#endif
1620 return irq_remapping_enable();
1621}
1622
1623void __init enable_IR_x2apic(void)
1624{
1625 unsigned long flags;
1626 int ret, ir_stat;
1627
1628 if (skip_ioapic_setup)
1629 return;
1630
1631 ir_stat = irq_remapping_prepare();
1632 if (ir_stat < 0 && !x2apic_supported())
1633 return;
1634
1635 ret = save_ioapic_entries();
1636 if (ret) {
1637 pr_info("Saving IO-APIC state failed: %d\n", ret);
1638 return;
1639 }
1640
1641 local_irq_save(flags);
1642 legacy_pic->mask_all();
1643 mask_ioapic_entries();
1644
1645 /* If irq_remapping_prepare() succeeded, try to enable it */
1646 if (ir_stat >= 0)
1647 ir_stat = try_to_enable_IR();
1648 /* ir_stat contains the remap mode or an error code */
1649 try_to_enable_x2apic(ir_stat);
1650
1651 if (ir_stat < 0)
1652 restore_ioapic_entries();
1653 legacy_pic->restore_mask();
1654 local_irq_restore(flags);
1655}
1656
1657#ifdef CONFIG_X86_64
1658/*
1659 * Detect and enable local APICs on non-SMP boards.
1660 * Original code written by Keir Fraser.
1661 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1662 * not correctly set up (usually the APIC timer won't work etc.)
1663 */
1664static int __init detect_init_APIC(void)
1665{
1666 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1667 pr_info("No local APIC present\n");
1668 return -1;
1669 }
1670
1671 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1672 return 0;
1673}
1674#else
1675
1676static int __init apic_verify(void)
1677{
1678 u32 features, h, l;
1679
1680 /*
1681 * The APIC feature bit should now be enabled
1682 * in `cpuid'
1683 */
1684 features = cpuid_edx(1);
1685 if (!(features & (1 << X86_FEATURE_APIC))) {
1686 pr_warning("Could not enable APIC!\n");
1687 return -1;
1688 }
1689 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1690 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1691
1692 /* The BIOS may have set up the APIC at some other address */
1693 if (boot_cpu_data.x86 >= 6) {
1694 rdmsr(MSR_IA32_APICBASE, l, h);
1695 if (l & MSR_IA32_APICBASE_ENABLE)
1696 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1697 }
1698
1699 pr_info("Found and enabled local APIC!\n");
1700 return 0;
1701}
1702
1703int __init apic_force_enable(unsigned long addr)
1704{
1705 u32 h, l;
1706
1707 if (disable_apic)
1708 return -1;
1709
1710 /*
1711 * Some BIOSes disable the local APIC in the APIC_BASE
1712 * MSR. This can only be done in software for Intel P6 or later
1713 * and AMD K7 (Model > 1) or later.
1714 */
1715 if (boot_cpu_data.x86 >= 6) {
1716 rdmsr(MSR_IA32_APICBASE, l, h);
1717 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1718 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1719 l &= ~MSR_IA32_APICBASE_BASE;
1720 l |= MSR_IA32_APICBASE_ENABLE | addr;
1721 wrmsr(MSR_IA32_APICBASE, l, h);
1722 enabled_via_apicbase = 1;
1723 }
1724 }
1725 return apic_verify();
1726}
1727
1728/*
1729 * Detect and initialize APIC
1730 */
1731static int __init detect_init_APIC(void)
1732{
1733 /* Disabled by kernel option? */
1734 if (disable_apic)
1735 return -1;
1736
1737 switch (boot_cpu_data.x86_vendor) {
1738 case X86_VENDOR_AMD:
1739 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1740 (boot_cpu_data.x86 >= 15))
1741 break;
1742 goto no_apic;
1743 case X86_VENDOR_INTEL:
1744 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1745 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1746 break;
1747 goto no_apic;
1748 default:
1749 goto no_apic;
1750 }
1751
1752 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1753 /*
1754 * Over-ride BIOS and try to enable the local APIC only if
1755 * "lapic" specified.
1756 */
1757 if (!force_enable_local_apic) {
1758 pr_info("Local APIC disabled by BIOS -- "
1759 "you can enable it with \"lapic\"\n");
1760 return -1;
1761 }
1762 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1763 return -1;
1764 } else {
1765 if (apic_verify())
1766 return -1;
1767 }
1768
1769 apic_pm_activate();
1770
1771 return 0;
1772
1773no_apic:
1774 pr_info("No local APIC present or hardware disabled\n");
1775 return -1;
1776}
1777#endif
1778
1779/**
1780 * init_apic_mappings - initialize APIC mappings
1781 */
1782void __init init_apic_mappings(void)
1783{
1784 unsigned int new_apicid;
1785
1786 if (x2apic_mode) {
1787 boot_cpu_physical_apicid = read_apic_id();
1788 return;
1789 }
1790
1791 /* If no local APIC can be found return early */
1792 if (!smp_found_config && detect_init_APIC()) {
1793 /* lets NOP'ify apic operations */
1794 pr_info("APIC: disable apic facility\n");
1795 apic_disable();
1796 } else {
1797 apic_phys = mp_lapic_addr;
1798
1799 /*
1800 * acpi lapic path already maps that address in
1801 * acpi_register_lapic_address()
1802 */
1803 if (!acpi_lapic && !smp_found_config)
1804 register_lapic_address(apic_phys);
1805 }
1806
1807 /*
1808 * Fetch the APIC ID of the BSP in case we have a
1809 * default configuration (or the MP table is broken).
1810 */
1811 new_apicid = read_apic_id();
1812 if (boot_cpu_physical_apicid != new_apicid) {
1813 boot_cpu_physical_apicid = new_apicid;
1814 /*
1815 * yeah -- we lie about apic_version
1816 * in case if apic was disabled via boot option
1817 * but it's not a problem for SMP compiled kernel
1818 * since smp_sanity_check is prepared for such a case
1819 * and disable smp mode
1820 */
1821 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1822 }
1823}
1824
1825void __init register_lapic_address(unsigned long address)
1826{
1827 mp_lapic_addr = address;
1828
1829 if (!x2apic_mode) {
1830 set_fixmap_nocache(FIX_APIC_BASE, address);
1831 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1832 APIC_BASE, address);
1833 }
1834 if (boot_cpu_physical_apicid == -1U) {
1835 boot_cpu_physical_apicid = read_apic_id();
1836 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1837 }
1838}
1839
1840/*
1841 * Local APIC interrupts
1842 */
1843
1844/*
1845 * This interrupt should _never_ happen with our APIC/SMP architecture
1846 */
1847static void __smp_spurious_interrupt(u8 vector)
1848{
1849 u32 v;
1850
1851 /*
1852 * Check if this really is a spurious interrupt and ACK it
1853 * if it is a vectored one. Just in case...
1854 * Spurious interrupts should not be ACKed.
1855 */
1856 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1857 if (v & (1 << (vector & 0x1f)))
1858 ack_APIC_irq();
1859
1860 inc_irq_stat(irq_spurious_count);
1861
1862 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1863 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1864 "should never happen.\n", vector, smp_processor_id());
1865}
1866
1867__visible void smp_spurious_interrupt(struct pt_regs *regs)
1868{
1869 entering_irq();
1870 __smp_spurious_interrupt(~regs->orig_ax);
1871 exiting_irq();
1872}
1873
1874__visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1875{
1876 u8 vector = ~regs->orig_ax;
1877
1878 entering_irq();
1879 trace_spurious_apic_entry(vector);
1880 __smp_spurious_interrupt(vector);
1881 trace_spurious_apic_exit(vector);
1882 exiting_irq();
1883}
1884
1885/*
1886 * This interrupt should never happen with our APIC/SMP architecture
1887 */
1888static void __smp_error_interrupt(struct pt_regs *regs)
1889{
1890 u32 v;
1891 u32 i = 0;
1892 static const char * const error_interrupt_reason[] = {
1893 "Send CS error", /* APIC Error Bit 0 */
1894 "Receive CS error", /* APIC Error Bit 1 */
1895 "Send accept error", /* APIC Error Bit 2 */
1896 "Receive accept error", /* APIC Error Bit 3 */
1897 "Redirectable IPI", /* APIC Error Bit 4 */
1898 "Send illegal vector", /* APIC Error Bit 5 */
1899 "Received illegal vector", /* APIC Error Bit 6 */
1900 "Illegal register address", /* APIC Error Bit 7 */
1901 };
1902
1903 /* First tickle the hardware, only then report what went on. -- REW */
1904 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1905 apic_write(APIC_ESR, 0);
1906 v = apic_read(APIC_ESR);
1907 ack_APIC_irq();
1908 atomic_inc(&irq_err_count);
1909
1910 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1911 smp_processor_id(), v);
1912
1913 v &= 0xff;
1914 while (v) {
1915 if (v & 0x1)
1916 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1917 i++;
1918 v >>= 1;
1919 }
1920
1921 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1922
1923}
1924
1925__visible void smp_error_interrupt(struct pt_regs *regs)
1926{
1927 entering_irq();
1928 __smp_error_interrupt(regs);
1929 exiting_irq();
1930}
1931
1932__visible void smp_trace_error_interrupt(struct pt_regs *regs)
1933{
1934 entering_irq();
1935 trace_error_apic_entry(ERROR_APIC_VECTOR);
1936 __smp_error_interrupt(regs);
1937 trace_error_apic_exit(ERROR_APIC_VECTOR);
1938 exiting_irq();
1939}
1940
1941/**
1942 * connect_bsp_APIC - attach the APIC to the interrupt system
1943 */
1944static void __init connect_bsp_APIC(void)
1945{
1946#ifdef CONFIG_X86_32
1947 if (pic_mode) {
1948 /*
1949 * Do not trust the local APIC being empty at bootup.
1950 */
1951 clear_local_APIC();
1952 /*
1953 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1954 * local APIC to INT and NMI lines.
1955 */
1956 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1957 "enabling APIC mode.\n");
1958 imcr_pic_to_apic();
1959 }
1960#endif
1961}
1962
1963/**
1964 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1965 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1966 *
1967 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1968 * APIC is disabled.
1969 */
1970void disconnect_bsp_APIC(int virt_wire_setup)
1971{
1972 unsigned int value;
1973
1974#ifdef CONFIG_X86_32
1975 if (pic_mode) {
1976 /*
1977 * Put the board back into PIC mode (has an effect only on
1978 * certain older boards). Note that APIC interrupts, including
1979 * IPIs, won't work beyond this point! The only exception are
1980 * INIT IPIs.
1981 */
1982 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1983 "entering PIC mode.\n");
1984 imcr_apic_to_pic();
1985 return;
1986 }
1987#endif
1988
1989 /* Go back to Virtual Wire compatibility mode */
1990
1991 /* For the spurious interrupt use vector F, and enable it */
1992 value = apic_read(APIC_SPIV);
1993 value &= ~APIC_VECTOR_MASK;
1994 value |= APIC_SPIV_APIC_ENABLED;
1995 value |= 0xf;
1996 apic_write(APIC_SPIV, value);
1997
1998 if (!virt_wire_setup) {
1999 /*
2000 * For LVT0 make it edge triggered, active high,
2001 * external and enabled
2002 */
2003 value = apic_read(APIC_LVT0);
2004 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2005 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2006 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2007 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2008 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2009 apic_write(APIC_LVT0, value);
2010 } else {
2011 /* Disable LVT0 */
2012 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2013 }
2014
2015 /*
2016 * For LVT1 make it edge triggered, active high,
2017 * nmi and enabled
2018 */
2019 value = apic_read(APIC_LVT1);
2020 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2021 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2022 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2023 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2024 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2025 apic_write(APIC_LVT1, value);
2026}
2027
2028/*
2029 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2030 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2031 * All allocated CPU ID should be in [0, nr_logical_cpuidi), so the maximum of
2032 * nr_logical_cpuids is nr_cpu_ids.
2033 *
2034 * NOTE: Reserve 0 for BSP.
2035 */
2036static int nr_logical_cpuids = 1;
2037
2038/*
2039 * Used to store mapping between logical CPU IDs and APIC IDs.
2040 */
2041static int cpuid_to_apicid[] = {
2042 [0 ... NR_CPUS - 1] = -1,
2043};
2044
2045/*
2046 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2047 * and cpuid_to_apicid[] synchronized.
2048 */
2049static int allocate_logical_cpuid(int apicid)
2050{
2051 int i;
2052
2053 /*
2054 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2055 * check if the kernel has allocated a cpuid for it.
2056 */
2057 for (i = 0; i < nr_logical_cpuids; i++) {
2058 if (cpuid_to_apicid[i] == apicid)
2059 return i;
2060 }
2061
2062 /* Allocate a new cpuid. */
2063 if (nr_logical_cpuids >= nr_cpu_ids) {
2064 WARN_ONCE(1, "Only %d processors supported."
2065 "Processor %d/0x%x and the rest are ignored.\n",
2066 nr_cpu_ids - 1, nr_logical_cpuids, apicid);
2067 return -1;
2068 }
2069
2070 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2071 return nr_logical_cpuids++;
2072}
2073
2074int __generic_processor_info(int apicid, int version, bool enabled)
2075{
2076 int cpu, max = nr_cpu_ids;
2077 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2078 phys_cpu_present_map);
2079
2080 /*
2081 * boot_cpu_physical_apicid is designed to have the apicid
2082 * returned by read_apic_id(), i.e, the apicid of the
2083 * currently booting-up processor. However, on some platforms,
2084 * it is temporarily modified by the apicid reported as BSP
2085 * through MP table. Concretely:
2086 *
2087 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2088 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2089 *
2090 * This function is executed with the modified
2091 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2092 * parameter doesn't work to disable APs on kdump 2nd kernel.
2093 *
2094 * Since fixing handling of boot_cpu_physical_apicid requires
2095 * another discussion and tests on each platform, we leave it
2096 * for now and here we use read_apic_id() directly in this
2097 * function, generic_processor_info().
2098 */
2099 if (disabled_cpu_apicid != BAD_APICID &&
2100 disabled_cpu_apicid != read_apic_id() &&
2101 disabled_cpu_apicid == apicid) {
2102 int thiscpu = num_processors + disabled_cpus;
2103
2104 pr_warning("APIC: Disabling requested cpu."
2105 " Processor %d/0x%x ignored.\n",
2106 thiscpu, apicid);
2107
2108 disabled_cpus++;
2109 return -ENODEV;
2110 }
2111
2112 /*
2113 * If boot cpu has not been detected yet, then only allow upto
2114 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2115 */
2116 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2117 apicid != boot_cpu_physical_apicid) {
2118 int thiscpu = max + disabled_cpus - 1;
2119
2120 pr_warning(
2121 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2122 " reached. Keeping one slot for boot cpu."
2123 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2124
2125 disabled_cpus++;
2126 return -ENODEV;
2127 }
2128
2129 if (num_processors >= nr_cpu_ids) {
2130 int thiscpu = max + disabled_cpus;
2131
2132 if (enabled) {
2133 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2134 "reached. Processor %d/0x%x ignored.\n",
2135 max, thiscpu, apicid);
2136 }
2137
2138 disabled_cpus++;
2139 return -EINVAL;
2140 }
2141
2142 if (apicid == boot_cpu_physical_apicid) {
2143 /*
2144 * x86_bios_cpu_apicid is required to have processors listed
2145 * in same order as logical cpu numbers. Hence the first
2146 * entry is BSP, and so on.
2147 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2148 * for BSP.
2149 */
2150 cpu = 0;
2151
2152 /* Logical cpuid 0 is reserved for BSP. */
2153 cpuid_to_apicid[0] = apicid;
2154 } else {
2155 cpu = allocate_logical_cpuid(apicid);
2156 if (cpu < 0) {
2157 disabled_cpus++;
2158 return -EINVAL;
2159 }
2160 }
2161
2162 /*
2163 * Validate version
2164 */
2165 if (version == 0x0) {
2166 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2167 cpu, apicid);
2168 version = 0x10;
2169 }
2170
2171 if (version != boot_cpu_apic_version) {
2172 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2173 boot_cpu_apic_version, cpu, version);
2174 }
2175
2176 if (apicid > max_physical_apicid)
2177 max_physical_apicid = apicid;
2178
2179#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2180 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2181 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2182#endif
2183#ifdef CONFIG_X86_32
2184 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2185 apic->x86_32_early_logical_apicid(cpu);
2186#endif
2187 set_cpu_possible(cpu, true);
2188
2189 if (enabled) {
2190 num_processors++;
2191 physid_set(apicid, phys_cpu_present_map);
2192 set_cpu_present(cpu, true);
2193 } else {
2194 disabled_cpus++;
2195 }
2196
2197 return cpu;
2198}
2199
2200int generic_processor_info(int apicid, int version)
2201{
2202 return __generic_processor_info(apicid, version, true);
2203}
2204
2205int hard_smp_processor_id(void)
2206{
2207 return read_apic_id();
2208}
2209
2210void default_init_apic_ldr(void)
2211{
2212 unsigned long val;
2213
2214 apic_write(APIC_DFR, APIC_DFR_VALUE);
2215 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2216 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2217 apic_write(APIC_LDR, val);
2218}
2219
2220int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2221 const struct cpumask *andmask,
2222 unsigned int *apicid)
2223{
2224 unsigned int cpu;
2225
2226 for_each_cpu_and(cpu, cpumask, andmask) {
2227 if (cpumask_test_cpu(cpu, cpu_online_mask))
2228 break;
2229 }
2230
2231 if (likely(cpu < nr_cpu_ids)) {
2232 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2233 return 0;
2234 }
2235
2236 return -EINVAL;
2237}
2238
2239/*
2240 * Override the generic EOI implementation with an optimized version.
2241 * Only called during early boot when only one CPU is active and with
2242 * interrupts disabled, so we know this does not race with actual APIC driver
2243 * use.
2244 */
2245void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2246{
2247 struct apic **drv;
2248
2249 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2250 /* Should happen once for each apic */
2251 WARN_ON((*drv)->eoi_write == eoi_write);
2252 (*drv)->native_eoi_write = (*drv)->eoi_write;
2253 (*drv)->eoi_write = eoi_write;
2254 }
2255}
2256
2257static void __init apic_bsp_up_setup(void)
2258{
2259#ifdef CONFIG_X86_64
2260 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
2261#else
2262 /*
2263 * Hack: In case of kdump, after a crash, kernel might be booting
2264 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2265 * might be zero if read from MP tables. Get it from LAPIC.
2266 */
2267# ifdef CONFIG_CRASH_DUMP
2268 boot_cpu_physical_apicid = read_apic_id();
2269# endif
2270#endif
2271 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2272}
2273
2274/**
2275 * apic_bsp_setup - Setup function for local apic and io-apic
2276 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2277 *
2278 * Returns:
2279 * apic_id of BSP APIC
2280 */
2281int __init apic_bsp_setup(bool upmode)
2282{
2283 int id;
2284
2285 connect_bsp_APIC();
2286 if (upmode)
2287 apic_bsp_up_setup();
2288 setup_local_APIC();
2289
2290 if (x2apic_mode)
2291 id = apic_read(APIC_LDR);
2292 else
2293 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2294
2295 enable_IO_APIC();
2296 end_local_APIC_setup();
2297 irq_remap_enable_fault_handling();
2298 setup_IO_APIC();
2299 /* Setup local timer */
2300 x86_init.timers.setup_percpu_clockev();
2301 return id;
2302}
2303
2304/*
2305 * This initializes the IO-APIC and APIC hardware if this is
2306 * a UP kernel.
2307 */
2308int __init APIC_init_uniprocessor(void)
2309{
2310 if (disable_apic) {
2311 pr_info("Apic disabled\n");
2312 return -1;
2313 }
2314#ifdef CONFIG_X86_64
2315 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2316 disable_apic = 1;
2317 pr_info("Apic disabled by BIOS\n");
2318 return -1;
2319 }
2320#else
2321 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2322 return -1;
2323
2324 /*
2325 * Complain if the BIOS pretends there is one.
2326 */
2327 if (!boot_cpu_has(X86_FEATURE_APIC) &&
2328 APIC_INTEGRATED(boot_cpu_apic_version)) {
2329 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2330 boot_cpu_physical_apicid);
2331 return -1;
2332 }
2333#endif
2334
2335 if (!smp_found_config)
2336 disable_ioapic_support();
2337
2338 default_setup_apic_routing();
2339 apic_bsp_setup(true);
2340 return 0;
2341}
2342
2343#ifdef CONFIG_UP_LATE_INIT
2344void __init up_late_init(void)
2345{
2346 APIC_init_uniprocessor();
2347}
2348#endif
2349
2350/*
2351 * Power management
2352 */
2353#ifdef CONFIG_PM
2354
2355static struct {
2356 /*
2357 * 'active' is true if the local APIC was enabled by us and
2358 * not the BIOS; this signifies that we are also responsible
2359 * for disabling it before entering apm/acpi suspend
2360 */
2361 int active;
2362 /* r/w apic fields */
2363 unsigned int apic_id;
2364 unsigned int apic_taskpri;
2365 unsigned int apic_ldr;
2366 unsigned int apic_dfr;
2367 unsigned int apic_spiv;
2368 unsigned int apic_lvtt;
2369 unsigned int apic_lvtpc;
2370 unsigned int apic_lvt0;
2371 unsigned int apic_lvt1;
2372 unsigned int apic_lvterr;
2373 unsigned int apic_tmict;
2374 unsigned int apic_tdcr;
2375 unsigned int apic_thmr;
2376 unsigned int apic_cmci;
2377} apic_pm_state;
2378
2379static int lapic_suspend(void)
2380{
2381 unsigned long flags;
2382 int maxlvt;
2383
2384 if (!apic_pm_state.active)
2385 return 0;
2386
2387 maxlvt = lapic_get_maxlvt();
2388
2389 apic_pm_state.apic_id = apic_read(APIC_ID);
2390 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2391 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2392 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2393 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2394 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2395 if (maxlvt >= 4)
2396 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2397 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2398 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2399 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2400 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2401 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2402#ifdef CONFIG_X86_THERMAL_VECTOR
2403 if (maxlvt >= 5)
2404 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2405#endif
2406#ifdef CONFIG_X86_MCE_INTEL
2407 if (maxlvt >= 6)
2408 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2409#endif
2410
2411 local_irq_save(flags);
2412 disable_local_APIC();
2413
2414 irq_remapping_disable();
2415
2416 local_irq_restore(flags);
2417 return 0;
2418}
2419
2420static void lapic_resume(void)
2421{
2422 unsigned int l, h;
2423 unsigned long flags;
2424 int maxlvt;
2425
2426 if (!apic_pm_state.active)
2427 return;
2428
2429 local_irq_save(flags);
2430
2431 /*
2432 * IO-APIC and PIC have their own resume routines.
2433 * We just mask them here to make sure the interrupt
2434 * subsystem is completely quiet while we enable x2apic
2435 * and interrupt-remapping.
2436 */
2437 mask_ioapic_entries();
2438 legacy_pic->mask_all();
2439
2440 if (x2apic_mode) {
2441 __x2apic_enable();
2442 } else {
2443 /*
2444 * Make sure the APICBASE points to the right address
2445 *
2446 * FIXME! This will be wrong if we ever support suspend on
2447 * SMP! We'll need to do this as part of the CPU restore!
2448 */
2449 if (boot_cpu_data.x86 >= 6) {
2450 rdmsr(MSR_IA32_APICBASE, l, h);
2451 l &= ~MSR_IA32_APICBASE_BASE;
2452 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2453 wrmsr(MSR_IA32_APICBASE, l, h);
2454 }
2455 }
2456
2457 maxlvt = lapic_get_maxlvt();
2458 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2459 apic_write(APIC_ID, apic_pm_state.apic_id);
2460 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2461 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2462 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2463 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2464 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2465 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2466#ifdef CONFIG_X86_THERMAL_VECTOR
2467 if (maxlvt >= 5)
2468 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2469#endif
2470#ifdef CONFIG_X86_MCE_INTEL
2471 if (maxlvt >= 6)
2472 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2473#endif
2474 if (maxlvt >= 4)
2475 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2476 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2477 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2478 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2479 apic_write(APIC_ESR, 0);
2480 apic_read(APIC_ESR);
2481 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2482 apic_write(APIC_ESR, 0);
2483 apic_read(APIC_ESR);
2484
2485 irq_remapping_reenable(x2apic_mode);
2486
2487 local_irq_restore(flags);
2488}
2489
2490/*
2491 * This device has no shutdown method - fully functioning local APICs
2492 * are needed on every CPU up until machine_halt/restart/poweroff.
2493 */
2494
2495static struct syscore_ops lapic_syscore_ops = {
2496 .resume = lapic_resume,
2497 .suspend = lapic_suspend,
2498};
2499
2500static void apic_pm_activate(void)
2501{
2502 apic_pm_state.active = 1;
2503}
2504
2505static int __init init_lapic_sysfs(void)
2506{
2507 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2508 if (boot_cpu_has(X86_FEATURE_APIC))
2509 register_syscore_ops(&lapic_syscore_ops);
2510
2511 return 0;
2512}
2513
2514/* local apic needs to resume before other devices access its registers. */
2515core_initcall(init_lapic_sysfs);
2516
2517#else /* CONFIG_PM */
2518
2519static void apic_pm_activate(void) { }
2520
2521#endif /* CONFIG_PM */
2522
2523#ifdef CONFIG_X86_64
2524
2525static int multi_checked;
2526static int multi;
2527
2528static int set_multi(const struct dmi_system_id *d)
2529{
2530 if (multi)
2531 return 0;
2532 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2533 multi = 1;
2534 return 0;
2535}
2536
2537static const struct dmi_system_id multi_dmi_table[] = {
2538 {
2539 .callback = set_multi,
2540 .ident = "IBM System Summit2",
2541 .matches = {
2542 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2543 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2544 },
2545 },
2546 {}
2547};
2548
2549static void dmi_check_multi(void)
2550{
2551 if (multi_checked)
2552 return;
2553
2554 dmi_check_system(multi_dmi_table);
2555 multi_checked = 1;
2556}
2557
2558/*
2559 * apic_is_clustered_box() -- Check if we can expect good TSC
2560 *
2561 * Thus far, the major user of this is IBM's Summit2 series:
2562 * Clustered boxes may have unsynced TSC problems if they are
2563 * multi-chassis.
2564 * Use DMI to check them
2565 */
2566int apic_is_clustered_box(void)
2567{
2568 dmi_check_multi();
2569 return multi;
2570}
2571#endif
2572
2573/*
2574 * APIC command line parameters
2575 */
2576static int __init setup_disableapic(char *arg)
2577{
2578 disable_apic = 1;
2579 setup_clear_cpu_cap(X86_FEATURE_APIC);
2580 return 0;
2581}
2582early_param("disableapic", setup_disableapic);
2583
2584/* same as disableapic, for compatibility */
2585static int __init setup_nolapic(char *arg)
2586{
2587 return setup_disableapic(arg);
2588}
2589early_param("nolapic", setup_nolapic);
2590
2591static int __init parse_lapic_timer_c2_ok(char *arg)
2592{
2593 local_apic_timer_c2_ok = 1;
2594 return 0;
2595}
2596early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2597
2598static int __init parse_disable_apic_timer(char *arg)
2599{
2600 disable_apic_timer = 1;
2601 return 0;
2602}
2603early_param("noapictimer", parse_disable_apic_timer);
2604
2605static int __init parse_nolapic_timer(char *arg)
2606{
2607 disable_apic_timer = 1;
2608 return 0;
2609}
2610early_param("nolapic_timer", parse_nolapic_timer);
2611
2612static int __init apic_set_verbosity(char *arg)
2613{
2614 if (!arg) {
2615#ifdef CONFIG_X86_64
2616 skip_ioapic_setup = 0;
2617 return 0;
2618#endif
2619 return -EINVAL;
2620 }
2621
2622 if (strcmp("debug", arg) == 0)
2623 apic_verbosity = APIC_DEBUG;
2624 else if (strcmp("verbose", arg) == 0)
2625 apic_verbosity = APIC_VERBOSE;
2626 else {
2627 pr_warning("APIC Verbosity level %s not recognised"
2628 " use apic=verbose or apic=debug\n", arg);
2629 return -EINVAL;
2630 }
2631
2632 return 0;
2633}
2634early_param("apic", apic_set_verbosity);
2635
2636static int __init lapic_insert_resource(void)
2637{
2638 if (!apic_phys)
2639 return -1;
2640
2641 /* Put local APIC into the resource map. */
2642 lapic_resource.start = apic_phys;
2643 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2644 insert_resource(&iomem_resource, &lapic_resource);
2645
2646 return 0;
2647}
2648
2649/*
2650 * need call insert after e820_reserve_resources()
2651 * that is using request_resource
2652 */
2653late_initcall(lapic_insert_resource);
2654
2655static int __init apic_set_disabled_cpu_apicid(char *arg)
2656{
2657 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2658 return -EINVAL;
2659
2660 return 0;
2661}
2662early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2663
2664static int __init apic_set_extnmi(char *arg)
2665{
2666 if (!arg)
2667 return -EINVAL;
2668
2669 if (!strncmp("all", arg, 3))
2670 apic_extnmi = APIC_EXTNMI_ALL;
2671 else if (!strncmp("none", arg, 4))
2672 apic_extnmi = APIC_EXTNMI_NONE;
2673 else if (!strncmp("bsp", arg, 3))
2674 apic_extnmi = APIC_EXTNMI_BSP;
2675 else {
2676 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2677 return -EINVAL;
2678 }
2679
2680 return 0;
2681}
2682early_param("apic_extnmi", apic_set_extnmi);