1// SPDX-License-Identifier: GPL-2.0
 2/dts-v1/;
 3
 4/ {
 5	compatible = "jcore,j2-soc";
 6	model = "J2 FPGA SoC on Mimas v2 board";
 7
 8	#address-cells = <1>;
 9	#size-cells = <1>;
10
11	interrupt-parent = <&aic>;
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "jcore,j2";
20			reg = <0>;
21			clock-frequency = <50000000>;
22			d-cache-size = <8192>;
23			i-cache-size = <8192>;
24			d-cache-block-size = <16>;
25			i-cache-block-size = <16>;
26		};
27	};
28
29	memory@10000000 {
30		device_type = "memory";
31		reg = <0x10000000 0x4000000>;
32	};
33
34	aliases {
35		serial0 = &uart0;
36		spi0 = &spi0;
37	};
38
39	chosen {
40		stdout-path = "serial0";
41	};
42
43	soc@abcd0000 {
44		compatible = "simple-bus";
45		ranges = <0 0xabcd0000 0x100000>;
46
47		#address-cells = <1>;
48		#size-cells = <1>;
49
50		aic: interrupt-controller@200 {
51			compatible = "jcore,aic1";
52			reg = <0x200 0x10>;
53			interrupt-controller;
54			#interrupt-cells = <1>;
55		};
56
57		cache-controller@c0 {
58			compatible = "jcore,cache";
59			reg = <0xc0 4>;
60		};
61
62		timer@200 {
63			compatible = "jcore,pit";
64			reg = <0x200 0x30>;
65			interrupts = <0x48>;
66		};
67
68		spi0: spi@40 {
69			compatible = "jcore,spi2";
70
71			#address-cells = <1>;
72			#size-cells = <0>;
73
74			spi-max-frequency = <25000000>;
75
76			reg = <0x40 0x8>;
77
78			sdcard@0 {
79				compatible = "mmc-spi-slot";
80				reg = <0>;
81				spi-max-frequency = <25000000>;
82				voltage-ranges = <3200 3400>;
83				mode = <0>;
84			};
85		};
86
87		uart0: serial@100 {
88			clock-frequency = <125000000>;
89			compatible = "xlnx,xps-uartlite-1.00.a";
90			current-speed = <19200>;
91			device_type = "serial";
92			interrupts = <0x12>;
93			port-number = <0>;
94			reg = <0x100 0x10>;
95		};
96	};
97};

 
 1/dts-v1/;
 2
 3/ {
 4	compatible = "jcore,j2-soc";
 5	model = "J2 FPGA SoC on Mimas v2 board";
 6
 7	#address-cells = <1>;
 8	#size-cells = <1>;
 9
10	interrupt-parent = <&aic>;
11
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu@0 {
17			device_type = "cpu";
18			compatible = "jcore,j2";
19			reg = <0>;
20			clock-frequency = <50000000>;
21			d-cache-size = <8192>;
22			i-cache-size = <8192>;
23			d-cache-block-size = <16>;
24			i-cache-block-size = <16>;
25		};
26	};
27
28	memory@10000000 {
29		device_type = "memory";
30		reg = <0x10000000 0x4000000>;
31	};
32
33	aliases {
34		serial0 = &uart0;
35		spi0 = &spi0;
36	};
37
38	chosen {
39		stdout-path = "serial0";
40	};
41
42	soc@abcd0000 {
43		compatible = "simple-bus";
44		ranges = <0 0xabcd0000 0x100000>;
45
46		#address-cells = <1>;
47		#size-cells = <1>;
48
49		aic: interrupt-controller@200 {
50			compatible = "jcore,aic1";
51			reg = <0x200 0x10>;
52			interrupt-controller;
53			#interrupt-cells = <1>;
54		};
55
56		cache-controller@c0 {
57			compatible = "jcore,cache";
58			reg = <0xc0 4>;
59		};
60
61		timer@200 {
62			compatible = "jcore,pit";
63			reg = <0x200 0x30>;
64			interrupts = <0x48>;
65		};
66
67		spi0: spi@40 {
68			compatible = "jcore,spi2";
69
70			#address-cells = <1>;
71			#size-cells = <0>;
72
73			spi-max-frequency = <25000000>;
74
75			reg = <0x40 0x8>;
76
77			sdcard@0 {
78				compatible = "mmc-spi-slot";
79				reg = <0>;
80				spi-max-frequency = <25000000>;
81				voltage-ranges = <3200 3400>;
82				mode = <0>;
83			};
84		};
85
86		uart0: serial@100 {
87			clock-frequency = <125000000>;
88			compatible = "xlnx,xps-uartlite-1.00.a";
89			current-speed = <19200>;
90			device_type = "serial";
91			interrupts = <0x12>;
92			port-number = <0>;
93			reg = <0x100 0x10>;
94		};
95	};
96};