Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
4 */
5
6/*
7 * Device tree for AXC001 770D/EM6/AS221 CPU card
8 * Note that this file only supports the 770D CPU
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "snps,arc";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpu_card {
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
24
25 core_clk: core_clk {
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <750000000>;
29 };
30
31 core_intc: arc700-intc@cpu {
32 compatible = "snps,arc700-intc";
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 };
36
37 /*
38 * this GPIO block ORs all interrupts on CPU card (creg,..)
39 * to uplink only 1 IRQ to ARC core intc
40 */
41 dw-apb-gpio@2000 {
42 compatible = "snps,dw-apb-gpio";
43 reg = < 0x2000 0x80 >;
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 ictl_intc: gpio-controller@0 {
48 compatible = "snps,dw-apb-gpio-port";
49 gpio-controller;
50 #gpio-cells = <2>;
51 snps,nr-gpios = <30>;
52 reg = <0>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 interrupt-parent = <&core_intc>;
56 interrupts = <15>;
57 };
58 };
59
60 debug_uart: dw-apb-uart@5000 {
61 compatible = "snps,dw-apb-uart";
62 reg = <0x5000 0x100>;
63 clock-frequency = <33333000>;
64 interrupt-parent = <&ictl_intc>;
65 interrupts = <19 4>;
66 baud = <115200>;
67 reg-shift = <2>;
68 reg-io-width = <4>;
69 };
70
71 arcpct0: pct {
72 compatible = "snps,arc700-pct";
73 };
74 };
75
76 /*
77 * This INTC is actually connected to DW APB GPIO
78 * which acts as a wire between MB INTC and CPU INTC.
79 * GPIO INTC is configured in platform init code
80 * and here we mimic direct connection from MB INTC to
81 * CPU INTC, thus we set "interrupts = <7>" instead of
82 * "interrupts = <12>"
83 *
84 * This intc actually resides on MB, but we move it here to
85 * avoid duplicating the MB dtsi file given that IRQ from
86 * this intc to cpu intc are different for axs101 and axs103
87 */
88 mb_intc: dw-apb-ictl@e0012000 {
89 #interrupt-cells = <1>;
90 compatible = "snps,dw-apb-ictl";
91 reg = < 0x0 0xe0012000 0x0 0x200 >;
92 interrupt-controller;
93 interrupt-parent = <&core_intc>;
94 interrupts = < 7 >;
95 };
96
97 memory {
98 device_type = "memory";
99 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
100 reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
101 };
102
103 reserved-memory {
104 #address-cells = <2>;
105 #size-cells = <2>;
106 ranges;
107 /*
108 * We just move frame buffer area to the very end of
109 * available DDR. And even though in case of ARC770 there's
110 * no strict requirement for a frame-buffer to be in any
111 * particular location it allows us to use the same
112 * base board's DT node for ARC PGU as for ARc HS38.
113 */
114 frame_buffer: frame_buffer@9e000000 {
115 compatible = "shared-dma-pool";
116 reg = <0x0 0x9e000000 0x0 0x2000000>;
117 no-map;
118 };
119 };
120};
1/*
2 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device tree for AXC001 770D/EM6/AS221 CPU card
11 * Note that this file only supports the 770D CPU
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 compatible = "snps,arc";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 cpu_card {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
25
26 ranges = <0x00000000 0xf0000000 0x10000000>;
27
28 core_clk: core_clk {
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <750000000>;
32 };
33
34 core_intc: arc700-intc@cpu {
35 compatible = "snps,arc700-intc";
36 interrupt-controller;
37 #interrupt-cells = <1>;
38 };
39
40 /*
41 * this GPIO block ORs all interrupts on CPU card (creg,..)
42 * to uplink only 1 IRQ to ARC core intc
43 */
44 dw-apb-gpio@0x2000 {
45 compatible = "snps,dw-apb-gpio";
46 reg = < 0x2000 0x80 >;
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 ictl_intc: gpio-controller@0 {
51 compatible = "snps,dw-apb-gpio-port";
52 gpio-controller;
53 #gpio-cells = <2>;
54 snps,nr-gpios = <30>;
55 reg = <0>;
56 interrupt-controller;
57 #interrupt-cells = <2>;
58 interrupt-parent = <&core_intc>;
59 interrupts = <15>;
60 };
61 };
62
63 debug_uart: dw-apb-uart@0x5000 {
64 compatible = "snps,dw-apb-uart";
65 reg = <0x5000 0x100>;
66 clock-frequency = <33333000>;
67 interrupt-parent = <&ictl_intc>;
68 interrupts = <19 4>;
69 baud = <115200>;
70 reg-shift = <2>;
71 reg-io-width = <4>;
72 };
73
74 arcpct0: pct {
75 compatible = "snps,arc700-pct";
76 };
77 };
78
79 /*
80 * This INTC is actually connected to DW APB GPIO
81 * which acts as a wire between MB INTC and CPU INTC.
82 * GPIO INTC is configured in platform init code
83 * and here we mimic direct connection from MB INTC to
84 * CPU INTC, thus we set "interrupts = <7>" instead of
85 * "interrupts = <12>"
86 *
87 * This intc actually resides on MB, but we move it here to
88 * avoid duplicating the MB dtsi file given that IRQ from
89 * this intc to cpu intc are different for axs101 and axs103
90 */
91 mb_intc: dw-apb-ictl@0xe0012000 {
92 #interrupt-cells = <1>;
93 compatible = "snps,dw-apb-ictl";
94 reg = < 0xe0012000 0x200 >;
95 interrupt-controller;
96 interrupt-parent = <&core_intc>;
97 interrupts = < 7 >;
98 };
99
100 memory {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges = <0x00000000 0x80000000 0x20000000>;
104 device_type = "memory";
105 reg = <0x80000000 0x1b000000>; /* (512 - 32) MiB */
106 };
107
108 reserved-memory {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges;
112 /*
113 * We just move frame buffer area to the very end of
114 * available DDR. And even though in case of ARC770 there's
115 * no strict requirement for a frame-buffer to be in any
116 * particular location it allows us to use the same
117 * base board's DT node for ARC PGU as for ARc HS38.
118 */
119 frame_buffer: frame_buffer@9e000000 {
120 compatible = "shared-dma-pool";
121 reg = <0x9e000000 0x2000000>;
122 no-map;
123 };
124 };
125};