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1/*
2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
20
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
24
25#define DISPC_IRQ_FRAMEDONE (1 << 0)
26#define DISPC_IRQ_VSYNC (1 << 1)
27#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32#define DISPC_IRQ_GFX_END_WIN (1 << 7)
33#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34#define DISPC_IRQ_OCP_ERR (1 << 9)
35#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36#define DISPC_IRQ_VID1_END_WIN (1 << 11)
37#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38#define DISPC_IRQ_VID2_END_WIN (1 << 13)
39#define DISPC_IRQ_SYNC_LOST (1 << 14)
40#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41#define DISPC_IRQ_WAKEUP (1 << 16)
42#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43#define DISPC_IRQ_VSYNC2 (1 << 18)
44#define DISPC_IRQ_VID3_END_WIN (1 << 19)
45#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
46#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
47#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
48#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
49#define DISPC_IRQ_FRAMEDONETV (1 << 24)
50#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
51
52struct omap_dss_device;
53struct omap_overlay_manager;
54struct snd_aes_iec958;
55struct snd_cea_861_aud_if;
56
57enum omap_display_type {
58 OMAP_DISPLAY_TYPE_NONE = 0,
59 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
60 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
61 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
62 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
63 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
64 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
65};
66
67enum omap_plane {
68 OMAP_DSS_GFX = 0,
69 OMAP_DSS_VIDEO1 = 1,
70 OMAP_DSS_VIDEO2 = 2,
71 OMAP_DSS_VIDEO3 = 3,
72};
73
74enum omap_channel {
75 OMAP_DSS_CHANNEL_LCD = 0,
76 OMAP_DSS_CHANNEL_DIGIT = 1,
77 OMAP_DSS_CHANNEL_LCD2 = 2,
78};
79
80enum omap_color_mode {
81 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
82 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
83 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
84 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
85 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
86 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
87 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
88 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
89 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
90 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
91 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
92 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
93 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
94 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
95 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
96 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
97 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
98 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
99 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
100};
101
102enum omap_lcd_display_type {
103 OMAP_DSS_LCD_DISPLAY_STN,
104 OMAP_DSS_LCD_DISPLAY_TFT,
105};
106
107enum omap_dss_load_mode {
108 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
109 OMAP_DSS_LOAD_CLUT_ONLY = 1,
110 OMAP_DSS_LOAD_FRAME_ONLY = 2,
111 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
112};
113
114enum omap_dss_trans_key_type {
115 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
116 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
117};
118
119enum omap_rfbi_te_mode {
120 OMAP_DSS_RFBI_TE_MODE_1 = 1,
121 OMAP_DSS_RFBI_TE_MODE_2 = 2,
122};
123
124enum omap_panel_config {
125 OMAP_DSS_LCD_IVS = 1<<0,
126 OMAP_DSS_LCD_IHS = 1<<1,
127 OMAP_DSS_LCD_IPC = 1<<2,
128 OMAP_DSS_LCD_IEO = 1<<3,
129 OMAP_DSS_LCD_RF = 1<<4,
130 OMAP_DSS_LCD_ONOFF = 1<<5,
131
132 OMAP_DSS_LCD_TFT = 1<<20,
133};
134
135enum omap_dss_venc_type {
136 OMAP_DSS_VENC_TYPE_COMPOSITE,
137 OMAP_DSS_VENC_TYPE_SVIDEO,
138};
139
140enum omap_dss_dsi_pixel_format {
141 OMAP_DSS_DSI_FMT_RGB888,
142 OMAP_DSS_DSI_FMT_RGB666,
143 OMAP_DSS_DSI_FMT_RGB666_PACKED,
144 OMAP_DSS_DSI_FMT_RGB565,
145};
146
147enum omap_dss_dsi_mode {
148 OMAP_DSS_DSI_CMD_MODE = 0,
149 OMAP_DSS_DSI_VIDEO_MODE,
150};
151
152enum omap_display_caps {
153 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
154 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
155};
156
157enum omap_dss_display_state {
158 OMAP_DSS_DISPLAY_DISABLED = 0,
159 OMAP_DSS_DISPLAY_ACTIVE,
160 OMAP_DSS_DISPLAY_SUSPENDED,
161};
162
163enum omap_dss_audio_state {
164 OMAP_DSS_AUDIO_DISABLED = 0,
165 OMAP_DSS_AUDIO_ENABLED,
166 OMAP_DSS_AUDIO_CONFIGURED,
167 OMAP_DSS_AUDIO_PLAYING,
168};
169
170/* XXX perhaps this should be removed */
171enum omap_dss_overlay_managers {
172 OMAP_DSS_OVL_MGR_LCD,
173 OMAP_DSS_OVL_MGR_TV,
174 OMAP_DSS_OVL_MGR_LCD2,
175};
176
177enum omap_dss_rotation_type {
178 OMAP_DSS_ROT_DMA = 1 << 0,
179 OMAP_DSS_ROT_VRFB = 1 << 1,
180 OMAP_DSS_ROT_TILER = 1 << 2,
181};
182
183/* clockwise rotation angle */
184enum omap_dss_rotation_angle {
185 OMAP_DSS_ROT_0 = 0,
186 OMAP_DSS_ROT_90 = 1,
187 OMAP_DSS_ROT_180 = 2,
188 OMAP_DSS_ROT_270 = 3,
189};
190
191enum omap_overlay_caps {
192 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
193 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
194 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
195 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
196};
197
198enum omap_overlay_manager_caps {
199 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
200};
201
202enum omap_dss_clk_source {
203 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
204 * OMAP4: DSS_FCLK */
205 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
206 * OMAP4: PLL1_CLK1 */
207 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
208 * OMAP4: PLL1_CLK2 */
209 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
210 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
211};
212
213enum omap_hdmi_flags {
214 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
215};
216
217/* RFBI */
218
219struct rfbi_timings {
220 int cs_on_time;
221 int cs_off_time;
222 int we_on_time;
223 int we_off_time;
224 int re_on_time;
225 int re_off_time;
226 int we_cycle_time;
227 int re_cycle_time;
228 int cs_pulse_width;
229 int access_time;
230
231 int clk_div;
232
233 u32 tim[5]; /* set by rfbi_convert_timings() */
234
235 int converted;
236};
237
238void omap_rfbi_write_command(const void *buf, u32 len);
239void omap_rfbi_read_data(void *buf, u32 len);
240void omap_rfbi_write_data(const void *buf, u32 len);
241void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
242 u16 x, u16 y,
243 u16 w, u16 h);
244int omap_rfbi_enable_te(bool enable, unsigned line);
245int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
246 unsigned hs_pulse_time, unsigned vs_pulse_time,
247 int hs_pol_inv, int vs_pol_inv, int extif_div);
248void rfbi_bus_lock(void);
249void rfbi_bus_unlock(void);
250
251/* DSI */
252
253struct omap_dss_dsi_videomode_data {
254 /* DSI video mode blanking data */
255 /* Unit: byte clock cycles */
256 u16 hsa;
257 u16 hfp;
258 u16 hbp;
259 /* Unit: line clocks */
260 u16 vsa;
261 u16 vfp;
262 u16 vbp;
263
264 /* DSI blanking modes */
265 int blanking_mode;
266 int hsa_blanking_mode;
267 int hbp_blanking_mode;
268 int hfp_blanking_mode;
269
270 /* Video port sync events */
271 int vp_de_pol;
272 int vp_hsync_pol;
273 int vp_vsync_pol;
274 bool vp_vsync_end;
275 bool vp_hsync_end;
276
277 bool ddr_clk_always_on;
278 int window_sync;
279};
280
281void dsi_bus_lock(struct omap_dss_device *dssdev);
282void dsi_bus_unlock(struct omap_dss_device *dssdev);
283int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
284 int len);
285int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
286 int len);
287int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
288int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
289int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
290 u8 param);
291int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
292 u8 param);
293int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
294 u8 param1, u8 param2);
295int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
296 u8 *data, int len);
297int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
298 u8 *data, int len);
299int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
300 u8 *buf, int buflen);
301int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
302 int buflen);
303int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
304 u8 *buf, int buflen);
305int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
306 u8 param1, u8 param2, u8 *buf, int buflen);
307int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
308 u16 len);
309int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
310int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
311int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
312void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
313
314/* Board specific data */
315struct omap_dss_board_info {
316 int (*get_context_loss_count)(struct device *dev);
317 int num_devices;
318 struct omap_dss_device **devices;
319 struct omap_dss_device *default_device;
320 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
321 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
322 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
323};
324
325/* Init with the board info */
326extern int omap_display_init(struct omap_dss_board_info *board_data);
327/* HDMI mux init*/
328extern int omap_hdmi_init(enum omap_hdmi_flags flags);
329
330struct omap_video_timings {
331 /* Unit: pixels */
332 u16 x_res;
333 /* Unit: pixels */
334 u16 y_res;
335 /* Unit: KHz */
336 u32 pixel_clock;
337 /* Unit: pixel clocks */
338 u16 hsw; /* Horizontal synchronization pulse width */
339 /* Unit: pixel clocks */
340 u16 hfp; /* Horizontal front porch */
341 /* Unit: pixel clocks */
342 u16 hbp; /* Horizontal back porch */
343 /* Unit: line clocks */
344 u16 vsw; /* Vertical synchronization pulse width */
345 /* Unit: line clocks */
346 u16 vfp; /* Vertical front porch */
347 /* Unit: line clocks */
348 u16 vbp; /* Vertical back porch */
349};
350
351#ifdef CONFIG_OMAP2_DSS_VENC
352/* Hardcoded timings for tv modes. Venc only uses these to
353 * identify the mode, and does not actually use the configs
354 * itself. However, the configs should be something that
355 * a normal monitor can also show */
356extern const struct omap_video_timings omap_dss_pal_timings;
357extern const struct omap_video_timings omap_dss_ntsc_timings;
358#endif
359
360struct omap_dss_cpr_coefs {
361 s16 rr, rg, rb;
362 s16 gr, gg, gb;
363 s16 br, bg, bb;
364};
365
366struct omap_overlay_info {
367 u32 paddr;
368 u32 p_uv_addr; /* for NV12 format */
369 u16 screen_width;
370 u16 width;
371 u16 height;
372 enum omap_color_mode color_mode;
373 u8 rotation;
374 enum omap_dss_rotation_type rotation_type;
375 bool mirror;
376
377 u16 pos_x;
378 u16 pos_y;
379 u16 out_width; /* if 0, out_width == width */
380 u16 out_height; /* if 0, out_height == height */
381 u8 global_alpha;
382 u8 pre_mult_alpha;
383 u8 zorder;
384};
385
386struct omap_overlay {
387 struct kobject kobj;
388 struct list_head list;
389
390 /* static fields */
391 const char *name;
392 enum omap_plane id;
393 enum omap_color_mode supported_modes;
394 enum omap_overlay_caps caps;
395
396 /* dynamic fields */
397 struct omap_overlay_manager *manager;
398
399 /*
400 * The following functions do not block:
401 *
402 * is_enabled
403 * set_overlay_info
404 * get_overlay_info
405 *
406 * The rest of the functions may block and cannot be called from
407 * interrupt context
408 */
409
410 int (*enable)(struct omap_overlay *ovl);
411 int (*disable)(struct omap_overlay *ovl);
412 bool (*is_enabled)(struct omap_overlay *ovl);
413
414 int (*set_manager)(struct omap_overlay *ovl,
415 struct omap_overlay_manager *mgr);
416 int (*unset_manager)(struct omap_overlay *ovl);
417
418 int (*set_overlay_info)(struct omap_overlay *ovl,
419 struct omap_overlay_info *info);
420 void (*get_overlay_info)(struct omap_overlay *ovl,
421 struct omap_overlay_info *info);
422
423 int (*wait_for_go)(struct omap_overlay *ovl);
424};
425
426struct omap_overlay_manager_info {
427 u32 default_color;
428
429 enum omap_dss_trans_key_type trans_key_type;
430 u32 trans_key;
431 bool trans_enabled;
432
433 bool partial_alpha_enabled;
434
435 bool cpr_enable;
436 struct omap_dss_cpr_coefs cpr_coefs;
437};
438
439struct omap_overlay_manager {
440 struct kobject kobj;
441
442 /* static fields */
443 const char *name;
444 enum omap_channel id;
445 enum omap_overlay_manager_caps caps;
446 struct list_head overlays;
447 enum omap_display_type supported_displays;
448
449 /* dynamic fields */
450 struct omap_dss_device *device;
451
452 /*
453 * The following functions do not block:
454 *
455 * set_manager_info
456 * get_manager_info
457 * apply
458 *
459 * The rest of the functions may block and cannot be called from
460 * interrupt context
461 */
462
463 int (*set_device)(struct omap_overlay_manager *mgr,
464 struct omap_dss_device *dssdev);
465 int (*unset_device)(struct omap_overlay_manager *mgr);
466
467 int (*set_manager_info)(struct omap_overlay_manager *mgr,
468 struct omap_overlay_manager_info *info);
469 void (*get_manager_info)(struct omap_overlay_manager *mgr,
470 struct omap_overlay_manager_info *info);
471
472 int (*apply)(struct omap_overlay_manager *mgr);
473 int (*wait_for_go)(struct omap_overlay_manager *mgr);
474 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
475};
476
477/* 22 pins means 1 clk lane and 10 data lanes */
478#define OMAP_DSS_MAX_DSI_PINS 22
479
480struct omap_dsi_pin_config {
481 int num_pins;
482 /*
483 * pin numbers in the following order:
484 * clk+, clk-
485 * data1+, data1-
486 * data2+, data2-
487 * ...
488 */
489 int pins[OMAP_DSS_MAX_DSI_PINS];
490};
491
492struct omap_dss_device {
493 struct device dev;
494
495 enum omap_display_type type;
496
497 enum omap_channel channel;
498
499 union {
500 struct {
501 u8 data_lines;
502 } dpi;
503
504 struct {
505 u8 channel;
506 u8 data_lines;
507 } rfbi;
508
509 struct {
510 u8 datapairs;
511 } sdi;
512
513 struct {
514 int module;
515
516 bool ext_te;
517 u8 ext_te_gpio;
518 } dsi;
519
520 struct {
521 enum omap_dss_venc_type type;
522 bool invert_polarity;
523 } venc;
524 } phy;
525
526 struct {
527 struct {
528 struct {
529 u16 lck_div;
530 u16 pck_div;
531 enum omap_dss_clk_source lcd_clk_src;
532 } channel;
533
534 enum omap_dss_clk_source dispc_fclk_src;
535 } dispc;
536
537 struct {
538 /* regn is one greater than TRM's REGN value */
539 u16 regn;
540 u16 regm;
541 u16 regm_dispc;
542 u16 regm_dsi;
543
544 u16 lp_clk_div;
545 enum omap_dss_clk_source dsi_fclk_src;
546 } dsi;
547
548 struct {
549 /* regn is one greater than TRM's REGN value */
550 u16 regn;
551 u16 regm2;
552 } hdmi;
553 } clocks;
554
555 struct {
556 struct omap_video_timings timings;
557
558 int acbi; /* ac-bias pin transitions per interrupt */
559 /* Unit: line clocks */
560 int acb; /* ac-bias pin frequency */
561
562 enum omap_panel_config config;
563
564 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
565 enum omap_dss_dsi_mode dsi_mode;
566 struct omap_dss_dsi_videomode_data dsi_vm_data;
567 } panel;
568
569 struct {
570 u8 pixel_size;
571 struct rfbi_timings rfbi_timings;
572 } ctrl;
573
574 int reset_gpio;
575
576 int max_backlight_level;
577
578 const char *name;
579
580 /* used to match device to driver */
581 const char *driver_name;
582
583 void *data;
584
585 struct omap_dss_driver *driver;
586
587 /* helper variable for driver suspend/resume */
588 bool activate_after_resume;
589
590 enum omap_display_caps caps;
591
592 struct omap_overlay_manager *manager;
593
594 enum omap_dss_display_state state;
595
596 enum omap_dss_audio_state audio_state;
597
598 /* platform specific */
599 int (*platform_enable)(struct omap_dss_device *dssdev);
600 void (*platform_disable)(struct omap_dss_device *dssdev);
601 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
602 int (*get_backlight)(struct omap_dss_device *dssdev);
603};
604
605struct omap_dss_hdmi_data
606{
607 int hpd_gpio;
608};
609
610struct omap_dss_audio {
611 struct snd_aes_iec958 *iec;
612 struct snd_cea_861_aud_if *cea;
613};
614
615struct omap_dss_driver {
616 struct device_driver driver;
617
618 int (*probe)(struct omap_dss_device *);
619 void (*remove)(struct omap_dss_device *);
620
621 int (*enable)(struct omap_dss_device *display);
622 void (*disable)(struct omap_dss_device *display);
623 int (*suspend)(struct omap_dss_device *display);
624 int (*resume)(struct omap_dss_device *display);
625 int (*run_test)(struct omap_dss_device *display, int test);
626
627 int (*update)(struct omap_dss_device *dssdev,
628 u16 x, u16 y, u16 w, u16 h);
629 int (*sync)(struct omap_dss_device *dssdev);
630
631 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
632 int (*get_te)(struct omap_dss_device *dssdev);
633
634 u8 (*get_rotate)(struct omap_dss_device *dssdev);
635 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
636
637 bool (*get_mirror)(struct omap_dss_device *dssdev);
638 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
639
640 int (*memory_read)(struct omap_dss_device *dssdev,
641 void *buf, size_t size,
642 u16 x, u16 y, u16 w, u16 h);
643
644 void (*get_resolution)(struct omap_dss_device *dssdev,
645 u16 *xres, u16 *yres);
646 void (*get_dimensions)(struct omap_dss_device *dssdev,
647 u32 *width, u32 *height);
648 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
649
650 int (*check_timings)(struct omap_dss_device *dssdev,
651 struct omap_video_timings *timings);
652 void (*set_timings)(struct omap_dss_device *dssdev,
653 struct omap_video_timings *timings);
654 void (*get_timings)(struct omap_dss_device *dssdev,
655 struct omap_video_timings *timings);
656
657 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
658 u32 (*get_wss)(struct omap_dss_device *dssdev);
659
660 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
661 bool (*detect)(struct omap_dss_device *dssdev);
662
663 /*
664 * For display drivers that support audio. This encompasses
665 * HDMI and DisplayPort at the moment.
666 */
667 /*
668 * Note: These functions might sleep. Do not call while
669 * holding a spinlock/readlock.
670 */
671 int (*audio_enable)(struct omap_dss_device *dssdev);
672 void (*audio_disable)(struct omap_dss_device *dssdev);
673 bool (*audio_supported)(struct omap_dss_device *dssdev);
674 int (*audio_config)(struct omap_dss_device *dssdev,
675 struct omap_dss_audio *audio);
676 /* Note: These functions may not sleep */
677 int (*audio_start)(struct omap_dss_device *dssdev);
678 void (*audio_stop)(struct omap_dss_device *dssdev);
679
680};
681
682int omap_dss_register_driver(struct omap_dss_driver *);
683void omap_dss_unregister_driver(struct omap_dss_driver *);
684
685void omap_dss_get_device(struct omap_dss_device *dssdev);
686void omap_dss_put_device(struct omap_dss_device *dssdev);
687#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
688struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
689struct omap_dss_device *omap_dss_find_device(void *data,
690 int (*match)(struct omap_dss_device *dssdev, void *data));
691
692int omap_dss_start_device(struct omap_dss_device *dssdev);
693void omap_dss_stop_device(struct omap_dss_device *dssdev);
694
695int omap_dss_get_num_overlay_managers(void);
696struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
697
698int omap_dss_get_num_overlays(void);
699struct omap_overlay *omap_dss_get_overlay(int num);
700
701void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
702 u16 *xres, u16 *yres);
703int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
704void omapdss_default_get_timings(struct omap_dss_device *dssdev,
705 struct omap_video_timings *timings);
706
707typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
708int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
709int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
710
711int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
712int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
713 unsigned long timeout);
714
715#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
716#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
717
718void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
719 bool enable);
720int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
721
722int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
723 void (*callback)(int, void *), void *data);
724int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
725int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
726void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
727int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
728 const struct omap_dsi_pin_config *pin_cfg);
729
730int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
731void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
732 bool disconnect_lanes, bool enter_ulps);
733
734int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
735void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
736void dpi_set_timings(struct omap_dss_device *dssdev,
737 struct omap_video_timings *timings);
738int dpi_check_timings(struct omap_dss_device *dssdev,
739 struct omap_video_timings *timings);
740
741int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
742void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
743
744int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
745void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
746int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
747 u16 *x, u16 *y, u16 *w, u16 *h);
748int omap_rfbi_update(struct omap_dss_device *dssdev,
749 u16 x, u16 y, u16 w, u16 h,
750 void (*callback)(void *), void *data);
751int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
752 int data_lines);
753
754#endif