1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
   4 *
   5 * FIXME According to the usermanual the status bits in the status register
   6 * are only updated when the peripherals access the FIFO and not when the
   7 * CPU access them. So since we use this bits to know when we stop writing
   8 * and reading, they may not be updated in-time and a race condition may
   9 * exists. But I haven't be able to prove this and I don't care. But if
  10 * any problem arises, it might worth checking. The TX/RX FIFO Stats
  11 * registers should be used in addition.
  12 * Update: Actually, they seem updated ... At least the bits we use.
  13 *
  14 *
  15 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
  16 *
  17 * Some of the code has been inspired/copied from the 2.4 code written
  18 * by Dale Farnsworth <dfarnsworth@mvista.com>.
  19 *
  20 * Copyright (C) 2008 Freescale Semiconductor Inc.
  21 *                    John Rigby <jrigby@gmail.com>
  22 * Added support for MPC5121
  23 * Copyright (C) 2006 Secret Lab Technologies Ltd.
  24 *                    Grant Likely <grant.likely@secretlab.ca>
  25 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
  26 * Copyright (C) 2003 MontaVista, Software, Inc.
 
 
 
 
  27 */
  28
  29#undef DEBUG
  30
  31#include <linux/device.h>
  32#include <linux/module.h>
  33#include <linux/tty.h>
  34#include <linux/tty_flip.h>
  35#include <linux/serial.h>
  36#include <linux/sysrq.h>
  37#include <linux/console.h>
  38#include <linux/delay.h>
  39#include <linux/io.h>
  40#include <linux/of.h>
  41#include <linux/of_platform.h>
  42#include <linux/clk.h>
  43
  44#include <asm/mpc52xx.h>
  45#include <asm/mpc52xx_psc.h>
  46
  47#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  48#define SUPPORT_SYSRQ
  49#endif
  50
  51#include <linux/serial_core.h>
  52
  53
  54/* We've been assigned a range on the "Low-density serial ports" major */
  55#define SERIAL_PSC_MAJOR	204
  56#define SERIAL_PSC_MINOR	148
  57
  58
  59#define ISR_PASS_LIMIT 256	/* Max number of iteration in the interrupt */
  60
  61
  62static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
  63	/* Rem: - We use the read_status_mask as a shadow of
  64	 *        psc->mpc52xx_psc_imr
  65	 *      - It's important that is array is all zero on start as we
  66	 *        use it to know if it's initialized or not ! If it's not sure
  67	 *        it's cleared, then a memset(...,0,...) should be added to
  68	 *        the console_init
  69	 */
  70
  71/* lookup table for matching device nodes to index numbers */
  72static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
  73
  74static void mpc52xx_uart_of_enumerate(void);
  75
  76
  77#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
  78
  79
  80/* Forward declaration of the interruption handling routine */
  81static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
  82static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
  83
 
 
 
 
 
 
 
 
 
 
  84/* ======================================================================== */
  85/* PSC fifo operations for isolating differences between 52xx and 512x      */
  86/* ======================================================================== */
  87
  88struct psc_ops {
  89	void		(*fifo_init)(struct uart_port *port);
  90	int		(*raw_rx_rdy)(struct uart_port *port);
  91	int		(*raw_tx_rdy)(struct uart_port *port);
  92	int		(*rx_rdy)(struct uart_port *port);
  93	int		(*tx_rdy)(struct uart_port *port);
  94	int		(*tx_empty)(struct uart_port *port);
  95	void		(*stop_rx)(struct uart_port *port);
  96	void		(*start_tx)(struct uart_port *port);
  97	void		(*stop_tx)(struct uart_port *port);
  98	void		(*rx_clr_irq)(struct uart_port *port);
  99	void		(*tx_clr_irq)(struct uart_port *port);
 100	void		(*write_char)(struct uart_port *port, unsigned char c);
 101	unsigned char	(*read_char)(struct uart_port *port);
 102	void		(*cw_disable_ints)(struct uart_port *port);
 103	void		(*cw_restore_ints)(struct uart_port *port);
 104	unsigned int	(*set_baudrate)(struct uart_port *port,
 105					struct ktermios *new,
 106					struct ktermios *old);
 107	int		(*clock_alloc)(struct uart_port *port);
 108	void		(*clock_relse)(struct uart_port *port);
 109	int		(*clock)(struct uart_port *port, int enable);
 110	int		(*fifoc_init)(void);
 111	void		(*fifoc_uninit)(void);
 112	void		(*get_irq)(struct uart_port *, struct device_node *);
 113	irqreturn_t	(*handle_irq)(struct uart_port *port);
 114	u16		(*get_status)(struct uart_port *port);
 115	u8		(*get_ipcr)(struct uart_port *port);
 116	void		(*command)(struct uart_port *port, u8 cmd);
 117	void		(*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
 118	void		(*set_rts)(struct uart_port *port, int state);
 119	void		(*enable_ms)(struct uart_port *port);
 120	void		(*set_sicr)(struct uart_port *port, u32 val);
 121	void		(*set_imr)(struct uart_port *port, u16 val);
 122	u8		(*get_mr1)(struct uart_port *port);
 123};
 124
 125/* setting the prescaler and divisor reg is common for all chips */
 126static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
 127				       u16 prescaler, unsigned int divisor)
 128{
 129	/* select prescaler */
 130	out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
 131	out_8(&psc->ctur, divisor >> 8);
 132	out_8(&psc->ctlr, divisor & 0xff);
 133}
 134
 135static u16 mpc52xx_psc_get_status(struct uart_port *port)
 136{
 137	return in_be16(&PSC(port)->mpc52xx_psc_status);
 138}
 139
 140static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
 141{
 142	return in_8(&PSC(port)->mpc52xx_psc_ipcr);
 143}
 144
 145static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
 146{
 147	out_8(&PSC(port)->command, cmd);
 148}
 149
 150static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
 151{
 152	out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
 153	out_8(&PSC(port)->mode, mr1);
 154	out_8(&PSC(port)->mode, mr2);
 155}
 156
 157static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
 158{
 159	if (state)
 160		out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
 161	else
 162		out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
 163}
 164
 165static void mpc52xx_psc_enable_ms(struct uart_port *port)
 166{
 167	struct mpc52xx_psc __iomem *psc = PSC(port);
 168
 169	/* clear D_*-bits by reading them */
 170	in_8(&psc->mpc52xx_psc_ipcr);
 171	/* enable CTS and DCD as IPC interrupts */
 172	out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
 173
 174	port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
 175	out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
 176}
 177
 178static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
 179{
 180	out_be32(&PSC(port)->sicr, val);
 181}
 182
 183static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
 184{
 185	out_be16(&PSC(port)->mpc52xx_psc_imr, val);
 186}
 187
 188static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
 189{
 190	out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
 191	return in_8(&PSC(port)->mode);
 192}
 193
 194#ifdef CONFIG_PPC_MPC52xx
 195#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
 196static void mpc52xx_psc_fifo_init(struct uart_port *port)
 197{
 198	struct mpc52xx_psc __iomem *psc = PSC(port);
 199	struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
 200
 201	out_8(&fifo->rfcntl, 0x00);
 202	out_be16(&fifo->rfalarm, 0x1ff);
 203	out_8(&fifo->tfcntl, 0x07);
 204	out_be16(&fifo->tfalarm, 0x80);
 205
 206	port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
 207	out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
 208}
 209
 210static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
 211{
 212	return in_be16(&PSC(port)->mpc52xx_psc_status)
 213	    & MPC52xx_PSC_SR_RXRDY;
 214}
 215
 216static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
 217{
 218	return in_be16(&PSC(port)->mpc52xx_psc_status)
 219	    & MPC52xx_PSC_SR_TXRDY;
 220}
 221
 222
 223static int mpc52xx_psc_rx_rdy(struct uart_port *port)
 224{
 225	return in_be16(&PSC(port)->mpc52xx_psc_isr)
 226	    & port->read_status_mask
 227	    & MPC52xx_PSC_IMR_RXRDY;
 228}
 229
 230static int mpc52xx_psc_tx_rdy(struct uart_port *port)
 231{
 232	return in_be16(&PSC(port)->mpc52xx_psc_isr)
 233	    & port->read_status_mask
 234	    & MPC52xx_PSC_IMR_TXRDY;
 235}
 236
 237static int mpc52xx_psc_tx_empty(struct uart_port *port)
 238{
 239	u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
 240
 241	return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
 242}
 243
 244static void mpc52xx_psc_start_tx(struct uart_port *port)
 245{
 246	port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
 247	out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
 248}
 249
 250static void mpc52xx_psc_stop_tx(struct uart_port *port)
 251{
 252	port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
 253	out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
 254}
 255
 256static void mpc52xx_psc_stop_rx(struct uart_port *port)
 257{
 258	port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
 259	out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
 260}
 261
 262static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
 263{
 264}
 265
 266static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
 267{
 268}
 269
 270static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
 271{
 272	out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
 273}
 274
 275static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
 276{
 277	return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
 278}
 279
 280static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
 281{
 282	out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
 283}
 284
 285static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
 286{
 287	out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
 288}
 289
 290static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
 291					     struct ktermios *new,
 292					     struct ktermios *old)
 293{
 294	unsigned int baud;
 295	unsigned int divisor;
 296
 297	/* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
 298	baud = uart_get_baud_rate(port, new, old,
 299				  port->uartclk / (32 * 0xffff) + 1,
 300				  port->uartclk / 32);
 301	divisor = (port->uartclk + 16 * baud) / (32 * baud);
 302
 303	/* enable the /32 prescaler and set the divisor */
 304	mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
 305	return baud;
 306}
 307
 308static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
 309					      struct ktermios *new,
 310					      struct ktermios *old)
 311{
 312	unsigned int baud;
 313	unsigned int divisor;
 314	u16 prescaler;
 315
 316	/* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
 317	 * ipb freq */
 318	baud = uart_get_baud_rate(port, new, old,
 319				  port->uartclk / (32 * 0xffff) + 1,
 320				  port->uartclk / 4);
 321	divisor = (port->uartclk + 2 * baud) / (4 * baud);
 322
 323	/* select the proper prescaler and set the divisor
 324	 * prefer high prescaler for more tolerance on low baudrates */
 325	if (divisor > 0xffff || baud <= 115200) {
 326		divisor = (divisor + 4) / 8;
 327		prescaler = 0xdd00; /* /32 */
 328	} else
 329		prescaler = 0xff00; /* /4 */
 330	mpc52xx_set_divisor(PSC(port), prescaler, divisor);
 331	return baud;
 332}
 333
 334static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
 335{
 336	port->irqflags = 0;
 337	port->irq = irq_of_parse_and_map(np, 0);
 338}
 339
 340/* 52xx specific interrupt handler. The caller holds the port lock */
 341static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
 342{
 343	return mpc5xxx_uart_process_int(port);
 344}
 345
 346static const struct psc_ops mpc52xx_psc_ops = {
 347	.fifo_init = mpc52xx_psc_fifo_init,
 348	.raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
 349	.raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
 350	.rx_rdy = mpc52xx_psc_rx_rdy,
 351	.tx_rdy = mpc52xx_psc_tx_rdy,
 352	.tx_empty = mpc52xx_psc_tx_empty,
 353	.stop_rx = mpc52xx_psc_stop_rx,
 354	.start_tx = mpc52xx_psc_start_tx,
 355	.stop_tx = mpc52xx_psc_stop_tx,
 356	.rx_clr_irq = mpc52xx_psc_rx_clr_irq,
 357	.tx_clr_irq = mpc52xx_psc_tx_clr_irq,
 358	.write_char = mpc52xx_psc_write_char,
 359	.read_char = mpc52xx_psc_read_char,
 360	.cw_disable_ints = mpc52xx_psc_cw_disable_ints,
 361	.cw_restore_ints = mpc52xx_psc_cw_restore_ints,
 362	.set_baudrate = mpc5200_psc_set_baudrate,
 363	.get_irq = mpc52xx_psc_get_irq,
 364	.handle_irq = mpc52xx_psc_handle_irq,
 365	.get_status = mpc52xx_psc_get_status,
 366	.get_ipcr = mpc52xx_psc_get_ipcr,
 367	.command = mpc52xx_psc_command,
 368	.set_mode = mpc52xx_psc_set_mode,
 369	.set_rts = mpc52xx_psc_set_rts,
 370	.enable_ms = mpc52xx_psc_enable_ms,
 371	.set_sicr = mpc52xx_psc_set_sicr,
 372	.set_imr = mpc52xx_psc_set_imr,
 373	.get_mr1 = mpc52xx_psc_get_mr1,
 374};
 375
 376static const struct psc_ops mpc5200b_psc_ops = {
 377	.fifo_init = mpc52xx_psc_fifo_init,
 378	.raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
 379	.raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
 380	.rx_rdy = mpc52xx_psc_rx_rdy,
 381	.tx_rdy = mpc52xx_psc_tx_rdy,
 382	.tx_empty = mpc52xx_psc_tx_empty,
 383	.stop_rx = mpc52xx_psc_stop_rx,
 384	.start_tx = mpc52xx_psc_start_tx,
 385	.stop_tx = mpc52xx_psc_stop_tx,
 386	.rx_clr_irq = mpc52xx_psc_rx_clr_irq,
 387	.tx_clr_irq = mpc52xx_psc_tx_clr_irq,
 388	.write_char = mpc52xx_psc_write_char,
 389	.read_char = mpc52xx_psc_read_char,
 390	.cw_disable_ints = mpc52xx_psc_cw_disable_ints,
 391	.cw_restore_ints = mpc52xx_psc_cw_restore_ints,
 392	.set_baudrate = mpc5200b_psc_set_baudrate,
 393	.get_irq = mpc52xx_psc_get_irq,
 394	.handle_irq = mpc52xx_psc_handle_irq,
 395	.get_status = mpc52xx_psc_get_status,
 396	.get_ipcr = mpc52xx_psc_get_ipcr,
 397	.command = mpc52xx_psc_command,
 398	.set_mode = mpc52xx_psc_set_mode,
 399	.set_rts = mpc52xx_psc_set_rts,
 400	.enable_ms = mpc52xx_psc_enable_ms,
 401	.set_sicr = mpc52xx_psc_set_sicr,
 402	.set_imr = mpc52xx_psc_set_imr,
 403	.get_mr1 = mpc52xx_psc_get_mr1,
 404};
 405
 406#endif /* CONFIG_PPC_MPC52xx */
 407
 408#ifdef CONFIG_PPC_MPC512x
 409#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
 410
 411/* PSC FIFO Controller for mpc512x */
 412struct psc_fifoc {
 413	u32 fifoc_cmd;
 414	u32 fifoc_int;
 415	u32 fifoc_dma;
 416	u32 fifoc_axe;
 417	u32 fifoc_debug;
 418};
 419
 420static struct psc_fifoc __iomem *psc_fifoc;
 421static unsigned int psc_fifoc_irq;
 422static struct clk *psc_fifoc_clk;
 423
 424static void mpc512x_psc_fifo_init(struct uart_port *port)
 425{
 426	/* /32 prescaler */
 427	out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
 428
 429	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
 430	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
 431	out_be32(&FIFO_512x(port)->txalarm, 1);
 432	out_be32(&FIFO_512x(port)->tximr, 0);
 433
 434	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
 435	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
 436	out_be32(&FIFO_512x(port)->rxalarm, 1);
 437	out_be32(&FIFO_512x(port)->rximr, 0);
 438
 439	out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
 440	out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
 441}
 442
 443static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
 444{
 445	return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
 446}
 447
 448static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
 449{
 450	return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
 451}
 452
 453static int mpc512x_psc_rx_rdy(struct uart_port *port)
 454{
 455	return in_be32(&FIFO_512x(port)->rxsr)
 456	    & in_be32(&FIFO_512x(port)->rximr)
 457	    & MPC512x_PSC_FIFO_ALARM;
 458}
 459
 460static int mpc512x_psc_tx_rdy(struct uart_port *port)
 461{
 462	return in_be32(&FIFO_512x(port)->txsr)
 463	    & in_be32(&FIFO_512x(port)->tximr)
 464	    & MPC512x_PSC_FIFO_ALARM;
 465}
 466
 467static int mpc512x_psc_tx_empty(struct uart_port *port)
 468{
 469	return in_be32(&FIFO_512x(port)->txsr)
 470	    & MPC512x_PSC_FIFO_EMPTY;
 471}
 472
 473static void mpc512x_psc_stop_rx(struct uart_port *port)
 474{
 475	unsigned long rx_fifo_imr;
 476
 477	rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
 478	rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
 479	out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
 480}
 481
 482static void mpc512x_psc_start_tx(struct uart_port *port)
 483{
 484	unsigned long tx_fifo_imr;
 485
 486	tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
 487	tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
 488	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
 489}
 490
 491static void mpc512x_psc_stop_tx(struct uart_port *port)
 492{
 493	unsigned long tx_fifo_imr;
 494
 495	tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
 496	tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
 497	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
 498}
 499
 500static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
 501{
 502	out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
 503}
 504
 505static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
 506{
 507	out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
 508}
 509
 510static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
 511{
 512	out_8(&FIFO_512x(port)->txdata_8, c);
 513}
 514
 515static unsigned char mpc512x_psc_read_char(struct uart_port *port)
 516{
 517	return in_8(&FIFO_512x(port)->rxdata_8);
 518}
 519
 520static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
 521{
 522	port->read_status_mask =
 523		in_be32(&FIFO_512x(port)->tximr) << 16 |
 524		in_be32(&FIFO_512x(port)->rximr);
 525	out_be32(&FIFO_512x(port)->tximr, 0);
 526	out_be32(&FIFO_512x(port)->rximr, 0);
 527}
 528
 529static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
 530{
 531	out_be32(&FIFO_512x(port)->tximr,
 532		(port->read_status_mask >> 16) & 0x7f);
 533	out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
 534}
 535
 536static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
 537					     struct ktermios *new,
 538					     struct ktermios *old)
 539{
 540	unsigned int baud;
 541	unsigned int divisor;
 542
 543	/*
 544	 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
 545	 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
 546	 * Furthermore, it states that "After reset, the prescaler by 10
 547	 * for the UART mode is selected", but the reset register value is
 548	 * 0x0000 which means a /32 prescaler. This is wrong.
 549	 *
 550	 * In reality using /32 prescaler doesn't work, as it is not supported!
 551	 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
 552	 * Chapter 4.1 PSC in UART Mode.
 553	 * Calculate with a /16 prescaler here.
 554	 */
 555
 556	/* uartclk contains the ips freq */
 557	baud = uart_get_baud_rate(port, new, old,
 558				  port->uartclk / (16 * 0xffff) + 1,
 559				  port->uartclk / 16);
 560	divisor = (port->uartclk + 8 * baud) / (16 * baud);
 561
 562	/* enable the /16 prescaler and set the divisor */
 563	mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
 564	return baud;
 565}
 566
 567/* Init PSC FIFO Controller */
 568static int __init mpc512x_psc_fifoc_init(void)
 569{
 570	int err;
 571	struct device_node *np;
 572	struct clk *clk;
 573
 574	/* default error code, potentially overwritten by clock calls */
 575	err = -ENODEV;
 576
 577	np = of_find_compatible_node(NULL, NULL,
 578				     "fsl,mpc5121-psc-fifo");
 579	if (!np) {
 580		pr_err("%s: Can't find FIFOC node\n", __func__);
 581		goto out_err;
 582	}
 583
 584	clk = of_clk_get(np, 0);
 585	if (IS_ERR(clk)) {
 586		/* backwards compat with device trees that lack clock specs */
 587		clk = clk_get_sys(np->name, "ipg");
 588	}
 589	if (IS_ERR(clk)) {
 590		pr_err("%s: Can't lookup FIFO clock\n", __func__);
 591		err = PTR_ERR(clk);
 592		goto out_ofnode_put;
 593	}
 594	if (clk_prepare_enable(clk)) {
 595		pr_err("%s: Can't enable FIFO clock\n", __func__);
 596		clk_put(clk);
 597		goto out_ofnode_put;
 598	}
 599	psc_fifoc_clk = clk;
 600
 601	psc_fifoc = of_iomap(np, 0);
 602	if (!psc_fifoc) {
 603		pr_err("%s: Can't map FIFOC\n", __func__);
 604		goto out_clk_disable;
 
 605	}
 606
 607	psc_fifoc_irq = irq_of_parse_and_map(np, 0);
 
 608	if (psc_fifoc_irq == 0) {
 609		pr_err("%s: Can't get FIFOC irq\n", __func__);
 610		goto out_unmap;
 
 611	}
 612
 613	of_node_put(np);
 614	return 0;
 615
 616out_unmap:
 617	iounmap(psc_fifoc);
 618out_clk_disable:
 619	clk_disable_unprepare(psc_fifoc_clk);
 620	clk_put(psc_fifoc_clk);
 621out_ofnode_put:
 622	of_node_put(np);
 623out_err:
 624	return err;
 625}
 626
 627static void __exit mpc512x_psc_fifoc_uninit(void)
 628{
 629	iounmap(psc_fifoc);
 630
 631	/* disable the clock, errors are not fatal */
 632	if (psc_fifoc_clk) {
 633		clk_disable_unprepare(psc_fifoc_clk);
 634		clk_put(psc_fifoc_clk);
 635		psc_fifoc_clk = NULL;
 636	}
 637}
 638
 639/* 512x specific interrupt handler. The caller holds the port lock */
 640static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
 641{
 642	unsigned long fifoc_int;
 643	int psc_num;
 644
 645	/* Read pending PSC FIFOC interrupts */
 646	fifoc_int = in_be32(&psc_fifoc->fifoc_int);
 647
 648	/* Check if it is an interrupt for this port */
 649	psc_num = (port->mapbase & 0xf00) >> 8;
 650	if (test_bit(psc_num, &fifoc_int) ||
 651	    test_bit(psc_num + 16, &fifoc_int))
 652		return mpc5xxx_uart_process_int(port);
 653
 654	return IRQ_NONE;
 655}
 656
 657static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
 658static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM];
 659
 660/* called from within the .request_port() callback (allocation) */
 661static int mpc512x_psc_alloc_clock(struct uart_port *port)
 662{
 663	int psc_num;
 664	struct clk *clk;
 665	int err;
 666
 667	psc_num = (port->mapbase & 0xf00) >> 8;
 668
 669	clk = devm_clk_get(port->dev, "mclk");
 670	if (IS_ERR(clk)) {
 671		dev_err(port->dev, "Failed to get MCLK!\n");
 672		err = PTR_ERR(clk);
 673		goto out_err;
 674	}
 675	err = clk_prepare_enable(clk);
 676	if (err) {
 677		dev_err(port->dev, "Failed to enable MCLK!\n");
 678		goto out_err;
 679	}
 680	psc_mclk_clk[psc_num] = clk;
 681
 682	clk = devm_clk_get(port->dev, "ipg");
 683	if (IS_ERR(clk)) {
 684		dev_err(port->dev, "Failed to get IPG clock!\n");
 685		err = PTR_ERR(clk);
 686		goto out_err;
 687	}
 688	err = clk_prepare_enable(clk);
 689	if (err) {
 690		dev_err(port->dev, "Failed to enable IPG clock!\n");
 691		goto out_err;
 692	}
 693	psc_ipg_clk[psc_num] = clk;
 694
 695	return 0;
 696
 697out_err:
 698	if (psc_mclk_clk[psc_num]) {
 699		clk_disable_unprepare(psc_mclk_clk[psc_num]);
 700		psc_mclk_clk[psc_num] = NULL;
 701	}
 702	if (psc_ipg_clk[psc_num]) {
 703		clk_disable_unprepare(psc_ipg_clk[psc_num]);
 704		psc_ipg_clk[psc_num] = NULL;
 705	}
 706	return err;
 707}
 708
 709/* called from within the .release_port() callback (release) */
 710static void mpc512x_psc_relse_clock(struct uart_port *port)
 711{
 712	int psc_num;
 713	struct clk *clk;
 714
 715	psc_num = (port->mapbase & 0xf00) >> 8;
 716	clk = psc_mclk_clk[psc_num];
 717	if (clk) {
 718		clk_disable_unprepare(clk);
 719		psc_mclk_clk[psc_num] = NULL;
 720	}
 721	if (psc_ipg_clk[psc_num]) {
 722		clk_disable_unprepare(psc_ipg_clk[psc_num]);
 723		psc_ipg_clk[psc_num] = NULL;
 724	}
 725}
 726
 727/* implementation of the .clock() callback (enable/disable) */
 728static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
 729{
 730	int psc_num;
 731	struct clk *psc_clk;
 732	int ret;
 
 733
 734	if (uart_console(port))
 735		return 0;
 736
 737	psc_num = (port->mapbase & 0xf00) >> 8;
 738	psc_clk = psc_mclk_clk[psc_num];
 739	if (!psc_clk) {
 
 740		dev_err(port->dev, "Failed to get PSC clock entry!\n");
 741		return -ENODEV;
 742	}
 743
 744	dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
 745	if (enable) {
 746		ret = clk_enable(psc_clk);
 747		if (ret)
 748			dev_err(port->dev, "Failed to enable MCLK!\n");
 749		return ret;
 750	} else {
 751		clk_disable(psc_clk);
 752		return 0;
 753	}
 754}
 755
 756static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
 757{
 758	port->irqflags = IRQF_SHARED;
 759	port->irq = psc_fifoc_irq;
 760}
 761#endif
 762
 763#ifdef CONFIG_PPC_MPC512x
 764
 765#define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
 766#define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
 767
 768static void mpc5125_psc_fifo_init(struct uart_port *port)
 769{
 770	/* /32 prescaler */
 771	out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
 772
 773	out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
 774	out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
 775	out_be32(&FIFO_5125(port)->txalarm, 1);
 776	out_be32(&FIFO_5125(port)->tximr, 0);
 777
 778	out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
 779	out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
 780	out_be32(&FIFO_5125(port)->rxalarm, 1);
 781	out_be32(&FIFO_5125(port)->rximr, 0);
 782
 783	out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
 784	out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
 785}
 786
 787static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
 788{
 789	return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
 790}
 791
 792static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
 793{
 794	return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
 795}
 796
 797static int mpc5125_psc_rx_rdy(struct uart_port *port)
 798{
 799	return in_be32(&FIFO_5125(port)->rxsr) &
 800	       in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
 801}
 802
 803static int mpc5125_psc_tx_rdy(struct uart_port *port)
 804{
 805	return in_be32(&FIFO_5125(port)->txsr) &
 806	       in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
 807}
 808
 809static int mpc5125_psc_tx_empty(struct uart_port *port)
 810{
 811	return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
 812}
 813
 814static void mpc5125_psc_stop_rx(struct uart_port *port)
 815{
 816	unsigned long rx_fifo_imr;
 817
 818	rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
 819	rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
 820	out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
 821}
 822
 823static void mpc5125_psc_start_tx(struct uart_port *port)
 824{
 825	unsigned long tx_fifo_imr;
 826
 827	tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
 828	tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
 829	out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
 830}
 831
 832static void mpc5125_psc_stop_tx(struct uart_port *port)
 833{
 834	unsigned long tx_fifo_imr;
 835
 836	tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
 837	tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
 838	out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
 839}
 840
 841static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
 842{
 843	out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
 844}
 845
 846static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
 847{
 848	out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
 849}
 850
 851static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
 852{
 853	out_8(&FIFO_5125(port)->txdata_8, c);
 854}
 855
 856static unsigned char mpc5125_psc_read_char(struct uart_port *port)
 857{
 858	return in_8(&FIFO_5125(port)->rxdata_8);
 859}
 860
 861static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
 862{
 863	port->read_status_mask =
 864		in_be32(&FIFO_5125(port)->tximr) << 16 |
 865		in_be32(&FIFO_5125(port)->rximr);
 866	out_be32(&FIFO_5125(port)->tximr, 0);
 867	out_be32(&FIFO_5125(port)->rximr, 0);
 868}
 869
 870static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
 871{
 872	out_be32(&FIFO_5125(port)->tximr,
 873		(port->read_status_mask >> 16) & 0x7f);
 874	out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
 875}
 876
 877static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
 878		u8 prescaler, unsigned int divisor)
 879{
 880	/* select prescaler */
 881	out_8(&psc->mpc52xx_psc_clock_select, prescaler);
 882	out_8(&psc->ctur, divisor >> 8);
 883	out_8(&psc->ctlr, divisor & 0xff);
 884}
 885
 886static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
 887					     struct ktermios *new,
 888					     struct ktermios *old)
 889{
 890	unsigned int baud;
 891	unsigned int divisor;
 892
 893	/*
 894	 * Calculate with a /16 prescaler here.
 895	 */
 896
 897	/* uartclk contains the ips freq */
 898	baud = uart_get_baud_rate(port, new, old,
 899				  port->uartclk / (16 * 0xffff) + 1,
 900				  port->uartclk / 16);
 901	divisor = (port->uartclk + 8 * baud) / (16 * baud);
 902
 903	/* enable the /16 prescaler and set the divisor */
 904	mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
 905	return baud;
 906}
 907
 908/*
 909 * MPC5125 have compatible PSC FIFO Controller.
 910 * Special init not needed.
 911 */
 912static u16 mpc5125_psc_get_status(struct uart_port *port)
 913{
 914	return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
 915}
 916
 917static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
 918{
 919	return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
 920}
 921
 922static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
 923{
 924	out_8(&PSC_5125(port)->command, cmd);
 925}
 926
 927static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
 928{
 929	out_8(&PSC_5125(port)->mr1, mr1);
 930	out_8(&PSC_5125(port)->mr2, mr2);
 931}
 932
 933static void mpc5125_psc_set_rts(struct uart_port *port, int state)
 934{
 935	if (state & TIOCM_RTS)
 936		out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
 937	else
 938		out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
 939}
 940
 941static void mpc5125_psc_enable_ms(struct uart_port *port)
 942{
 943	struct mpc5125_psc __iomem *psc = PSC_5125(port);
 944
 945	/* clear D_*-bits by reading them */
 946	in_8(&psc->mpc52xx_psc_ipcr);
 947	/* enable CTS and DCD as IPC interrupts */
 948	out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
 949
 950	port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
 951	out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
 952}
 953
 954static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
 955{
 956	out_be32(&PSC_5125(port)->sicr, val);
 957}
 958
 959static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
 960{
 961	out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
 962}
 963
 964static u8 mpc5125_psc_get_mr1(struct uart_port *port)
 965{
 966	return in_8(&PSC_5125(port)->mr1);
 967}
 968
 969static const struct psc_ops mpc5125_psc_ops = {
 970	.fifo_init = mpc5125_psc_fifo_init,
 971	.raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
 972	.raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
 973	.rx_rdy = mpc5125_psc_rx_rdy,
 974	.tx_rdy = mpc5125_psc_tx_rdy,
 975	.tx_empty = mpc5125_psc_tx_empty,
 976	.stop_rx = mpc5125_psc_stop_rx,
 977	.start_tx = mpc5125_psc_start_tx,
 978	.stop_tx = mpc5125_psc_stop_tx,
 979	.rx_clr_irq = mpc5125_psc_rx_clr_irq,
 980	.tx_clr_irq = mpc5125_psc_tx_clr_irq,
 981	.write_char = mpc5125_psc_write_char,
 982	.read_char = mpc5125_psc_read_char,
 983	.cw_disable_ints = mpc5125_psc_cw_disable_ints,
 984	.cw_restore_ints = mpc5125_psc_cw_restore_ints,
 985	.set_baudrate = mpc5125_psc_set_baudrate,
 986	.clock_alloc = mpc512x_psc_alloc_clock,
 987	.clock_relse = mpc512x_psc_relse_clock,
 988	.clock = mpc512x_psc_endis_clock,
 989	.fifoc_init = mpc512x_psc_fifoc_init,
 990	.fifoc_uninit = mpc512x_psc_fifoc_uninit,
 991	.get_irq = mpc512x_psc_get_irq,
 992	.handle_irq = mpc512x_psc_handle_irq,
 993	.get_status = mpc5125_psc_get_status,
 994	.get_ipcr = mpc5125_psc_get_ipcr,
 995	.command = mpc5125_psc_command,
 996	.set_mode = mpc5125_psc_set_mode,
 997	.set_rts = mpc5125_psc_set_rts,
 998	.enable_ms = mpc5125_psc_enable_ms,
 999	.set_sicr = mpc5125_psc_set_sicr,
1000	.set_imr = mpc5125_psc_set_imr,
1001	.get_mr1 = mpc5125_psc_get_mr1,
1002};
1003
1004static const struct psc_ops mpc512x_psc_ops = {
1005	.fifo_init = mpc512x_psc_fifo_init,
1006	.raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
1007	.raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
1008	.rx_rdy = mpc512x_psc_rx_rdy,
1009	.tx_rdy = mpc512x_psc_tx_rdy,
1010	.tx_empty = mpc512x_psc_tx_empty,
1011	.stop_rx = mpc512x_psc_stop_rx,
1012	.start_tx = mpc512x_psc_start_tx,
1013	.stop_tx = mpc512x_psc_stop_tx,
1014	.rx_clr_irq = mpc512x_psc_rx_clr_irq,
1015	.tx_clr_irq = mpc512x_psc_tx_clr_irq,
1016	.write_char = mpc512x_psc_write_char,
1017	.read_char = mpc512x_psc_read_char,
1018	.cw_disable_ints = mpc512x_psc_cw_disable_ints,
1019	.cw_restore_ints = mpc512x_psc_cw_restore_ints,
1020	.set_baudrate = mpc512x_psc_set_baudrate,
1021	.clock_alloc = mpc512x_psc_alloc_clock,
1022	.clock_relse = mpc512x_psc_relse_clock,
1023	.clock = mpc512x_psc_endis_clock,
1024	.fifoc_init = mpc512x_psc_fifoc_init,
1025	.fifoc_uninit = mpc512x_psc_fifoc_uninit,
1026	.get_irq = mpc512x_psc_get_irq,
1027	.handle_irq = mpc512x_psc_handle_irq,
1028	.get_status = mpc52xx_psc_get_status,
1029	.get_ipcr = mpc52xx_psc_get_ipcr,
1030	.command = mpc52xx_psc_command,
1031	.set_mode = mpc52xx_psc_set_mode,
1032	.set_rts = mpc52xx_psc_set_rts,
1033	.enable_ms = mpc52xx_psc_enable_ms,
1034	.set_sicr = mpc52xx_psc_set_sicr,
1035	.set_imr = mpc52xx_psc_set_imr,
1036	.get_mr1 = mpc52xx_psc_get_mr1,
1037};
1038#endif /* CONFIG_PPC_MPC512x */
1039
1040
1041static const struct psc_ops *psc_ops;
1042
1043/* ======================================================================== */
1044/* UART operations                                                          */
1045/* ======================================================================== */
1046
1047static unsigned int
1048mpc52xx_uart_tx_empty(struct uart_port *port)
1049{
1050	return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
1051}
1052
1053static void
1054mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1055{
1056	psc_ops->set_rts(port, mctrl & TIOCM_RTS);
 
 
 
1057}
1058
1059static unsigned int
1060mpc52xx_uart_get_mctrl(struct uart_port *port)
1061{
1062	unsigned int ret = TIOCM_DSR;
1063	u8 status = psc_ops->get_ipcr(port);
1064
1065	if (!(status & MPC52xx_PSC_CTS))
1066		ret |= TIOCM_CTS;
1067	if (!(status & MPC52xx_PSC_DCD))
1068		ret |= TIOCM_CAR;
1069
1070	return ret;
1071}
1072
1073static void
1074mpc52xx_uart_stop_tx(struct uart_port *port)
1075{
1076	/* port->lock taken by caller */
1077	psc_ops->stop_tx(port);
1078}
1079
1080static void
1081mpc52xx_uart_start_tx(struct uart_port *port)
1082{
1083	/* port->lock taken by caller */
1084	psc_ops->start_tx(port);
1085}
1086
1087static void
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1088mpc52xx_uart_stop_rx(struct uart_port *port)
1089{
1090	/* port->lock taken by caller */
1091	psc_ops->stop_rx(port);
1092}
1093
1094static void
1095mpc52xx_uart_enable_ms(struct uart_port *port)
1096{
1097	psc_ops->enable_ms(port);
 
 
 
 
 
 
 
 
1098}
1099
1100static void
1101mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1102{
1103	unsigned long flags;
1104	spin_lock_irqsave(&port->lock, flags);
1105
1106	if (ctl == -1)
1107		psc_ops->command(port, MPC52xx_PSC_START_BRK);
1108	else
1109		psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1110
1111	spin_unlock_irqrestore(&port->lock, flags);
1112}
1113
1114static int
1115mpc52xx_uart_startup(struct uart_port *port)
1116{
 
1117	int ret;
1118
1119	if (psc_ops->clock) {
1120		ret = psc_ops->clock(port, 1);
1121		if (ret)
1122			return ret;
1123	}
1124
1125	/* Request IRQ */
1126	ret = request_irq(port->irq, mpc52xx_uart_int,
1127			  port->irqflags, "mpc52xx_psc_uart", port);
1128	if (ret)
1129		return ret;
1130
1131	/* Reset/activate the port, clear and enable interrupts */
1132	psc_ops->command(port, MPC52xx_PSC_RST_RX);
1133	psc_ops->command(port, MPC52xx_PSC_RST_TX);
1134
1135	/*
1136	 * According to Freescale's support the RST_TX command can produce a
1137	 * spike on the TX pin. So they recommend to delay "for one character".
1138	 * One millisecond should be enough for everyone.
1139	 */
1140	msleep(1);
1141
1142	psc_ops->set_sicr(port, 0);	/* UART mode DCD ignored */
1143
1144	psc_ops->fifo_init(port);
1145
1146	psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1147	psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1148
1149	return 0;
1150}
1151
1152static void
1153mpc52xx_uart_shutdown(struct uart_port *port)
1154{
 
 
1155	/* Shut down the port.  Leave TX active if on a console port */
1156	psc_ops->command(port, MPC52xx_PSC_RST_RX);
1157	if (!uart_console(port))
1158		psc_ops->command(port, MPC52xx_PSC_RST_TX);
1159
1160	port->read_status_mask = 0;
1161	psc_ops->set_imr(port, port->read_status_mask);
1162
1163	if (psc_ops->clock)
1164		psc_ops->clock(port, 0);
1165
1166	/* Disable interrupt */
1167	psc_ops->cw_disable_ints(port);
1168
1169	/* Release interrupt */
1170	free_irq(port->irq, port);
1171}
1172
1173static void
1174mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1175			 struct ktermios *old)
1176{
 
1177	unsigned long flags;
1178	unsigned char mr1, mr2;
1179	unsigned int j;
1180	unsigned int baud;
1181
1182	/* Prepare what we're gonna write */
1183	mr1 = 0;
1184
1185	switch (new->c_cflag & CSIZE) {
1186	case CS5:	mr1 |= MPC52xx_PSC_MODE_5_BITS;
1187		break;
1188	case CS6:	mr1 |= MPC52xx_PSC_MODE_6_BITS;
1189		break;
1190	case CS7:	mr1 |= MPC52xx_PSC_MODE_7_BITS;
1191		break;
1192	case CS8:
1193	default:	mr1 |= MPC52xx_PSC_MODE_8_BITS;
1194	}
1195
1196	if (new->c_cflag & PARENB) {
1197		if (new->c_cflag & CMSPAR)
1198			mr1 |= MPC52xx_PSC_MODE_PARFORCE;
1199
1200		/* With CMSPAR, PARODD also means high parity (same as termios) */
1201		mr1 |= (new->c_cflag & PARODD) ?
1202			MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
1203	} else {
1204		mr1 |= MPC52xx_PSC_MODE_PARNONE;
1205	}
1206
1207	mr2 = 0;
1208
1209	if (new->c_cflag & CSTOPB)
1210		mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
1211	else
1212		mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
1213			MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
1214			MPC52xx_PSC_MODE_ONE_STOP;
1215
1216	if (new->c_cflag & CRTSCTS) {
1217		mr1 |= MPC52xx_PSC_MODE_RXRTS;
1218		mr2 |= MPC52xx_PSC_MODE_TXCTS;
1219	}
1220
1221	/* Get the lock */
1222	spin_lock_irqsave(&port->lock, flags);
1223
1224	/* Do our best to flush TX & RX, so we don't lose anything */
1225	/* But we don't wait indefinitely ! */
1226	j = 5000000;	/* Maximum wait */
1227	/* FIXME Can't receive chars since set_termios might be called at early
1228	 * boot for the console, all stuff is not yet ready to receive at that
1229	 * time and that just makes the kernel oops */
1230	/* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1231	while (!mpc52xx_uart_tx_empty(port) && --j)
1232		udelay(1);
1233
1234	if (!j)
1235		printk(KERN_ERR "mpc52xx_uart.c: "
1236			"Unable to flush RX & TX fifos in-time in set_termios."
1237			"Some chars may have been lost.\n");
1238
1239	/* Reset the TX & RX */
1240	psc_ops->command(port, MPC52xx_PSC_RST_RX);
1241	psc_ops->command(port, MPC52xx_PSC_RST_TX);
1242
1243	/* Send new mode settings */
1244	psc_ops->set_mode(port, mr1, mr2);
 
 
1245	baud = psc_ops->set_baudrate(port, new, old);
1246
1247	/* Update the per-port timeout */
1248	uart_update_timeout(port, new->c_cflag, baud);
1249
1250	if (UART_ENABLE_MS(port, new->c_cflag))
1251		mpc52xx_uart_enable_ms(port);
1252
1253	/* Reenable TX & RX */
1254	psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1255	psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1256
1257	/* We're all set, release the lock */
1258	spin_unlock_irqrestore(&port->lock, flags);
1259}
1260
1261static const char *
1262mpc52xx_uart_type(struct uart_port *port)
1263{
1264	/*
1265	 * We keep using PORT_MPC52xx for historic reasons although it applies
1266	 * for MPC512x, too, but print "MPC5xxx" to not irritate users
1267	 */
1268	return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1269}
1270
1271static void
1272mpc52xx_uart_release_port(struct uart_port *port)
1273{
1274	if (psc_ops->clock_relse)
1275		psc_ops->clock_relse(port);
1276
1277	/* remapped by us ? */
1278	if (port->flags & UPF_IOREMAP) {
1279		iounmap(port->membase);
1280		port->membase = NULL;
1281	}
1282
1283	release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1284}
1285
1286static int
1287mpc52xx_uart_request_port(struct uart_port *port)
1288{
1289	int err;
1290
1291	if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1292		port->membase = ioremap(port->mapbase,
1293					sizeof(struct mpc52xx_psc));
1294
1295	if (!port->membase)
1296		return -EINVAL;
1297
1298	err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1299			"mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
1300
1301	if (err)
1302		goto out_membase;
1303
1304	if (psc_ops->clock_alloc) {
1305		err = psc_ops->clock_alloc(port);
1306		if (err)
1307			goto out_mapregion;
1308	}
1309
1310	return 0;
1311
1312out_mapregion:
1313	release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1314out_membase:
1315	if (port->flags & UPF_IOREMAP) {
1316		iounmap(port->membase);
1317		port->membase = NULL;
1318	}
 
1319	return err;
1320}
1321
1322static void
1323mpc52xx_uart_config_port(struct uart_port *port, int flags)
1324{
1325	if ((flags & UART_CONFIG_TYPE)
1326		&& (mpc52xx_uart_request_port(port) == 0))
1327		port->type = PORT_MPC52xx;
1328}
1329
1330static int
1331mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1332{
1333	if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
1334		return -EINVAL;
1335
1336	if ((ser->irq != port->irq) ||
1337	    (ser->io_type != UPIO_MEM) ||
1338	    (ser->baud_base != port->uartclk)  ||
1339	    (ser->iomem_base != (void *)port->mapbase) ||
1340	    (ser->hub6 != 0))
1341		return -EINVAL;
1342
1343	return 0;
1344}
1345
1346
1347static const struct uart_ops mpc52xx_uart_ops = {
1348	.tx_empty	= mpc52xx_uart_tx_empty,
1349	.set_mctrl	= mpc52xx_uart_set_mctrl,
1350	.get_mctrl	= mpc52xx_uart_get_mctrl,
1351	.stop_tx	= mpc52xx_uart_stop_tx,
1352	.start_tx	= mpc52xx_uart_start_tx,
 
1353	.stop_rx	= mpc52xx_uart_stop_rx,
1354	.enable_ms	= mpc52xx_uart_enable_ms,
1355	.break_ctl	= mpc52xx_uart_break_ctl,
1356	.startup	= mpc52xx_uart_startup,
1357	.shutdown	= mpc52xx_uart_shutdown,
1358	.set_termios	= mpc52xx_uart_set_termios,
1359/*	.pm		= mpc52xx_uart_pm,		Not supported yet */
 
1360	.type		= mpc52xx_uart_type,
1361	.release_port	= mpc52xx_uart_release_port,
1362	.request_port	= mpc52xx_uart_request_port,
1363	.config_port	= mpc52xx_uart_config_port,
1364	.verify_port	= mpc52xx_uart_verify_port
1365};
1366
1367
1368/* ======================================================================== */
1369/* Interrupt handling                                                       */
1370/* ======================================================================== */
1371
1372static inline int
1373mpc52xx_uart_int_rx_chars(struct uart_port *port)
1374{
1375	struct tty_port *tport = &port->state->port;
1376	unsigned char ch, flag;
1377	unsigned short status;
1378
1379	/* While we can read, do so ! */
1380	while (psc_ops->raw_rx_rdy(port)) {
1381		/* Get the char */
1382		ch = psc_ops->read_char(port);
1383
1384		/* Handle sysreq char */
1385#ifdef SUPPORT_SYSRQ
1386		if (uart_handle_sysrq_char(port, ch)) {
1387			port->sysrq = 0;
1388			continue;
1389		}
1390#endif
1391
1392		/* Store it */
1393
1394		flag = TTY_NORMAL;
1395		port->icount.rx++;
1396
1397		status = psc_ops->get_status(port);
1398
1399		if (status & (MPC52xx_PSC_SR_PE |
1400			      MPC52xx_PSC_SR_FE |
1401			      MPC52xx_PSC_SR_RB)) {
1402
1403			if (status & MPC52xx_PSC_SR_RB) {
1404				flag = TTY_BREAK;
1405				uart_handle_break(port);
1406				port->icount.brk++;
1407			} else if (status & MPC52xx_PSC_SR_PE) {
1408				flag = TTY_PARITY;
1409				port->icount.parity++;
1410			}
1411			else if (status & MPC52xx_PSC_SR_FE) {
1412				flag = TTY_FRAME;
1413				port->icount.frame++;
1414			}
1415
1416			/* Clear error condition */
1417			psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1418
1419		}
1420		tty_insert_flip_char(tport, ch, flag);
1421		if (status & MPC52xx_PSC_SR_OE) {
1422			/*
1423			 * Overrun is special, since it's
1424			 * reported immediately, and doesn't
1425			 * affect the current character
1426			 */
1427			tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1428			port->icount.overrun++;
1429		}
1430	}
1431
1432	spin_unlock(&port->lock);
1433	tty_flip_buffer_push(tport);
1434	spin_lock(&port->lock);
1435
1436	return psc_ops->raw_rx_rdy(port);
1437}
1438
1439static inline int
1440mpc52xx_uart_int_tx_chars(struct uart_port *port)
1441{
1442	struct circ_buf *xmit = &port->state->xmit;
1443
1444	/* Process out of band chars */
1445	if (port->x_char) {
1446		psc_ops->write_char(port, port->x_char);
1447		port->icount.tx++;
1448		port->x_char = 0;
1449		return 1;
1450	}
1451
1452	/* Nothing to do ? */
1453	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1454		mpc52xx_uart_stop_tx(port);
1455		return 0;
1456	}
1457
1458	/* Send chars */
1459	while (psc_ops->raw_tx_rdy(port)) {
1460		psc_ops->write_char(port, xmit->buf[xmit->tail]);
1461		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1462		port->icount.tx++;
1463		if (uart_circ_empty(xmit))
1464			break;
1465	}
1466
1467	/* Wake up */
1468	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1469		uart_write_wakeup(port);
1470
1471	/* Maybe we're done after all */
1472	if (uart_circ_empty(xmit)) {
1473		mpc52xx_uart_stop_tx(port);
1474		return 0;
1475	}
1476
1477	return 1;
1478}
1479
1480static irqreturn_t
1481mpc5xxx_uart_process_int(struct uart_port *port)
1482{
1483	unsigned long pass = ISR_PASS_LIMIT;
1484	unsigned int keepgoing;
1485	u8 status;
1486
1487	/* While we have stuff to do, we continue */
1488	do {
1489		/* If we don't find anything to do, we stop */
1490		keepgoing = 0;
1491
1492		psc_ops->rx_clr_irq(port);
1493		if (psc_ops->rx_rdy(port))
1494			keepgoing |= mpc52xx_uart_int_rx_chars(port);
1495
1496		psc_ops->tx_clr_irq(port);
1497		if (psc_ops->tx_rdy(port))
1498			keepgoing |= mpc52xx_uart_int_tx_chars(port);
1499
1500		status = psc_ops->get_ipcr(port);
1501		if (status & MPC52xx_PSC_D_DCD)
1502			uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1503
1504		if (status & MPC52xx_PSC_D_CTS)
1505			uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1506
1507		/* Limit number of iteration */
1508		if (!(--pass))
1509			keepgoing = 0;
1510
1511	} while (keepgoing);
1512
1513	return IRQ_HANDLED;
1514}
1515
1516static irqreturn_t
1517mpc52xx_uart_int(int irq, void *dev_id)
1518{
1519	struct uart_port *port = dev_id;
1520	irqreturn_t ret;
1521
1522	spin_lock(&port->lock);
1523
1524	ret = psc_ops->handle_irq(port);
1525
1526	spin_unlock(&port->lock);
1527
1528	return ret;
1529}
1530
1531/* ======================================================================== */
1532/* Console ( if applicable )                                                */
1533/* ======================================================================== */
1534
1535#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1536
1537static void __init
1538mpc52xx_console_get_options(struct uart_port *port,
1539			    int *baud, int *parity, int *bits, int *flow)
1540{
 
1541	unsigned char mr1;
1542
1543	pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1544
1545	/* Read the mode registers */
1546	mr1 = psc_ops->get_mr1(port);
 
1547
1548	/* CT{U,L}R are write-only ! */
1549	*baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1550
1551	/* Parse them */
1552	switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1553	case MPC52xx_PSC_MODE_5_BITS:
1554		*bits = 5;
1555		break;
1556	case MPC52xx_PSC_MODE_6_BITS:
1557		*bits = 6;
1558		break;
1559	case MPC52xx_PSC_MODE_7_BITS:
1560		*bits = 7;
1561		break;
1562	case MPC52xx_PSC_MODE_8_BITS:
1563	default:
1564		*bits = 8;
1565	}
1566
1567	if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1568		*parity = 'n';
1569	else
1570		*parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1571}
1572
1573static void
1574mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1575{
1576	struct uart_port *port = &mpc52xx_uart_ports[co->index];
1577	unsigned int i, j;
1578
1579	/* Disable interrupts */
1580	psc_ops->cw_disable_ints(port);
1581
1582	/* Wait the TX buffer to be empty */
1583	j = 5000000;	/* Maximum wait */
1584	while (!mpc52xx_uart_tx_empty(port) && --j)
1585		udelay(1);
1586
1587	/* Write all the chars */
1588	for (i = 0; i < count; i++, s++) {
1589		/* Line return handling */
1590		if (*s == '\n')
1591			psc_ops->write_char(port, '\r');
1592
1593		/* Send the char */
1594		psc_ops->write_char(port, *s);
1595
1596		/* Wait the TX buffer to be empty */
1597		j = 20000;	/* Maximum wait */
1598		while (!mpc52xx_uart_tx_empty(port) && --j)
1599			udelay(1);
1600	}
1601
1602	/* Restore interrupt state */
1603	psc_ops->cw_restore_ints(port);
1604}
1605
1606
1607static int __init
1608mpc52xx_console_setup(struct console *co, char *options)
1609{
1610	struct uart_port *port = &mpc52xx_uart_ports[co->index];
1611	struct device_node *np = mpc52xx_uart_nodes[co->index];
1612	unsigned int uartclk;
1613	struct resource res;
1614	int ret;
1615
1616	int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1617	int bits = 8;
1618	int parity = 'n';
1619	int flow = 'n';
1620
1621	pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1622		 co, co->index, options);
1623
1624	if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1625		pr_debug("PSC%x out of range\n", co->index);
1626		return -EINVAL;
1627	}
1628
1629	if (!np) {
1630		pr_debug("PSC%x not found in device tree\n", co->index);
1631		return -EINVAL;
1632	}
1633
1634	pr_debug("Console on ttyPSC%x is %pOF\n",
1635		 co->index, mpc52xx_uart_nodes[co->index]);
1636
1637	/* Fetch register locations */
1638	ret = of_address_to_resource(np, 0, &res);
1639	if (ret) {
1640		pr_debug("Could not get resources for PSC%x\n", co->index);
1641		return ret;
1642	}
1643
1644	uartclk = mpc5xxx_get_bus_frequency(np);
1645	if (uartclk == 0) {
1646		pr_debug("Could not find uart clock frequency!\n");
1647		return -EINVAL;
1648	}
1649
1650	/* Basic port init. Needed since we use some uart_??? func before
1651	 * real init for early access */
1652	spin_lock_init(&port->lock);
1653	port->uartclk = uartclk;
1654	port->ops	= &mpc52xx_uart_ops;
1655	port->mapbase = res.start;
1656	port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1657	port->irq = irq_of_parse_and_map(np, 0);
1658
1659	if (port->membase == NULL)
1660		return -EINVAL;
1661
1662	pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1663		 (void *)port->mapbase, port->membase,
1664		 port->irq, port->uartclk);
1665
1666	/* Setup the port parameters accoding to options */
1667	if (options)
1668		uart_parse_options(options, &baud, &parity, &bits, &flow);
1669	else
1670		mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1671
1672	pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1673		 baud, bits, parity, flow);
1674
1675	return uart_set_options(port, co, baud, parity, bits, flow);
1676}
1677
1678
1679static struct uart_driver mpc52xx_uart_driver;
1680
1681static struct console mpc52xx_console = {
1682	.name	= "ttyPSC",
1683	.write	= mpc52xx_console_write,
1684	.device	= uart_console_device,
1685	.setup	= mpc52xx_console_setup,
1686	.flags	= CON_PRINTBUFFER,
1687	.index	= -1,	/* Specified on the cmdline (e.g. console=ttyPSC0) */
1688	.data	= &mpc52xx_uart_driver,
1689};
1690
1691
1692static int __init
1693mpc52xx_console_init(void)
1694{
1695	mpc52xx_uart_of_enumerate();
1696	register_console(&mpc52xx_console);
1697	return 0;
1698}
1699
1700console_initcall(mpc52xx_console_init);
1701
1702#define MPC52xx_PSC_CONSOLE &mpc52xx_console
1703#else
1704#define MPC52xx_PSC_CONSOLE NULL
1705#endif
1706
1707
1708/* ======================================================================== */
1709/* UART Driver                                                              */
1710/* ======================================================================== */
1711
1712static struct uart_driver mpc52xx_uart_driver = {
1713	.driver_name	= "mpc52xx_psc_uart",
1714	.dev_name	= "ttyPSC",
1715	.major		= SERIAL_PSC_MAJOR,
1716	.minor		= SERIAL_PSC_MINOR,
1717	.nr		= MPC52xx_PSC_MAXNUM,
1718	.cons		= MPC52xx_PSC_CONSOLE,
1719};
1720
1721/* ======================================================================== */
1722/* OF Platform Driver                                                       */
1723/* ======================================================================== */
1724
1725static const struct of_device_id mpc52xx_uart_of_match[] = {
1726#ifdef CONFIG_PPC_MPC52xx
1727	{ .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1728	{ .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1729	/* binding used by old lite5200 device trees: */
1730	{ .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1731	/* binding used by efika: */
1732	{ .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1733#endif
1734#ifdef CONFIG_PPC_MPC512x
1735	{ .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1736	{ .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1737#endif
1738	{},
1739};
1740
1741static int mpc52xx_uart_of_probe(struct platform_device *op)
1742{
1743	int idx = -1;
1744	unsigned int uartclk;
1745	struct uart_port *port = NULL;
1746	struct resource res;
1747	int ret;
1748
1749	/* Check validity & presence */
1750	for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1751		if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1752			break;
1753	if (idx >= MPC52xx_PSC_MAXNUM)
1754		return -EINVAL;
1755	pr_debug("Found %pOF assigned to ttyPSC%x\n",
1756		 mpc52xx_uart_nodes[idx], idx);
1757
1758	/* set the uart clock to the input clock of the psc, the different
1759	 * prescalers are taken into account in the set_baudrate() methods
1760	 * of the respective chip */
1761	uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1762	if (uartclk == 0) {
1763		dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1764		return -EINVAL;
1765	}
1766
1767	/* Init the port structure */
1768	port = &mpc52xx_uart_ports[idx];
1769
1770	spin_lock_init(&port->lock);
1771	port->uartclk = uartclk;
1772	port->fifosize	= 512;
1773	port->iotype	= UPIO_MEM;
1774	port->flags	= UPF_BOOT_AUTOCONF |
1775			  (uart_console(port) ? 0 : UPF_IOREMAP);
1776	port->line	= idx;
1777	port->ops	= &mpc52xx_uart_ops;
1778	port->dev	= &op->dev;
1779
1780	/* Search for IRQ and mapbase */
1781	ret = of_address_to_resource(op->dev.of_node, 0, &res);
1782	if (ret)
1783		return ret;
1784
1785	port->mapbase = res.start;
1786	if (!port->mapbase) {
1787		dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1788		return -EINVAL;
1789	}
1790
1791	psc_ops->get_irq(port, op->dev.of_node);
1792	if (port->irq == 0) {
1793		dev_dbg(&op->dev, "Could not get irq\n");
1794		return -EINVAL;
1795	}
1796
1797	dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1798		(void *)port->mapbase, port->irq, port->uartclk);
1799
1800	/* Add the port to the uart sub-system */
1801	ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1802	if (ret)
1803		return ret;
1804
1805	platform_set_drvdata(op, (void *)port);
1806	return 0;
1807}
1808
1809static int
1810mpc52xx_uart_of_remove(struct platform_device *op)
1811{
1812	struct uart_port *port = platform_get_drvdata(op);
 
1813
1814	if (port)
1815		uart_remove_one_port(&mpc52xx_uart_driver, port);
1816
1817	return 0;
1818}
1819
1820#ifdef CONFIG_PM
1821static int
1822mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1823{
1824	struct uart_port *port = platform_get_drvdata(op);
1825
1826	if (port)
1827		uart_suspend_port(&mpc52xx_uart_driver, port);
1828
1829	return 0;
1830}
1831
1832static int
1833mpc52xx_uart_of_resume(struct platform_device *op)
1834{
1835	struct uart_port *port = platform_get_drvdata(op);
1836
1837	if (port)
1838		uart_resume_port(&mpc52xx_uart_driver, port);
1839
1840	return 0;
1841}
1842#endif
1843
1844static void
1845mpc52xx_uart_of_assign(struct device_node *np)
1846{
1847	int i;
1848
1849	/* Find the first free PSC number */
1850	for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1851		if (mpc52xx_uart_nodes[i] == NULL) {
1852			of_node_get(np);
1853			mpc52xx_uart_nodes[i] = np;
1854			return;
1855		}
1856	}
1857}
1858
1859static void
1860mpc52xx_uart_of_enumerate(void)
1861{
1862	static int enum_done;
1863	struct device_node *np;
1864	const struct  of_device_id *match;
1865	int i;
1866
1867	if (enum_done)
1868		return;
1869
1870	/* Assign index to each PSC in device tree */
1871	for_each_matching_node(np, mpc52xx_uart_of_match) {
1872		match = of_match_node(mpc52xx_uart_of_match, np);
1873		psc_ops = match->data;
1874		mpc52xx_uart_of_assign(np);
1875	}
1876
1877	enum_done = 1;
1878
1879	for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1880		if (mpc52xx_uart_nodes[i])
1881			pr_debug("%pOF assigned to ttyPSC%x\n",
1882				 mpc52xx_uart_nodes[i], i);
1883	}
1884}
1885
1886MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1887
1888static struct platform_driver mpc52xx_uart_of_driver = {
1889	.probe		= mpc52xx_uart_of_probe,
1890	.remove		= mpc52xx_uart_of_remove,
1891#ifdef CONFIG_PM
1892	.suspend	= mpc52xx_uart_of_suspend,
1893	.resume		= mpc52xx_uart_of_resume,
1894#endif
1895	.driver = {
1896		.name = "mpc52xx-psc-uart",
 
1897		.of_match_table = mpc52xx_uart_of_match,
1898	},
1899};
1900
1901
1902/* ======================================================================== */
1903/* Module                                                                   */
1904/* ======================================================================== */
1905
1906static int __init
1907mpc52xx_uart_init(void)
1908{
1909	int ret;
1910
1911	printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1912
1913	ret = uart_register_driver(&mpc52xx_uart_driver);
1914	if (ret) {
1915		printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1916		       __FILE__, ret);
1917		return ret;
1918	}
1919
1920	mpc52xx_uart_of_enumerate();
1921
1922	/*
1923	 * Map the PSC FIFO Controller and init if on MPC512x.
1924	 */
1925	if (psc_ops && psc_ops->fifoc_init) {
1926		ret = psc_ops->fifoc_init();
1927		if (ret)
1928			goto err_init;
1929	}
1930
1931	ret = platform_driver_register(&mpc52xx_uart_of_driver);
1932	if (ret) {
1933		printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1934		       __FILE__, ret);
1935		goto err_reg;
 
1936	}
1937
1938	return 0;
1939err_reg:
1940	if (psc_ops && psc_ops->fifoc_uninit)
1941		psc_ops->fifoc_uninit();
1942err_init:
1943	uart_unregister_driver(&mpc52xx_uart_driver);
1944	return ret;
1945}
1946
1947static void __exit
1948mpc52xx_uart_exit(void)
1949{
1950	if (psc_ops->fifoc_uninit)
1951		psc_ops->fifoc_uninit();
1952
1953	platform_driver_unregister(&mpc52xx_uart_of_driver);
1954	uart_unregister_driver(&mpc52xx_uart_driver);
1955}
1956
1957
1958module_init(mpc52xx_uart_init);
1959module_exit(mpc52xx_uart_exit);
1960
1961MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1962MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1963MODULE_LICENSE("GPL");