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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2006 Intel Corporation. */
3
4/*
5 * e100.c: Intel(R) PRO/100 ethernet driver
6 *
7 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
8 * original e100 driver, but better described as a munging of
9 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
10 *
11 * References:
12 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
13 * Open Source Software Developers Manual,
14 * http://sourceforge.net/projects/e1000
15 *
16 *
17 * Theory of Operation
18 *
19 * I. General
20 *
21 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
22 * controller family, which includes the 82557, 82558, 82559, 82550,
23 * 82551, and 82562 devices. 82558 and greater controllers
24 * integrate the Intel 82555 PHY. The controllers are used in
25 * server and client network interface cards, as well as in
26 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
27 * configurations. 8255x supports a 32-bit linear addressing
28 * mode and operates at 33Mhz PCI clock rate.
29 *
30 * II. Driver Operation
31 *
32 * Memory-mapped mode is used exclusively to access the device's
33 * shared-memory structure, the Control/Status Registers (CSR). All
34 * setup, configuration, and control of the device, including queuing
35 * of Tx, Rx, and configuration commands is through the CSR.
36 * cmd_lock serializes accesses to the CSR command register. cb_lock
37 * protects the shared Command Block List (CBL).
38 *
39 * 8255x is highly MII-compliant and all access to the PHY go
40 * through the Management Data Interface (MDI). Consequently, the
41 * driver leverages the mii.c library shared with other MII-compliant
42 * devices.
43 *
44 * Big- and Little-Endian byte order as well as 32- and 64-bit
45 * archs are supported. Weak-ordered memory and non-cache-coherent
46 * archs are supported.
47 *
48 * III. Transmit
49 *
50 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
51 * together in a fixed-size ring (CBL) thus forming the flexible mode
52 * memory structure. A TCB marked with the suspend-bit indicates
53 * the end of the ring. The last TCB processed suspends the
54 * controller, and the controller can be restarted by issue a CU
55 * resume command to continue from the suspend point, or a CU start
56 * command to start at a given position in the ring.
57 *
58 * Non-Tx commands (config, multicast setup, etc) are linked
59 * into the CBL ring along with Tx commands. The common structure
60 * used for both Tx and non-Tx commands is the Command Block (CB).
61 *
62 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
63 * is the next CB to check for completion; cb_to_send is the first
64 * CB to start on in case of a previous failure to resume. CB clean
65 * up happens in interrupt context in response to a CU interrupt.
66 * cbs_avail keeps track of number of free CB resources available.
67 *
68 * Hardware padding of short packets to minimum packet size is
69 * enabled. 82557 pads with 7Eh, while the later controllers pad
70 * with 00h.
71 *
72 * IV. Receive
73 *
74 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
75 * Descriptors (RFD) + data buffer, thus forming the simplified mode
76 * memory structure. Rx skbs are allocated to contain both the RFD
77 * and the data buffer, but the RFD is pulled off before the skb is
78 * indicated. The data buffer is aligned such that encapsulated
79 * protocol headers are u32-aligned. Since the RFD is part of the
80 * mapped shared memory, and completion status is contained within
81 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
82 * view from software and hardware.
83 *
84 * In order to keep updates to the RFD link field from colliding with
85 * hardware writes to mark packets complete, we use the feature that
86 * hardware will not write to a size 0 descriptor and mark the previous
87 * packet as end-of-list (EL). After updating the link, we remove EL
88 * and only then restore the size such that hardware may use the
89 * previous-to-end RFD.
90 *
91 * Under typical operation, the receive unit (RU) is start once,
92 * and the controller happily fills RFDs as frames arrive. If
93 * replacement RFDs cannot be allocated, or the RU goes non-active,
94 * the RU must be restarted. Frame arrival generates an interrupt,
95 * and Rx indication and re-allocation happen in the same context,
96 * therefore no locking is required. A software-generated interrupt
97 * is generated from the watchdog to recover from a failed allocation
98 * scenario where all Rx resources have been indicated and none re-
99 * placed.
100 *
101 * V. Miscellaneous
102 *
103 * VLAN offloading of tagging, stripping and filtering is not
104 * supported, but driver will accommodate the extra 4-byte VLAN tag
105 * for processing by upper layers. Tx/Rx Checksum offloading is not
106 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
107 * not supported (hardware limitation).
108 *
109 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
110 *
111 * Thanks to JC (jchapman@katalix.com) for helping with
112 * testing/troubleshooting the development driver.
113 *
114 * TODO:
115 * o several entry points race with dev->close
116 * o check for tx-no-resources/stop Q races with tx clean/wake Q
117 *
118 * FIXES:
119 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
120 * - Stratus87247: protect MDI control register manipulations
121 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
122 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
123 */
124
125#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
126
127#include <linux/hardirq.h>
128#include <linux/interrupt.h>
129#include <linux/module.h>
130#include <linux/moduleparam.h>
131#include <linux/kernel.h>
132#include <linux/types.h>
133#include <linux/sched.h>
134#include <linux/slab.h>
135#include <linux/delay.h>
136#include <linux/init.h>
137#include <linux/pci.h>
138#include <linux/dma-mapping.h>
139#include <linux/dmapool.h>
140#include <linux/netdevice.h>
141#include <linux/etherdevice.h>
142#include <linux/mii.h>
143#include <linux/if_vlan.h>
144#include <linux/skbuff.h>
145#include <linux/ethtool.h>
146#include <linux/string.h>
147#include <linux/firmware.h>
148#include <linux/rtnetlink.h>
149#include <asm/unaligned.h>
150
151
152#define DRV_NAME "e100"
153#define DRV_EXT "-NAPI"
154#define DRV_VERSION "3.5.24-k2"DRV_EXT
155#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
156#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
157
158#define E100_WATCHDOG_PERIOD (2 * HZ)
159#define E100_NAPI_WEIGHT 16
160
161#define FIRMWARE_D101M "e100/d101m_ucode.bin"
162#define FIRMWARE_D101S "e100/d101s_ucode.bin"
163#define FIRMWARE_D102E "e100/d102e_ucode.bin"
164
165MODULE_DESCRIPTION(DRV_DESCRIPTION);
166MODULE_AUTHOR(DRV_COPYRIGHT);
167MODULE_LICENSE("GPL v2");
168MODULE_VERSION(DRV_VERSION);
169MODULE_FIRMWARE(FIRMWARE_D101M);
170MODULE_FIRMWARE(FIRMWARE_D101S);
171MODULE_FIRMWARE(FIRMWARE_D102E);
172
173static int debug = 3;
174static int eeprom_bad_csum_allow = 0;
175static int use_io = 0;
176module_param(debug, int, 0);
177module_param(eeprom_bad_csum_allow, int, 0);
178module_param(use_io, int, 0);
179MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
180MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
181MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
182
183#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
184 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
185 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
186static const struct pci_device_id e100_id_table[] = {
187 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
188 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
189 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
192 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
193 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
194 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
198 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
199 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
200 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
205 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
206 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
207 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
208 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
209 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
214 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
215 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
216 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
217 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
218 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
219 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
220 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
221 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
222 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
223 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
224 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
225 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
226 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
227 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
228 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
229 { 0, }
230};
231MODULE_DEVICE_TABLE(pci, e100_id_table);
232
233enum mac {
234 mac_82557_D100_A = 0,
235 mac_82557_D100_B = 1,
236 mac_82557_D100_C = 2,
237 mac_82558_D101_A4 = 4,
238 mac_82558_D101_B0 = 5,
239 mac_82559_D101M = 8,
240 mac_82559_D101S = 9,
241 mac_82550_D102 = 12,
242 mac_82550_D102_C = 13,
243 mac_82551_E = 14,
244 mac_82551_F = 15,
245 mac_82551_10 = 16,
246 mac_unknown = 0xFF,
247};
248
249enum phy {
250 phy_100a = 0x000003E0,
251 phy_100c = 0x035002A8,
252 phy_82555_tx = 0x015002A8,
253 phy_nsc_tx = 0x5C002000,
254 phy_82562_et = 0x033002A8,
255 phy_82562_em = 0x032002A8,
256 phy_82562_ek = 0x031002A8,
257 phy_82562_eh = 0x017002A8,
258 phy_82552_v = 0xd061004d,
259 phy_unknown = 0xFFFFFFFF,
260};
261
262/* CSR (Control/Status Registers) */
263struct csr {
264 struct {
265 u8 status;
266 u8 stat_ack;
267 u8 cmd_lo;
268 u8 cmd_hi;
269 u32 gen_ptr;
270 } scb;
271 u32 port;
272 u16 flash_ctrl;
273 u8 eeprom_ctrl_lo;
274 u8 eeprom_ctrl_hi;
275 u32 mdi_ctrl;
276 u32 rx_dma_count;
277};
278
279enum scb_status {
280 rus_no_res = 0x08,
281 rus_ready = 0x10,
282 rus_mask = 0x3C,
283};
284
285enum ru_state {
286 RU_SUSPENDED = 0,
287 RU_RUNNING = 1,
288 RU_UNINITIALIZED = -1,
289};
290
291enum scb_stat_ack {
292 stat_ack_not_ours = 0x00,
293 stat_ack_sw_gen = 0x04,
294 stat_ack_rnr = 0x10,
295 stat_ack_cu_idle = 0x20,
296 stat_ack_frame_rx = 0x40,
297 stat_ack_cu_cmd_done = 0x80,
298 stat_ack_not_present = 0xFF,
299 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
300 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
301};
302
303enum scb_cmd_hi {
304 irq_mask_none = 0x00,
305 irq_mask_all = 0x01,
306 irq_sw_gen = 0x02,
307};
308
309enum scb_cmd_lo {
310 cuc_nop = 0x00,
311 ruc_start = 0x01,
312 ruc_load_base = 0x06,
313 cuc_start = 0x10,
314 cuc_resume = 0x20,
315 cuc_dump_addr = 0x40,
316 cuc_dump_stats = 0x50,
317 cuc_load_base = 0x60,
318 cuc_dump_reset = 0x70,
319};
320
321enum cuc_dump {
322 cuc_dump_complete = 0x0000A005,
323 cuc_dump_reset_complete = 0x0000A007,
324};
325
326enum port {
327 software_reset = 0x0000,
328 selftest = 0x0001,
329 selective_reset = 0x0002,
330};
331
332enum eeprom_ctrl_lo {
333 eesk = 0x01,
334 eecs = 0x02,
335 eedi = 0x04,
336 eedo = 0x08,
337};
338
339enum mdi_ctrl {
340 mdi_write = 0x04000000,
341 mdi_read = 0x08000000,
342 mdi_ready = 0x10000000,
343};
344
345enum eeprom_op {
346 op_write = 0x05,
347 op_read = 0x06,
348 op_ewds = 0x10,
349 op_ewen = 0x13,
350};
351
352enum eeprom_offsets {
353 eeprom_cnfg_mdix = 0x03,
354 eeprom_phy_iface = 0x06,
355 eeprom_id = 0x0A,
356 eeprom_config_asf = 0x0D,
357 eeprom_smbus_addr = 0x90,
358};
359
360enum eeprom_cnfg_mdix {
361 eeprom_mdix_enabled = 0x0080,
362};
363
364enum eeprom_phy_iface {
365 NoSuchPhy = 0,
366 I82553AB,
367 I82553C,
368 I82503,
369 DP83840,
370 S80C240,
371 S80C24,
372 I82555,
373 DP83840A = 10,
374};
375
376enum eeprom_id {
377 eeprom_id_wol = 0x0020,
378};
379
380enum eeprom_config_asf {
381 eeprom_asf = 0x8000,
382 eeprom_gcl = 0x4000,
383};
384
385enum cb_status {
386 cb_complete = 0x8000,
387 cb_ok = 0x2000,
388};
389
390/**
391 * cb_command - Command Block flags
392 * @cb_tx_nc: 0: controller does CRC (normal), 1: CRC from skb memory
393 */
394enum cb_command {
395 cb_nop = 0x0000,
396 cb_iaaddr = 0x0001,
397 cb_config = 0x0002,
398 cb_multi = 0x0003,
399 cb_tx = 0x0004,
400 cb_ucode = 0x0005,
401 cb_dump = 0x0006,
402 cb_tx_sf = 0x0008,
403 cb_tx_nc = 0x0010,
404 cb_cid = 0x1f00,
405 cb_i = 0x2000,
406 cb_s = 0x4000,
407 cb_el = 0x8000,
408};
409
410struct rfd {
411 __le16 status;
412 __le16 command;
413 __le32 link;
414 __le32 rbd;
415 __le16 actual_size;
416 __le16 size;
417};
418
419struct rx {
420 struct rx *next, *prev;
421 struct sk_buff *skb;
422 dma_addr_t dma_addr;
423};
424
425#if defined(__BIG_ENDIAN_BITFIELD)
426#define X(a,b) b,a
427#else
428#define X(a,b) a,b
429#endif
430struct config {
431/*0*/ u8 X(byte_count:6, pad0:2);
432/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
433/*2*/ u8 adaptive_ifs;
434/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
435 term_write_cache_line:1), pad3:4);
436/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
437/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
438/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
439 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
440 rx_save_overruns : 1), rx_save_bad_frames : 1);
441/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
442 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
443 tx_dynamic_tbd:1);
444/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
445/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
446 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
447/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
448 loopback:2);
449/*11*/ u8 X(linear_priority:3, pad11:5);
450/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
451/*13*/ u8 ip_addr_lo;
452/*14*/ u8 ip_addr_hi;
453/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
454 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
455 pad15_2:1), crs_or_cdt:1);
456/*16*/ u8 fc_delay_lo;
457/*17*/ u8 fc_delay_hi;
458/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
459 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
460/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
461 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
462 full_duplex_force:1), full_duplex_pin:1);
463/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
464/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
465/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
466 u8 pad_d102[9];
467};
468
469#define E100_MAX_MULTICAST_ADDRS 64
470struct multi {
471 __le16 count;
472 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
473};
474
475/* Important: keep total struct u32-aligned */
476#define UCODE_SIZE 134
477struct cb {
478 __le16 status;
479 __le16 command;
480 __le32 link;
481 union {
482 u8 iaaddr[ETH_ALEN];
483 __le32 ucode[UCODE_SIZE];
484 struct config config;
485 struct multi multi;
486 struct {
487 u32 tbd_array;
488 u16 tcb_byte_count;
489 u8 threshold;
490 u8 tbd_count;
491 struct {
492 __le32 buf_addr;
493 __le16 size;
494 u16 eol;
495 } tbd;
496 } tcb;
497 __le32 dump_buffer_addr;
498 } u;
499 struct cb *next, *prev;
500 dma_addr_t dma_addr;
501 struct sk_buff *skb;
502};
503
504enum loopback {
505 lb_none = 0, lb_mac = 1, lb_phy = 3,
506};
507
508struct stats {
509 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
510 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
511 tx_multiple_collisions, tx_total_collisions;
512 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
513 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
514 rx_short_frame_errors;
515 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
516 __le16 xmt_tco_frames, rcv_tco_frames;
517 __le32 complete;
518};
519
520struct mem {
521 struct {
522 u32 signature;
523 u32 result;
524 } selftest;
525 struct stats stats;
526 u8 dump_buf[596];
527};
528
529struct param_range {
530 u32 min;
531 u32 max;
532 u32 count;
533};
534
535struct params {
536 struct param_range rfds;
537 struct param_range cbs;
538};
539
540struct nic {
541 /* Begin: frequently used values: keep adjacent for cache effect */
542 u32 msg_enable ____cacheline_aligned;
543 struct net_device *netdev;
544 struct pci_dev *pdev;
545 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
546
547 struct rx *rxs ____cacheline_aligned;
548 struct rx *rx_to_use;
549 struct rx *rx_to_clean;
550 struct rfd blank_rfd;
551 enum ru_state ru_running;
552
553 spinlock_t cb_lock ____cacheline_aligned;
554 spinlock_t cmd_lock;
555 struct csr __iomem *csr;
556 enum scb_cmd_lo cuc_cmd;
557 unsigned int cbs_avail;
558 struct napi_struct napi;
559 struct cb *cbs;
560 struct cb *cb_to_use;
561 struct cb *cb_to_send;
562 struct cb *cb_to_clean;
563 __le16 tx_command;
564 /* End: frequently used values: keep adjacent for cache effect */
565
566 enum {
567 ich = (1 << 0),
568 promiscuous = (1 << 1),
569 multicast_all = (1 << 2),
570 wol_magic = (1 << 3),
571 ich_10h_workaround = (1 << 4),
572 } flags ____cacheline_aligned;
573
574 enum mac mac;
575 enum phy phy;
576 struct params params;
577 struct timer_list watchdog;
578 struct mii_if_info mii;
579 struct work_struct tx_timeout_task;
580 enum loopback loopback;
581
582 struct mem *mem;
583 dma_addr_t dma_addr;
584
585 struct dma_pool *cbs_pool;
586 dma_addr_t cbs_dma_addr;
587 u8 adaptive_ifs;
588 u8 tx_threshold;
589 u32 tx_frames;
590 u32 tx_collisions;
591 u32 tx_deferred;
592 u32 tx_single_collisions;
593 u32 tx_multiple_collisions;
594 u32 tx_fc_pause;
595 u32 tx_tco_frames;
596
597 u32 rx_fc_pause;
598 u32 rx_fc_unsupported;
599 u32 rx_tco_frames;
600 u32 rx_short_frame_errors;
601 u32 rx_over_length_errors;
602
603 u16 eeprom_wc;
604 __le16 eeprom[256];
605 spinlock_t mdio_lock;
606 const struct firmware *fw;
607};
608
609static inline void e100_write_flush(struct nic *nic)
610{
611 /* Flush previous PCI writes through intermediate bridges
612 * by doing a benign read */
613 (void)ioread8(&nic->csr->scb.status);
614}
615
616static void e100_enable_irq(struct nic *nic)
617{
618 unsigned long flags;
619
620 spin_lock_irqsave(&nic->cmd_lock, flags);
621 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
622 e100_write_flush(nic);
623 spin_unlock_irqrestore(&nic->cmd_lock, flags);
624}
625
626static void e100_disable_irq(struct nic *nic)
627{
628 unsigned long flags;
629
630 spin_lock_irqsave(&nic->cmd_lock, flags);
631 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
632 e100_write_flush(nic);
633 spin_unlock_irqrestore(&nic->cmd_lock, flags);
634}
635
636static void e100_hw_reset(struct nic *nic)
637{
638 /* Put CU and RU into idle with a selective reset to get
639 * device off of PCI bus */
640 iowrite32(selective_reset, &nic->csr->port);
641 e100_write_flush(nic); udelay(20);
642
643 /* Now fully reset device */
644 iowrite32(software_reset, &nic->csr->port);
645 e100_write_flush(nic); udelay(20);
646
647 /* Mask off our interrupt line - it's unmasked after reset */
648 e100_disable_irq(nic);
649}
650
651static int e100_self_test(struct nic *nic)
652{
653 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
654
655 /* Passing the self-test is a pretty good indication
656 * that the device can DMA to/from host memory */
657
658 nic->mem->selftest.signature = 0;
659 nic->mem->selftest.result = 0xFFFFFFFF;
660
661 iowrite32(selftest | dma_addr, &nic->csr->port);
662 e100_write_flush(nic);
663 /* Wait 10 msec for self-test to complete */
664 msleep(10);
665
666 /* Interrupts are enabled after self-test */
667 e100_disable_irq(nic);
668
669 /* Check results of self-test */
670 if (nic->mem->selftest.result != 0) {
671 netif_err(nic, hw, nic->netdev,
672 "Self-test failed: result=0x%08X\n",
673 nic->mem->selftest.result);
674 return -ETIMEDOUT;
675 }
676 if (nic->mem->selftest.signature == 0) {
677 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n");
678 return -ETIMEDOUT;
679 }
680
681 return 0;
682}
683
684static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
685{
686 u32 cmd_addr_data[3];
687 u8 ctrl;
688 int i, j;
689
690 /* Three cmds: write/erase enable, write data, write/erase disable */
691 cmd_addr_data[0] = op_ewen << (addr_len - 2);
692 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
693 le16_to_cpu(data);
694 cmd_addr_data[2] = op_ewds << (addr_len - 2);
695
696 /* Bit-bang cmds to write word to eeprom */
697 for (j = 0; j < 3; j++) {
698
699 /* Chip select */
700 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
701 e100_write_flush(nic); udelay(4);
702
703 for (i = 31; i >= 0; i--) {
704 ctrl = (cmd_addr_data[j] & (1 << i)) ?
705 eecs | eedi : eecs;
706 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
707 e100_write_flush(nic); udelay(4);
708
709 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
710 e100_write_flush(nic); udelay(4);
711 }
712 /* Wait 10 msec for cmd to complete */
713 msleep(10);
714
715 /* Chip deselect */
716 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
717 e100_write_flush(nic); udelay(4);
718 }
719};
720
721/* General technique stolen from the eepro100 driver - very clever */
722static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
723{
724 u32 cmd_addr_data;
725 u16 data = 0;
726 u8 ctrl;
727 int i;
728
729 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
730
731 /* Chip select */
732 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
733 e100_write_flush(nic); udelay(4);
734
735 /* Bit-bang to read word from eeprom */
736 for (i = 31; i >= 0; i--) {
737 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
738 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
739 e100_write_flush(nic); udelay(4);
740
741 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
742 e100_write_flush(nic); udelay(4);
743
744 /* Eeprom drives a dummy zero to EEDO after receiving
745 * complete address. Use this to adjust addr_len. */
746 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
747 if (!(ctrl & eedo) && i > 16) {
748 *addr_len -= (i - 16);
749 i = 17;
750 }
751
752 data = (data << 1) | (ctrl & eedo ? 1 : 0);
753 }
754
755 /* Chip deselect */
756 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
757 e100_write_flush(nic); udelay(4);
758
759 return cpu_to_le16(data);
760};
761
762/* Load entire EEPROM image into driver cache and validate checksum */
763static int e100_eeprom_load(struct nic *nic)
764{
765 u16 addr, addr_len = 8, checksum = 0;
766
767 /* Try reading with an 8-bit addr len to discover actual addr len */
768 e100_eeprom_read(nic, &addr_len, 0);
769 nic->eeprom_wc = 1 << addr_len;
770
771 for (addr = 0; addr < nic->eeprom_wc; addr++) {
772 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
773 if (addr < nic->eeprom_wc - 1)
774 checksum += le16_to_cpu(nic->eeprom[addr]);
775 }
776
777 /* The checksum, stored in the last word, is calculated such that
778 * the sum of words should be 0xBABA */
779 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
780 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n");
781 if (!eeprom_bad_csum_allow)
782 return -EAGAIN;
783 }
784
785 return 0;
786}
787
788/* Save (portion of) driver EEPROM cache to device and update checksum */
789static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
790{
791 u16 addr, addr_len = 8, checksum = 0;
792
793 /* Try reading with an 8-bit addr len to discover actual addr len */
794 e100_eeprom_read(nic, &addr_len, 0);
795 nic->eeprom_wc = 1 << addr_len;
796
797 if (start + count >= nic->eeprom_wc)
798 return -EINVAL;
799
800 for (addr = start; addr < start + count; addr++)
801 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
802
803 /* The checksum, stored in the last word, is calculated such that
804 * the sum of words should be 0xBABA */
805 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
806 checksum += le16_to_cpu(nic->eeprom[addr]);
807 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
808 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
809 nic->eeprom[nic->eeprom_wc - 1]);
810
811 return 0;
812}
813
814#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
815#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
816static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
817{
818 unsigned long flags;
819 unsigned int i;
820 int err = 0;
821
822 spin_lock_irqsave(&nic->cmd_lock, flags);
823
824 /* Previous command is accepted when SCB clears */
825 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
826 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
827 break;
828 cpu_relax();
829 if (unlikely(i > E100_WAIT_SCB_FAST))
830 udelay(5);
831 }
832 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
833 err = -EAGAIN;
834 goto err_unlock;
835 }
836
837 if (unlikely(cmd != cuc_resume))
838 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
839 iowrite8(cmd, &nic->csr->scb.cmd_lo);
840
841err_unlock:
842 spin_unlock_irqrestore(&nic->cmd_lock, flags);
843
844 return err;
845}
846
847static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
848 int (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
849{
850 struct cb *cb;
851 unsigned long flags;
852 int err;
853
854 spin_lock_irqsave(&nic->cb_lock, flags);
855
856 if (unlikely(!nic->cbs_avail)) {
857 err = -ENOMEM;
858 goto err_unlock;
859 }
860
861 cb = nic->cb_to_use;
862 nic->cb_to_use = cb->next;
863 nic->cbs_avail--;
864 cb->skb = skb;
865
866 err = cb_prepare(nic, cb, skb);
867 if (err)
868 goto err_unlock;
869
870 if (unlikely(!nic->cbs_avail))
871 err = -ENOSPC;
872
873
874 /* Order is important otherwise we'll be in a race with h/w:
875 * set S-bit in current first, then clear S-bit in previous. */
876 cb->command |= cpu_to_le16(cb_s);
877 dma_wmb();
878 cb->prev->command &= cpu_to_le16(~cb_s);
879
880 while (nic->cb_to_send != nic->cb_to_use) {
881 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
882 nic->cb_to_send->dma_addr))) {
883 /* Ok, here's where things get sticky. It's
884 * possible that we can't schedule the command
885 * because the controller is too busy, so
886 * let's just queue the command and try again
887 * when another command is scheduled. */
888 if (err == -ENOSPC) {
889 //request a reset
890 schedule_work(&nic->tx_timeout_task);
891 }
892 break;
893 } else {
894 nic->cuc_cmd = cuc_resume;
895 nic->cb_to_send = nic->cb_to_send->next;
896 }
897 }
898
899err_unlock:
900 spin_unlock_irqrestore(&nic->cb_lock, flags);
901
902 return err;
903}
904
905static int mdio_read(struct net_device *netdev, int addr, int reg)
906{
907 struct nic *nic = netdev_priv(netdev);
908 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
909}
910
911static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
912{
913 struct nic *nic = netdev_priv(netdev);
914
915 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
916}
917
918/* the standard mdio_ctrl() function for usual MII-compliant hardware */
919static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
920{
921 u32 data_out = 0;
922 unsigned int i;
923 unsigned long flags;
924
925
926 /*
927 * Stratus87247: we shouldn't be writing the MDI control
928 * register until the Ready bit shows True. Also, since
929 * manipulation of the MDI control registers is a multi-step
930 * procedure it should be done under lock.
931 */
932 spin_lock_irqsave(&nic->mdio_lock, flags);
933 for (i = 100; i; --i) {
934 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
935 break;
936 udelay(20);
937 }
938 if (unlikely(!i)) {
939 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n");
940 spin_unlock_irqrestore(&nic->mdio_lock, flags);
941 return 0; /* No way to indicate timeout error */
942 }
943 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
944
945 for (i = 0; i < 100; i++) {
946 udelay(20);
947 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
948 break;
949 }
950 spin_unlock_irqrestore(&nic->mdio_lock, flags);
951 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
952 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
953 dir == mdi_read ? "READ" : "WRITE",
954 addr, reg, data, data_out);
955 return (u16)data_out;
956}
957
958/* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
959static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
960 u32 addr,
961 u32 dir,
962 u32 reg,
963 u16 data)
964{
965 if ((reg == MII_BMCR) && (dir == mdi_write)) {
966 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
967 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
968 MII_ADVERTISE);
969
970 /*
971 * Workaround Si issue where sometimes the part will not
972 * autoneg to 100Mbps even when advertised.
973 */
974 if (advert & ADVERTISE_100FULL)
975 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
976 else if (advert & ADVERTISE_100HALF)
977 data |= BMCR_SPEED100;
978 }
979 }
980 return mdio_ctrl_hw(nic, addr, dir, reg, data);
981}
982
983/* Fully software-emulated mdio_ctrl() function for cards without
984 * MII-compliant PHYs.
985 * For now, this is mainly geared towards 80c24 support; in case of further
986 * requirements for other types (i82503, ...?) either extend this mechanism
987 * or split it, whichever is cleaner.
988 */
989static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
990 u32 addr,
991 u32 dir,
992 u32 reg,
993 u16 data)
994{
995 /* might need to allocate a netdev_priv'ed register array eventually
996 * to be able to record state changes, but for now
997 * some fully hardcoded register handling ought to be ok I guess. */
998
999 if (dir == mdi_read) {
1000 switch (reg) {
1001 case MII_BMCR:
1002 /* Auto-negotiation, right? */
1003 return BMCR_ANENABLE |
1004 BMCR_FULLDPLX;
1005 case MII_BMSR:
1006 return BMSR_LSTATUS /* for mii_link_ok() */ |
1007 BMSR_ANEGCAPABLE |
1008 BMSR_10FULL;
1009 case MII_ADVERTISE:
1010 /* 80c24 is a "combo card" PHY, right? */
1011 return ADVERTISE_10HALF |
1012 ADVERTISE_10FULL;
1013 default:
1014 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1015 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1016 dir == mdi_read ? "READ" : "WRITE",
1017 addr, reg, data);
1018 return 0xFFFF;
1019 }
1020 } else {
1021 switch (reg) {
1022 default:
1023 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1024 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1025 dir == mdi_read ? "READ" : "WRITE",
1026 addr, reg, data);
1027 return 0xFFFF;
1028 }
1029 }
1030}
1031static inline int e100_phy_supports_mii(struct nic *nic)
1032{
1033 /* for now, just check it by comparing whether we
1034 are using MII software emulation.
1035 */
1036 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1037}
1038
1039static void e100_get_defaults(struct nic *nic)
1040{
1041 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1042 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1043
1044 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1045 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1046 if (nic->mac == mac_unknown)
1047 nic->mac = mac_82557_D100_A;
1048
1049 nic->params.rfds = rfds;
1050 nic->params.cbs = cbs;
1051
1052 /* Quadwords to DMA into FIFO before starting frame transmit */
1053 nic->tx_threshold = 0xE0;
1054
1055 /* no interrupt for every tx completion, delay = 256us if not 557 */
1056 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1057 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1058
1059 /* Template for a freshly allocated RFD */
1060 nic->blank_rfd.command = 0;
1061 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1062 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN);
1063
1064 /* MII setup */
1065 nic->mii.phy_id_mask = 0x1F;
1066 nic->mii.reg_num_mask = 0x1F;
1067 nic->mii.dev = nic->netdev;
1068 nic->mii.mdio_read = mdio_read;
1069 nic->mii.mdio_write = mdio_write;
1070}
1071
1072static int e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1073{
1074 struct config *config = &cb->u.config;
1075 u8 *c = (u8 *)config;
1076 struct net_device *netdev = nic->netdev;
1077
1078 cb->command = cpu_to_le16(cb_config);
1079
1080 memset(config, 0, sizeof(struct config));
1081
1082 config->byte_count = 0x16; /* bytes in this struct */
1083 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1084 config->direct_rx_dma = 0x1; /* reserved */
1085 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1086 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1087 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1088 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1089 if (e100_phy_supports_mii(nic))
1090 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1091 config->pad10 = 0x6;
1092 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1093 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1094 config->ifs = 0x6; /* x16 = inter frame spacing */
1095 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1096 config->pad15_1 = 0x1;
1097 config->pad15_2 = 0x1;
1098 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1099 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1100 config->tx_padding = 0x1; /* 1=pad short frames */
1101 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1102 config->pad18 = 0x1;
1103 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1104 config->pad20_1 = 0x1F;
1105 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1106 config->pad21_1 = 0x5;
1107
1108 config->adaptive_ifs = nic->adaptive_ifs;
1109 config->loopback = nic->loopback;
1110
1111 if (nic->mii.force_media && nic->mii.full_duplex)
1112 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1113
1114 if (nic->flags & promiscuous || nic->loopback) {
1115 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1116 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1117 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1118 }
1119
1120 if (unlikely(netdev->features & NETIF_F_RXFCS))
1121 config->rx_crc_transfer = 0x1; /* 1=save, 0=discard */
1122
1123 if (nic->flags & multicast_all)
1124 config->multicast_all = 0x1; /* 1=accept, 0=no */
1125
1126 /* disable WoL when up */
1127 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1128 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1129
1130 if (nic->mac >= mac_82558_D101_A4) {
1131 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1132 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1133 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1134 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1135 if (nic->mac >= mac_82559_D101M) {
1136 config->tno_intr = 0x1; /* TCO stats enable */
1137 /* Enable TCO in extended config */
1138 if (nic->mac >= mac_82551_10) {
1139 config->byte_count = 0x20; /* extended bytes */
1140 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1141 }
1142 } else {
1143 config->standard_stat_counter = 0x0;
1144 }
1145 }
1146
1147 if (netdev->features & NETIF_F_RXALL) {
1148 config->rx_save_overruns = 0x1; /* 1=save, 0=discard */
1149 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1150 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1151 }
1152
1153 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[00-07]=%8ph\n",
1154 c + 0);
1155 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[08-15]=%8ph\n",
1156 c + 8);
1157 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[16-23]=%8ph\n",
1158 c + 16);
1159 return 0;
1160}
1161
1162/*************************************************************************
1163* CPUSaver parameters
1164*
1165* All CPUSaver parameters are 16-bit literals that are part of a
1166* "move immediate value" instruction. By changing the value of
1167* the literal in the instruction before the code is loaded, the
1168* driver can change the algorithm.
1169*
1170* INTDELAY - This loads the dead-man timer with its initial value.
1171* When this timer expires the interrupt is asserted, and the
1172* timer is reset each time a new packet is received. (see
1173* BUNDLEMAX below to set the limit on number of chained packets)
1174* The current default is 0x600 or 1536. Experiments show that
1175* the value should probably stay within the 0x200 - 0x1000.
1176*
1177* BUNDLEMAX -
1178* This sets the maximum number of frames that will be bundled. In
1179* some situations, such as the TCP windowing algorithm, it may be
1180* better to limit the growth of the bundle size than let it go as
1181* high as it can, because that could cause too much added latency.
1182* The default is six, because this is the number of packets in the
1183* default TCP window size. A value of 1 would make CPUSaver indicate
1184* an interrupt for every frame received. If you do not want to put
1185* a limit on the bundle size, set this value to xFFFF.
1186*
1187* BUNDLESMALL -
1188* This contains a bit-mask describing the minimum size frame that
1189* will be bundled. The default masks the lower 7 bits, which means
1190* that any frame less than 128 bytes in length will not be bundled,
1191* but will instead immediately generate an interrupt. This does
1192* not affect the current bundle in any way. Any frame that is 128
1193* bytes or large will be bundled normally. This feature is meant
1194* to provide immediate indication of ACK frames in a TCP environment.
1195* Customers were seeing poor performance when a machine with CPUSaver
1196* enabled was sending but not receiving. The delay introduced when
1197* the ACKs were received was enough to reduce total throughput, because
1198* the sender would sit idle until the ACK was finally seen.
1199*
1200* The current default is 0xFF80, which masks out the lower 7 bits.
1201* This means that any frame which is x7F (127) bytes or smaller
1202* will cause an immediate interrupt. Because this value must be a
1203* bit mask, there are only a few valid values that can be used. To
1204* turn this feature off, the driver can write the value xFFFF to the
1205* lower word of this instruction (in the same way that the other
1206* parameters are used). Likewise, a value of 0xF800 (2047) would
1207* cause an interrupt to be generated for every frame, because all
1208* standard Ethernet frames are <= 2047 bytes in length.
1209*************************************************************************/
1210
1211/* if you wish to disable the ucode functionality, while maintaining the
1212 * workarounds it provides, set the following defines to:
1213 * BUNDLESMALL 0
1214 * BUNDLEMAX 1
1215 * INTDELAY 1
1216 */
1217#define BUNDLESMALL 1
1218#define BUNDLEMAX (u16)6
1219#define INTDELAY (u16)1536 /* 0x600 */
1220
1221/* Initialize firmware */
1222static const struct firmware *e100_request_firmware(struct nic *nic)
1223{
1224 const char *fw_name;
1225 const struct firmware *fw = nic->fw;
1226 u8 timer, bundle, min_size;
1227 int err = 0;
1228 bool required = false;
1229
1230 /* do not load u-code for ICH devices */
1231 if (nic->flags & ich)
1232 return NULL;
1233
1234 /* Search for ucode match against h/w revision
1235 *
1236 * Based on comments in the source code for the FreeBSD fxp
1237 * driver, the FIRMWARE_D102E ucode includes both CPUSaver and
1238 *
1239 * "fixes for bugs in the B-step hardware (specifically, bugs
1240 * with Inline Receive)."
1241 *
1242 * So we must fail if it cannot be loaded.
1243 *
1244 * The other microcode files are only required for the optional
1245 * CPUSaver feature. Nice to have, but no reason to fail.
1246 */
1247 if (nic->mac == mac_82559_D101M) {
1248 fw_name = FIRMWARE_D101M;
1249 } else if (nic->mac == mac_82559_D101S) {
1250 fw_name = FIRMWARE_D101S;
1251 } else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
1252 fw_name = FIRMWARE_D102E;
1253 required = true;
1254 } else { /* No ucode on other devices */
1255 return NULL;
1256 }
1257
1258 /* If the firmware has not previously been loaded, request a pointer
1259 * to it. If it was previously loaded, we are reinitializing the
1260 * adapter, possibly in a resume from hibernate, in which case
1261 * request_firmware() cannot be used.
1262 */
1263 if (!fw)
1264 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1265
1266 if (err) {
1267 if (required) {
1268 netif_err(nic, probe, nic->netdev,
1269 "Failed to load firmware \"%s\": %d\n",
1270 fw_name, err);
1271 return ERR_PTR(err);
1272 } else {
1273 netif_info(nic, probe, nic->netdev,
1274 "CPUSaver disabled. Needs \"%s\": %d\n",
1275 fw_name, err);
1276 return NULL;
1277 }
1278 }
1279
1280 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1281 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1282 if (fw->size != UCODE_SIZE * 4 + 3) {
1283 netif_err(nic, probe, nic->netdev,
1284 "Firmware \"%s\" has wrong size %zu\n",
1285 fw_name, fw->size);
1286 release_firmware(fw);
1287 return ERR_PTR(-EINVAL);
1288 }
1289
1290 /* Read timer, bundle and min_size from end of firmware blob */
1291 timer = fw->data[UCODE_SIZE * 4];
1292 bundle = fw->data[UCODE_SIZE * 4 + 1];
1293 min_size = fw->data[UCODE_SIZE * 4 + 2];
1294
1295 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1296 min_size >= UCODE_SIZE) {
1297 netif_err(nic, probe, nic->netdev,
1298 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1299 fw_name, timer, bundle, min_size);
1300 release_firmware(fw);
1301 return ERR_PTR(-EINVAL);
1302 }
1303
1304 /* OK, firmware is validated and ready to use. Save a pointer
1305 * to it in the nic */
1306 nic->fw = fw;
1307 return fw;
1308}
1309
1310static int e100_setup_ucode(struct nic *nic, struct cb *cb,
1311 struct sk_buff *skb)
1312{
1313 const struct firmware *fw = (void *)skb;
1314 u8 timer, bundle, min_size;
1315
1316 /* It's not a real skb; we just abused the fact that e100_exec_cb
1317 will pass it through to here... */
1318 cb->skb = NULL;
1319
1320 /* firmware is stored as little endian already */
1321 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1322
1323 /* Read timer, bundle and min_size from end of firmware blob */
1324 timer = fw->data[UCODE_SIZE * 4];
1325 bundle = fw->data[UCODE_SIZE * 4 + 1];
1326 min_size = fw->data[UCODE_SIZE * 4 + 2];
1327
1328 /* Insert user-tunable settings in cb->u.ucode */
1329 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1330 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1331 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1332 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1333 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1334 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1335
1336 cb->command = cpu_to_le16(cb_ucode | cb_el);
1337 return 0;
1338}
1339
1340static inline int e100_load_ucode_wait(struct nic *nic)
1341{
1342 const struct firmware *fw;
1343 int err = 0, counter = 50;
1344 struct cb *cb = nic->cb_to_clean;
1345
1346 fw = e100_request_firmware(nic);
1347 /* If it's NULL, then no ucode is required */
1348 if (IS_ERR_OR_NULL(fw))
1349 return PTR_ERR_OR_ZERO(fw);
1350
1351 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1352 netif_err(nic, probe, nic->netdev,
1353 "ucode cmd failed with error %d\n", err);
1354
1355 /* must restart cuc */
1356 nic->cuc_cmd = cuc_start;
1357
1358 /* wait for completion */
1359 e100_write_flush(nic);
1360 udelay(10);
1361
1362 /* wait for possibly (ouch) 500ms */
1363 while (!(cb->status & cpu_to_le16(cb_complete))) {
1364 msleep(10);
1365 if (!--counter) break;
1366 }
1367
1368 /* ack any interrupts, something could have been set */
1369 iowrite8(~0, &nic->csr->scb.stat_ack);
1370
1371 /* if the command failed, or is not OK, notify and return */
1372 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1373 netif_err(nic, probe, nic->netdev, "ucode load failed\n");
1374 err = -EPERM;
1375 }
1376
1377 return err;
1378}
1379
1380static int e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1381 struct sk_buff *skb)
1382{
1383 cb->command = cpu_to_le16(cb_iaaddr);
1384 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1385 return 0;
1386}
1387
1388static int e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1389{
1390 cb->command = cpu_to_le16(cb_dump);
1391 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1392 offsetof(struct mem, dump_buf));
1393 return 0;
1394}
1395
1396static int e100_phy_check_without_mii(struct nic *nic)
1397{
1398 u8 phy_type;
1399 int without_mii;
1400
1401 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1402
1403 switch (phy_type) {
1404 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1405 case I82503: /* Non-MII PHY; UNTESTED! */
1406 case S80C24: /* Non-MII PHY; tested and working */
1407 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1408 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1409 * doesn't have a programming interface of any sort. The
1410 * media is sensed automatically based on how the link partner
1411 * is configured. This is, in essence, manual configuration.
1412 */
1413 netif_info(nic, probe, nic->netdev,
1414 "found MII-less i82503 or 80c24 or other PHY\n");
1415
1416 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1417 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1418
1419 /* these might be needed for certain MII-less cards...
1420 * nic->flags |= ich;
1421 * nic->flags |= ich_10h_workaround; */
1422
1423 without_mii = 1;
1424 break;
1425 default:
1426 without_mii = 0;
1427 break;
1428 }
1429 return without_mii;
1430}
1431
1432#define NCONFIG_AUTO_SWITCH 0x0080
1433#define MII_NSC_CONG MII_RESV1
1434#define NSC_CONG_ENABLE 0x0100
1435#define NSC_CONG_TXREADY 0x0400
1436#define ADVERTISE_FC_SUPPORTED 0x0400
1437static int e100_phy_init(struct nic *nic)
1438{
1439 struct net_device *netdev = nic->netdev;
1440 u32 addr;
1441 u16 bmcr, stat, id_lo, id_hi, cong;
1442
1443 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1444 for (addr = 0; addr < 32; addr++) {
1445 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1446 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1447 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1448 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1449 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1450 break;
1451 }
1452 if (addr == 32) {
1453 /* uhoh, no PHY detected: check whether we seem to be some
1454 * weird, rare variant which is *known* to not have any MII.
1455 * But do this AFTER MII checking only, since this does
1456 * lookup of EEPROM values which may easily be unreliable. */
1457 if (e100_phy_check_without_mii(nic))
1458 return 0; /* simply return and hope for the best */
1459 else {
1460 /* for unknown cases log a fatal error */
1461 netif_err(nic, hw, nic->netdev,
1462 "Failed to locate any known PHY, aborting\n");
1463 return -EAGAIN;
1464 }
1465 } else
1466 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1467 "phy_addr = %d\n", nic->mii.phy_id);
1468
1469 /* Get phy ID */
1470 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1471 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1472 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1473 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1474 "phy ID = 0x%08X\n", nic->phy);
1475
1476 /* Select the phy and isolate the rest */
1477 for (addr = 0; addr < 32; addr++) {
1478 if (addr != nic->mii.phy_id) {
1479 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1480 } else if (nic->phy != phy_82552_v) {
1481 bmcr = mdio_read(netdev, addr, MII_BMCR);
1482 mdio_write(netdev, addr, MII_BMCR,
1483 bmcr & ~BMCR_ISOLATE);
1484 }
1485 }
1486 /*
1487 * Workaround for 82552:
1488 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1489 * other phy_id's) using bmcr value from addr discovery loop above.
1490 */
1491 if (nic->phy == phy_82552_v)
1492 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1493 bmcr & ~BMCR_ISOLATE);
1494
1495 /* Handle National tx phys */
1496#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1497 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1498 /* Disable congestion control */
1499 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1500 cong |= NSC_CONG_TXREADY;
1501 cong &= ~NSC_CONG_ENABLE;
1502 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1503 }
1504
1505 if (nic->phy == phy_82552_v) {
1506 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1507
1508 /* assign special tweaked mdio_ctrl() function */
1509 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1510
1511 /* Workaround Si not advertising flow-control during autoneg */
1512 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1513 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1514
1515 /* Reset for the above changes to take effect */
1516 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1517 bmcr |= BMCR_RESET;
1518 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1519 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1520 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1521 (nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1522 /* enable/disable MDI/MDI-X auto-switching. */
1523 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1524 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1525 }
1526
1527 return 0;
1528}
1529
1530static int e100_hw_init(struct nic *nic)
1531{
1532 int err = 0;
1533
1534 e100_hw_reset(nic);
1535
1536 netif_err(nic, hw, nic->netdev, "e100_hw_init\n");
1537 if (!in_interrupt() && (err = e100_self_test(nic)))
1538 return err;
1539
1540 if ((err = e100_phy_init(nic)))
1541 return err;
1542 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1543 return err;
1544 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1545 return err;
1546 if ((err = e100_load_ucode_wait(nic)))
1547 return err;
1548 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1549 return err;
1550 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1551 return err;
1552 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1553 nic->dma_addr + offsetof(struct mem, stats))))
1554 return err;
1555 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1556 return err;
1557
1558 e100_disable_irq(nic);
1559
1560 return 0;
1561}
1562
1563static int e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1564{
1565 struct net_device *netdev = nic->netdev;
1566 struct netdev_hw_addr *ha;
1567 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1568
1569 cb->command = cpu_to_le16(cb_multi);
1570 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1571 i = 0;
1572 netdev_for_each_mc_addr(ha, netdev) {
1573 if (i == count)
1574 break;
1575 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr,
1576 ETH_ALEN);
1577 }
1578 return 0;
1579}
1580
1581static void e100_set_multicast_list(struct net_device *netdev)
1582{
1583 struct nic *nic = netdev_priv(netdev);
1584
1585 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1586 "mc_count=%d, flags=0x%04X\n",
1587 netdev_mc_count(netdev), netdev->flags);
1588
1589 if (netdev->flags & IFF_PROMISC)
1590 nic->flags |= promiscuous;
1591 else
1592 nic->flags &= ~promiscuous;
1593
1594 if (netdev->flags & IFF_ALLMULTI ||
1595 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1596 nic->flags |= multicast_all;
1597 else
1598 nic->flags &= ~multicast_all;
1599
1600 e100_exec_cb(nic, NULL, e100_configure);
1601 e100_exec_cb(nic, NULL, e100_multi);
1602}
1603
1604static void e100_update_stats(struct nic *nic)
1605{
1606 struct net_device *dev = nic->netdev;
1607 struct net_device_stats *ns = &dev->stats;
1608 struct stats *s = &nic->mem->stats;
1609 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1610 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1611 &s->complete;
1612
1613 /* Device's stats reporting may take several microseconds to
1614 * complete, so we're always waiting for results of the
1615 * previous command. */
1616
1617 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1618 *complete = 0;
1619 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1620 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1621 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1622 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1623 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1624 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1625 ns->collisions += nic->tx_collisions;
1626 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1627 le32_to_cpu(s->tx_lost_crs);
1628 nic->rx_short_frame_errors +=
1629 le32_to_cpu(s->rx_short_frame_errors);
1630 ns->rx_length_errors = nic->rx_short_frame_errors +
1631 nic->rx_over_length_errors;
1632 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1633 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1634 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1635 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1636 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1637 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1638 le32_to_cpu(s->rx_alignment_errors) +
1639 le32_to_cpu(s->rx_short_frame_errors) +
1640 le32_to_cpu(s->rx_cdt_errors);
1641 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1642 nic->tx_single_collisions +=
1643 le32_to_cpu(s->tx_single_collisions);
1644 nic->tx_multiple_collisions +=
1645 le32_to_cpu(s->tx_multiple_collisions);
1646 if (nic->mac >= mac_82558_D101_A4) {
1647 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1648 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1649 nic->rx_fc_unsupported +=
1650 le32_to_cpu(s->fc_rcv_unsupported);
1651 if (nic->mac >= mac_82559_D101M) {
1652 nic->tx_tco_frames +=
1653 le16_to_cpu(s->xmt_tco_frames);
1654 nic->rx_tco_frames +=
1655 le16_to_cpu(s->rcv_tco_frames);
1656 }
1657 }
1658 }
1659
1660
1661 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1662 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1663 "exec cuc_dump_reset failed\n");
1664}
1665
1666static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1667{
1668 /* Adjust inter-frame-spacing (IFS) between two transmits if
1669 * we're getting collisions on a half-duplex connection. */
1670
1671 if (duplex == DUPLEX_HALF) {
1672 u32 prev = nic->adaptive_ifs;
1673 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1674
1675 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1676 (nic->tx_frames > min_frames)) {
1677 if (nic->adaptive_ifs < 60)
1678 nic->adaptive_ifs += 5;
1679 } else if (nic->tx_frames < min_frames) {
1680 if (nic->adaptive_ifs >= 5)
1681 nic->adaptive_ifs -= 5;
1682 }
1683 if (nic->adaptive_ifs != prev)
1684 e100_exec_cb(nic, NULL, e100_configure);
1685 }
1686}
1687
1688static void e100_watchdog(struct timer_list *t)
1689{
1690 struct nic *nic = from_timer(nic, t, watchdog);
1691 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1692 u32 speed;
1693
1694 netif_printk(nic, timer, KERN_DEBUG, nic->netdev,
1695 "right now = %ld\n", jiffies);
1696
1697 /* mii library handles link maintenance tasks */
1698
1699 mii_ethtool_gset(&nic->mii, &cmd);
1700 speed = ethtool_cmd_speed(&cmd);
1701
1702 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1703 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n",
1704 speed == SPEED_100 ? 100 : 10,
1705 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1706 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1707 netdev_info(nic->netdev, "NIC Link is Down\n");
1708 }
1709
1710 mii_check_link(&nic->mii);
1711
1712 /* Software generated interrupt to recover from (rare) Rx
1713 * allocation failure.
1714 * Unfortunately have to use a spinlock to not re-enable interrupts
1715 * accidentally, due to hardware that shares a register between the
1716 * interrupt mask bit and the SW Interrupt generation bit */
1717 spin_lock_irq(&nic->cmd_lock);
1718 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1719 e100_write_flush(nic);
1720 spin_unlock_irq(&nic->cmd_lock);
1721
1722 e100_update_stats(nic);
1723 e100_adjust_adaptive_ifs(nic, speed, cmd.duplex);
1724
1725 if (nic->mac <= mac_82557_D100_C)
1726 /* Issue a multicast command to workaround a 557 lock up */
1727 e100_set_multicast_list(nic->netdev);
1728
1729 if (nic->flags & ich && speed == SPEED_10 && cmd.duplex == DUPLEX_HALF)
1730 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1731 nic->flags |= ich_10h_workaround;
1732 else
1733 nic->flags &= ~ich_10h_workaround;
1734
1735 mod_timer(&nic->watchdog,
1736 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1737}
1738
1739static int e100_xmit_prepare(struct nic *nic, struct cb *cb,
1740 struct sk_buff *skb)
1741{
1742 dma_addr_t dma_addr;
1743 cb->command = nic->tx_command;
1744
1745 dma_addr = pci_map_single(nic->pdev,
1746 skb->data, skb->len, PCI_DMA_TODEVICE);
1747 /* If we can't map the skb, have the upper layer try later */
1748 if (pci_dma_mapping_error(nic->pdev, dma_addr)) {
1749 dev_kfree_skb_any(skb);
1750 skb = NULL;
1751 return -ENOMEM;
1752 }
1753
1754 /*
1755 * Use the last 4 bytes of the SKB payload packet as the CRC, used for
1756 * testing, ie sending frames with bad CRC.
1757 */
1758 if (unlikely(skb->no_fcs))
1759 cb->command |= cpu_to_le16(cb_tx_nc);
1760 else
1761 cb->command &= ~cpu_to_le16(cb_tx_nc);
1762
1763 /* interrupt every 16 packets regardless of delay */
1764 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1765 cb->command |= cpu_to_le16(cb_i);
1766 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1767 cb->u.tcb.tcb_byte_count = 0;
1768 cb->u.tcb.threshold = nic->tx_threshold;
1769 cb->u.tcb.tbd_count = 1;
1770 cb->u.tcb.tbd.buf_addr = cpu_to_le32(dma_addr);
1771 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1772 skb_tx_timestamp(skb);
1773 return 0;
1774}
1775
1776static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1777 struct net_device *netdev)
1778{
1779 struct nic *nic = netdev_priv(netdev);
1780 int err;
1781
1782 if (nic->flags & ich_10h_workaround) {
1783 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1784 Issue a NOP command followed by a 1us delay before
1785 issuing the Tx command. */
1786 if (e100_exec_cmd(nic, cuc_nop, 0))
1787 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1788 "exec cuc_nop failed\n");
1789 udelay(1);
1790 }
1791
1792 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1793
1794 switch (err) {
1795 case -ENOSPC:
1796 /* We queued the skb, but now we're out of space. */
1797 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1798 "No space for CB\n");
1799 netif_stop_queue(netdev);
1800 break;
1801 case -ENOMEM:
1802 /* This is a hard error - log it. */
1803 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1804 "Out of Tx resources, returning skb\n");
1805 netif_stop_queue(netdev);
1806 return NETDEV_TX_BUSY;
1807 }
1808
1809 return NETDEV_TX_OK;
1810}
1811
1812static int e100_tx_clean(struct nic *nic)
1813{
1814 struct net_device *dev = nic->netdev;
1815 struct cb *cb;
1816 int tx_cleaned = 0;
1817
1818 spin_lock(&nic->cb_lock);
1819
1820 /* Clean CBs marked complete */
1821 for (cb = nic->cb_to_clean;
1822 cb->status & cpu_to_le16(cb_complete);
1823 cb = nic->cb_to_clean = cb->next) {
1824 dma_rmb(); /* read skb after status */
1825 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev,
1826 "cb[%d]->status = 0x%04X\n",
1827 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1828 cb->status);
1829
1830 if (likely(cb->skb != NULL)) {
1831 dev->stats.tx_packets++;
1832 dev->stats.tx_bytes += cb->skb->len;
1833
1834 pci_unmap_single(nic->pdev,
1835 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1836 le16_to_cpu(cb->u.tcb.tbd.size),
1837 PCI_DMA_TODEVICE);
1838 dev_kfree_skb_any(cb->skb);
1839 cb->skb = NULL;
1840 tx_cleaned = 1;
1841 }
1842 cb->status = 0;
1843 nic->cbs_avail++;
1844 }
1845
1846 spin_unlock(&nic->cb_lock);
1847
1848 /* Recover from running out of Tx resources in xmit_frame */
1849 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1850 netif_wake_queue(nic->netdev);
1851
1852 return tx_cleaned;
1853}
1854
1855static void e100_clean_cbs(struct nic *nic)
1856{
1857 if (nic->cbs) {
1858 while (nic->cbs_avail != nic->params.cbs.count) {
1859 struct cb *cb = nic->cb_to_clean;
1860 if (cb->skb) {
1861 pci_unmap_single(nic->pdev,
1862 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1863 le16_to_cpu(cb->u.tcb.tbd.size),
1864 PCI_DMA_TODEVICE);
1865 dev_kfree_skb(cb->skb);
1866 }
1867 nic->cb_to_clean = nic->cb_to_clean->next;
1868 nic->cbs_avail++;
1869 }
1870 dma_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1871 nic->cbs = NULL;
1872 nic->cbs_avail = 0;
1873 }
1874 nic->cuc_cmd = cuc_start;
1875 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1876 nic->cbs;
1877}
1878
1879static int e100_alloc_cbs(struct nic *nic)
1880{
1881 struct cb *cb;
1882 unsigned int i, count = nic->params.cbs.count;
1883
1884 nic->cuc_cmd = cuc_start;
1885 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1886 nic->cbs_avail = 0;
1887
1888 nic->cbs = dma_pool_zalloc(nic->cbs_pool, GFP_KERNEL,
1889 &nic->cbs_dma_addr);
1890 if (!nic->cbs)
1891 return -ENOMEM;
1892
1893 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1894 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1895 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1896
1897 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1898 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1899 ((i+1) % count) * sizeof(struct cb));
1900 }
1901
1902 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1903 nic->cbs_avail = count;
1904
1905 return 0;
1906}
1907
1908static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1909{
1910 if (!nic->rxs) return;
1911 if (RU_SUSPENDED != nic->ru_running) return;
1912
1913 /* handle init time starts */
1914 if (!rx) rx = nic->rxs;
1915
1916 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1917 if (rx->skb) {
1918 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1919 nic->ru_running = RU_RUNNING;
1920 }
1921}
1922
1923#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
1924static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1925{
1926 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1927 return -ENOMEM;
1928
1929 /* Init, and map the RFD. */
1930 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1931 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1932 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1933
1934 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1935 dev_kfree_skb_any(rx->skb);
1936 rx->skb = NULL;
1937 rx->dma_addr = 0;
1938 return -ENOMEM;
1939 }
1940
1941 /* Link the RFD to end of RFA by linking previous RFD to
1942 * this one. We are safe to touch the previous RFD because
1943 * it is protected by the before last buffer's el bit being set */
1944 if (rx->prev->skb) {
1945 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1946 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1947 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1948 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1949 }
1950
1951 return 0;
1952}
1953
1954static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1955 unsigned int *work_done, unsigned int work_to_do)
1956{
1957 struct net_device *dev = nic->netdev;
1958 struct sk_buff *skb = rx->skb;
1959 struct rfd *rfd = (struct rfd *)skb->data;
1960 u16 rfd_status, actual_size;
1961 u16 fcs_pad = 0;
1962
1963 if (unlikely(work_done && *work_done >= work_to_do))
1964 return -EAGAIN;
1965
1966 /* Need to sync before taking a peek at cb_complete bit */
1967 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1968 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1969 rfd_status = le16_to_cpu(rfd->status);
1970
1971 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev,
1972 "status=0x%04X\n", rfd_status);
1973 dma_rmb(); /* read size after status bit */
1974
1975 /* If data isn't ready, nothing to indicate */
1976 if (unlikely(!(rfd_status & cb_complete))) {
1977 /* If the next buffer has the el bit, but we think the receiver
1978 * is still running, check to see if it really stopped while
1979 * we had interrupts off.
1980 * This allows for a fast restart without re-enabling
1981 * interrupts */
1982 if ((le16_to_cpu(rfd->command) & cb_el) &&
1983 (RU_RUNNING == nic->ru_running))
1984
1985 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1986 nic->ru_running = RU_SUSPENDED;
1987 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1988 sizeof(struct rfd),
1989 PCI_DMA_FROMDEVICE);
1990 return -ENODATA;
1991 }
1992
1993 /* Get actual data size */
1994 if (unlikely(dev->features & NETIF_F_RXFCS))
1995 fcs_pad = 4;
1996 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1997 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1998 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1999
2000 /* Get data */
2001 pci_unmap_single(nic->pdev, rx->dma_addr,
2002 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2003
2004 /* If this buffer has the el bit, but we think the receiver
2005 * is still running, check to see if it really stopped while
2006 * we had interrupts off.
2007 * This allows for a fast restart without re-enabling interrupts.
2008 * This can happen when the RU sees the size change but also sees
2009 * the el bit set. */
2010 if ((le16_to_cpu(rfd->command) & cb_el) &&
2011 (RU_RUNNING == nic->ru_running)) {
2012
2013 if (ioread8(&nic->csr->scb.status) & rus_no_res)
2014 nic->ru_running = RU_SUSPENDED;
2015 }
2016
2017 /* Pull off the RFD and put the actual data (minus eth hdr) */
2018 skb_reserve(skb, sizeof(struct rfd));
2019 skb_put(skb, actual_size);
2020 skb->protocol = eth_type_trans(skb, nic->netdev);
2021
2022 /* If we are receiving all frames, then don't bother
2023 * checking for errors.
2024 */
2025 if (unlikely(dev->features & NETIF_F_RXALL)) {
2026 if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad)
2027 /* Received oversized frame, but keep it. */
2028 nic->rx_over_length_errors++;
2029 goto process_skb;
2030 }
2031
2032 if (unlikely(!(rfd_status & cb_ok))) {
2033 /* Don't indicate if hardware indicates errors */
2034 dev_kfree_skb_any(skb);
2035 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad) {
2036 /* Don't indicate oversized frames */
2037 nic->rx_over_length_errors++;
2038 dev_kfree_skb_any(skb);
2039 } else {
2040process_skb:
2041 dev->stats.rx_packets++;
2042 dev->stats.rx_bytes += (actual_size - fcs_pad);
2043 netif_receive_skb(skb);
2044 if (work_done)
2045 (*work_done)++;
2046 }
2047
2048 rx->skb = NULL;
2049
2050 return 0;
2051}
2052
2053static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
2054 unsigned int work_to_do)
2055{
2056 struct rx *rx;
2057 int restart_required = 0, err = 0;
2058 struct rx *old_before_last_rx, *new_before_last_rx;
2059 struct rfd *old_before_last_rfd, *new_before_last_rfd;
2060
2061 /* Indicate newly arrived packets */
2062 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
2063 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
2064 /* Hit quota or no more to clean */
2065 if (-EAGAIN == err || -ENODATA == err)
2066 break;
2067 }
2068
2069
2070 /* On EAGAIN, hit quota so have more work to do, restart once
2071 * cleanup is complete.
2072 * Else, are we already rnr? then pay attention!!! this ensures that
2073 * the state machine progression never allows a start with a
2074 * partially cleaned list, avoiding a race between hardware
2075 * and rx_to_clean when in NAPI mode */
2076 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2077 restart_required = 1;
2078
2079 old_before_last_rx = nic->rx_to_use->prev->prev;
2080 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
2081
2082 /* Alloc new skbs to refill list */
2083 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2084 if (unlikely(e100_rx_alloc_skb(nic, rx)))
2085 break; /* Better luck next time (see watchdog) */
2086 }
2087
2088 new_before_last_rx = nic->rx_to_use->prev->prev;
2089 if (new_before_last_rx != old_before_last_rx) {
2090 /* Set the el-bit on the buffer that is before the last buffer.
2091 * This lets us update the next pointer on the last buffer
2092 * without worrying about hardware touching it.
2093 * We set the size to 0 to prevent hardware from touching this
2094 * buffer.
2095 * When the hardware hits the before last buffer with el-bit
2096 * and size of 0, it will RNR interrupt, the RUS will go into
2097 * the No Resources state. It will not complete nor write to
2098 * this buffer. */
2099 new_before_last_rfd =
2100 (struct rfd *)new_before_last_rx->skb->data;
2101 new_before_last_rfd->size = 0;
2102 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2103 pci_dma_sync_single_for_device(nic->pdev,
2104 new_before_last_rx->dma_addr, sizeof(struct rfd),
2105 PCI_DMA_BIDIRECTIONAL);
2106
2107 /* Now that we have a new stopping point, we can clear the old
2108 * stopping point. We must sync twice to get the proper
2109 * ordering on the hardware side of things. */
2110 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2111 pci_dma_sync_single_for_device(nic->pdev,
2112 old_before_last_rx->dma_addr, sizeof(struct rfd),
2113 PCI_DMA_BIDIRECTIONAL);
2114 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN
2115 + ETH_FCS_LEN);
2116 pci_dma_sync_single_for_device(nic->pdev,
2117 old_before_last_rx->dma_addr, sizeof(struct rfd),
2118 PCI_DMA_BIDIRECTIONAL);
2119 }
2120
2121 if (restart_required) {
2122 // ack the rnr?
2123 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2124 e100_start_receiver(nic, nic->rx_to_clean);
2125 if (work_done)
2126 (*work_done)++;
2127 }
2128}
2129
2130static void e100_rx_clean_list(struct nic *nic)
2131{
2132 struct rx *rx;
2133 unsigned int i, count = nic->params.rfds.count;
2134
2135 nic->ru_running = RU_UNINITIALIZED;
2136
2137 if (nic->rxs) {
2138 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2139 if (rx->skb) {
2140 pci_unmap_single(nic->pdev, rx->dma_addr,
2141 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2142 dev_kfree_skb(rx->skb);
2143 }
2144 }
2145 kfree(nic->rxs);
2146 nic->rxs = NULL;
2147 }
2148
2149 nic->rx_to_use = nic->rx_to_clean = NULL;
2150}
2151
2152static int e100_rx_alloc_list(struct nic *nic)
2153{
2154 struct rx *rx;
2155 unsigned int i, count = nic->params.rfds.count;
2156 struct rfd *before_last;
2157
2158 nic->rx_to_use = nic->rx_to_clean = NULL;
2159 nic->ru_running = RU_UNINITIALIZED;
2160
2161 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2162 return -ENOMEM;
2163
2164 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2165 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2166 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2167 if (e100_rx_alloc_skb(nic, rx)) {
2168 e100_rx_clean_list(nic);
2169 return -ENOMEM;
2170 }
2171 }
2172 /* Set the el-bit on the buffer that is before the last buffer.
2173 * This lets us update the next pointer on the last buffer without
2174 * worrying about hardware touching it.
2175 * We set the size to 0 to prevent hardware from touching this buffer.
2176 * When the hardware hits the before last buffer with el-bit and size
2177 * of 0, it will RNR interrupt, the RU will go into the No Resources
2178 * state. It will not complete nor write to this buffer. */
2179 rx = nic->rxs->prev->prev;
2180 before_last = (struct rfd *)rx->skb->data;
2181 before_last->command |= cpu_to_le16(cb_el);
2182 before_last->size = 0;
2183 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2184 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2185
2186 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2187 nic->ru_running = RU_SUSPENDED;
2188
2189 return 0;
2190}
2191
2192static irqreturn_t e100_intr(int irq, void *dev_id)
2193{
2194 struct net_device *netdev = dev_id;
2195 struct nic *nic = netdev_priv(netdev);
2196 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2197
2198 netif_printk(nic, intr, KERN_DEBUG, nic->netdev,
2199 "stat_ack = 0x%02X\n", stat_ack);
2200
2201 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2202 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2203 return IRQ_NONE;
2204
2205 /* Ack interrupt(s) */
2206 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2207
2208 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2209 if (stat_ack & stat_ack_rnr)
2210 nic->ru_running = RU_SUSPENDED;
2211
2212 if (likely(napi_schedule_prep(&nic->napi))) {
2213 e100_disable_irq(nic);
2214 __napi_schedule(&nic->napi);
2215 }
2216
2217 return IRQ_HANDLED;
2218}
2219
2220static int e100_poll(struct napi_struct *napi, int budget)
2221{
2222 struct nic *nic = container_of(napi, struct nic, napi);
2223 unsigned int work_done = 0;
2224
2225 e100_rx_clean(nic, &work_done, budget);
2226 e100_tx_clean(nic);
2227
2228 /* If budget fully consumed, continue polling */
2229 if (work_done == budget)
2230 return budget;
2231
2232 /* only re-enable interrupt if stack agrees polling is really done */
2233 if (likely(napi_complete_done(napi, work_done)))
2234 e100_enable_irq(nic);
2235
2236 return work_done;
2237}
2238
2239#ifdef CONFIG_NET_POLL_CONTROLLER
2240static void e100_netpoll(struct net_device *netdev)
2241{
2242 struct nic *nic = netdev_priv(netdev);
2243
2244 e100_disable_irq(nic);
2245 e100_intr(nic->pdev->irq, netdev);
2246 e100_tx_clean(nic);
2247 e100_enable_irq(nic);
2248}
2249#endif
2250
2251static int e100_set_mac_address(struct net_device *netdev, void *p)
2252{
2253 struct nic *nic = netdev_priv(netdev);
2254 struct sockaddr *addr = p;
2255
2256 if (!is_valid_ether_addr(addr->sa_data))
2257 return -EADDRNOTAVAIL;
2258
2259 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2260 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2261
2262 return 0;
2263}
2264
2265static int e100_asf(struct nic *nic)
2266{
2267 /* ASF can be enabled from eeprom */
2268 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2269 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2270 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2271 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE);
2272}
2273
2274static int e100_up(struct nic *nic)
2275{
2276 int err;
2277
2278 if ((err = e100_rx_alloc_list(nic)))
2279 return err;
2280 if ((err = e100_alloc_cbs(nic)))
2281 goto err_rx_clean_list;
2282 if ((err = e100_hw_init(nic)))
2283 goto err_clean_cbs;
2284 e100_set_multicast_list(nic->netdev);
2285 e100_start_receiver(nic, NULL);
2286 mod_timer(&nic->watchdog, jiffies);
2287 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2288 nic->netdev->name, nic->netdev)))
2289 goto err_no_irq;
2290 netif_wake_queue(nic->netdev);
2291 napi_enable(&nic->napi);
2292 /* enable ints _after_ enabling poll, preventing a race between
2293 * disable ints+schedule */
2294 e100_enable_irq(nic);
2295 return 0;
2296
2297err_no_irq:
2298 del_timer_sync(&nic->watchdog);
2299err_clean_cbs:
2300 e100_clean_cbs(nic);
2301err_rx_clean_list:
2302 e100_rx_clean_list(nic);
2303 return err;
2304}
2305
2306static void e100_down(struct nic *nic)
2307{
2308 /* wait here for poll to complete */
2309 napi_disable(&nic->napi);
2310 netif_stop_queue(nic->netdev);
2311 e100_hw_reset(nic);
2312 free_irq(nic->pdev->irq, nic->netdev);
2313 del_timer_sync(&nic->watchdog);
2314 netif_carrier_off(nic->netdev);
2315 e100_clean_cbs(nic);
2316 e100_rx_clean_list(nic);
2317}
2318
2319static void e100_tx_timeout(struct net_device *netdev)
2320{
2321 struct nic *nic = netdev_priv(netdev);
2322
2323 /* Reset outside of interrupt context, to avoid request_irq
2324 * in interrupt context */
2325 schedule_work(&nic->tx_timeout_task);
2326}
2327
2328static void e100_tx_timeout_task(struct work_struct *work)
2329{
2330 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2331 struct net_device *netdev = nic->netdev;
2332
2333 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
2334 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status));
2335
2336 rtnl_lock();
2337 if (netif_running(netdev)) {
2338 e100_down(netdev_priv(netdev));
2339 e100_up(netdev_priv(netdev));
2340 }
2341 rtnl_unlock();
2342}
2343
2344static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2345{
2346 int err;
2347 struct sk_buff *skb;
2348
2349 /* Use driver resources to perform internal MAC or PHY
2350 * loopback test. A single packet is prepared and transmitted
2351 * in loopback mode, and the test passes if the received
2352 * packet compares byte-for-byte to the transmitted packet. */
2353
2354 if ((err = e100_rx_alloc_list(nic)))
2355 return err;
2356 if ((err = e100_alloc_cbs(nic)))
2357 goto err_clean_rx;
2358
2359 /* ICH PHY loopback is broken so do MAC loopback instead */
2360 if (nic->flags & ich && loopback_mode == lb_phy)
2361 loopback_mode = lb_mac;
2362
2363 nic->loopback = loopback_mode;
2364 if ((err = e100_hw_init(nic)))
2365 goto err_loopback_none;
2366
2367 if (loopback_mode == lb_phy)
2368 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2369 BMCR_LOOPBACK);
2370
2371 e100_start_receiver(nic, NULL);
2372
2373 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2374 err = -ENOMEM;
2375 goto err_loopback_none;
2376 }
2377 skb_put(skb, ETH_DATA_LEN);
2378 memset(skb->data, 0xFF, ETH_DATA_LEN);
2379 e100_xmit_frame(skb, nic->netdev);
2380
2381 msleep(10);
2382
2383 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2384 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2385
2386 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2387 skb->data, ETH_DATA_LEN))
2388 err = -EAGAIN;
2389
2390err_loopback_none:
2391 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2392 nic->loopback = lb_none;
2393 e100_clean_cbs(nic);
2394 e100_hw_reset(nic);
2395err_clean_rx:
2396 e100_rx_clean_list(nic);
2397 return err;
2398}
2399
2400#define MII_LED_CONTROL 0x1B
2401#define E100_82552_LED_OVERRIDE 0x19
2402#define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2403#define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2404
2405static int e100_get_link_ksettings(struct net_device *netdev,
2406 struct ethtool_link_ksettings *cmd)
2407{
2408 struct nic *nic = netdev_priv(netdev);
2409
2410 mii_ethtool_get_link_ksettings(&nic->mii, cmd);
2411
2412 return 0;
2413}
2414
2415static int e100_set_link_ksettings(struct net_device *netdev,
2416 const struct ethtool_link_ksettings *cmd)
2417{
2418 struct nic *nic = netdev_priv(netdev);
2419 int err;
2420
2421 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2422 err = mii_ethtool_set_link_ksettings(&nic->mii, cmd);
2423 e100_exec_cb(nic, NULL, e100_configure);
2424
2425 return err;
2426}
2427
2428static void e100_get_drvinfo(struct net_device *netdev,
2429 struct ethtool_drvinfo *info)
2430{
2431 struct nic *nic = netdev_priv(netdev);
2432 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2433 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2434 strlcpy(info->bus_info, pci_name(nic->pdev),
2435 sizeof(info->bus_info));
2436}
2437
2438#define E100_PHY_REGS 0x1C
2439static int e100_get_regs_len(struct net_device *netdev)
2440{
2441 struct nic *nic = netdev_priv(netdev);
2442 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2443}
2444
2445static void e100_get_regs(struct net_device *netdev,
2446 struct ethtool_regs *regs, void *p)
2447{
2448 struct nic *nic = netdev_priv(netdev);
2449 u32 *buff = p;
2450 int i;
2451
2452 regs->version = (1 << 24) | nic->pdev->revision;
2453 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2454 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2455 ioread16(&nic->csr->scb.status);
2456 for (i = E100_PHY_REGS; i >= 0; i--)
2457 buff[1 + E100_PHY_REGS - i] =
2458 mdio_read(netdev, nic->mii.phy_id, i);
2459 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2460 e100_exec_cb(nic, NULL, e100_dump);
2461 msleep(10);
2462 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2463 sizeof(nic->mem->dump_buf));
2464}
2465
2466static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2467{
2468 struct nic *nic = netdev_priv(netdev);
2469 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2470 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2471}
2472
2473static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2474{
2475 struct nic *nic = netdev_priv(netdev);
2476
2477 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2478 !device_can_wakeup(&nic->pdev->dev))
2479 return -EOPNOTSUPP;
2480
2481 if (wol->wolopts)
2482 nic->flags |= wol_magic;
2483 else
2484 nic->flags &= ~wol_magic;
2485
2486 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2487
2488 e100_exec_cb(nic, NULL, e100_configure);
2489
2490 return 0;
2491}
2492
2493static u32 e100_get_msglevel(struct net_device *netdev)
2494{
2495 struct nic *nic = netdev_priv(netdev);
2496 return nic->msg_enable;
2497}
2498
2499static void e100_set_msglevel(struct net_device *netdev, u32 value)
2500{
2501 struct nic *nic = netdev_priv(netdev);
2502 nic->msg_enable = value;
2503}
2504
2505static int e100_nway_reset(struct net_device *netdev)
2506{
2507 struct nic *nic = netdev_priv(netdev);
2508 return mii_nway_restart(&nic->mii);
2509}
2510
2511static u32 e100_get_link(struct net_device *netdev)
2512{
2513 struct nic *nic = netdev_priv(netdev);
2514 return mii_link_ok(&nic->mii);
2515}
2516
2517static int e100_get_eeprom_len(struct net_device *netdev)
2518{
2519 struct nic *nic = netdev_priv(netdev);
2520 return nic->eeprom_wc << 1;
2521}
2522
2523#define E100_EEPROM_MAGIC 0x1234
2524static int e100_get_eeprom(struct net_device *netdev,
2525 struct ethtool_eeprom *eeprom, u8 *bytes)
2526{
2527 struct nic *nic = netdev_priv(netdev);
2528
2529 eeprom->magic = E100_EEPROM_MAGIC;
2530 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2531
2532 return 0;
2533}
2534
2535static int e100_set_eeprom(struct net_device *netdev,
2536 struct ethtool_eeprom *eeprom, u8 *bytes)
2537{
2538 struct nic *nic = netdev_priv(netdev);
2539
2540 if (eeprom->magic != E100_EEPROM_MAGIC)
2541 return -EINVAL;
2542
2543 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2544
2545 return e100_eeprom_save(nic, eeprom->offset >> 1,
2546 (eeprom->len >> 1) + 1);
2547}
2548
2549static void e100_get_ringparam(struct net_device *netdev,
2550 struct ethtool_ringparam *ring)
2551{
2552 struct nic *nic = netdev_priv(netdev);
2553 struct param_range *rfds = &nic->params.rfds;
2554 struct param_range *cbs = &nic->params.cbs;
2555
2556 ring->rx_max_pending = rfds->max;
2557 ring->tx_max_pending = cbs->max;
2558 ring->rx_pending = rfds->count;
2559 ring->tx_pending = cbs->count;
2560}
2561
2562static int e100_set_ringparam(struct net_device *netdev,
2563 struct ethtool_ringparam *ring)
2564{
2565 struct nic *nic = netdev_priv(netdev);
2566 struct param_range *rfds = &nic->params.rfds;
2567 struct param_range *cbs = &nic->params.cbs;
2568
2569 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2570 return -EINVAL;
2571
2572 if (netif_running(netdev))
2573 e100_down(nic);
2574 rfds->count = max(ring->rx_pending, rfds->min);
2575 rfds->count = min(rfds->count, rfds->max);
2576 cbs->count = max(ring->tx_pending, cbs->min);
2577 cbs->count = min(cbs->count, cbs->max);
2578 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n",
2579 rfds->count, cbs->count);
2580 if (netif_running(netdev))
2581 e100_up(nic);
2582
2583 return 0;
2584}
2585
2586static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2587 "Link test (on/offline)",
2588 "Eeprom test (on/offline)",
2589 "Self test (offline)",
2590 "Mac loopback (offline)",
2591 "Phy loopback (offline)",
2592};
2593#define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2594
2595static void e100_diag_test(struct net_device *netdev,
2596 struct ethtool_test *test, u64 *data)
2597{
2598 struct ethtool_cmd cmd;
2599 struct nic *nic = netdev_priv(netdev);
2600 int i, err;
2601
2602 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2603 data[0] = !mii_link_ok(&nic->mii);
2604 data[1] = e100_eeprom_load(nic);
2605 if (test->flags & ETH_TEST_FL_OFFLINE) {
2606
2607 /* save speed, duplex & autoneg settings */
2608 err = mii_ethtool_gset(&nic->mii, &cmd);
2609
2610 if (netif_running(netdev))
2611 e100_down(nic);
2612 data[2] = e100_self_test(nic);
2613 data[3] = e100_loopback_test(nic, lb_mac);
2614 data[4] = e100_loopback_test(nic, lb_phy);
2615
2616 /* restore speed, duplex & autoneg settings */
2617 err = mii_ethtool_sset(&nic->mii, &cmd);
2618
2619 if (netif_running(netdev))
2620 e100_up(nic);
2621 }
2622 for (i = 0; i < E100_TEST_LEN; i++)
2623 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2624
2625 msleep_interruptible(4 * 1000);
2626}
2627
2628static int e100_set_phys_id(struct net_device *netdev,
2629 enum ethtool_phys_id_state state)
2630{
2631 struct nic *nic = netdev_priv(netdev);
2632 enum led_state {
2633 led_on = 0x01,
2634 led_off = 0x04,
2635 led_on_559 = 0x05,
2636 led_on_557 = 0x07,
2637 };
2638 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2639 MII_LED_CONTROL;
2640 u16 leds = 0;
2641
2642 switch (state) {
2643 case ETHTOOL_ID_ACTIVE:
2644 return 2;
2645
2646 case ETHTOOL_ID_ON:
2647 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_ON :
2648 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2649 break;
2650
2651 case ETHTOOL_ID_OFF:
2652 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_OFF : led_off;
2653 break;
2654
2655 case ETHTOOL_ID_INACTIVE:
2656 break;
2657 }
2658
2659 mdio_write(netdev, nic->mii.phy_id, led_reg, leds);
2660 return 0;
2661}
2662
2663static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2664 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2665 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2666 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2667 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2668 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2669 "tx_heartbeat_errors", "tx_window_errors",
2670 /* device-specific stats */
2671 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2672 "tx_flow_control_pause", "rx_flow_control_pause",
2673 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2674 "rx_short_frame_errors", "rx_over_length_errors",
2675};
2676#define E100_NET_STATS_LEN 21
2677#define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2678
2679static int e100_get_sset_count(struct net_device *netdev, int sset)
2680{
2681 switch (sset) {
2682 case ETH_SS_TEST:
2683 return E100_TEST_LEN;
2684 case ETH_SS_STATS:
2685 return E100_STATS_LEN;
2686 default:
2687 return -EOPNOTSUPP;
2688 }
2689}
2690
2691static void e100_get_ethtool_stats(struct net_device *netdev,
2692 struct ethtool_stats *stats, u64 *data)
2693{
2694 struct nic *nic = netdev_priv(netdev);
2695 int i;
2696
2697 for (i = 0; i < E100_NET_STATS_LEN; i++)
2698 data[i] = ((unsigned long *)&netdev->stats)[i];
2699
2700 data[i++] = nic->tx_deferred;
2701 data[i++] = nic->tx_single_collisions;
2702 data[i++] = nic->tx_multiple_collisions;
2703 data[i++] = nic->tx_fc_pause;
2704 data[i++] = nic->rx_fc_pause;
2705 data[i++] = nic->rx_fc_unsupported;
2706 data[i++] = nic->tx_tco_frames;
2707 data[i++] = nic->rx_tco_frames;
2708 data[i++] = nic->rx_short_frame_errors;
2709 data[i++] = nic->rx_over_length_errors;
2710}
2711
2712static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2713{
2714 switch (stringset) {
2715 case ETH_SS_TEST:
2716 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2717 break;
2718 case ETH_SS_STATS:
2719 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2720 break;
2721 }
2722}
2723
2724static const struct ethtool_ops e100_ethtool_ops = {
2725 .get_drvinfo = e100_get_drvinfo,
2726 .get_regs_len = e100_get_regs_len,
2727 .get_regs = e100_get_regs,
2728 .get_wol = e100_get_wol,
2729 .set_wol = e100_set_wol,
2730 .get_msglevel = e100_get_msglevel,
2731 .set_msglevel = e100_set_msglevel,
2732 .nway_reset = e100_nway_reset,
2733 .get_link = e100_get_link,
2734 .get_eeprom_len = e100_get_eeprom_len,
2735 .get_eeprom = e100_get_eeprom,
2736 .set_eeprom = e100_set_eeprom,
2737 .get_ringparam = e100_get_ringparam,
2738 .set_ringparam = e100_set_ringparam,
2739 .self_test = e100_diag_test,
2740 .get_strings = e100_get_strings,
2741 .set_phys_id = e100_set_phys_id,
2742 .get_ethtool_stats = e100_get_ethtool_stats,
2743 .get_sset_count = e100_get_sset_count,
2744 .get_ts_info = ethtool_op_get_ts_info,
2745 .get_link_ksettings = e100_get_link_ksettings,
2746 .set_link_ksettings = e100_set_link_ksettings,
2747};
2748
2749static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2750{
2751 struct nic *nic = netdev_priv(netdev);
2752
2753 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2754}
2755
2756static int e100_alloc(struct nic *nic)
2757{
2758 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2759 &nic->dma_addr);
2760 return nic->mem ? 0 : -ENOMEM;
2761}
2762
2763static void e100_free(struct nic *nic)
2764{
2765 if (nic->mem) {
2766 pci_free_consistent(nic->pdev, sizeof(struct mem),
2767 nic->mem, nic->dma_addr);
2768 nic->mem = NULL;
2769 }
2770}
2771
2772static int e100_open(struct net_device *netdev)
2773{
2774 struct nic *nic = netdev_priv(netdev);
2775 int err = 0;
2776
2777 netif_carrier_off(netdev);
2778 if ((err = e100_up(nic)))
2779 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n");
2780 return err;
2781}
2782
2783static int e100_close(struct net_device *netdev)
2784{
2785 e100_down(netdev_priv(netdev));
2786 return 0;
2787}
2788
2789static int e100_set_features(struct net_device *netdev,
2790 netdev_features_t features)
2791{
2792 struct nic *nic = netdev_priv(netdev);
2793 netdev_features_t changed = features ^ netdev->features;
2794
2795 if (!(changed & (NETIF_F_RXFCS | NETIF_F_RXALL)))
2796 return 0;
2797
2798 netdev->features = features;
2799 e100_exec_cb(nic, NULL, e100_configure);
2800 return 1;
2801}
2802
2803static const struct net_device_ops e100_netdev_ops = {
2804 .ndo_open = e100_open,
2805 .ndo_stop = e100_close,
2806 .ndo_start_xmit = e100_xmit_frame,
2807 .ndo_validate_addr = eth_validate_addr,
2808 .ndo_set_rx_mode = e100_set_multicast_list,
2809 .ndo_set_mac_address = e100_set_mac_address,
2810 .ndo_do_ioctl = e100_do_ioctl,
2811 .ndo_tx_timeout = e100_tx_timeout,
2812#ifdef CONFIG_NET_POLL_CONTROLLER
2813 .ndo_poll_controller = e100_netpoll,
2814#endif
2815 .ndo_set_features = e100_set_features,
2816};
2817
2818static int e100_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2819{
2820 struct net_device *netdev;
2821 struct nic *nic;
2822 int err;
2823
2824 if (!(netdev = alloc_etherdev(sizeof(struct nic))))
2825 return -ENOMEM;
2826
2827 netdev->hw_features |= NETIF_F_RXFCS;
2828 netdev->priv_flags |= IFF_SUPP_NOFCS;
2829 netdev->hw_features |= NETIF_F_RXALL;
2830
2831 netdev->netdev_ops = &e100_netdev_ops;
2832 netdev->ethtool_ops = &e100_ethtool_ops;
2833 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2834 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2835
2836 nic = netdev_priv(netdev);
2837 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2838 nic->netdev = netdev;
2839 nic->pdev = pdev;
2840 nic->msg_enable = (1 << debug) - 1;
2841 nic->mdio_ctrl = mdio_ctrl_hw;
2842 pci_set_drvdata(pdev, netdev);
2843
2844 if ((err = pci_enable_device(pdev))) {
2845 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n");
2846 goto err_out_free_dev;
2847 }
2848
2849 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2850 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n");
2851 err = -ENODEV;
2852 goto err_out_disable_pdev;
2853 }
2854
2855 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2856 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n");
2857 goto err_out_disable_pdev;
2858 }
2859
2860 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2861 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n");
2862 goto err_out_free_res;
2863 }
2864
2865 SET_NETDEV_DEV(netdev, &pdev->dev);
2866
2867 if (use_io)
2868 netif_info(nic, probe, nic->netdev, "using i/o access mode\n");
2869
2870 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2871 if (!nic->csr) {
2872 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n");
2873 err = -ENOMEM;
2874 goto err_out_free_res;
2875 }
2876
2877 if (ent->driver_data)
2878 nic->flags |= ich;
2879 else
2880 nic->flags &= ~ich;
2881
2882 e100_get_defaults(nic);
2883
2884 /* D100 MAC doesn't allow rx of vlan packets with normal MTU */
2885 if (nic->mac < mac_82558_D101_A4)
2886 netdev->features |= NETIF_F_VLAN_CHALLENGED;
2887
2888 /* locks must be initialized before calling hw_reset */
2889 spin_lock_init(&nic->cb_lock);
2890 spin_lock_init(&nic->cmd_lock);
2891 spin_lock_init(&nic->mdio_lock);
2892
2893 /* Reset the device before pci_set_master() in case device is in some
2894 * funky state and has an interrupt pending - hint: we don't have the
2895 * interrupt handler registered yet. */
2896 e100_hw_reset(nic);
2897
2898 pci_set_master(pdev);
2899
2900 timer_setup(&nic->watchdog, e100_watchdog, 0);
2901
2902 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2903
2904 if ((err = e100_alloc(nic))) {
2905 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n");
2906 goto err_out_iounmap;
2907 }
2908
2909 if ((err = e100_eeprom_load(nic)))
2910 goto err_out_free;
2911
2912 e100_phy_init(nic);
2913
2914 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2915 if (!is_valid_ether_addr(netdev->dev_addr)) {
2916 if (!eeprom_bad_csum_allow) {
2917 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n");
2918 err = -EAGAIN;
2919 goto err_out_free;
2920 } else {
2921 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n");
2922 }
2923 }
2924
2925 /* Wol magic packet can be enabled from eeprom */
2926 if ((nic->mac >= mac_82558_D101_A4) &&
2927 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2928 nic->flags |= wol_magic;
2929 device_set_wakeup_enable(&pdev->dev, true);
2930 }
2931
2932 /* ack any pending wake events, disable PME */
2933 pci_pme_active(pdev, false);
2934
2935 strcpy(netdev->name, "eth%d");
2936 if ((err = register_netdev(netdev))) {
2937 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n");
2938 goto err_out_free;
2939 }
2940 nic->cbs_pool = dma_pool_create(netdev->name,
2941 &nic->pdev->dev,
2942 nic->params.cbs.max * sizeof(struct cb),
2943 sizeof(u32),
2944 0);
2945 if (!nic->cbs_pool) {
2946 netif_err(nic, probe, nic->netdev, "Cannot create DMA pool, aborting\n");
2947 err = -ENOMEM;
2948 goto err_out_pool;
2949 }
2950 netif_info(nic, probe, nic->netdev,
2951 "addr 0x%llx, irq %d, MAC addr %pM\n",
2952 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2953 pdev->irq, netdev->dev_addr);
2954
2955 return 0;
2956
2957err_out_pool:
2958 unregister_netdev(netdev);
2959err_out_free:
2960 e100_free(nic);
2961err_out_iounmap:
2962 pci_iounmap(pdev, nic->csr);
2963err_out_free_res:
2964 pci_release_regions(pdev);
2965err_out_disable_pdev:
2966 pci_disable_device(pdev);
2967err_out_free_dev:
2968 free_netdev(netdev);
2969 return err;
2970}
2971
2972static void e100_remove(struct pci_dev *pdev)
2973{
2974 struct net_device *netdev = pci_get_drvdata(pdev);
2975
2976 if (netdev) {
2977 struct nic *nic = netdev_priv(netdev);
2978 unregister_netdev(netdev);
2979 e100_free(nic);
2980 pci_iounmap(pdev, nic->csr);
2981 dma_pool_destroy(nic->cbs_pool);
2982 free_netdev(netdev);
2983 pci_release_regions(pdev);
2984 pci_disable_device(pdev);
2985 }
2986}
2987
2988#define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2989#define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2990#define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2991static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2992{
2993 struct net_device *netdev = pci_get_drvdata(pdev);
2994 struct nic *nic = netdev_priv(netdev);
2995
2996 if (netif_running(netdev))
2997 e100_down(nic);
2998 netif_device_detach(netdev);
2999
3000 pci_save_state(pdev);
3001
3002 if ((nic->flags & wol_magic) | e100_asf(nic)) {
3003 /* enable reverse auto-negotiation */
3004 if (nic->phy == phy_82552_v) {
3005 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
3006 E100_82552_SMARTSPEED);
3007
3008 mdio_write(netdev, nic->mii.phy_id,
3009 E100_82552_SMARTSPEED, smartspeed |
3010 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
3011 }
3012 *enable_wake = true;
3013 } else {
3014 *enable_wake = false;
3015 }
3016
3017 pci_clear_master(pdev);
3018}
3019
3020static int __e100_power_off(struct pci_dev *pdev, bool wake)
3021{
3022 if (wake)
3023 return pci_prepare_to_sleep(pdev);
3024
3025 pci_wake_from_d3(pdev, false);
3026 pci_set_power_state(pdev, PCI_D3hot);
3027
3028 return 0;
3029}
3030
3031#ifdef CONFIG_PM
3032static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
3033{
3034 bool wake;
3035 __e100_shutdown(pdev, &wake);
3036 return __e100_power_off(pdev, wake);
3037}
3038
3039static int e100_resume(struct pci_dev *pdev)
3040{
3041 struct net_device *netdev = pci_get_drvdata(pdev);
3042 struct nic *nic = netdev_priv(netdev);
3043
3044 pci_set_power_state(pdev, PCI_D0);
3045 pci_restore_state(pdev);
3046 /* ack any pending wake events, disable PME */
3047 pci_enable_wake(pdev, PCI_D0, 0);
3048
3049 /* disable reverse auto-negotiation */
3050 if (nic->phy == phy_82552_v) {
3051 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
3052 E100_82552_SMARTSPEED);
3053
3054 mdio_write(netdev, nic->mii.phy_id,
3055 E100_82552_SMARTSPEED,
3056 smartspeed & ~(E100_82552_REV_ANEG));
3057 }
3058
3059 netif_device_attach(netdev);
3060 if (netif_running(netdev))
3061 e100_up(nic);
3062
3063 return 0;
3064}
3065#endif /* CONFIG_PM */
3066
3067static void e100_shutdown(struct pci_dev *pdev)
3068{
3069 bool wake;
3070 __e100_shutdown(pdev, &wake);
3071 if (system_state == SYSTEM_POWER_OFF)
3072 __e100_power_off(pdev, wake);
3073}
3074
3075/* ------------------ PCI Error Recovery infrastructure -------------- */
3076/**
3077 * e100_io_error_detected - called when PCI error is detected.
3078 * @pdev: Pointer to PCI device
3079 * @state: The current pci connection state
3080 */
3081static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3082{
3083 struct net_device *netdev = pci_get_drvdata(pdev);
3084 struct nic *nic = netdev_priv(netdev);
3085
3086 netif_device_detach(netdev);
3087
3088 if (state == pci_channel_io_perm_failure)
3089 return PCI_ERS_RESULT_DISCONNECT;
3090
3091 if (netif_running(netdev))
3092 e100_down(nic);
3093 pci_disable_device(pdev);
3094
3095 /* Request a slot reset. */
3096 return PCI_ERS_RESULT_NEED_RESET;
3097}
3098
3099/**
3100 * e100_io_slot_reset - called after the pci bus has been reset.
3101 * @pdev: Pointer to PCI device
3102 *
3103 * Restart the card from scratch.
3104 */
3105static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3106{
3107 struct net_device *netdev = pci_get_drvdata(pdev);
3108 struct nic *nic = netdev_priv(netdev);
3109
3110 if (pci_enable_device(pdev)) {
3111 pr_err("Cannot re-enable PCI device after reset\n");
3112 return PCI_ERS_RESULT_DISCONNECT;
3113 }
3114 pci_set_master(pdev);
3115
3116 /* Only one device per card can do a reset */
3117 if (0 != PCI_FUNC(pdev->devfn))
3118 return PCI_ERS_RESULT_RECOVERED;
3119 e100_hw_reset(nic);
3120 e100_phy_init(nic);
3121
3122 return PCI_ERS_RESULT_RECOVERED;
3123}
3124
3125/**
3126 * e100_io_resume - resume normal operations
3127 * @pdev: Pointer to PCI device
3128 *
3129 * Resume normal operations after an error recovery
3130 * sequence has been completed.
3131 */
3132static void e100_io_resume(struct pci_dev *pdev)
3133{
3134 struct net_device *netdev = pci_get_drvdata(pdev);
3135 struct nic *nic = netdev_priv(netdev);
3136
3137 /* ack any pending wake events, disable PME */
3138 pci_enable_wake(pdev, PCI_D0, 0);
3139
3140 netif_device_attach(netdev);
3141 if (netif_running(netdev)) {
3142 e100_open(netdev);
3143 mod_timer(&nic->watchdog, jiffies);
3144 }
3145}
3146
3147static const struct pci_error_handlers e100_err_handler = {
3148 .error_detected = e100_io_error_detected,
3149 .slot_reset = e100_io_slot_reset,
3150 .resume = e100_io_resume,
3151};
3152
3153static struct pci_driver e100_driver = {
3154 .name = DRV_NAME,
3155 .id_table = e100_id_table,
3156 .probe = e100_probe,
3157 .remove = e100_remove,
3158#ifdef CONFIG_PM
3159 /* Power Management hooks */
3160 .suspend = e100_suspend,
3161 .resume = e100_resume,
3162#endif
3163 .shutdown = e100_shutdown,
3164 .err_handler = &e100_err_handler,
3165};
3166
3167static int __init e100_init_module(void)
3168{
3169 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3170 pr_info("%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3171 pr_info("%s\n", DRV_COPYRIGHT);
3172 }
3173 return pci_register_driver(&e100_driver);
3174}
3175
3176static void __exit e100_cleanup_module(void)
3177{
3178 pci_unregister_driver(&e100_driver);
3179}
3180
3181module_init(e100_init_module);
3182module_exit(e100_cleanup_module);
1/*******************************************************************************
2
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Receive
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
123 * scenario where all Rx resources have been indicated and none re-
124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
148 */
149
150#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
151
152#include <linux/hardirq.h>
153#include <linux/interrupt.h>
154#include <linux/module.h>
155#include <linux/moduleparam.h>
156#include <linux/kernel.h>
157#include <linux/types.h>
158#include <linux/sched.h>
159#include <linux/slab.h>
160#include <linux/delay.h>
161#include <linux/init.h>
162#include <linux/pci.h>
163#include <linux/dma-mapping.h>
164#include <linux/dmapool.h>
165#include <linux/netdevice.h>
166#include <linux/etherdevice.h>
167#include <linux/mii.h>
168#include <linux/if_vlan.h>
169#include <linux/skbuff.h>
170#include <linux/ethtool.h>
171#include <linux/string.h>
172#include <linux/firmware.h>
173#include <linux/rtnetlink.h>
174#include <asm/unaligned.h>
175
176
177#define DRV_NAME "e100"
178#define DRV_EXT "-NAPI"
179#define DRV_VERSION "3.5.24-k2"DRV_EXT
180#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
181#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
182
183#define E100_WATCHDOG_PERIOD (2 * HZ)
184#define E100_NAPI_WEIGHT 16
185
186#define FIRMWARE_D101M "e100/d101m_ucode.bin"
187#define FIRMWARE_D101S "e100/d101s_ucode.bin"
188#define FIRMWARE_D102E "e100/d102e_ucode.bin"
189
190MODULE_DESCRIPTION(DRV_DESCRIPTION);
191MODULE_AUTHOR(DRV_COPYRIGHT);
192MODULE_LICENSE("GPL");
193MODULE_VERSION(DRV_VERSION);
194MODULE_FIRMWARE(FIRMWARE_D101M);
195MODULE_FIRMWARE(FIRMWARE_D101S);
196MODULE_FIRMWARE(FIRMWARE_D102E);
197
198static int debug = 3;
199static int eeprom_bad_csum_allow = 0;
200static int use_io = 0;
201module_param(debug, int, 0);
202module_param(eeprom_bad_csum_allow, int, 0);
203module_param(use_io, int, 0);
204MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
205MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
206MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
207
208#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
209 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
210 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
211static DEFINE_PCI_DEVICE_TABLE(e100_id_table) = {
212 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
213 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
218 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
219 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
224 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
225 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
232 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
233 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
234 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
240 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
241 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
242 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
245 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
246 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
247 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
248 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
249 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
250 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
251 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
252 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
253 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
254 { 0, }
255};
256MODULE_DEVICE_TABLE(pci, e100_id_table);
257
258enum mac {
259 mac_82557_D100_A = 0,
260 mac_82557_D100_B = 1,
261 mac_82557_D100_C = 2,
262 mac_82558_D101_A4 = 4,
263 mac_82558_D101_B0 = 5,
264 mac_82559_D101M = 8,
265 mac_82559_D101S = 9,
266 mac_82550_D102 = 12,
267 mac_82550_D102_C = 13,
268 mac_82551_E = 14,
269 mac_82551_F = 15,
270 mac_82551_10 = 16,
271 mac_unknown = 0xFF,
272};
273
274enum phy {
275 phy_100a = 0x000003E0,
276 phy_100c = 0x035002A8,
277 phy_82555_tx = 0x015002A8,
278 phy_nsc_tx = 0x5C002000,
279 phy_82562_et = 0x033002A8,
280 phy_82562_em = 0x032002A8,
281 phy_82562_ek = 0x031002A8,
282 phy_82562_eh = 0x017002A8,
283 phy_82552_v = 0xd061004d,
284 phy_unknown = 0xFFFFFFFF,
285};
286
287/* CSR (Control/Status Registers) */
288struct csr {
289 struct {
290 u8 status;
291 u8 stat_ack;
292 u8 cmd_lo;
293 u8 cmd_hi;
294 u32 gen_ptr;
295 } scb;
296 u32 port;
297 u16 flash_ctrl;
298 u8 eeprom_ctrl_lo;
299 u8 eeprom_ctrl_hi;
300 u32 mdi_ctrl;
301 u32 rx_dma_count;
302};
303
304enum scb_status {
305 rus_no_res = 0x08,
306 rus_ready = 0x10,
307 rus_mask = 0x3C,
308};
309
310enum ru_state {
311 RU_SUSPENDED = 0,
312 RU_RUNNING = 1,
313 RU_UNINITIALIZED = -1,
314};
315
316enum scb_stat_ack {
317 stat_ack_not_ours = 0x00,
318 stat_ack_sw_gen = 0x04,
319 stat_ack_rnr = 0x10,
320 stat_ack_cu_idle = 0x20,
321 stat_ack_frame_rx = 0x40,
322 stat_ack_cu_cmd_done = 0x80,
323 stat_ack_not_present = 0xFF,
324 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
325 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
326};
327
328enum scb_cmd_hi {
329 irq_mask_none = 0x00,
330 irq_mask_all = 0x01,
331 irq_sw_gen = 0x02,
332};
333
334enum scb_cmd_lo {
335 cuc_nop = 0x00,
336 ruc_start = 0x01,
337 ruc_load_base = 0x06,
338 cuc_start = 0x10,
339 cuc_resume = 0x20,
340 cuc_dump_addr = 0x40,
341 cuc_dump_stats = 0x50,
342 cuc_load_base = 0x60,
343 cuc_dump_reset = 0x70,
344};
345
346enum cuc_dump {
347 cuc_dump_complete = 0x0000A005,
348 cuc_dump_reset_complete = 0x0000A007,
349};
350
351enum port {
352 software_reset = 0x0000,
353 selftest = 0x0001,
354 selective_reset = 0x0002,
355};
356
357enum eeprom_ctrl_lo {
358 eesk = 0x01,
359 eecs = 0x02,
360 eedi = 0x04,
361 eedo = 0x08,
362};
363
364enum mdi_ctrl {
365 mdi_write = 0x04000000,
366 mdi_read = 0x08000000,
367 mdi_ready = 0x10000000,
368};
369
370enum eeprom_op {
371 op_write = 0x05,
372 op_read = 0x06,
373 op_ewds = 0x10,
374 op_ewen = 0x13,
375};
376
377enum eeprom_offsets {
378 eeprom_cnfg_mdix = 0x03,
379 eeprom_phy_iface = 0x06,
380 eeprom_id = 0x0A,
381 eeprom_config_asf = 0x0D,
382 eeprom_smbus_addr = 0x90,
383};
384
385enum eeprom_cnfg_mdix {
386 eeprom_mdix_enabled = 0x0080,
387};
388
389enum eeprom_phy_iface {
390 NoSuchPhy = 0,
391 I82553AB,
392 I82553C,
393 I82503,
394 DP83840,
395 S80C240,
396 S80C24,
397 I82555,
398 DP83840A = 10,
399};
400
401enum eeprom_id {
402 eeprom_id_wol = 0x0020,
403};
404
405enum eeprom_config_asf {
406 eeprom_asf = 0x8000,
407 eeprom_gcl = 0x4000,
408};
409
410enum cb_status {
411 cb_complete = 0x8000,
412 cb_ok = 0x2000,
413};
414
415/**
416 * cb_command - Command Block flags
417 * @cb_tx_nc: 0: controler does CRC (normal), 1: CRC from skb memory
418 */
419enum cb_command {
420 cb_nop = 0x0000,
421 cb_iaaddr = 0x0001,
422 cb_config = 0x0002,
423 cb_multi = 0x0003,
424 cb_tx = 0x0004,
425 cb_ucode = 0x0005,
426 cb_dump = 0x0006,
427 cb_tx_sf = 0x0008,
428 cb_tx_nc = 0x0010,
429 cb_cid = 0x1f00,
430 cb_i = 0x2000,
431 cb_s = 0x4000,
432 cb_el = 0x8000,
433};
434
435struct rfd {
436 __le16 status;
437 __le16 command;
438 __le32 link;
439 __le32 rbd;
440 __le16 actual_size;
441 __le16 size;
442};
443
444struct rx {
445 struct rx *next, *prev;
446 struct sk_buff *skb;
447 dma_addr_t dma_addr;
448};
449
450#if defined(__BIG_ENDIAN_BITFIELD)
451#define X(a,b) b,a
452#else
453#define X(a,b) a,b
454#endif
455struct config {
456/*0*/ u8 X(byte_count:6, pad0:2);
457/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
458/*2*/ u8 adaptive_ifs;
459/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
460 term_write_cache_line:1), pad3:4);
461/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
462/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
463/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
464 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
465 rx_save_overruns : 1), rx_save_bad_frames : 1);
466/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
467 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
468 tx_dynamic_tbd:1);
469/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
470/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
471 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
472/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
473 loopback:2);
474/*11*/ u8 X(linear_priority:3, pad11:5);
475/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
476/*13*/ u8 ip_addr_lo;
477/*14*/ u8 ip_addr_hi;
478/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
479 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
480 pad15_2:1), crs_or_cdt:1);
481/*16*/ u8 fc_delay_lo;
482/*17*/ u8 fc_delay_hi;
483/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
484 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
485/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
486 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
487 full_duplex_force:1), full_duplex_pin:1);
488/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
489/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
490/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
491 u8 pad_d102[9];
492};
493
494#define E100_MAX_MULTICAST_ADDRS 64
495struct multi {
496 __le16 count;
497 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
498};
499
500/* Important: keep total struct u32-aligned */
501#define UCODE_SIZE 134
502struct cb {
503 __le16 status;
504 __le16 command;
505 __le32 link;
506 union {
507 u8 iaaddr[ETH_ALEN];
508 __le32 ucode[UCODE_SIZE];
509 struct config config;
510 struct multi multi;
511 struct {
512 u32 tbd_array;
513 u16 tcb_byte_count;
514 u8 threshold;
515 u8 tbd_count;
516 struct {
517 __le32 buf_addr;
518 __le16 size;
519 u16 eol;
520 } tbd;
521 } tcb;
522 __le32 dump_buffer_addr;
523 } u;
524 struct cb *next, *prev;
525 dma_addr_t dma_addr;
526 struct sk_buff *skb;
527};
528
529enum loopback {
530 lb_none = 0, lb_mac = 1, lb_phy = 3,
531};
532
533struct stats {
534 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
535 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
536 tx_multiple_collisions, tx_total_collisions;
537 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
538 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
539 rx_short_frame_errors;
540 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
541 __le16 xmt_tco_frames, rcv_tco_frames;
542 __le32 complete;
543};
544
545struct mem {
546 struct {
547 u32 signature;
548 u32 result;
549 } selftest;
550 struct stats stats;
551 u8 dump_buf[596];
552};
553
554struct param_range {
555 u32 min;
556 u32 max;
557 u32 count;
558};
559
560struct params {
561 struct param_range rfds;
562 struct param_range cbs;
563};
564
565struct nic {
566 /* Begin: frequently used values: keep adjacent for cache effect */
567 u32 msg_enable ____cacheline_aligned;
568 struct net_device *netdev;
569 struct pci_dev *pdev;
570 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
571
572 struct rx *rxs ____cacheline_aligned;
573 struct rx *rx_to_use;
574 struct rx *rx_to_clean;
575 struct rfd blank_rfd;
576 enum ru_state ru_running;
577
578 spinlock_t cb_lock ____cacheline_aligned;
579 spinlock_t cmd_lock;
580 struct csr __iomem *csr;
581 enum scb_cmd_lo cuc_cmd;
582 unsigned int cbs_avail;
583 struct napi_struct napi;
584 struct cb *cbs;
585 struct cb *cb_to_use;
586 struct cb *cb_to_send;
587 struct cb *cb_to_clean;
588 __le16 tx_command;
589 /* End: frequently used values: keep adjacent for cache effect */
590
591 enum {
592 ich = (1 << 0),
593 promiscuous = (1 << 1),
594 multicast_all = (1 << 2),
595 wol_magic = (1 << 3),
596 ich_10h_workaround = (1 << 4),
597 } flags ____cacheline_aligned;
598
599 enum mac mac;
600 enum phy phy;
601 struct params params;
602 struct timer_list watchdog;
603 struct mii_if_info mii;
604 struct work_struct tx_timeout_task;
605 enum loopback loopback;
606
607 struct mem *mem;
608 dma_addr_t dma_addr;
609
610 struct pci_pool *cbs_pool;
611 dma_addr_t cbs_dma_addr;
612 u8 adaptive_ifs;
613 u8 tx_threshold;
614 u32 tx_frames;
615 u32 tx_collisions;
616 u32 tx_deferred;
617 u32 tx_single_collisions;
618 u32 tx_multiple_collisions;
619 u32 tx_fc_pause;
620 u32 tx_tco_frames;
621
622 u32 rx_fc_pause;
623 u32 rx_fc_unsupported;
624 u32 rx_tco_frames;
625 u32 rx_short_frame_errors;
626 u32 rx_over_length_errors;
627
628 u16 eeprom_wc;
629 __le16 eeprom[256];
630 spinlock_t mdio_lock;
631 const struct firmware *fw;
632};
633
634static inline void e100_write_flush(struct nic *nic)
635{
636 /* Flush previous PCI writes through intermediate bridges
637 * by doing a benign read */
638 (void)ioread8(&nic->csr->scb.status);
639}
640
641static void e100_enable_irq(struct nic *nic)
642{
643 unsigned long flags;
644
645 spin_lock_irqsave(&nic->cmd_lock, flags);
646 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
647 e100_write_flush(nic);
648 spin_unlock_irqrestore(&nic->cmd_lock, flags);
649}
650
651static void e100_disable_irq(struct nic *nic)
652{
653 unsigned long flags;
654
655 spin_lock_irqsave(&nic->cmd_lock, flags);
656 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
657 e100_write_flush(nic);
658 spin_unlock_irqrestore(&nic->cmd_lock, flags);
659}
660
661static void e100_hw_reset(struct nic *nic)
662{
663 /* Put CU and RU into idle with a selective reset to get
664 * device off of PCI bus */
665 iowrite32(selective_reset, &nic->csr->port);
666 e100_write_flush(nic); udelay(20);
667
668 /* Now fully reset device */
669 iowrite32(software_reset, &nic->csr->port);
670 e100_write_flush(nic); udelay(20);
671
672 /* Mask off our interrupt line - it's unmasked after reset */
673 e100_disable_irq(nic);
674}
675
676static int e100_self_test(struct nic *nic)
677{
678 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
679
680 /* Passing the self-test is a pretty good indication
681 * that the device can DMA to/from host memory */
682
683 nic->mem->selftest.signature = 0;
684 nic->mem->selftest.result = 0xFFFFFFFF;
685
686 iowrite32(selftest | dma_addr, &nic->csr->port);
687 e100_write_flush(nic);
688 /* Wait 10 msec for self-test to complete */
689 msleep(10);
690
691 /* Interrupts are enabled after self-test */
692 e100_disable_irq(nic);
693
694 /* Check results of self-test */
695 if (nic->mem->selftest.result != 0) {
696 netif_err(nic, hw, nic->netdev,
697 "Self-test failed: result=0x%08X\n",
698 nic->mem->selftest.result);
699 return -ETIMEDOUT;
700 }
701 if (nic->mem->selftest.signature == 0) {
702 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n");
703 return -ETIMEDOUT;
704 }
705
706 return 0;
707}
708
709static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
710{
711 u32 cmd_addr_data[3];
712 u8 ctrl;
713 int i, j;
714
715 /* Three cmds: write/erase enable, write data, write/erase disable */
716 cmd_addr_data[0] = op_ewen << (addr_len - 2);
717 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
718 le16_to_cpu(data);
719 cmd_addr_data[2] = op_ewds << (addr_len - 2);
720
721 /* Bit-bang cmds to write word to eeprom */
722 for (j = 0; j < 3; j++) {
723
724 /* Chip select */
725 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
726 e100_write_flush(nic); udelay(4);
727
728 for (i = 31; i >= 0; i--) {
729 ctrl = (cmd_addr_data[j] & (1 << i)) ?
730 eecs | eedi : eecs;
731 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
732 e100_write_flush(nic); udelay(4);
733
734 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
735 e100_write_flush(nic); udelay(4);
736 }
737 /* Wait 10 msec for cmd to complete */
738 msleep(10);
739
740 /* Chip deselect */
741 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
742 e100_write_flush(nic); udelay(4);
743 }
744};
745
746/* General technique stolen from the eepro100 driver - very clever */
747static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
748{
749 u32 cmd_addr_data;
750 u16 data = 0;
751 u8 ctrl;
752 int i;
753
754 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
755
756 /* Chip select */
757 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
758 e100_write_flush(nic); udelay(4);
759
760 /* Bit-bang to read word from eeprom */
761 for (i = 31; i >= 0; i--) {
762 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
763 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
764 e100_write_flush(nic); udelay(4);
765
766 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
767 e100_write_flush(nic); udelay(4);
768
769 /* Eeprom drives a dummy zero to EEDO after receiving
770 * complete address. Use this to adjust addr_len. */
771 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
772 if (!(ctrl & eedo) && i > 16) {
773 *addr_len -= (i - 16);
774 i = 17;
775 }
776
777 data = (data << 1) | (ctrl & eedo ? 1 : 0);
778 }
779
780 /* Chip deselect */
781 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
782 e100_write_flush(nic); udelay(4);
783
784 return cpu_to_le16(data);
785};
786
787/* Load entire EEPROM image into driver cache and validate checksum */
788static int e100_eeprom_load(struct nic *nic)
789{
790 u16 addr, addr_len = 8, checksum = 0;
791
792 /* Try reading with an 8-bit addr len to discover actual addr len */
793 e100_eeprom_read(nic, &addr_len, 0);
794 nic->eeprom_wc = 1 << addr_len;
795
796 for (addr = 0; addr < nic->eeprom_wc; addr++) {
797 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
798 if (addr < nic->eeprom_wc - 1)
799 checksum += le16_to_cpu(nic->eeprom[addr]);
800 }
801
802 /* The checksum, stored in the last word, is calculated such that
803 * the sum of words should be 0xBABA */
804 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
805 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n");
806 if (!eeprom_bad_csum_allow)
807 return -EAGAIN;
808 }
809
810 return 0;
811}
812
813/* Save (portion of) driver EEPROM cache to device and update checksum */
814static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
815{
816 u16 addr, addr_len = 8, checksum = 0;
817
818 /* Try reading with an 8-bit addr len to discover actual addr len */
819 e100_eeprom_read(nic, &addr_len, 0);
820 nic->eeprom_wc = 1 << addr_len;
821
822 if (start + count >= nic->eeprom_wc)
823 return -EINVAL;
824
825 for (addr = start; addr < start + count; addr++)
826 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
827
828 /* The checksum, stored in the last word, is calculated such that
829 * the sum of words should be 0xBABA */
830 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
831 checksum += le16_to_cpu(nic->eeprom[addr]);
832 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
833 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
834 nic->eeprom[nic->eeprom_wc - 1]);
835
836 return 0;
837}
838
839#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
840#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
841static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
842{
843 unsigned long flags;
844 unsigned int i;
845 int err = 0;
846
847 spin_lock_irqsave(&nic->cmd_lock, flags);
848
849 /* Previous command is accepted when SCB clears */
850 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
851 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
852 break;
853 cpu_relax();
854 if (unlikely(i > E100_WAIT_SCB_FAST))
855 udelay(5);
856 }
857 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
858 err = -EAGAIN;
859 goto err_unlock;
860 }
861
862 if (unlikely(cmd != cuc_resume))
863 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
864 iowrite8(cmd, &nic->csr->scb.cmd_lo);
865
866err_unlock:
867 spin_unlock_irqrestore(&nic->cmd_lock, flags);
868
869 return err;
870}
871
872static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
873 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
874{
875 struct cb *cb;
876 unsigned long flags;
877 int err = 0;
878
879 spin_lock_irqsave(&nic->cb_lock, flags);
880
881 if (unlikely(!nic->cbs_avail)) {
882 err = -ENOMEM;
883 goto err_unlock;
884 }
885
886 cb = nic->cb_to_use;
887 nic->cb_to_use = cb->next;
888 nic->cbs_avail--;
889 cb->skb = skb;
890
891 if (unlikely(!nic->cbs_avail))
892 err = -ENOSPC;
893
894 cb_prepare(nic, cb, skb);
895
896 /* Order is important otherwise we'll be in a race with h/w:
897 * set S-bit in current first, then clear S-bit in previous. */
898 cb->command |= cpu_to_le16(cb_s);
899 wmb();
900 cb->prev->command &= cpu_to_le16(~cb_s);
901
902 while (nic->cb_to_send != nic->cb_to_use) {
903 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
904 nic->cb_to_send->dma_addr))) {
905 /* Ok, here's where things get sticky. It's
906 * possible that we can't schedule the command
907 * because the controller is too busy, so
908 * let's just queue the command and try again
909 * when another command is scheduled. */
910 if (err == -ENOSPC) {
911 //request a reset
912 schedule_work(&nic->tx_timeout_task);
913 }
914 break;
915 } else {
916 nic->cuc_cmd = cuc_resume;
917 nic->cb_to_send = nic->cb_to_send->next;
918 }
919 }
920
921err_unlock:
922 spin_unlock_irqrestore(&nic->cb_lock, flags);
923
924 return err;
925}
926
927static int mdio_read(struct net_device *netdev, int addr, int reg)
928{
929 struct nic *nic = netdev_priv(netdev);
930 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
931}
932
933static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
934{
935 struct nic *nic = netdev_priv(netdev);
936
937 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
938}
939
940/* the standard mdio_ctrl() function for usual MII-compliant hardware */
941static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
942{
943 u32 data_out = 0;
944 unsigned int i;
945 unsigned long flags;
946
947
948 /*
949 * Stratus87247: we shouldn't be writing the MDI control
950 * register until the Ready bit shows True. Also, since
951 * manipulation of the MDI control registers is a multi-step
952 * procedure it should be done under lock.
953 */
954 spin_lock_irqsave(&nic->mdio_lock, flags);
955 for (i = 100; i; --i) {
956 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
957 break;
958 udelay(20);
959 }
960 if (unlikely(!i)) {
961 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n");
962 spin_unlock_irqrestore(&nic->mdio_lock, flags);
963 return 0; /* No way to indicate timeout error */
964 }
965 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
966
967 for (i = 0; i < 100; i++) {
968 udelay(20);
969 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
970 break;
971 }
972 spin_unlock_irqrestore(&nic->mdio_lock, flags);
973 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
974 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
975 dir == mdi_read ? "READ" : "WRITE",
976 addr, reg, data, data_out);
977 return (u16)data_out;
978}
979
980/* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
981static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
982 u32 addr,
983 u32 dir,
984 u32 reg,
985 u16 data)
986{
987 if ((reg == MII_BMCR) && (dir == mdi_write)) {
988 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
989 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
990 MII_ADVERTISE);
991
992 /*
993 * Workaround Si issue where sometimes the part will not
994 * autoneg to 100Mbps even when advertised.
995 */
996 if (advert & ADVERTISE_100FULL)
997 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
998 else if (advert & ADVERTISE_100HALF)
999 data |= BMCR_SPEED100;
1000 }
1001 }
1002 return mdio_ctrl_hw(nic, addr, dir, reg, data);
1003}
1004
1005/* Fully software-emulated mdio_ctrl() function for cards without
1006 * MII-compliant PHYs.
1007 * For now, this is mainly geared towards 80c24 support; in case of further
1008 * requirements for other types (i82503, ...?) either extend this mechanism
1009 * or split it, whichever is cleaner.
1010 */
1011static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1012 u32 addr,
1013 u32 dir,
1014 u32 reg,
1015 u16 data)
1016{
1017 /* might need to allocate a netdev_priv'ed register array eventually
1018 * to be able to record state changes, but for now
1019 * some fully hardcoded register handling ought to be ok I guess. */
1020
1021 if (dir == mdi_read) {
1022 switch (reg) {
1023 case MII_BMCR:
1024 /* Auto-negotiation, right? */
1025 return BMCR_ANENABLE |
1026 BMCR_FULLDPLX;
1027 case MII_BMSR:
1028 return BMSR_LSTATUS /* for mii_link_ok() */ |
1029 BMSR_ANEGCAPABLE |
1030 BMSR_10FULL;
1031 case MII_ADVERTISE:
1032 /* 80c24 is a "combo card" PHY, right? */
1033 return ADVERTISE_10HALF |
1034 ADVERTISE_10FULL;
1035 default:
1036 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1037 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1038 dir == mdi_read ? "READ" : "WRITE",
1039 addr, reg, data);
1040 return 0xFFFF;
1041 }
1042 } else {
1043 switch (reg) {
1044 default:
1045 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1046 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1047 dir == mdi_read ? "READ" : "WRITE",
1048 addr, reg, data);
1049 return 0xFFFF;
1050 }
1051 }
1052}
1053static inline int e100_phy_supports_mii(struct nic *nic)
1054{
1055 /* for now, just check it by comparing whether we
1056 are using MII software emulation.
1057 */
1058 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1059}
1060
1061static void e100_get_defaults(struct nic *nic)
1062{
1063 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1064 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1065
1066 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1067 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1068 if (nic->mac == mac_unknown)
1069 nic->mac = mac_82557_D100_A;
1070
1071 nic->params.rfds = rfds;
1072 nic->params.cbs = cbs;
1073
1074 /* Quadwords to DMA into FIFO before starting frame transmit */
1075 nic->tx_threshold = 0xE0;
1076
1077 /* no interrupt for every tx completion, delay = 256us if not 557 */
1078 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1079 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1080
1081 /* Template for a freshly allocated RFD */
1082 nic->blank_rfd.command = 0;
1083 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1084 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN);
1085
1086 /* MII setup */
1087 nic->mii.phy_id_mask = 0x1F;
1088 nic->mii.reg_num_mask = 0x1F;
1089 nic->mii.dev = nic->netdev;
1090 nic->mii.mdio_read = mdio_read;
1091 nic->mii.mdio_write = mdio_write;
1092}
1093
1094static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1095{
1096 struct config *config = &cb->u.config;
1097 u8 *c = (u8 *)config;
1098 struct net_device *netdev = nic->netdev;
1099
1100 cb->command = cpu_to_le16(cb_config);
1101
1102 memset(config, 0, sizeof(struct config));
1103
1104 config->byte_count = 0x16; /* bytes in this struct */
1105 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1106 config->direct_rx_dma = 0x1; /* reserved */
1107 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1108 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1109 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1110 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1111 if (e100_phy_supports_mii(nic))
1112 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1113 config->pad10 = 0x6;
1114 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1115 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1116 config->ifs = 0x6; /* x16 = inter frame spacing */
1117 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1118 config->pad15_1 = 0x1;
1119 config->pad15_2 = 0x1;
1120 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1121 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1122 config->tx_padding = 0x1; /* 1=pad short frames */
1123 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1124 config->pad18 = 0x1;
1125 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1126 config->pad20_1 = 0x1F;
1127 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1128 config->pad21_1 = 0x5;
1129
1130 config->adaptive_ifs = nic->adaptive_ifs;
1131 config->loopback = nic->loopback;
1132
1133 if (nic->mii.force_media && nic->mii.full_duplex)
1134 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1135
1136 if (nic->flags & promiscuous || nic->loopback) {
1137 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1138 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1139 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1140 }
1141
1142 if (unlikely(netdev->features & NETIF_F_RXFCS))
1143 config->rx_crc_transfer = 0x1; /* 1=save, 0=discard */
1144
1145 if (nic->flags & multicast_all)
1146 config->multicast_all = 0x1; /* 1=accept, 0=no */
1147
1148 /* disable WoL when up */
1149 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1150 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1151
1152 if (nic->mac >= mac_82558_D101_A4) {
1153 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1154 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1155 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1156 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1157 if (nic->mac >= mac_82559_D101M) {
1158 config->tno_intr = 0x1; /* TCO stats enable */
1159 /* Enable TCO in extended config */
1160 if (nic->mac >= mac_82551_10) {
1161 config->byte_count = 0x20; /* extended bytes */
1162 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1163 }
1164 } else {
1165 config->standard_stat_counter = 0x0;
1166 }
1167 }
1168
1169 if (netdev->features & NETIF_F_RXALL) {
1170 config->rx_save_overruns = 0x1; /* 1=save, 0=discard */
1171 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1172 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1173 }
1174
1175 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1176 "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1177 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1178 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1179 "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1180 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1181 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1182 "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1183 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1184}
1185
1186/*************************************************************************
1187* CPUSaver parameters
1188*
1189* All CPUSaver parameters are 16-bit literals that are part of a
1190* "move immediate value" instruction. By changing the value of
1191* the literal in the instruction before the code is loaded, the
1192* driver can change the algorithm.
1193*
1194* INTDELAY - This loads the dead-man timer with its initial value.
1195* When this timer expires the interrupt is asserted, and the
1196* timer is reset each time a new packet is received. (see
1197* BUNDLEMAX below to set the limit on number of chained packets)
1198* The current default is 0x600 or 1536. Experiments show that
1199* the value should probably stay within the 0x200 - 0x1000.
1200*
1201* BUNDLEMAX -
1202* This sets the maximum number of frames that will be bundled. In
1203* some situations, such as the TCP windowing algorithm, it may be
1204* better to limit the growth of the bundle size than let it go as
1205* high as it can, because that could cause too much added latency.
1206* The default is six, because this is the number of packets in the
1207* default TCP window size. A value of 1 would make CPUSaver indicate
1208* an interrupt for every frame received. If you do not want to put
1209* a limit on the bundle size, set this value to xFFFF.
1210*
1211* BUNDLESMALL -
1212* This contains a bit-mask describing the minimum size frame that
1213* will be bundled. The default masks the lower 7 bits, which means
1214* that any frame less than 128 bytes in length will not be bundled,
1215* but will instead immediately generate an interrupt. This does
1216* not affect the current bundle in any way. Any frame that is 128
1217* bytes or large will be bundled normally. This feature is meant
1218* to provide immediate indication of ACK frames in a TCP environment.
1219* Customers were seeing poor performance when a machine with CPUSaver
1220* enabled was sending but not receiving. The delay introduced when
1221* the ACKs were received was enough to reduce total throughput, because
1222* the sender would sit idle until the ACK was finally seen.
1223*
1224* The current default is 0xFF80, which masks out the lower 7 bits.
1225* This means that any frame which is x7F (127) bytes or smaller
1226* will cause an immediate interrupt. Because this value must be a
1227* bit mask, there are only a few valid values that can be used. To
1228* turn this feature off, the driver can write the value xFFFF to the
1229* lower word of this instruction (in the same way that the other
1230* parameters are used). Likewise, a value of 0xF800 (2047) would
1231* cause an interrupt to be generated for every frame, because all
1232* standard Ethernet frames are <= 2047 bytes in length.
1233*************************************************************************/
1234
1235/* if you wish to disable the ucode functionality, while maintaining the
1236 * workarounds it provides, set the following defines to:
1237 * BUNDLESMALL 0
1238 * BUNDLEMAX 1
1239 * INTDELAY 1
1240 */
1241#define BUNDLESMALL 1
1242#define BUNDLEMAX (u16)6
1243#define INTDELAY (u16)1536 /* 0x600 */
1244
1245/* Initialize firmware */
1246static const struct firmware *e100_request_firmware(struct nic *nic)
1247{
1248 const char *fw_name;
1249 const struct firmware *fw = nic->fw;
1250 u8 timer, bundle, min_size;
1251 int err = 0;
1252
1253 /* do not load u-code for ICH devices */
1254 if (nic->flags & ich)
1255 return NULL;
1256
1257 /* Search for ucode match against h/w revision */
1258 if (nic->mac == mac_82559_D101M)
1259 fw_name = FIRMWARE_D101M;
1260 else if (nic->mac == mac_82559_D101S)
1261 fw_name = FIRMWARE_D101S;
1262 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1263 fw_name = FIRMWARE_D102E;
1264 else /* No ucode on other devices */
1265 return NULL;
1266
1267 /* If the firmware has not previously been loaded, request a pointer
1268 * to it. If it was previously loaded, we are reinitializing the
1269 * adapter, possibly in a resume from hibernate, in which case
1270 * request_firmware() cannot be used.
1271 */
1272 if (!fw)
1273 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1274
1275 if (err) {
1276 netif_err(nic, probe, nic->netdev,
1277 "Failed to load firmware \"%s\": %d\n",
1278 fw_name, err);
1279 return ERR_PTR(err);
1280 }
1281
1282 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1283 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1284 if (fw->size != UCODE_SIZE * 4 + 3) {
1285 netif_err(nic, probe, nic->netdev,
1286 "Firmware \"%s\" has wrong size %zu\n",
1287 fw_name, fw->size);
1288 release_firmware(fw);
1289 return ERR_PTR(-EINVAL);
1290 }
1291
1292 /* Read timer, bundle and min_size from end of firmware blob */
1293 timer = fw->data[UCODE_SIZE * 4];
1294 bundle = fw->data[UCODE_SIZE * 4 + 1];
1295 min_size = fw->data[UCODE_SIZE * 4 + 2];
1296
1297 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1298 min_size >= UCODE_SIZE) {
1299 netif_err(nic, probe, nic->netdev,
1300 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1301 fw_name, timer, bundle, min_size);
1302 release_firmware(fw);
1303 return ERR_PTR(-EINVAL);
1304 }
1305
1306 /* OK, firmware is validated and ready to use. Save a pointer
1307 * to it in the nic */
1308 nic->fw = fw;
1309 return fw;
1310}
1311
1312static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1313 struct sk_buff *skb)
1314{
1315 const struct firmware *fw = (void *)skb;
1316 u8 timer, bundle, min_size;
1317
1318 /* It's not a real skb; we just abused the fact that e100_exec_cb
1319 will pass it through to here... */
1320 cb->skb = NULL;
1321
1322 /* firmware is stored as little endian already */
1323 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1324
1325 /* Read timer, bundle and min_size from end of firmware blob */
1326 timer = fw->data[UCODE_SIZE * 4];
1327 bundle = fw->data[UCODE_SIZE * 4 + 1];
1328 min_size = fw->data[UCODE_SIZE * 4 + 2];
1329
1330 /* Insert user-tunable settings in cb->u.ucode */
1331 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1332 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1333 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1334 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1335 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1336 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1337
1338 cb->command = cpu_to_le16(cb_ucode | cb_el);
1339}
1340
1341static inline int e100_load_ucode_wait(struct nic *nic)
1342{
1343 const struct firmware *fw;
1344 int err = 0, counter = 50;
1345 struct cb *cb = nic->cb_to_clean;
1346
1347 fw = e100_request_firmware(nic);
1348 /* If it's NULL, then no ucode is required */
1349 if (!fw || IS_ERR(fw))
1350 return PTR_ERR(fw);
1351
1352 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1353 netif_err(nic, probe, nic->netdev,
1354 "ucode cmd failed with error %d\n", err);
1355
1356 /* must restart cuc */
1357 nic->cuc_cmd = cuc_start;
1358
1359 /* wait for completion */
1360 e100_write_flush(nic);
1361 udelay(10);
1362
1363 /* wait for possibly (ouch) 500ms */
1364 while (!(cb->status & cpu_to_le16(cb_complete))) {
1365 msleep(10);
1366 if (!--counter) break;
1367 }
1368
1369 /* ack any interrupts, something could have been set */
1370 iowrite8(~0, &nic->csr->scb.stat_ack);
1371
1372 /* if the command failed, or is not OK, notify and return */
1373 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1374 netif_err(nic, probe, nic->netdev, "ucode load failed\n");
1375 err = -EPERM;
1376 }
1377
1378 return err;
1379}
1380
1381static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1382 struct sk_buff *skb)
1383{
1384 cb->command = cpu_to_le16(cb_iaaddr);
1385 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1386}
1387
1388static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1389{
1390 cb->command = cpu_to_le16(cb_dump);
1391 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1392 offsetof(struct mem, dump_buf));
1393}
1394
1395static int e100_phy_check_without_mii(struct nic *nic)
1396{
1397 u8 phy_type;
1398 int without_mii;
1399
1400 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1401
1402 switch (phy_type) {
1403 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1404 case I82503: /* Non-MII PHY; UNTESTED! */
1405 case S80C24: /* Non-MII PHY; tested and working */
1406 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1407 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1408 * doesn't have a programming interface of any sort. The
1409 * media is sensed automatically based on how the link partner
1410 * is configured. This is, in essence, manual configuration.
1411 */
1412 netif_info(nic, probe, nic->netdev,
1413 "found MII-less i82503 or 80c24 or other PHY\n");
1414
1415 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1416 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1417
1418 /* these might be needed for certain MII-less cards...
1419 * nic->flags |= ich;
1420 * nic->flags |= ich_10h_workaround; */
1421
1422 without_mii = 1;
1423 break;
1424 default:
1425 without_mii = 0;
1426 break;
1427 }
1428 return without_mii;
1429}
1430
1431#define NCONFIG_AUTO_SWITCH 0x0080
1432#define MII_NSC_CONG MII_RESV1
1433#define NSC_CONG_ENABLE 0x0100
1434#define NSC_CONG_TXREADY 0x0400
1435#define ADVERTISE_FC_SUPPORTED 0x0400
1436static int e100_phy_init(struct nic *nic)
1437{
1438 struct net_device *netdev = nic->netdev;
1439 u32 addr;
1440 u16 bmcr, stat, id_lo, id_hi, cong;
1441
1442 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1443 for (addr = 0; addr < 32; addr++) {
1444 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1445 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1446 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1447 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1448 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1449 break;
1450 }
1451 if (addr == 32) {
1452 /* uhoh, no PHY detected: check whether we seem to be some
1453 * weird, rare variant which is *known* to not have any MII.
1454 * But do this AFTER MII checking only, since this does
1455 * lookup of EEPROM values which may easily be unreliable. */
1456 if (e100_phy_check_without_mii(nic))
1457 return 0; /* simply return and hope for the best */
1458 else {
1459 /* for unknown cases log a fatal error */
1460 netif_err(nic, hw, nic->netdev,
1461 "Failed to locate any known PHY, aborting\n");
1462 return -EAGAIN;
1463 }
1464 } else
1465 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1466 "phy_addr = %d\n", nic->mii.phy_id);
1467
1468 /* Get phy ID */
1469 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1470 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1471 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1472 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1473 "phy ID = 0x%08X\n", nic->phy);
1474
1475 /* Select the phy and isolate the rest */
1476 for (addr = 0; addr < 32; addr++) {
1477 if (addr != nic->mii.phy_id) {
1478 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1479 } else if (nic->phy != phy_82552_v) {
1480 bmcr = mdio_read(netdev, addr, MII_BMCR);
1481 mdio_write(netdev, addr, MII_BMCR,
1482 bmcr & ~BMCR_ISOLATE);
1483 }
1484 }
1485 /*
1486 * Workaround for 82552:
1487 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1488 * other phy_id's) using bmcr value from addr discovery loop above.
1489 */
1490 if (nic->phy == phy_82552_v)
1491 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1492 bmcr & ~BMCR_ISOLATE);
1493
1494 /* Handle National tx phys */
1495#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1496 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1497 /* Disable congestion control */
1498 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1499 cong |= NSC_CONG_TXREADY;
1500 cong &= ~NSC_CONG_ENABLE;
1501 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1502 }
1503
1504 if (nic->phy == phy_82552_v) {
1505 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1506
1507 /* assign special tweaked mdio_ctrl() function */
1508 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1509
1510 /* Workaround Si not advertising flow-control during autoneg */
1511 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1512 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1513
1514 /* Reset for the above changes to take effect */
1515 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1516 bmcr |= BMCR_RESET;
1517 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1518 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1519 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1520 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1521 /* enable/disable MDI/MDI-X auto-switching. */
1522 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1523 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1524 }
1525
1526 return 0;
1527}
1528
1529static int e100_hw_init(struct nic *nic)
1530{
1531 int err = 0;
1532
1533 e100_hw_reset(nic);
1534
1535 netif_err(nic, hw, nic->netdev, "e100_hw_init\n");
1536 if (!in_interrupt() && (err = e100_self_test(nic)))
1537 return err;
1538
1539 if ((err = e100_phy_init(nic)))
1540 return err;
1541 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1542 return err;
1543 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1544 return err;
1545 if ((err = e100_load_ucode_wait(nic)))
1546 return err;
1547 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1548 return err;
1549 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1550 return err;
1551 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1552 nic->dma_addr + offsetof(struct mem, stats))))
1553 return err;
1554 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1555 return err;
1556
1557 e100_disable_irq(nic);
1558
1559 return 0;
1560}
1561
1562static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1563{
1564 struct net_device *netdev = nic->netdev;
1565 struct netdev_hw_addr *ha;
1566 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1567
1568 cb->command = cpu_to_le16(cb_multi);
1569 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1570 i = 0;
1571 netdev_for_each_mc_addr(ha, netdev) {
1572 if (i == count)
1573 break;
1574 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr,
1575 ETH_ALEN);
1576 }
1577}
1578
1579static void e100_set_multicast_list(struct net_device *netdev)
1580{
1581 struct nic *nic = netdev_priv(netdev);
1582
1583 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1584 "mc_count=%d, flags=0x%04X\n",
1585 netdev_mc_count(netdev), netdev->flags);
1586
1587 if (netdev->flags & IFF_PROMISC)
1588 nic->flags |= promiscuous;
1589 else
1590 nic->flags &= ~promiscuous;
1591
1592 if (netdev->flags & IFF_ALLMULTI ||
1593 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1594 nic->flags |= multicast_all;
1595 else
1596 nic->flags &= ~multicast_all;
1597
1598 e100_exec_cb(nic, NULL, e100_configure);
1599 e100_exec_cb(nic, NULL, e100_multi);
1600}
1601
1602static void e100_update_stats(struct nic *nic)
1603{
1604 struct net_device *dev = nic->netdev;
1605 struct net_device_stats *ns = &dev->stats;
1606 struct stats *s = &nic->mem->stats;
1607 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1608 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1609 &s->complete;
1610
1611 /* Device's stats reporting may take several microseconds to
1612 * complete, so we're always waiting for results of the
1613 * previous command. */
1614
1615 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1616 *complete = 0;
1617 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1618 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1619 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1620 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1621 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1622 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1623 ns->collisions += nic->tx_collisions;
1624 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1625 le32_to_cpu(s->tx_lost_crs);
1626 nic->rx_short_frame_errors +=
1627 le32_to_cpu(s->rx_short_frame_errors);
1628 ns->rx_length_errors = nic->rx_short_frame_errors +
1629 nic->rx_over_length_errors;
1630 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1631 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1632 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1633 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1634 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1635 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1636 le32_to_cpu(s->rx_alignment_errors) +
1637 le32_to_cpu(s->rx_short_frame_errors) +
1638 le32_to_cpu(s->rx_cdt_errors);
1639 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1640 nic->tx_single_collisions +=
1641 le32_to_cpu(s->tx_single_collisions);
1642 nic->tx_multiple_collisions +=
1643 le32_to_cpu(s->tx_multiple_collisions);
1644 if (nic->mac >= mac_82558_D101_A4) {
1645 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1646 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1647 nic->rx_fc_unsupported +=
1648 le32_to_cpu(s->fc_rcv_unsupported);
1649 if (nic->mac >= mac_82559_D101M) {
1650 nic->tx_tco_frames +=
1651 le16_to_cpu(s->xmt_tco_frames);
1652 nic->rx_tco_frames +=
1653 le16_to_cpu(s->rcv_tco_frames);
1654 }
1655 }
1656 }
1657
1658
1659 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1660 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1661 "exec cuc_dump_reset failed\n");
1662}
1663
1664static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1665{
1666 /* Adjust inter-frame-spacing (IFS) between two transmits if
1667 * we're getting collisions on a half-duplex connection. */
1668
1669 if (duplex == DUPLEX_HALF) {
1670 u32 prev = nic->adaptive_ifs;
1671 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1672
1673 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1674 (nic->tx_frames > min_frames)) {
1675 if (nic->adaptive_ifs < 60)
1676 nic->adaptive_ifs += 5;
1677 } else if (nic->tx_frames < min_frames) {
1678 if (nic->adaptive_ifs >= 5)
1679 nic->adaptive_ifs -= 5;
1680 }
1681 if (nic->adaptive_ifs != prev)
1682 e100_exec_cb(nic, NULL, e100_configure);
1683 }
1684}
1685
1686static void e100_watchdog(unsigned long data)
1687{
1688 struct nic *nic = (struct nic *)data;
1689 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1690 u32 speed;
1691
1692 netif_printk(nic, timer, KERN_DEBUG, nic->netdev,
1693 "right now = %ld\n", jiffies);
1694
1695 /* mii library handles link maintenance tasks */
1696
1697 mii_ethtool_gset(&nic->mii, &cmd);
1698 speed = ethtool_cmd_speed(&cmd);
1699
1700 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1701 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n",
1702 speed == SPEED_100 ? 100 : 10,
1703 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1704 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1705 netdev_info(nic->netdev, "NIC Link is Down\n");
1706 }
1707
1708 mii_check_link(&nic->mii);
1709
1710 /* Software generated interrupt to recover from (rare) Rx
1711 * allocation failure.
1712 * Unfortunately have to use a spinlock to not re-enable interrupts
1713 * accidentally, due to hardware that shares a register between the
1714 * interrupt mask bit and the SW Interrupt generation bit */
1715 spin_lock_irq(&nic->cmd_lock);
1716 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1717 e100_write_flush(nic);
1718 spin_unlock_irq(&nic->cmd_lock);
1719
1720 e100_update_stats(nic);
1721 e100_adjust_adaptive_ifs(nic, speed, cmd.duplex);
1722
1723 if (nic->mac <= mac_82557_D100_C)
1724 /* Issue a multicast command to workaround a 557 lock up */
1725 e100_set_multicast_list(nic->netdev);
1726
1727 if (nic->flags & ich && speed == SPEED_10 && cmd.duplex == DUPLEX_HALF)
1728 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1729 nic->flags |= ich_10h_workaround;
1730 else
1731 nic->flags &= ~ich_10h_workaround;
1732
1733 mod_timer(&nic->watchdog,
1734 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1735}
1736
1737static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1738 struct sk_buff *skb)
1739{
1740 cb->command = nic->tx_command;
1741
1742 /*
1743 * Use the last 4 bytes of the SKB payload packet as the CRC, used for
1744 * testing, ie sending frames with bad CRC.
1745 */
1746 if (unlikely(skb->no_fcs))
1747 cb->command |= __constant_cpu_to_le16(cb_tx_nc);
1748 else
1749 cb->command &= ~__constant_cpu_to_le16(cb_tx_nc);
1750
1751 /* interrupt every 16 packets regardless of delay */
1752 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1753 cb->command |= cpu_to_le16(cb_i);
1754 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1755 cb->u.tcb.tcb_byte_count = 0;
1756 cb->u.tcb.threshold = nic->tx_threshold;
1757 cb->u.tcb.tbd_count = 1;
1758 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1759 skb->data, skb->len, PCI_DMA_TODEVICE));
1760 /* check for mapping failure? */
1761 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1762 skb_tx_timestamp(skb);
1763}
1764
1765static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1766 struct net_device *netdev)
1767{
1768 struct nic *nic = netdev_priv(netdev);
1769 int err;
1770
1771 if (nic->flags & ich_10h_workaround) {
1772 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1773 Issue a NOP command followed by a 1us delay before
1774 issuing the Tx command. */
1775 if (e100_exec_cmd(nic, cuc_nop, 0))
1776 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1777 "exec cuc_nop failed\n");
1778 udelay(1);
1779 }
1780
1781 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1782
1783 switch (err) {
1784 case -ENOSPC:
1785 /* We queued the skb, but now we're out of space. */
1786 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1787 "No space for CB\n");
1788 netif_stop_queue(netdev);
1789 break;
1790 case -ENOMEM:
1791 /* This is a hard error - log it. */
1792 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1793 "Out of Tx resources, returning skb\n");
1794 netif_stop_queue(netdev);
1795 return NETDEV_TX_BUSY;
1796 }
1797
1798 return NETDEV_TX_OK;
1799}
1800
1801static int e100_tx_clean(struct nic *nic)
1802{
1803 struct net_device *dev = nic->netdev;
1804 struct cb *cb;
1805 int tx_cleaned = 0;
1806
1807 spin_lock(&nic->cb_lock);
1808
1809 /* Clean CBs marked complete */
1810 for (cb = nic->cb_to_clean;
1811 cb->status & cpu_to_le16(cb_complete);
1812 cb = nic->cb_to_clean = cb->next) {
1813 rmb(); /* read skb after status */
1814 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev,
1815 "cb[%d]->status = 0x%04X\n",
1816 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1817 cb->status);
1818
1819 if (likely(cb->skb != NULL)) {
1820 dev->stats.tx_packets++;
1821 dev->stats.tx_bytes += cb->skb->len;
1822
1823 pci_unmap_single(nic->pdev,
1824 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1825 le16_to_cpu(cb->u.tcb.tbd.size),
1826 PCI_DMA_TODEVICE);
1827 dev_kfree_skb_any(cb->skb);
1828 cb->skb = NULL;
1829 tx_cleaned = 1;
1830 }
1831 cb->status = 0;
1832 nic->cbs_avail++;
1833 }
1834
1835 spin_unlock(&nic->cb_lock);
1836
1837 /* Recover from running out of Tx resources in xmit_frame */
1838 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1839 netif_wake_queue(nic->netdev);
1840
1841 return tx_cleaned;
1842}
1843
1844static void e100_clean_cbs(struct nic *nic)
1845{
1846 if (nic->cbs) {
1847 while (nic->cbs_avail != nic->params.cbs.count) {
1848 struct cb *cb = nic->cb_to_clean;
1849 if (cb->skb) {
1850 pci_unmap_single(nic->pdev,
1851 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1852 le16_to_cpu(cb->u.tcb.tbd.size),
1853 PCI_DMA_TODEVICE);
1854 dev_kfree_skb(cb->skb);
1855 }
1856 nic->cb_to_clean = nic->cb_to_clean->next;
1857 nic->cbs_avail++;
1858 }
1859 pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1860 nic->cbs = NULL;
1861 nic->cbs_avail = 0;
1862 }
1863 nic->cuc_cmd = cuc_start;
1864 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1865 nic->cbs;
1866}
1867
1868static int e100_alloc_cbs(struct nic *nic)
1869{
1870 struct cb *cb;
1871 unsigned int i, count = nic->params.cbs.count;
1872
1873 nic->cuc_cmd = cuc_start;
1874 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1875 nic->cbs_avail = 0;
1876
1877 nic->cbs = pci_pool_alloc(nic->cbs_pool, GFP_KERNEL,
1878 &nic->cbs_dma_addr);
1879 if (!nic->cbs)
1880 return -ENOMEM;
1881 memset(nic->cbs, 0, count * sizeof(struct cb));
1882
1883 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1884 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1885 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1886
1887 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1888 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1889 ((i+1) % count) * sizeof(struct cb));
1890 }
1891
1892 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1893 nic->cbs_avail = count;
1894
1895 return 0;
1896}
1897
1898static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1899{
1900 if (!nic->rxs) return;
1901 if (RU_SUSPENDED != nic->ru_running) return;
1902
1903 /* handle init time starts */
1904 if (!rx) rx = nic->rxs;
1905
1906 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1907 if (rx->skb) {
1908 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1909 nic->ru_running = RU_RUNNING;
1910 }
1911}
1912
1913#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
1914static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1915{
1916 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1917 return -ENOMEM;
1918
1919 /* Init, and map the RFD. */
1920 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1921 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1922 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1923
1924 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1925 dev_kfree_skb_any(rx->skb);
1926 rx->skb = NULL;
1927 rx->dma_addr = 0;
1928 return -ENOMEM;
1929 }
1930
1931 /* Link the RFD to end of RFA by linking previous RFD to
1932 * this one. We are safe to touch the previous RFD because
1933 * it is protected by the before last buffer's el bit being set */
1934 if (rx->prev->skb) {
1935 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1936 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1937 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1938 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1939 }
1940
1941 return 0;
1942}
1943
1944static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1945 unsigned int *work_done, unsigned int work_to_do)
1946{
1947 struct net_device *dev = nic->netdev;
1948 struct sk_buff *skb = rx->skb;
1949 struct rfd *rfd = (struct rfd *)skb->data;
1950 u16 rfd_status, actual_size;
1951 u16 fcs_pad = 0;
1952
1953 if (unlikely(work_done && *work_done >= work_to_do))
1954 return -EAGAIN;
1955
1956 /* Need to sync before taking a peek at cb_complete bit */
1957 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1958 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1959 rfd_status = le16_to_cpu(rfd->status);
1960
1961 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev,
1962 "status=0x%04X\n", rfd_status);
1963 rmb(); /* read size after status bit */
1964
1965 /* If data isn't ready, nothing to indicate */
1966 if (unlikely(!(rfd_status & cb_complete))) {
1967 /* If the next buffer has the el bit, but we think the receiver
1968 * is still running, check to see if it really stopped while
1969 * we had interrupts off.
1970 * This allows for a fast restart without re-enabling
1971 * interrupts */
1972 if ((le16_to_cpu(rfd->command) & cb_el) &&
1973 (RU_RUNNING == nic->ru_running))
1974
1975 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1976 nic->ru_running = RU_SUSPENDED;
1977 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1978 sizeof(struct rfd),
1979 PCI_DMA_FROMDEVICE);
1980 return -ENODATA;
1981 }
1982
1983 /* Get actual data size */
1984 if (unlikely(dev->features & NETIF_F_RXFCS))
1985 fcs_pad = 4;
1986 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1987 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1988 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1989
1990 /* Get data */
1991 pci_unmap_single(nic->pdev, rx->dma_addr,
1992 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1993
1994 /* If this buffer has the el bit, but we think the receiver
1995 * is still running, check to see if it really stopped while
1996 * we had interrupts off.
1997 * This allows for a fast restart without re-enabling interrupts.
1998 * This can happen when the RU sees the size change but also sees
1999 * the el bit set. */
2000 if ((le16_to_cpu(rfd->command) & cb_el) &&
2001 (RU_RUNNING == nic->ru_running)) {
2002
2003 if (ioread8(&nic->csr->scb.status) & rus_no_res)
2004 nic->ru_running = RU_SUSPENDED;
2005 }
2006
2007 /* Pull off the RFD and put the actual data (minus eth hdr) */
2008 skb_reserve(skb, sizeof(struct rfd));
2009 skb_put(skb, actual_size);
2010 skb->protocol = eth_type_trans(skb, nic->netdev);
2011
2012 /* If we are receiving all frames, then don't bother
2013 * checking for errors.
2014 */
2015 if (unlikely(dev->features & NETIF_F_RXALL)) {
2016 if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad)
2017 /* Received oversized frame, but keep it. */
2018 nic->rx_over_length_errors++;
2019 goto process_skb;
2020 }
2021
2022 if (unlikely(!(rfd_status & cb_ok))) {
2023 /* Don't indicate if hardware indicates errors */
2024 dev_kfree_skb_any(skb);
2025 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad) {
2026 /* Don't indicate oversized frames */
2027 nic->rx_over_length_errors++;
2028 dev_kfree_skb_any(skb);
2029 } else {
2030process_skb:
2031 dev->stats.rx_packets++;
2032 dev->stats.rx_bytes += (actual_size - fcs_pad);
2033 netif_receive_skb(skb);
2034 if (work_done)
2035 (*work_done)++;
2036 }
2037
2038 rx->skb = NULL;
2039
2040 return 0;
2041}
2042
2043static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
2044 unsigned int work_to_do)
2045{
2046 struct rx *rx;
2047 int restart_required = 0, err = 0;
2048 struct rx *old_before_last_rx, *new_before_last_rx;
2049 struct rfd *old_before_last_rfd, *new_before_last_rfd;
2050
2051 /* Indicate newly arrived packets */
2052 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
2053 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
2054 /* Hit quota or no more to clean */
2055 if (-EAGAIN == err || -ENODATA == err)
2056 break;
2057 }
2058
2059
2060 /* On EAGAIN, hit quota so have more work to do, restart once
2061 * cleanup is complete.
2062 * Else, are we already rnr? then pay attention!!! this ensures that
2063 * the state machine progression never allows a start with a
2064 * partially cleaned list, avoiding a race between hardware
2065 * and rx_to_clean when in NAPI mode */
2066 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2067 restart_required = 1;
2068
2069 old_before_last_rx = nic->rx_to_use->prev->prev;
2070 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
2071
2072 /* Alloc new skbs to refill list */
2073 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2074 if (unlikely(e100_rx_alloc_skb(nic, rx)))
2075 break; /* Better luck next time (see watchdog) */
2076 }
2077
2078 new_before_last_rx = nic->rx_to_use->prev->prev;
2079 if (new_before_last_rx != old_before_last_rx) {
2080 /* Set the el-bit on the buffer that is before the last buffer.
2081 * This lets us update the next pointer on the last buffer
2082 * without worrying about hardware touching it.
2083 * We set the size to 0 to prevent hardware from touching this
2084 * buffer.
2085 * When the hardware hits the before last buffer with el-bit
2086 * and size of 0, it will RNR interrupt, the RUS will go into
2087 * the No Resources state. It will not complete nor write to
2088 * this buffer. */
2089 new_before_last_rfd =
2090 (struct rfd *)new_before_last_rx->skb->data;
2091 new_before_last_rfd->size = 0;
2092 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2093 pci_dma_sync_single_for_device(nic->pdev,
2094 new_before_last_rx->dma_addr, sizeof(struct rfd),
2095 PCI_DMA_BIDIRECTIONAL);
2096
2097 /* Now that we have a new stopping point, we can clear the old
2098 * stopping point. We must sync twice to get the proper
2099 * ordering on the hardware side of things. */
2100 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2101 pci_dma_sync_single_for_device(nic->pdev,
2102 old_before_last_rx->dma_addr, sizeof(struct rfd),
2103 PCI_DMA_BIDIRECTIONAL);
2104 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN
2105 + ETH_FCS_LEN);
2106 pci_dma_sync_single_for_device(nic->pdev,
2107 old_before_last_rx->dma_addr, sizeof(struct rfd),
2108 PCI_DMA_BIDIRECTIONAL);
2109 }
2110
2111 if (restart_required) {
2112 // ack the rnr?
2113 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2114 e100_start_receiver(nic, nic->rx_to_clean);
2115 if (work_done)
2116 (*work_done)++;
2117 }
2118}
2119
2120static void e100_rx_clean_list(struct nic *nic)
2121{
2122 struct rx *rx;
2123 unsigned int i, count = nic->params.rfds.count;
2124
2125 nic->ru_running = RU_UNINITIALIZED;
2126
2127 if (nic->rxs) {
2128 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2129 if (rx->skb) {
2130 pci_unmap_single(nic->pdev, rx->dma_addr,
2131 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2132 dev_kfree_skb(rx->skb);
2133 }
2134 }
2135 kfree(nic->rxs);
2136 nic->rxs = NULL;
2137 }
2138
2139 nic->rx_to_use = nic->rx_to_clean = NULL;
2140}
2141
2142static int e100_rx_alloc_list(struct nic *nic)
2143{
2144 struct rx *rx;
2145 unsigned int i, count = nic->params.rfds.count;
2146 struct rfd *before_last;
2147
2148 nic->rx_to_use = nic->rx_to_clean = NULL;
2149 nic->ru_running = RU_UNINITIALIZED;
2150
2151 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2152 return -ENOMEM;
2153
2154 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2155 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2156 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2157 if (e100_rx_alloc_skb(nic, rx)) {
2158 e100_rx_clean_list(nic);
2159 return -ENOMEM;
2160 }
2161 }
2162 /* Set the el-bit on the buffer that is before the last buffer.
2163 * This lets us update the next pointer on the last buffer without
2164 * worrying about hardware touching it.
2165 * We set the size to 0 to prevent hardware from touching this buffer.
2166 * When the hardware hits the before last buffer with el-bit and size
2167 * of 0, it will RNR interrupt, the RU will go into the No Resources
2168 * state. It will not complete nor write to this buffer. */
2169 rx = nic->rxs->prev->prev;
2170 before_last = (struct rfd *)rx->skb->data;
2171 before_last->command |= cpu_to_le16(cb_el);
2172 before_last->size = 0;
2173 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2174 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2175
2176 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2177 nic->ru_running = RU_SUSPENDED;
2178
2179 return 0;
2180}
2181
2182static irqreturn_t e100_intr(int irq, void *dev_id)
2183{
2184 struct net_device *netdev = dev_id;
2185 struct nic *nic = netdev_priv(netdev);
2186 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2187
2188 netif_printk(nic, intr, KERN_DEBUG, nic->netdev,
2189 "stat_ack = 0x%02X\n", stat_ack);
2190
2191 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2192 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2193 return IRQ_NONE;
2194
2195 /* Ack interrupt(s) */
2196 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2197
2198 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2199 if (stat_ack & stat_ack_rnr)
2200 nic->ru_running = RU_SUSPENDED;
2201
2202 if (likely(napi_schedule_prep(&nic->napi))) {
2203 e100_disable_irq(nic);
2204 __napi_schedule(&nic->napi);
2205 }
2206
2207 return IRQ_HANDLED;
2208}
2209
2210static int e100_poll(struct napi_struct *napi, int budget)
2211{
2212 struct nic *nic = container_of(napi, struct nic, napi);
2213 unsigned int work_done = 0;
2214
2215 e100_rx_clean(nic, &work_done, budget);
2216 e100_tx_clean(nic);
2217
2218 /* If budget not fully consumed, exit the polling mode */
2219 if (work_done < budget) {
2220 napi_complete(napi);
2221 e100_enable_irq(nic);
2222 }
2223
2224 return work_done;
2225}
2226
2227#ifdef CONFIG_NET_POLL_CONTROLLER
2228static void e100_netpoll(struct net_device *netdev)
2229{
2230 struct nic *nic = netdev_priv(netdev);
2231
2232 e100_disable_irq(nic);
2233 e100_intr(nic->pdev->irq, netdev);
2234 e100_tx_clean(nic);
2235 e100_enable_irq(nic);
2236}
2237#endif
2238
2239static int e100_set_mac_address(struct net_device *netdev, void *p)
2240{
2241 struct nic *nic = netdev_priv(netdev);
2242 struct sockaddr *addr = p;
2243
2244 if (!is_valid_ether_addr(addr->sa_data))
2245 return -EADDRNOTAVAIL;
2246
2247 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2248 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2249
2250 return 0;
2251}
2252
2253static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2254{
2255 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2256 return -EINVAL;
2257 netdev->mtu = new_mtu;
2258 return 0;
2259}
2260
2261static int e100_asf(struct nic *nic)
2262{
2263 /* ASF can be enabled from eeprom */
2264 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2265 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2266 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2267 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE);
2268}
2269
2270static int e100_up(struct nic *nic)
2271{
2272 int err;
2273
2274 if ((err = e100_rx_alloc_list(nic)))
2275 return err;
2276 if ((err = e100_alloc_cbs(nic)))
2277 goto err_rx_clean_list;
2278 if ((err = e100_hw_init(nic)))
2279 goto err_clean_cbs;
2280 e100_set_multicast_list(nic->netdev);
2281 e100_start_receiver(nic, NULL);
2282 mod_timer(&nic->watchdog, jiffies);
2283 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2284 nic->netdev->name, nic->netdev)))
2285 goto err_no_irq;
2286 netif_wake_queue(nic->netdev);
2287 napi_enable(&nic->napi);
2288 /* enable ints _after_ enabling poll, preventing a race between
2289 * disable ints+schedule */
2290 e100_enable_irq(nic);
2291 return 0;
2292
2293err_no_irq:
2294 del_timer_sync(&nic->watchdog);
2295err_clean_cbs:
2296 e100_clean_cbs(nic);
2297err_rx_clean_list:
2298 e100_rx_clean_list(nic);
2299 return err;
2300}
2301
2302static void e100_down(struct nic *nic)
2303{
2304 /* wait here for poll to complete */
2305 napi_disable(&nic->napi);
2306 netif_stop_queue(nic->netdev);
2307 e100_hw_reset(nic);
2308 free_irq(nic->pdev->irq, nic->netdev);
2309 del_timer_sync(&nic->watchdog);
2310 netif_carrier_off(nic->netdev);
2311 e100_clean_cbs(nic);
2312 e100_rx_clean_list(nic);
2313}
2314
2315static void e100_tx_timeout(struct net_device *netdev)
2316{
2317 struct nic *nic = netdev_priv(netdev);
2318
2319 /* Reset outside of interrupt context, to avoid request_irq
2320 * in interrupt context */
2321 schedule_work(&nic->tx_timeout_task);
2322}
2323
2324static void e100_tx_timeout_task(struct work_struct *work)
2325{
2326 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2327 struct net_device *netdev = nic->netdev;
2328
2329 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
2330 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status));
2331
2332 rtnl_lock();
2333 if (netif_running(netdev)) {
2334 e100_down(netdev_priv(netdev));
2335 e100_up(netdev_priv(netdev));
2336 }
2337 rtnl_unlock();
2338}
2339
2340static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2341{
2342 int err;
2343 struct sk_buff *skb;
2344
2345 /* Use driver resources to perform internal MAC or PHY
2346 * loopback test. A single packet is prepared and transmitted
2347 * in loopback mode, and the test passes if the received
2348 * packet compares byte-for-byte to the transmitted packet. */
2349
2350 if ((err = e100_rx_alloc_list(nic)))
2351 return err;
2352 if ((err = e100_alloc_cbs(nic)))
2353 goto err_clean_rx;
2354
2355 /* ICH PHY loopback is broken so do MAC loopback instead */
2356 if (nic->flags & ich && loopback_mode == lb_phy)
2357 loopback_mode = lb_mac;
2358
2359 nic->loopback = loopback_mode;
2360 if ((err = e100_hw_init(nic)))
2361 goto err_loopback_none;
2362
2363 if (loopback_mode == lb_phy)
2364 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2365 BMCR_LOOPBACK);
2366
2367 e100_start_receiver(nic, NULL);
2368
2369 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2370 err = -ENOMEM;
2371 goto err_loopback_none;
2372 }
2373 skb_put(skb, ETH_DATA_LEN);
2374 memset(skb->data, 0xFF, ETH_DATA_LEN);
2375 e100_xmit_frame(skb, nic->netdev);
2376
2377 msleep(10);
2378
2379 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2380 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2381
2382 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2383 skb->data, ETH_DATA_LEN))
2384 err = -EAGAIN;
2385
2386err_loopback_none:
2387 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2388 nic->loopback = lb_none;
2389 e100_clean_cbs(nic);
2390 e100_hw_reset(nic);
2391err_clean_rx:
2392 e100_rx_clean_list(nic);
2393 return err;
2394}
2395
2396#define MII_LED_CONTROL 0x1B
2397#define E100_82552_LED_OVERRIDE 0x19
2398#define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2399#define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2400
2401static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2402{
2403 struct nic *nic = netdev_priv(netdev);
2404 return mii_ethtool_gset(&nic->mii, cmd);
2405}
2406
2407static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2408{
2409 struct nic *nic = netdev_priv(netdev);
2410 int err;
2411
2412 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2413 err = mii_ethtool_sset(&nic->mii, cmd);
2414 e100_exec_cb(nic, NULL, e100_configure);
2415
2416 return err;
2417}
2418
2419static void e100_get_drvinfo(struct net_device *netdev,
2420 struct ethtool_drvinfo *info)
2421{
2422 struct nic *nic = netdev_priv(netdev);
2423 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2424 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2425 strlcpy(info->bus_info, pci_name(nic->pdev),
2426 sizeof(info->bus_info));
2427}
2428
2429#define E100_PHY_REGS 0x1C
2430static int e100_get_regs_len(struct net_device *netdev)
2431{
2432 struct nic *nic = netdev_priv(netdev);
2433 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2434}
2435
2436static void e100_get_regs(struct net_device *netdev,
2437 struct ethtool_regs *regs, void *p)
2438{
2439 struct nic *nic = netdev_priv(netdev);
2440 u32 *buff = p;
2441 int i;
2442
2443 regs->version = (1 << 24) | nic->pdev->revision;
2444 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2445 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2446 ioread16(&nic->csr->scb.status);
2447 for (i = E100_PHY_REGS; i >= 0; i--)
2448 buff[1 + E100_PHY_REGS - i] =
2449 mdio_read(netdev, nic->mii.phy_id, i);
2450 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2451 e100_exec_cb(nic, NULL, e100_dump);
2452 msleep(10);
2453 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2454 sizeof(nic->mem->dump_buf));
2455}
2456
2457static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2458{
2459 struct nic *nic = netdev_priv(netdev);
2460 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2461 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2462}
2463
2464static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2465{
2466 struct nic *nic = netdev_priv(netdev);
2467
2468 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2469 !device_can_wakeup(&nic->pdev->dev))
2470 return -EOPNOTSUPP;
2471
2472 if (wol->wolopts)
2473 nic->flags |= wol_magic;
2474 else
2475 nic->flags &= ~wol_magic;
2476
2477 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2478
2479 e100_exec_cb(nic, NULL, e100_configure);
2480
2481 return 0;
2482}
2483
2484static u32 e100_get_msglevel(struct net_device *netdev)
2485{
2486 struct nic *nic = netdev_priv(netdev);
2487 return nic->msg_enable;
2488}
2489
2490static void e100_set_msglevel(struct net_device *netdev, u32 value)
2491{
2492 struct nic *nic = netdev_priv(netdev);
2493 nic->msg_enable = value;
2494}
2495
2496static int e100_nway_reset(struct net_device *netdev)
2497{
2498 struct nic *nic = netdev_priv(netdev);
2499 return mii_nway_restart(&nic->mii);
2500}
2501
2502static u32 e100_get_link(struct net_device *netdev)
2503{
2504 struct nic *nic = netdev_priv(netdev);
2505 return mii_link_ok(&nic->mii);
2506}
2507
2508static int e100_get_eeprom_len(struct net_device *netdev)
2509{
2510 struct nic *nic = netdev_priv(netdev);
2511 return nic->eeprom_wc << 1;
2512}
2513
2514#define E100_EEPROM_MAGIC 0x1234
2515static int e100_get_eeprom(struct net_device *netdev,
2516 struct ethtool_eeprom *eeprom, u8 *bytes)
2517{
2518 struct nic *nic = netdev_priv(netdev);
2519
2520 eeprom->magic = E100_EEPROM_MAGIC;
2521 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2522
2523 return 0;
2524}
2525
2526static int e100_set_eeprom(struct net_device *netdev,
2527 struct ethtool_eeprom *eeprom, u8 *bytes)
2528{
2529 struct nic *nic = netdev_priv(netdev);
2530
2531 if (eeprom->magic != E100_EEPROM_MAGIC)
2532 return -EINVAL;
2533
2534 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2535
2536 return e100_eeprom_save(nic, eeprom->offset >> 1,
2537 (eeprom->len >> 1) + 1);
2538}
2539
2540static void e100_get_ringparam(struct net_device *netdev,
2541 struct ethtool_ringparam *ring)
2542{
2543 struct nic *nic = netdev_priv(netdev);
2544 struct param_range *rfds = &nic->params.rfds;
2545 struct param_range *cbs = &nic->params.cbs;
2546
2547 ring->rx_max_pending = rfds->max;
2548 ring->tx_max_pending = cbs->max;
2549 ring->rx_pending = rfds->count;
2550 ring->tx_pending = cbs->count;
2551}
2552
2553static int e100_set_ringparam(struct net_device *netdev,
2554 struct ethtool_ringparam *ring)
2555{
2556 struct nic *nic = netdev_priv(netdev);
2557 struct param_range *rfds = &nic->params.rfds;
2558 struct param_range *cbs = &nic->params.cbs;
2559
2560 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2561 return -EINVAL;
2562
2563 if (netif_running(netdev))
2564 e100_down(nic);
2565 rfds->count = max(ring->rx_pending, rfds->min);
2566 rfds->count = min(rfds->count, rfds->max);
2567 cbs->count = max(ring->tx_pending, cbs->min);
2568 cbs->count = min(cbs->count, cbs->max);
2569 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n",
2570 rfds->count, cbs->count);
2571 if (netif_running(netdev))
2572 e100_up(nic);
2573
2574 return 0;
2575}
2576
2577static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2578 "Link test (on/offline)",
2579 "Eeprom test (on/offline)",
2580 "Self test (offline)",
2581 "Mac loopback (offline)",
2582 "Phy loopback (offline)",
2583};
2584#define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2585
2586static void e100_diag_test(struct net_device *netdev,
2587 struct ethtool_test *test, u64 *data)
2588{
2589 struct ethtool_cmd cmd;
2590 struct nic *nic = netdev_priv(netdev);
2591 int i, err;
2592
2593 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2594 data[0] = !mii_link_ok(&nic->mii);
2595 data[1] = e100_eeprom_load(nic);
2596 if (test->flags & ETH_TEST_FL_OFFLINE) {
2597
2598 /* save speed, duplex & autoneg settings */
2599 err = mii_ethtool_gset(&nic->mii, &cmd);
2600
2601 if (netif_running(netdev))
2602 e100_down(nic);
2603 data[2] = e100_self_test(nic);
2604 data[3] = e100_loopback_test(nic, lb_mac);
2605 data[4] = e100_loopback_test(nic, lb_phy);
2606
2607 /* restore speed, duplex & autoneg settings */
2608 err = mii_ethtool_sset(&nic->mii, &cmd);
2609
2610 if (netif_running(netdev))
2611 e100_up(nic);
2612 }
2613 for (i = 0; i < E100_TEST_LEN; i++)
2614 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2615
2616 msleep_interruptible(4 * 1000);
2617}
2618
2619static int e100_set_phys_id(struct net_device *netdev,
2620 enum ethtool_phys_id_state state)
2621{
2622 struct nic *nic = netdev_priv(netdev);
2623 enum led_state {
2624 led_on = 0x01,
2625 led_off = 0x04,
2626 led_on_559 = 0x05,
2627 led_on_557 = 0x07,
2628 };
2629 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2630 MII_LED_CONTROL;
2631 u16 leds = 0;
2632
2633 switch (state) {
2634 case ETHTOOL_ID_ACTIVE:
2635 return 2;
2636
2637 case ETHTOOL_ID_ON:
2638 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_ON :
2639 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2640 break;
2641
2642 case ETHTOOL_ID_OFF:
2643 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_OFF : led_off;
2644 break;
2645
2646 case ETHTOOL_ID_INACTIVE:
2647 break;
2648 }
2649
2650 mdio_write(netdev, nic->mii.phy_id, led_reg, leds);
2651 return 0;
2652}
2653
2654static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2655 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2656 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2657 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2658 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2659 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2660 "tx_heartbeat_errors", "tx_window_errors",
2661 /* device-specific stats */
2662 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2663 "tx_flow_control_pause", "rx_flow_control_pause",
2664 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2665 "rx_short_frame_errors", "rx_over_length_errors",
2666};
2667#define E100_NET_STATS_LEN 21
2668#define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2669
2670static int e100_get_sset_count(struct net_device *netdev, int sset)
2671{
2672 switch (sset) {
2673 case ETH_SS_TEST:
2674 return E100_TEST_LEN;
2675 case ETH_SS_STATS:
2676 return E100_STATS_LEN;
2677 default:
2678 return -EOPNOTSUPP;
2679 }
2680}
2681
2682static void e100_get_ethtool_stats(struct net_device *netdev,
2683 struct ethtool_stats *stats, u64 *data)
2684{
2685 struct nic *nic = netdev_priv(netdev);
2686 int i;
2687
2688 for (i = 0; i < E100_NET_STATS_LEN; i++)
2689 data[i] = ((unsigned long *)&netdev->stats)[i];
2690
2691 data[i++] = nic->tx_deferred;
2692 data[i++] = nic->tx_single_collisions;
2693 data[i++] = nic->tx_multiple_collisions;
2694 data[i++] = nic->tx_fc_pause;
2695 data[i++] = nic->rx_fc_pause;
2696 data[i++] = nic->rx_fc_unsupported;
2697 data[i++] = nic->tx_tco_frames;
2698 data[i++] = nic->rx_tco_frames;
2699 data[i++] = nic->rx_short_frame_errors;
2700 data[i++] = nic->rx_over_length_errors;
2701}
2702
2703static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2704{
2705 switch (stringset) {
2706 case ETH_SS_TEST:
2707 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2708 break;
2709 case ETH_SS_STATS:
2710 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2711 break;
2712 }
2713}
2714
2715static const struct ethtool_ops e100_ethtool_ops = {
2716 .get_settings = e100_get_settings,
2717 .set_settings = e100_set_settings,
2718 .get_drvinfo = e100_get_drvinfo,
2719 .get_regs_len = e100_get_regs_len,
2720 .get_regs = e100_get_regs,
2721 .get_wol = e100_get_wol,
2722 .set_wol = e100_set_wol,
2723 .get_msglevel = e100_get_msglevel,
2724 .set_msglevel = e100_set_msglevel,
2725 .nway_reset = e100_nway_reset,
2726 .get_link = e100_get_link,
2727 .get_eeprom_len = e100_get_eeprom_len,
2728 .get_eeprom = e100_get_eeprom,
2729 .set_eeprom = e100_set_eeprom,
2730 .get_ringparam = e100_get_ringparam,
2731 .set_ringparam = e100_set_ringparam,
2732 .self_test = e100_diag_test,
2733 .get_strings = e100_get_strings,
2734 .set_phys_id = e100_set_phys_id,
2735 .get_ethtool_stats = e100_get_ethtool_stats,
2736 .get_sset_count = e100_get_sset_count,
2737 .get_ts_info = ethtool_op_get_ts_info,
2738};
2739
2740static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2741{
2742 struct nic *nic = netdev_priv(netdev);
2743
2744 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2745}
2746
2747static int e100_alloc(struct nic *nic)
2748{
2749 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2750 &nic->dma_addr);
2751 return nic->mem ? 0 : -ENOMEM;
2752}
2753
2754static void e100_free(struct nic *nic)
2755{
2756 if (nic->mem) {
2757 pci_free_consistent(nic->pdev, sizeof(struct mem),
2758 nic->mem, nic->dma_addr);
2759 nic->mem = NULL;
2760 }
2761}
2762
2763static int e100_open(struct net_device *netdev)
2764{
2765 struct nic *nic = netdev_priv(netdev);
2766 int err = 0;
2767
2768 netif_carrier_off(netdev);
2769 if ((err = e100_up(nic)))
2770 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n");
2771 return err;
2772}
2773
2774static int e100_close(struct net_device *netdev)
2775{
2776 e100_down(netdev_priv(netdev));
2777 return 0;
2778}
2779
2780static int e100_set_features(struct net_device *netdev,
2781 netdev_features_t features)
2782{
2783 struct nic *nic = netdev_priv(netdev);
2784 netdev_features_t changed = features ^ netdev->features;
2785
2786 if (!(changed & (NETIF_F_RXFCS | NETIF_F_RXALL)))
2787 return 0;
2788
2789 netdev->features = features;
2790 e100_exec_cb(nic, NULL, e100_configure);
2791 return 0;
2792}
2793
2794static const struct net_device_ops e100_netdev_ops = {
2795 .ndo_open = e100_open,
2796 .ndo_stop = e100_close,
2797 .ndo_start_xmit = e100_xmit_frame,
2798 .ndo_validate_addr = eth_validate_addr,
2799 .ndo_set_rx_mode = e100_set_multicast_list,
2800 .ndo_set_mac_address = e100_set_mac_address,
2801 .ndo_change_mtu = e100_change_mtu,
2802 .ndo_do_ioctl = e100_do_ioctl,
2803 .ndo_tx_timeout = e100_tx_timeout,
2804#ifdef CONFIG_NET_POLL_CONTROLLER
2805 .ndo_poll_controller = e100_netpoll,
2806#endif
2807 .ndo_set_features = e100_set_features,
2808};
2809
2810static int __devinit e100_probe(struct pci_dev *pdev,
2811 const struct pci_device_id *ent)
2812{
2813 struct net_device *netdev;
2814 struct nic *nic;
2815 int err;
2816
2817 if (!(netdev = alloc_etherdev(sizeof(struct nic))))
2818 return -ENOMEM;
2819
2820 netdev->hw_features |= NETIF_F_RXFCS;
2821 netdev->priv_flags |= IFF_SUPP_NOFCS;
2822 netdev->hw_features |= NETIF_F_RXALL;
2823
2824 netdev->netdev_ops = &e100_netdev_ops;
2825 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2826 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2827 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2828
2829 nic = netdev_priv(netdev);
2830 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2831 nic->netdev = netdev;
2832 nic->pdev = pdev;
2833 nic->msg_enable = (1 << debug) - 1;
2834 nic->mdio_ctrl = mdio_ctrl_hw;
2835 pci_set_drvdata(pdev, netdev);
2836
2837 if ((err = pci_enable_device(pdev))) {
2838 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n");
2839 goto err_out_free_dev;
2840 }
2841
2842 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2843 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n");
2844 err = -ENODEV;
2845 goto err_out_disable_pdev;
2846 }
2847
2848 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2849 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n");
2850 goto err_out_disable_pdev;
2851 }
2852
2853 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2854 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n");
2855 goto err_out_free_res;
2856 }
2857
2858 SET_NETDEV_DEV(netdev, &pdev->dev);
2859
2860 if (use_io)
2861 netif_info(nic, probe, nic->netdev, "using i/o access mode\n");
2862
2863 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2864 if (!nic->csr) {
2865 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n");
2866 err = -ENOMEM;
2867 goto err_out_free_res;
2868 }
2869
2870 if (ent->driver_data)
2871 nic->flags |= ich;
2872 else
2873 nic->flags &= ~ich;
2874
2875 e100_get_defaults(nic);
2876
2877 /* D100 MAC doesn't allow rx of vlan packets with normal MTU */
2878 if (nic->mac < mac_82558_D101_A4)
2879 netdev->features |= NETIF_F_VLAN_CHALLENGED;
2880
2881 /* locks must be initialized before calling hw_reset */
2882 spin_lock_init(&nic->cb_lock);
2883 spin_lock_init(&nic->cmd_lock);
2884 spin_lock_init(&nic->mdio_lock);
2885
2886 /* Reset the device before pci_set_master() in case device is in some
2887 * funky state and has an interrupt pending - hint: we don't have the
2888 * interrupt handler registered yet. */
2889 e100_hw_reset(nic);
2890
2891 pci_set_master(pdev);
2892
2893 init_timer(&nic->watchdog);
2894 nic->watchdog.function = e100_watchdog;
2895 nic->watchdog.data = (unsigned long)nic;
2896
2897 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2898
2899 if ((err = e100_alloc(nic))) {
2900 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n");
2901 goto err_out_iounmap;
2902 }
2903
2904 if ((err = e100_eeprom_load(nic)))
2905 goto err_out_free;
2906
2907 e100_phy_init(nic);
2908
2909 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2910 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2911 if (!is_valid_ether_addr(netdev->perm_addr)) {
2912 if (!eeprom_bad_csum_allow) {
2913 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n");
2914 err = -EAGAIN;
2915 goto err_out_free;
2916 } else {
2917 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n");
2918 }
2919 }
2920
2921 /* Wol magic packet can be enabled from eeprom */
2922 if ((nic->mac >= mac_82558_D101_A4) &&
2923 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2924 nic->flags |= wol_magic;
2925 device_set_wakeup_enable(&pdev->dev, true);
2926 }
2927
2928 /* ack any pending wake events, disable PME */
2929 pci_pme_active(pdev, false);
2930
2931 strcpy(netdev->name, "eth%d");
2932 if ((err = register_netdev(netdev))) {
2933 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n");
2934 goto err_out_free;
2935 }
2936 nic->cbs_pool = pci_pool_create(netdev->name,
2937 nic->pdev,
2938 nic->params.cbs.max * sizeof(struct cb),
2939 sizeof(u32),
2940 0);
2941 netif_info(nic, probe, nic->netdev,
2942 "addr 0x%llx, irq %d, MAC addr %pM\n",
2943 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2944 pdev->irq, netdev->dev_addr);
2945
2946 return 0;
2947
2948err_out_free:
2949 e100_free(nic);
2950err_out_iounmap:
2951 pci_iounmap(pdev, nic->csr);
2952err_out_free_res:
2953 pci_release_regions(pdev);
2954err_out_disable_pdev:
2955 pci_disable_device(pdev);
2956err_out_free_dev:
2957 pci_set_drvdata(pdev, NULL);
2958 free_netdev(netdev);
2959 return err;
2960}
2961
2962static void __devexit e100_remove(struct pci_dev *pdev)
2963{
2964 struct net_device *netdev = pci_get_drvdata(pdev);
2965
2966 if (netdev) {
2967 struct nic *nic = netdev_priv(netdev);
2968 unregister_netdev(netdev);
2969 e100_free(nic);
2970 pci_iounmap(pdev, nic->csr);
2971 pci_pool_destroy(nic->cbs_pool);
2972 free_netdev(netdev);
2973 pci_release_regions(pdev);
2974 pci_disable_device(pdev);
2975 pci_set_drvdata(pdev, NULL);
2976 }
2977}
2978
2979#define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2980#define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2981#define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2982static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2983{
2984 struct net_device *netdev = pci_get_drvdata(pdev);
2985 struct nic *nic = netdev_priv(netdev);
2986
2987 if (netif_running(netdev))
2988 e100_down(nic);
2989 netif_device_detach(netdev);
2990
2991 pci_save_state(pdev);
2992
2993 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2994 /* enable reverse auto-negotiation */
2995 if (nic->phy == phy_82552_v) {
2996 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2997 E100_82552_SMARTSPEED);
2998
2999 mdio_write(netdev, nic->mii.phy_id,
3000 E100_82552_SMARTSPEED, smartspeed |
3001 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
3002 }
3003 *enable_wake = true;
3004 } else {
3005 *enable_wake = false;
3006 }
3007
3008 pci_disable_device(pdev);
3009}
3010
3011static int __e100_power_off(struct pci_dev *pdev, bool wake)
3012{
3013 if (wake)
3014 return pci_prepare_to_sleep(pdev);
3015
3016 pci_wake_from_d3(pdev, false);
3017 pci_set_power_state(pdev, PCI_D3hot);
3018
3019 return 0;
3020}
3021
3022#ifdef CONFIG_PM
3023static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
3024{
3025 bool wake;
3026 __e100_shutdown(pdev, &wake);
3027 return __e100_power_off(pdev, wake);
3028}
3029
3030static int e100_resume(struct pci_dev *pdev)
3031{
3032 struct net_device *netdev = pci_get_drvdata(pdev);
3033 struct nic *nic = netdev_priv(netdev);
3034
3035 pci_set_power_state(pdev, PCI_D0);
3036 pci_restore_state(pdev);
3037 /* ack any pending wake events, disable PME */
3038 pci_enable_wake(pdev, 0, 0);
3039
3040 /* disable reverse auto-negotiation */
3041 if (nic->phy == phy_82552_v) {
3042 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
3043 E100_82552_SMARTSPEED);
3044
3045 mdio_write(netdev, nic->mii.phy_id,
3046 E100_82552_SMARTSPEED,
3047 smartspeed & ~(E100_82552_REV_ANEG));
3048 }
3049
3050 netif_device_attach(netdev);
3051 if (netif_running(netdev))
3052 e100_up(nic);
3053
3054 return 0;
3055}
3056#endif /* CONFIG_PM */
3057
3058static void e100_shutdown(struct pci_dev *pdev)
3059{
3060 bool wake;
3061 __e100_shutdown(pdev, &wake);
3062 if (system_state == SYSTEM_POWER_OFF)
3063 __e100_power_off(pdev, wake);
3064}
3065
3066/* ------------------ PCI Error Recovery infrastructure -------------- */
3067/**
3068 * e100_io_error_detected - called when PCI error is detected.
3069 * @pdev: Pointer to PCI device
3070 * @state: The current pci connection state
3071 */
3072static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3073{
3074 struct net_device *netdev = pci_get_drvdata(pdev);
3075 struct nic *nic = netdev_priv(netdev);
3076
3077 netif_device_detach(netdev);
3078
3079 if (state == pci_channel_io_perm_failure)
3080 return PCI_ERS_RESULT_DISCONNECT;
3081
3082 if (netif_running(netdev))
3083 e100_down(nic);
3084 pci_disable_device(pdev);
3085
3086 /* Request a slot reset. */
3087 return PCI_ERS_RESULT_NEED_RESET;
3088}
3089
3090/**
3091 * e100_io_slot_reset - called after the pci bus has been reset.
3092 * @pdev: Pointer to PCI device
3093 *
3094 * Restart the card from scratch.
3095 */
3096static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3097{
3098 struct net_device *netdev = pci_get_drvdata(pdev);
3099 struct nic *nic = netdev_priv(netdev);
3100
3101 if (pci_enable_device(pdev)) {
3102 pr_err("Cannot re-enable PCI device after reset\n");
3103 return PCI_ERS_RESULT_DISCONNECT;
3104 }
3105 pci_set_master(pdev);
3106
3107 /* Only one device per card can do a reset */
3108 if (0 != PCI_FUNC(pdev->devfn))
3109 return PCI_ERS_RESULT_RECOVERED;
3110 e100_hw_reset(nic);
3111 e100_phy_init(nic);
3112
3113 return PCI_ERS_RESULT_RECOVERED;
3114}
3115
3116/**
3117 * e100_io_resume - resume normal operations
3118 * @pdev: Pointer to PCI device
3119 *
3120 * Resume normal operations after an error recovery
3121 * sequence has been completed.
3122 */
3123static void e100_io_resume(struct pci_dev *pdev)
3124{
3125 struct net_device *netdev = pci_get_drvdata(pdev);
3126 struct nic *nic = netdev_priv(netdev);
3127
3128 /* ack any pending wake events, disable PME */
3129 pci_enable_wake(pdev, 0, 0);
3130
3131 netif_device_attach(netdev);
3132 if (netif_running(netdev)) {
3133 e100_open(netdev);
3134 mod_timer(&nic->watchdog, jiffies);
3135 }
3136}
3137
3138static struct pci_error_handlers e100_err_handler = {
3139 .error_detected = e100_io_error_detected,
3140 .slot_reset = e100_io_slot_reset,
3141 .resume = e100_io_resume,
3142};
3143
3144static struct pci_driver e100_driver = {
3145 .name = DRV_NAME,
3146 .id_table = e100_id_table,
3147 .probe = e100_probe,
3148 .remove = __devexit_p(e100_remove),
3149#ifdef CONFIG_PM
3150 /* Power Management hooks */
3151 .suspend = e100_suspend,
3152 .resume = e100_resume,
3153#endif
3154 .shutdown = e100_shutdown,
3155 .err_handler = &e100_err_handler,
3156};
3157
3158static int __init e100_init_module(void)
3159{
3160 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3161 pr_info("%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3162 pr_info("%s\n", DRV_COPYRIGHT);
3163 }
3164 return pci_register_driver(&e100_driver);
3165}
3166
3167static void __exit e100_cleanup_module(void)
3168{
3169 pci_unregister_driver(&e100_driver);
3170}
3171
3172module_init(e100_init_module);
3173module_exit(e100_cleanup_module);