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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <dt-bindings/memory/tegra210-mc.h>
7
8#include "mc.h"
9
10static const struct tegra_mc_client tegra210_mc_clients[] = {
11 {
12 .id = 0x00,
13 .name = "ptcr",
14 .swgroup = TEGRA_SWGROUP_PTC,
15 }, {
16 .id = 0x01,
17 .name = "display0a",
18 .swgroup = TEGRA_SWGROUP_DC,
19 .smmu = {
20 .reg = 0x228,
21 .bit = 1,
22 },
23 .la = {
24 .reg = 0x2e8,
25 .shift = 0,
26 .mask = 0xff,
27 .def = 0xc2,
28 },
29 }, {
30 .id = 0x02,
31 .name = "display0ab",
32 .swgroup = TEGRA_SWGROUP_DCB,
33 .smmu = {
34 .reg = 0x228,
35 .bit = 2,
36 },
37 .la = {
38 .reg = 0x2f4,
39 .shift = 0,
40 .mask = 0xff,
41 .def = 0xc6,
42 },
43 }, {
44 .id = 0x03,
45 .name = "display0b",
46 .swgroup = TEGRA_SWGROUP_DC,
47 .smmu = {
48 .reg = 0x228,
49 .bit = 3,
50 },
51 .la = {
52 .reg = 0x2e8,
53 .shift = 16,
54 .mask = 0xff,
55 .def = 0x50,
56 },
57 }, {
58 .id = 0x04,
59 .name = "display0bb",
60 .swgroup = TEGRA_SWGROUP_DCB,
61 .smmu = {
62 .reg = 0x228,
63 .bit = 4,
64 },
65 .la = {
66 .reg = 0x2f4,
67 .shift = 16,
68 .mask = 0xff,
69 .def = 0x50,
70 },
71 }, {
72 .id = 0x05,
73 .name = "display0c",
74 .swgroup = TEGRA_SWGROUP_DC,
75 .smmu = {
76 .reg = 0x228,
77 .bit = 5,
78 },
79 .la = {
80 .reg = 0x2ec,
81 .shift = 0,
82 .mask = 0xff,
83 .def = 0x50,
84 },
85 }, {
86 .id = 0x06,
87 .name = "display0cb",
88 .swgroup = TEGRA_SWGROUP_DCB,
89 .smmu = {
90 .reg = 0x228,
91 .bit = 6,
92 },
93 .la = {
94 .reg = 0x2f8,
95 .shift = 0,
96 .mask = 0xff,
97 .def = 0x50,
98 },
99 }, {
100 .id = 0x0e,
101 .name = "afir",
102 .swgroup = TEGRA_SWGROUP_AFI,
103 .smmu = {
104 .reg = 0x228,
105 .bit = 14,
106 },
107 .la = {
108 .reg = 0x2e0,
109 .shift = 0,
110 .mask = 0xff,
111 .def = 0x13,
112 },
113 }, {
114 .id = 0x0f,
115 .name = "avpcarm7r",
116 .swgroup = TEGRA_SWGROUP_AVPC,
117 .smmu = {
118 .reg = 0x228,
119 .bit = 15,
120 },
121 .la = {
122 .reg = 0x2e4,
123 .shift = 0,
124 .mask = 0xff,
125 .def = 0x04,
126 },
127 }, {
128 .id = 0x10,
129 .name = "displayhc",
130 .swgroup = TEGRA_SWGROUP_DC,
131 .smmu = {
132 .reg = 0x228,
133 .bit = 16,
134 },
135 .la = {
136 .reg = 0x2f0,
137 .shift = 0,
138 .mask = 0xff,
139 .def = 0x50,
140 },
141 }, {
142 .id = 0x11,
143 .name = "displayhcb",
144 .swgroup = TEGRA_SWGROUP_DCB,
145 .smmu = {
146 .reg = 0x228,
147 .bit = 17,
148 },
149 .la = {
150 .reg = 0x2fc,
151 .shift = 0,
152 .mask = 0xff,
153 .def = 0x50,
154 },
155 }, {
156 .id = 0x15,
157 .name = "hdar",
158 .swgroup = TEGRA_SWGROUP_HDA,
159 .smmu = {
160 .reg = 0x228,
161 .bit = 21,
162 },
163 .la = {
164 .reg = 0x318,
165 .shift = 0,
166 .mask = 0xff,
167 .def = 0x24,
168 },
169 }, {
170 .id = 0x16,
171 .name = "host1xdmar",
172 .swgroup = TEGRA_SWGROUP_HC,
173 .smmu = {
174 .reg = 0x228,
175 .bit = 22,
176 },
177 .la = {
178 .reg = 0x310,
179 .shift = 0,
180 .mask = 0xff,
181 .def = 0x1e,
182 },
183 }, {
184 .id = 0x17,
185 .name = "host1xr",
186 .swgroup = TEGRA_SWGROUP_HC,
187 .smmu = {
188 .reg = 0x228,
189 .bit = 23,
190 },
191 .la = {
192 .reg = 0x310,
193 .shift = 16,
194 .mask = 0xff,
195 .def = 0x50,
196 },
197 }, {
198 .id = 0x1c,
199 .name = "nvencsrd",
200 .swgroup = TEGRA_SWGROUP_NVENC,
201 .smmu = {
202 .reg = 0x228,
203 .bit = 28,
204 },
205 .la = {
206 .reg = 0x328,
207 .shift = 0,
208 .mask = 0xff,
209 .def = 0x23,
210 },
211 }, {
212 .id = 0x1d,
213 .name = "ppcsahbdmar",
214 .swgroup = TEGRA_SWGROUP_PPCS,
215 .smmu = {
216 .reg = 0x228,
217 .bit = 29,
218 },
219 .la = {
220 .reg = 0x344,
221 .shift = 0,
222 .mask = 0xff,
223 .def = 0x49,
224 },
225 }, {
226 .id = 0x1e,
227 .name = "ppcsahbslvr",
228 .swgroup = TEGRA_SWGROUP_PPCS,
229 .smmu = {
230 .reg = 0x228,
231 .bit = 30,
232 },
233 .la = {
234 .reg = 0x344,
235 .shift = 16,
236 .mask = 0xff,
237 .def = 0x1a,
238 },
239 }, {
240 .id = 0x1f,
241 .name = "satar",
242 .swgroup = TEGRA_SWGROUP_SATA,
243 .smmu = {
244 .reg = 0x228,
245 .bit = 31,
246 },
247 .la = {
248 .reg = 0x350,
249 .shift = 0,
250 .mask = 0xff,
251 .def = 0x65,
252 },
253 }, {
254 .id = 0x27,
255 .name = "mpcorer",
256 .swgroup = TEGRA_SWGROUP_MPCORE,
257 .la = {
258 .reg = 0x320,
259 .shift = 0,
260 .mask = 0xff,
261 .def = 0x04,
262 },
263 }, {
264 .id = 0x2b,
265 .name = "nvencswr",
266 .swgroup = TEGRA_SWGROUP_NVENC,
267 .smmu = {
268 .reg = 0x22c,
269 .bit = 11,
270 },
271 .la = {
272 .reg = 0x328,
273 .shift = 16,
274 .mask = 0xff,
275 .def = 0x80,
276 },
277 }, {
278 .id = 0x31,
279 .name = "afiw",
280 .swgroup = TEGRA_SWGROUP_AFI,
281 .smmu = {
282 .reg = 0x22c,
283 .bit = 17,
284 },
285 .la = {
286 .reg = 0x2e0,
287 .shift = 16,
288 .mask = 0xff,
289 .def = 0x80,
290 },
291 }, {
292 .id = 0x32,
293 .name = "avpcarm7w",
294 .swgroup = TEGRA_SWGROUP_AVPC,
295 .smmu = {
296 .reg = 0x22c,
297 .bit = 18,
298 },
299 .la = {
300 .reg = 0x2e4,
301 .shift = 16,
302 .mask = 0xff,
303 .def = 0x80,
304 },
305 }, {
306 .id = 0x35,
307 .name = "hdaw",
308 .swgroup = TEGRA_SWGROUP_HDA,
309 .smmu = {
310 .reg = 0x22c,
311 .bit = 21,
312 },
313 .la = {
314 .reg = 0x318,
315 .shift = 16,
316 .mask = 0xff,
317 .def = 0x80,
318 },
319 }, {
320 .id = 0x36,
321 .name = "host1xw",
322 .swgroup = TEGRA_SWGROUP_HC,
323 .smmu = {
324 .reg = 0x22c,
325 .bit = 22,
326 },
327 .la = {
328 .reg = 0x314,
329 .shift = 0,
330 .mask = 0xff,
331 .def = 0x80,
332 },
333 }, {
334 .id = 0x39,
335 .name = "mpcorew",
336 .swgroup = TEGRA_SWGROUP_MPCORE,
337 .la = {
338 .reg = 0x320,
339 .shift = 16,
340 .mask = 0xff,
341 .def = 0x80,
342 },
343 }, {
344 .id = 0x3b,
345 .name = "ppcsahbdmaw",
346 .swgroup = TEGRA_SWGROUP_PPCS,
347 .smmu = {
348 .reg = 0x22c,
349 .bit = 27,
350 },
351 .la = {
352 .reg = 0x348,
353 .shift = 0,
354 .mask = 0xff,
355 .def = 0x80,
356 },
357 }, {
358 .id = 0x3c,
359 .name = "ppcsahbslvw",
360 .swgroup = TEGRA_SWGROUP_PPCS,
361 .smmu = {
362 .reg = 0x22c,
363 .bit = 28,
364 },
365 .la = {
366 .reg = 0x348,
367 .shift = 16,
368 .mask = 0xff,
369 .def = 0x80,
370 },
371 }, {
372 .id = 0x3d,
373 .name = "sataw",
374 .swgroup = TEGRA_SWGROUP_SATA,
375 .smmu = {
376 .reg = 0x22c,
377 .bit = 29,
378 },
379 .la = {
380 .reg = 0x350,
381 .shift = 16,
382 .mask = 0xff,
383 .def = 0x65,
384 },
385 }, {
386 .id = 0x44,
387 .name = "ispra",
388 .swgroup = TEGRA_SWGROUP_ISP2,
389 .smmu = {
390 .reg = 0x230,
391 .bit = 4,
392 },
393 .la = {
394 .reg = 0x370,
395 .shift = 0,
396 .mask = 0xff,
397 .def = 0x18,
398 },
399 }, {
400 .id = 0x46,
401 .name = "ispwa",
402 .swgroup = TEGRA_SWGROUP_ISP2,
403 .smmu = {
404 .reg = 0x230,
405 .bit = 6,
406 },
407 .la = {
408 .reg = 0x374,
409 .shift = 0,
410 .mask = 0xff,
411 .def = 0x80,
412 },
413 }, {
414 .id = 0x47,
415 .name = "ispwb",
416 .swgroup = TEGRA_SWGROUP_ISP2,
417 .smmu = {
418 .reg = 0x230,
419 .bit = 7,
420 },
421 .la = {
422 .reg = 0x374,
423 .shift = 16,
424 .mask = 0xff,
425 .def = 0x80,
426 },
427 }, {
428 .id = 0x4a,
429 .name = "xusb_hostr",
430 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
431 .smmu = {
432 .reg = 0x230,
433 .bit = 10,
434 },
435 .la = {
436 .reg = 0x37c,
437 .shift = 0,
438 .mask = 0xff,
439 .def = 0x39,
440 },
441 }, {
442 .id = 0x4b,
443 .name = "xusb_hostw",
444 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
445 .smmu = {
446 .reg = 0x230,
447 .bit = 11,
448 },
449 .la = {
450 .reg = 0x37c,
451 .shift = 16,
452 .mask = 0xff,
453 .def = 0x80,
454 },
455 }, {
456 .id = 0x4c,
457 .name = "xusb_devr",
458 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
459 .smmu = {
460 .reg = 0x230,
461 .bit = 12,
462 },
463 .la = {
464 .reg = 0x380,
465 .shift = 0,
466 .mask = 0xff,
467 .def = 0x39,
468 },
469 }, {
470 .id = 0x4d,
471 .name = "xusb_devw",
472 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
473 .smmu = {
474 .reg = 0x230,
475 .bit = 13,
476 },
477 .la = {
478 .reg = 0x380,
479 .shift = 16,
480 .mask = 0xff,
481 .def = 0x80,
482 },
483 }, {
484 .id = 0x4e,
485 .name = "isprab",
486 .swgroup = TEGRA_SWGROUP_ISP2B,
487 .smmu = {
488 .reg = 0x230,
489 .bit = 14,
490 },
491 .la = {
492 .reg = 0x384,
493 .shift = 0,
494 .mask = 0xff,
495 .def = 0x18,
496 },
497 }, {
498 .id = 0x50,
499 .name = "ispwab",
500 .swgroup = TEGRA_SWGROUP_ISP2B,
501 .smmu = {
502 .reg = 0x230,
503 .bit = 16,
504 },
505 .la = {
506 .reg = 0x388,
507 .shift = 0,
508 .mask = 0xff,
509 .def = 0x80,
510 },
511 }, {
512 .id = 0x51,
513 .name = "ispwbb",
514 .swgroup = TEGRA_SWGROUP_ISP2B,
515 .smmu = {
516 .reg = 0x230,
517 .bit = 17,
518 },
519 .la = {
520 .reg = 0x388,
521 .shift = 16,
522 .mask = 0xff,
523 .def = 0x80,
524 },
525 }, {
526 .id = 0x54,
527 .name = "tsecsrd",
528 .swgroup = TEGRA_SWGROUP_TSEC,
529 .smmu = {
530 .reg = 0x230,
531 .bit = 20,
532 },
533 .la = {
534 .reg = 0x390,
535 .shift = 0,
536 .mask = 0xff,
537 .def = 0x9b,
538 },
539 }, {
540 .id = 0x55,
541 .name = "tsecswr",
542 .swgroup = TEGRA_SWGROUP_TSEC,
543 .smmu = {
544 .reg = 0x230,
545 .bit = 21,
546 },
547 .la = {
548 .reg = 0x390,
549 .shift = 16,
550 .mask = 0xff,
551 .def = 0x80,
552 },
553 }, {
554 .id = 0x56,
555 .name = "a9avpscr",
556 .swgroup = TEGRA_SWGROUP_A9AVP,
557 .smmu = {
558 .reg = 0x230,
559 .bit = 22,
560 },
561 .la = {
562 .reg = 0x3a4,
563 .shift = 0,
564 .mask = 0xff,
565 .def = 0x04,
566 },
567 }, {
568 .id = 0x57,
569 .name = "a9avpscw",
570 .swgroup = TEGRA_SWGROUP_A9AVP,
571 .smmu = {
572 .reg = 0x230,
573 .bit = 23,
574 },
575 .la = {
576 .reg = 0x3a4,
577 .shift = 16,
578 .mask = 0xff,
579 .def = 0x80,
580 },
581 }, {
582 .id = 0x58,
583 .name = "gpusrd",
584 .swgroup = TEGRA_SWGROUP_GPU,
585 .smmu = {
586 /* read-only */
587 .reg = 0x230,
588 .bit = 24,
589 },
590 .la = {
591 .reg = 0x3c8,
592 .shift = 0,
593 .mask = 0xff,
594 .def = 0x1a,
595 },
596 }, {
597 .id = 0x59,
598 .name = "gpuswr",
599 .swgroup = TEGRA_SWGROUP_GPU,
600 .smmu = {
601 /* read-only */
602 .reg = 0x230,
603 .bit = 25,
604 },
605 .la = {
606 .reg = 0x3c8,
607 .shift = 16,
608 .mask = 0xff,
609 .def = 0x80,
610 },
611 }, {
612 .id = 0x5a,
613 .name = "displayt",
614 .swgroup = TEGRA_SWGROUP_DC,
615 .smmu = {
616 .reg = 0x230,
617 .bit = 26,
618 },
619 .la = {
620 .reg = 0x2f0,
621 .shift = 16,
622 .mask = 0xff,
623 .def = 0x50,
624 },
625 }, {
626 .id = 0x60,
627 .name = "sdmmcra",
628 .swgroup = TEGRA_SWGROUP_SDMMC1A,
629 .smmu = {
630 .reg = 0x234,
631 .bit = 0,
632 },
633 .la = {
634 .reg = 0x3b8,
635 .shift = 0,
636 .mask = 0xff,
637 .def = 0x49,
638 },
639 }, {
640 .id = 0x61,
641 .name = "sdmmcraa",
642 .swgroup = TEGRA_SWGROUP_SDMMC2A,
643 .smmu = {
644 .reg = 0x234,
645 .bit = 1,
646 },
647 .la = {
648 .reg = 0x3bc,
649 .shift = 0,
650 .mask = 0xff,
651 .def = 0x49,
652 },
653 }, {
654 .id = 0x62,
655 .name = "sdmmcr",
656 .swgroup = TEGRA_SWGROUP_SDMMC3A,
657 .smmu = {
658 .reg = 0x234,
659 .bit = 2,
660 },
661 .la = {
662 .reg = 0x3c0,
663 .shift = 0,
664 .mask = 0xff,
665 .def = 0x49,
666 },
667 }, {
668 .id = 0x63,
669 .swgroup = TEGRA_SWGROUP_SDMMC4A,
670 .name = "sdmmcrab",
671 .smmu = {
672 .reg = 0x234,
673 .bit = 3,
674 },
675 .la = {
676 .reg = 0x3c4,
677 .shift = 0,
678 .mask = 0xff,
679 .def = 0x49,
680 },
681 }, {
682 .id = 0x64,
683 .name = "sdmmcwa",
684 .swgroup = TEGRA_SWGROUP_SDMMC1A,
685 .smmu = {
686 .reg = 0x234,
687 .bit = 4,
688 },
689 .la = {
690 .reg = 0x3b8,
691 .shift = 16,
692 .mask = 0xff,
693 .def = 0x80,
694 },
695 }, {
696 .id = 0x65,
697 .name = "sdmmcwaa",
698 .swgroup = TEGRA_SWGROUP_SDMMC2A,
699 .smmu = {
700 .reg = 0x234,
701 .bit = 5,
702 },
703 .la = {
704 .reg = 0x3bc,
705 .shift = 16,
706 .mask = 0xff,
707 .def = 0x80,
708 },
709 }, {
710 .id = 0x66,
711 .name = "sdmmcw",
712 .swgroup = TEGRA_SWGROUP_SDMMC3A,
713 .smmu = {
714 .reg = 0x234,
715 .bit = 6,
716 },
717 .la = {
718 .reg = 0x3c0,
719 .shift = 16,
720 .mask = 0xff,
721 .def = 0x80,
722 },
723 }, {
724 .id = 0x67,
725 .name = "sdmmcwab",
726 .swgroup = TEGRA_SWGROUP_SDMMC4A,
727 .smmu = {
728 .reg = 0x234,
729 .bit = 7,
730 },
731 .la = {
732 .reg = 0x3c4,
733 .shift = 16,
734 .mask = 0xff,
735 .def = 0x80,
736 },
737 }, {
738 .id = 0x6c,
739 .name = "vicsrd",
740 .swgroup = TEGRA_SWGROUP_VIC,
741 .smmu = {
742 .reg = 0x234,
743 .bit = 12,
744 },
745 .la = {
746 .reg = 0x394,
747 .shift = 0,
748 .mask = 0xff,
749 .def = 0x1a,
750 },
751 }, {
752 .id = 0x6d,
753 .name = "vicswr",
754 .swgroup = TEGRA_SWGROUP_VIC,
755 .smmu = {
756 .reg = 0x234,
757 .bit = 13,
758 },
759 .la = {
760 .reg = 0x394,
761 .shift = 16,
762 .mask = 0xff,
763 .def = 0x80,
764 },
765 }, {
766 .id = 0x72,
767 .name = "viw",
768 .swgroup = TEGRA_SWGROUP_VI,
769 .smmu = {
770 .reg = 0x234,
771 .bit = 18,
772 },
773 .la = {
774 .reg = 0x398,
775 .shift = 0,
776 .mask = 0xff,
777 .def = 0x80,
778 },
779 }, {
780 .id = 0x73,
781 .name = "displayd",
782 .swgroup = TEGRA_SWGROUP_DC,
783 .smmu = {
784 .reg = 0x234,
785 .bit = 19,
786 },
787 .la = {
788 .reg = 0x3c8,
789 .shift = 0,
790 .mask = 0xff,
791 .def = 0x50,
792 },
793 }, {
794 .id = 0x78,
795 .name = "nvdecsrd",
796 .swgroup = TEGRA_SWGROUP_NVDEC,
797 .smmu = {
798 .reg = 0x234,
799 .bit = 24,
800 },
801 .la = {
802 .reg = 0x3d8,
803 .shift = 0,
804 .mask = 0xff,
805 .def = 0x23,
806 },
807 }, {
808 .id = 0x79,
809 .name = "nvdecswr",
810 .swgroup = TEGRA_SWGROUP_NVDEC,
811 .smmu = {
812 .reg = 0x234,
813 .bit = 25,
814 },
815 .la = {
816 .reg = 0x3d8,
817 .shift = 16,
818 .mask = 0xff,
819 .def = 0x80,
820 },
821 }, {
822 .id = 0x7a,
823 .name = "aper",
824 .swgroup = TEGRA_SWGROUP_APE,
825 .smmu = {
826 .reg = 0x234,
827 .bit = 26,
828 },
829 .la = {
830 .reg = 0x3dc,
831 .shift = 0,
832 .mask = 0xff,
833 .def = 0xff,
834 },
835 }, {
836 .id = 0x7b,
837 .name = "apew",
838 .swgroup = TEGRA_SWGROUP_APE,
839 .smmu = {
840 .reg = 0x234,
841 .bit = 27,
842 },
843 .la = {
844 .reg = 0x3dc,
845 .shift = 0,
846 .mask = 0xff,
847 .def = 0x80,
848 },
849 }, {
850 .id = 0x7e,
851 .name = "nvjpgsrd",
852 .swgroup = TEGRA_SWGROUP_NVJPG,
853 .smmu = {
854 .reg = 0x234,
855 .bit = 30,
856 },
857 .la = {
858 .reg = 0x3e4,
859 .shift = 0,
860 .mask = 0xff,
861 .def = 0x23,
862 },
863 }, {
864 .id = 0x7f,
865 .name = "nvjpgswr",
866 .swgroup = TEGRA_SWGROUP_NVJPG,
867 .smmu = {
868 .reg = 0x234,
869 .bit = 31,
870 },
871 .la = {
872 .reg = 0x3e4,
873 .shift = 16,
874 .mask = 0xff,
875 .def = 0x80,
876 },
877 }, {
878 .id = 0x80,
879 .name = "sesrd",
880 .swgroup = TEGRA_SWGROUP_SE,
881 .smmu = {
882 .reg = 0xb98,
883 .bit = 0,
884 },
885 .la = {
886 .reg = 0x3e0,
887 .shift = 0,
888 .mask = 0xff,
889 .def = 0x2e,
890 },
891 }, {
892 .id = 0x81,
893 .name = "seswr",
894 .swgroup = TEGRA_SWGROUP_SE,
895 .smmu = {
896 .reg = 0xb98,
897 .bit = 1,
898 },
899 .la = {
900 .reg = 0xb98,
901 .shift = 16,
902 .mask = 0xff,
903 .def = 0x80,
904 },
905 }, {
906 .id = 0x82,
907 .name = "axiapr",
908 .swgroup = TEGRA_SWGROUP_AXIAP,
909 .smmu = {
910 .reg = 0xb98,
911 .bit = 2,
912 },
913 .la = {
914 .reg = 0x3a0,
915 .shift = 0,
916 .mask = 0xff,
917 .def = 0xff,
918 },
919 }, {
920 .id = 0x83,
921 .name = "axiapw",
922 .swgroup = TEGRA_SWGROUP_AXIAP,
923 .smmu = {
924 .reg = 0xb98,
925 .bit = 3,
926 },
927 .la = {
928 .reg = 0x3a0,
929 .shift = 16,
930 .mask = 0xff,
931 .def = 0x80,
932 },
933 }, {
934 .id = 0x84,
935 .name = "etrr",
936 .swgroup = TEGRA_SWGROUP_ETR,
937 .smmu = {
938 .reg = 0xb98,
939 .bit = 4,
940 },
941 .la = {
942 .reg = 0x3ec,
943 .shift = 0,
944 .mask = 0xff,
945 .def = 0xff,
946 },
947 }, {
948 .id = 0x85,
949 .name = "etrw",
950 .swgroup = TEGRA_SWGROUP_ETR,
951 .smmu = {
952 .reg = 0xb98,
953 .bit = 5,
954 },
955 .la = {
956 .reg = 0x3ec,
957 .shift = 16,
958 .mask = 0xff,
959 .def = 0xff,
960 },
961 }, {
962 .id = 0x86,
963 .name = "tsecsrdb",
964 .swgroup = TEGRA_SWGROUP_TSECB,
965 .smmu = {
966 .reg = 0xb98,
967 .bit = 6,
968 },
969 .la = {
970 .reg = 0x3f0,
971 .shift = 0,
972 .mask = 0xff,
973 .def = 0x9b,
974 },
975 }, {
976 .id = 0x87,
977 .name = "tsecswrb",
978 .swgroup = TEGRA_SWGROUP_TSECB,
979 .smmu = {
980 .reg = 0xb98,
981 .bit = 7,
982 },
983 .la = {
984 .reg = 0x3f0,
985 .shift = 16,
986 .mask = 0xff,
987 .def = 0x80,
988 },
989 }, {
990 .id = 0x88,
991 .name = "gpusrd2",
992 .swgroup = TEGRA_SWGROUP_GPU,
993 .smmu = {
994 /* read-only */
995 .reg = 0xb98,
996 .bit = 8,
997 },
998 .la = {
999 .reg = 0x3e8,
1000 .shift = 0,
1001 .mask = 0xff,
1002 .def = 0x1a,
1003 },
1004 }, {
1005 .id = 0x89,
1006 .name = "gpuswr2",
1007 .swgroup = TEGRA_SWGROUP_GPU,
1008 .smmu = {
1009 /* read-only */
1010 .reg = 0xb98,
1011 .bit = 9,
1012 },
1013 .la = {
1014 .reg = 0x3e8,
1015 .shift = 16,
1016 .mask = 0xff,
1017 .def = 0x80,
1018 },
1019 },
1020};
1021
1022static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1023 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1024 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1025 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1026 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1027 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1028 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1029 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1030 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1031 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1032 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1033 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1034 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1035 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1036 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1037 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1038 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1039 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1040 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1041 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1042 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1043 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1044 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1045 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1046 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1047 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1048 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1049 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1050 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1051 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1052};
1053
1054static const unsigned int tegra210_group_display[] = {
1055 TEGRA_SWGROUP_DC,
1056 TEGRA_SWGROUP_DCB,
1057};
1058
1059static const struct tegra_smmu_group_soc tegra210_groups[] = {
1060 {
1061 .name = "display",
1062 .swgroups = tegra210_group_display,
1063 .num_swgroups = ARRAY_SIZE(tegra210_group_display),
1064 },
1065};
1066
1067static const struct tegra_smmu_soc tegra210_smmu_soc = {
1068 .clients = tegra210_mc_clients,
1069 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1070 .swgroups = tegra210_swgroups,
1071 .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1072 .groups = tegra210_groups,
1073 .num_groups = ARRAY_SIZE(tegra210_groups),
1074 .supports_round_robin_arbitration = true,
1075 .supports_request_limit = true,
1076 .num_tlb_lines = 32,
1077 .num_asids = 128,
1078};
1079
1080#define TEGRA210_MC_RESET(_name, _control, _status, _bit) \
1081 { \
1082 .name = #_name, \
1083 .id = TEGRA210_MC_RESET_##_name, \
1084 .control = _control, \
1085 .status = _status, \
1086 .bit = _bit, \
1087 }
1088
1089static const struct tegra_mc_reset tegra210_mc_resets[] = {
1090 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1091 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1092 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1093 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1094 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1095 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1096 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1097 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1098 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1099 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1100 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1101 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1102 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1103 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1104 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1105 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1106 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1107 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1108 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1109 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1110 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1111 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1112 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1113 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1114 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1115 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1116 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1117 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1118 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1119 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1120};
1121
1122const struct tegra_mc_soc tegra210_mc_soc = {
1123 .clients = tegra210_mc_clients,
1124 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1125 .num_address_bits = 34,
1126 .atom_size = 64,
1127 .client_id_mask = 0xff,
1128 .smmu = &tegra210_smmu_soc,
1129 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1130 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1131 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1132 .reset_ops = &tegra_mc_reset_ops_common,
1133 .resets = tegra210_mc_resets,
1134 .num_resets = ARRAY_SIZE(tegra210_mc_resets),
1135};