Loading...
Note: File does not exist in v5.4.
1/*
2 * IBM Summit-Specific Code
3 *
4 * Written By: Matthew Dobson, IBM Corporation
5 *
6 * Copyright (c) 2003 IBM Corp.
7 *
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
19 * details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Send feedback to <colpatch@us.ibm.com>
26 *
27 */
28
29#include <linux/mm.h>
30#include <linux/init.h>
31#include <asm/io.h>
32#include <asm/bios_ebda.h>
33
34/*
35 * APIC driver for the IBM "Summit" chipset.
36 */
37#include <linux/threads.h>
38#include <linux/cpumask.h>
39#include <asm/mpspec.h>
40#include <asm/apic.h>
41#include <asm/smp.h>
42#include <asm/fixmap.h>
43#include <asm/apicdef.h>
44#include <asm/ipi.h>
45#include <linux/kernel.h>
46#include <linux/string.h>
47#include <linux/gfp.h>
48#include <linux/smp.h>
49
50static unsigned summit_get_apic_id(unsigned long x)
51{
52 return (x >> 24) & 0xFF;
53}
54
55static inline void summit_send_IPI_mask(const struct cpumask *mask, int vector)
56{
57 default_send_IPI_mask_sequence_logical(mask, vector);
58}
59
60static void summit_send_IPI_allbutself(int vector)
61{
62 default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
63}
64
65static void summit_send_IPI_all(int vector)
66{
67 summit_send_IPI_mask(cpu_online_mask, vector);
68}
69
70#include <asm/tsc.h>
71
72extern int use_cyclone;
73
74#ifdef CONFIG_X86_SUMMIT_NUMA
75static void setup_summit(void);
76#else
77static inline void setup_summit(void) {}
78#endif
79
80static int summit_mps_oem_check(struct mpc_table *mpc, char *oem,
81 char *productid)
82{
83 if (!strncmp(oem, "IBM ENSW", 8) &&
84 (!strncmp(productid, "VIGIL SMP", 9)
85 || !strncmp(productid, "EXA", 3)
86 || !strncmp(productid, "RUTHLESS SMP", 12))){
87 mark_tsc_unstable("Summit based system");
88 use_cyclone = 1; /*enable cyclone-timer*/
89 setup_summit();
90 return 1;
91 }
92 return 0;
93}
94
95/* Hook from generic ACPI tables.c */
96static int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
97{
98 if (!strncmp(oem_id, "IBM", 3) &&
99 (!strncmp(oem_table_id, "SERVIGIL", 8)
100 || !strncmp(oem_table_id, "EXA", 3))){
101 mark_tsc_unstable("Summit based system");
102 use_cyclone = 1; /*enable cyclone-timer*/
103 setup_summit();
104 return 1;
105 }
106 return 0;
107}
108
109struct rio_table_hdr {
110 unsigned char version; /* Version number of this data structure */
111 /* Version 3 adds chassis_num & WP_index */
112 unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil) */
113 unsigned char num_rio_dev; /* # of RIO I/O devices (Cyclones and Winnipegs) */
114} __attribute__((packed));
115
116struct scal_detail {
117 unsigned char node_id; /* Scalability Node ID */
118 unsigned long CBAR; /* Address of 1MB register space */
119 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
120 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
121 unsigned char port1node; /* Node ID port connected to: 0xFF = None */
122 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
123 unsigned char port2node; /* Node ID port connected to: 0xFF = None */
124 unsigned char port2port; /* Port num port connected to: 0,1,2, or 0xFF=None */
125 unsigned char chassis_num; /* 1 based Chassis number (1 = boot node) */
126} __attribute__((packed));
127
128struct rio_detail {
129 unsigned char node_id; /* RIO Node ID */
130 unsigned long BBAR; /* Address of 1MB register space */
131 unsigned char type; /* Type of device */
132 unsigned char owner_id; /* For WPEG: Node ID of Cyclone that owns this WPEG*/
133 /* For CYC: Node ID of Twister that owns this CYC */
134 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
135 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
136 unsigned char port1node; /* Node ID port connected to: 0xFF=None */
137 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
138 unsigned char first_slot; /* For WPEG: Lowest slot number below this WPEG */
139 /* For CYC: 0 */
140 unsigned char status; /* For WPEG: Bit 0 = 1 : the XAPIC is used */
141 /* = 0 : the XAPIC is not used, ie:*/
142 /* ints fwded to another XAPIC */
143 /* Bits1:7 Reserved */
144 /* For CYC: Bits0:7 Reserved */
145 unsigned char WP_index; /* For WPEG: WPEG instance index - lower ones have */
146 /* lower slot numbers/PCI bus numbers */
147 /* For CYC: No meaning */
148 unsigned char chassis_num; /* 1 based Chassis number */
149 /* For LookOut WPEGs this field indicates the */
150 /* Expansion Chassis #, enumerated from Boot */
151 /* Node WPEG external port, then Boot Node CYC */
152 /* external port, then Next Vigil chassis WPEG */
153 /* external port, etc. */
154 /* Shared Lookouts have only 1 chassis number (the */
155 /* first one assigned) */
156} __attribute__((packed));
157
158
159typedef enum {
160 CompatTwister = 0, /* Compatibility Twister */
161 AltTwister = 1, /* Alternate Twister of internal 8-way */
162 CompatCyclone = 2, /* Compatibility Cyclone */
163 AltCyclone = 3, /* Alternate Cyclone of internal 8-way */
164 CompatWPEG = 4, /* Compatibility WPEG */
165 AltWPEG = 5, /* Second Planar WPEG */
166 LookOutAWPEG = 6, /* LookOut WPEG */
167 LookOutBWPEG = 7, /* LookOut WPEG */
168} node_type;
169
170static inline int is_WPEG(struct rio_detail *rio){
171 return (rio->type == CompatWPEG || rio->type == AltWPEG ||
172 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
173}
174
175#define SUMMIT_APIC_DFR_VALUE (APIC_DFR_CLUSTER)
176
177static const struct cpumask *summit_target_cpus(void)
178{
179 /* CPU_MASK_ALL (0xff) has undefined behaviour with
180 * dest_LowestPrio mode logical clustered apic interrupt routing
181 * Just start on cpu 0. IRQ balancing will spread load
182 */
183 return cpumask_of(0);
184}
185
186static unsigned long summit_check_apicid_used(physid_mask_t *map, int apicid)
187{
188 return 0;
189}
190
191/* we don't use the phys_cpu_present_map to indicate apicid presence */
192static unsigned long summit_check_apicid_present(int bit)
193{
194 return 1;
195}
196
197static int summit_early_logical_apicid(int cpu)
198{
199 int count = 0;
200 u8 my_id = early_per_cpu(x86_cpu_to_apicid, cpu);
201 u8 my_cluster = APIC_CLUSTER(my_id);
202#ifdef CONFIG_SMP
203 u8 lid;
204 int i;
205
206 /* Create logical APIC IDs by counting CPUs already in cluster. */
207 for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
208 lid = early_per_cpu(x86_cpu_to_logical_apicid, i);
209 if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)
210 ++count;
211 }
212#endif
213 /* We only have a 4 wide bitmap in cluster mode. If a deranged
214 * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
215 BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
216 return my_cluster | (1UL << count);
217}
218
219static void summit_init_apic_ldr(void)
220{
221 int cpu = smp_processor_id();
222 unsigned long id = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
223 unsigned long val;
224
225 apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE);
226 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
227 val |= SET_APIC_LOGICAL_ID(id);
228 apic_write(APIC_LDR, val);
229}
230
231static int summit_apic_id_registered(void)
232{
233 return 1;
234}
235
236static void summit_setup_apic_routing(void)
237{
238 printk("Enabling APIC mode: Summit. Using %d I/O APICs\n",
239 nr_ioapics);
240}
241
242static int summit_cpu_present_to_apicid(int mps_cpu)
243{
244 if (mps_cpu < nr_cpu_ids)
245 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
246 else
247 return BAD_APICID;
248}
249
250static void summit_ioapic_phys_id_map(physid_mask_t *phys_id_map, physid_mask_t *retmap)
251{
252 /* For clustered we don't have a good way to do this yet - hack */
253 physids_promote(0x0FL, retmap);
254}
255
256static void summit_apicid_to_cpu_present(int apicid, physid_mask_t *retmap)
257{
258 physid_set_mask_of_physid(0, retmap);
259}
260
261static int summit_check_phys_apicid_present(int physical_apicid)
262{
263 return 1;
264}
265
266static unsigned int summit_cpu_mask_to_apicid(const struct cpumask *cpumask)
267{
268 unsigned int round = 0;
269 int cpu, apicid = 0;
270
271 /*
272 * The cpus in the mask must all be on the apic cluster.
273 */
274 for_each_cpu(cpu, cpumask) {
275 int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
276
277 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
278 printk("%s: Not a valid mask!\n", __func__);
279 return BAD_APICID;
280 }
281 apicid |= new_apicid;
282 round++;
283 }
284 return apicid;
285}
286
287static unsigned int summit_cpu_mask_to_apicid_and(const struct cpumask *inmask,
288 const struct cpumask *andmask)
289{
290 int apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
291 cpumask_var_t cpumask;
292
293 if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
294 return apicid;
295
296 cpumask_and(cpumask, inmask, andmask);
297 cpumask_and(cpumask, cpumask, cpu_online_mask);
298 apicid = summit_cpu_mask_to_apicid(cpumask);
299
300 free_cpumask_var(cpumask);
301
302 return apicid;
303}
304
305/*
306 * cpuid returns the value latched in the HW at reset, not the APIC ID
307 * register's value. For any box whose BIOS changes APIC IDs, like
308 * clustered APIC systems, we must use hard_smp_processor_id.
309 *
310 * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
311 */
312static int summit_phys_pkg_id(int cpuid_apic, int index_msb)
313{
314 return hard_smp_processor_id() >> index_msb;
315}
316
317static int probe_summit(void)
318{
319 /* probed later in mptable/ACPI hooks */
320 return 0;
321}
322
323static void summit_vector_allocation_domain(int cpu, struct cpumask *retmask)
324{
325 /* Careful. Some cpus do not strictly honor the set of cpus
326 * specified in the interrupt destination when using lowest
327 * priority interrupt delivery mode.
328 *
329 * In particular there was a hyperthreading cpu observed to
330 * deliver interrupts to the wrong hyperthread when only one
331 * hyperthread was specified in the interrupt desitination.
332 */
333 cpumask_clear(retmask);
334 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
335}
336
337#ifdef CONFIG_X86_SUMMIT_NUMA
338static struct rio_table_hdr *rio_table_hdr;
339static struct scal_detail *scal_devs[MAX_NUMNODES];
340static struct rio_detail *rio_devs[MAX_NUMNODES*4];
341
342#ifndef CONFIG_X86_NUMAQ
343static int mp_bus_id_to_node[MAX_MP_BUSSES];
344#endif
345
346static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
347{
348 int twister = 0, node = 0;
349 int i, bus, num_buses;
350
351 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
352 if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) {
353 twister = rio_devs[i]->owner_id;
354 break;
355 }
356 }
357 if (i == rio_table_hdr->num_rio_dev) {
358 printk(KERN_ERR "%s: Couldn't find owner Cyclone for Winnipeg!\n", __func__);
359 return last_bus;
360 }
361
362 for (i = 0; i < rio_table_hdr->num_scal_dev; i++) {
363 if (scal_devs[i]->node_id == twister) {
364 node = scal_devs[i]->node_id;
365 break;
366 }
367 }
368 if (i == rio_table_hdr->num_scal_dev) {
369 printk(KERN_ERR "%s: Couldn't find owner Twister for Cyclone!\n", __func__);
370 return last_bus;
371 }
372
373 switch (rio_devs[wpeg_num]->type) {
374 case CompatWPEG:
375 /*
376 * The Compatibility Winnipeg controls the 2 legacy buses,
377 * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case
378 * a PCI-PCI bridge card is used in either slot: total 5 buses.
379 */
380 num_buses = 5;
381 break;
382 case AltWPEG:
383 /*
384 * The Alternate Winnipeg controls the 2 133MHz buses [1 slot
385 * each], their 2 "extra" buses, the 100MHz bus [2 slots] and
386 * the "extra" buses for each of those slots: total 7 buses.
387 */
388 num_buses = 7;
389 break;
390 case LookOutAWPEG:
391 case LookOutBWPEG:
392 /*
393 * A Lookout Winnipeg controls 3 100MHz buses [2 slots each]
394 * & the "extra" buses for each of those slots: total 9 buses.
395 */
396 num_buses = 9;
397 break;
398 default:
399 printk(KERN_INFO "%s: Unsupported Winnipeg type!\n", __func__);
400 return last_bus;
401 }
402
403 for (bus = last_bus; bus < last_bus + num_buses; bus++)
404 mp_bus_id_to_node[bus] = node;
405 return bus;
406}
407
408static int build_detail_arrays(void)
409{
410 unsigned long ptr;
411 int i, scal_detail_size, rio_detail_size;
412
413 if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) {
414 printk(KERN_WARNING "%s: MAX_NUMNODES too low! Defined as %d, but system has %d nodes.\n", __func__, MAX_NUMNODES, rio_table_hdr->num_scal_dev);
415 return 0;
416 }
417
418 switch (rio_table_hdr->version) {
419 default:
420 printk(KERN_WARNING "%s: Invalid Rio Grande Table Version: %d\n", __func__, rio_table_hdr->version);
421 return 0;
422 case 2:
423 scal_detail_size = 11;
424 rio_detail_size = 13;
425 break;
426 case 3:
427 scal_detail_size = 12;
428 rio_detail_size = 15;
429 break;
430 }
431
432 ptr = (unsigned long)rio_table_hdr + 3;
433 for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size)
434 scal_devs[i] = (struct scal_detail *)ptr;
435
436 for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size)
437 rio_devs[i] = (struct rio_detail *)ptr;
438
439 return 1;
440}
441
442void setup_summit(void)
443{
444 unsigned long ptr;
445 unsigned short offset;
446 int i, next_wpeg, next_bus = 0;
447
448 /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */
449 ptr = get_bios_ebda();
450 ptr = (unsigned long)phys_to_virt(ptr);
451
452 rio_table_hdr = NULL;
453 offset = 0x180;
454 while (offset) {
455 /* The block id is stored in the 2nd word */
456 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) {
457 /* set the pointer past the offset & block id */
458 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
459 break;
460 }
461 /* The next offset is stored in the 1st word. 0 means no more */
462 offset = *((unsigned short *)(ptr + offset));
463 }
464 if (!rio_table_hdr) {
465 printk(KERN_ERR "%s: Unable to locate Rio Grande Table in EBDA - bailing!\n", __func__);
466 return;
467 }
468
469 if (!build_detail_arrays())
470 return;
471
472 /* The first Winnipeg we're looking for has an index of 0 */
473 next_wpeg = 0;
474 do {
475 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
476 if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) {
477 /* It's the Winnipeg we're looking for! */
478 next_bus = setup_pci_node_map_for_wpeg(i, next_bus);
479 next_wpeg++;
480 break;
481 }
482 }
483 /*
484 * If we go through all Rio devices and don't find one with
485 * the next index, it means we've found all the Winnipegs,
486 * and thus all the PCI buses.
487 */
488 if (i == rio_table_hdr->num_rio_dev)
489 next_wpeg = 0;
490 } while (next_wpeg != 0);
491}
492#endif
493
494static struct apic apic_summit = {
495
496 .name = "summit",
497 .probe = probe_summit,
498 .acpi_madt_oem_check = summit_acpi_madt_oem_check,
499 .apic_id_valid = default_apic_id_valid,
500 .apic_id_registered = summit_apic_id_registered,
501
502 .irq_delivery_mode = dest_LowestPrio,
503 /* logical delivery broadcast to all CPUs: */
504 .irq_dest_mode = 1,
505
506 .target_cpus = summit_target_cpus,
507 .disable_esr = 1,
508 .dest_logical = APIC_DEST_LOGICAL,
509 .check_apicid_used = summit_check_apicid_used,
510 .check_apicid_present = summit_check_apicid_present,
511
512 .vector_allocation_domain = summit_vector_allocation_domain,
513 .init_apic_ldr = summit_init_apic_ldr,
514
515 .ioapic_phys_id_map = summit_ioapic_phys_id_map,
516 .setup_apic_routing = summit_setup_apic_routing,
517 .multi_timer_check = NULL,
518 .cpu_present_to_apicid = summit_cpu_present_to_apicid,
519 .apicid_to_cpu_present = summit_apicid_to_cpu_present,
520 .setup_portio_remap = NULL,
521 .check_phys_apicid_present = summit_check_phys_apicid_present,
522 .enable_apic_mode = NULL,
523 .phys_pkg_id = summit_phys_pkg_id,
524 .mps_oem_check = summit_mps_oem_check,
525
526 .get_apic_id = summit_get_apic_id,
527 .set_apic_id = NULL,
528 .apic_id_mask = 0xFF << 24,
529
530 .cpu_mask_to_apicid = summit_cpu_mask_to_apicid,
531 .cpu_mask_to_apicid_and = summit_cpu_mask_to_apicid_and,
532
533 .send_IPI_mask = summit_send_IPI_mask,
534 .send_IPI_mask_allbutself = NULL,
535 .send_IPI_allbutself = summit_send_IPI_allbutself,
536 .send_IPI_all = summit_send_IPI_all,
537 .send_IPI_self = default_send_IPI_self,
538
539 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
540 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
541
542 .wait_for_init_deassert = default_wait_for_init_deassert,
543
544 .smp_callin_clear_local_apic = NULL,
545 .inquire_remote_apic = default_inquire_remote_apic,
546
547 .read = native_apic_mem_read,
548 .write = native_apic_mem_write,
549 .eoi_write = native_apic_mem_write,
550 .icr_read = native_apic_icr_read,
551 .icr_write = native_apic_icr_write,
552 .wait_icr_idle = native_apic_wait_icr_idle,
553 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
554
555 .x86_32_early_logical_apicid = summit_early_logical_apicid,
556};
557
558apic_driver(apic_summit);