1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Numascale NumaConnect-Specific APIC Code
  7 *
  8 * Copyright (C) 2011 Numascale AS. All rights reserved.
  9 *
 10 * Send feedback to <support@numascale.com>
 11 *
 12 */
 13#include <linux/types.h>
 
 
 
 
 
 
 
 14#include <linux/init.h>
 
 
 15
 16#include <asm/numachip/numachip.h>
 17#include <asm/numachip/numachip_csr.h>
 
 
 
 
 18
 19#include <asm/pgtable.h>
 20
 21#include "local.h"
 22
 23u8 numachip_system __read_mostly;
 24static const struct apic apic_numachip1;
 25static const struct apic apic_numachip2;
 26static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
 27
 28static unsigned int numachip1_get_apic_id(unsigned long x)
 29{
 30	unsigned long value;
 31	unsigned int id = (x >> 24) & 0xff;
 32
 33	if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
 34		rdmsrl(MSR_FAM10H_NODE_ID, value);
 35		id |= (value << 2) & 0xff00;
 36	}
 37
 38	return id;
 39}
 40
 41static u32 numachip1_set_apic_id(unsigned int id)
 42{
 43	return (id & 0xff) << 24;
 44}
 45
 46static unsigned int numachip2_get_apic_id(unsigned long x)
 47{
 48	u64 mcfg;
 49
 50	rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
 51	return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
 52}
 53
 54static u32 numachip2_set_apic_id(unsigned int id)
 55{
 56	return id << 24;
 57}
 58
 59static int numachip_apic_id_valid(u32 apicid)
 60{
 61	/* Trust what bootloader passes in MADT */
 62	return 1;
 63}
 64
 65static int numachip_apic_id_registered(void)
 66{
 67	return 1;
 68}
 69
 70static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
 71{
 72	return initial_apic_id >> index_msb;
 73}
 74
 75static void numachip1_apic_icr_write(int apicid, unsigned int val)
 76{
 77	write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
 78}
 79
 80static void numachip2_apic_icr_write(int apicid, unsigned int val)
 81{
 82	numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);
 
 83}
 84
 85static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 86{
 87	numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
 88	numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
 89		(start_rip >> 12));
 
 
 
 
 
 
 
 
 
 
 90
 
 91	return 0;
 92}
 93
 94static void numachip_send_IPI_one(int cpu, int vector)
 95{
 96	int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu);
 97	unsigned int dmode;
 98
 99	preempt_disable();
100	local_apicid = __this_cpu_read(x86_cpu_to_apicid);
 
 
101
102	/* Send via local APIC where non-local part matches */
103	if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) {
104		unsigned long flags;
105
106		local_irq_save(flags);
107		__default_send_IPI_dest_field(apicid, vector,
108			APIC_DEST_PHYSICAL);
109		local_irq_restore(flags);
110		preempt_enable();
111		return;
112	}
113	preempt_enable();
114
115	dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;
116	numachip_apic_icr_write(apicid, dmode | vector);
117}
118
119static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
120{
121	unsigned int cpu;
122
123	for_each_cpu(cpu, mask)
124		numachip_send_IPI_one(cpu, vector);
125}
126
127static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
128						int vector)
129{
130	unsigned int this_cpu = smp_processor_id();
131	unsigned int cpu;
132
133	for_each_cpu(cpu, mask) {
134		if (cpu != this_cpu)
135			numachip_send_IPI_one(cpu, vector);
136	}
137}
138
139static void numachip_send_IPI_allbutself(int vector)
140{
141	unsigned int this_cpu = smp_processor_id();
142	unsigned int cpu;
143
144	for_each_online_cpu(cpu) {
145		if (cpu != this_cpu)
146			numachip_send_IPI_one(cpu, vector);
147	}
148}
149
150static void numachip_send_IPI_all(int vector)
151{
152	numachip_send_IPI_mask(cpu_online_mask, vector);
153}
154
155static void numachip_send_IPI_self(int vector)
156{
157	apic_write(APIC_SELF_IPI, vector);
158}
159
160static int __init numachip1_probe(void)
161{
162	return apic == &apic_numachip1;
163}
164
165static int __init numachip2_probe(void)
166{
167	return apic == &apic_numachip2;
 
 
 
 
 
 
168}
169
170static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
 
 
171{
172	u64 val;
173	u32 nodes = 1;
174
175	this_cpu_write(cpu_llc_id, node);
176
177	/* Account for nodes per socket in multi-core-module processors */
178	if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
179		rdmsrl(MSR_FAM10H_NODE_ID, val);
180		nodes = ((val >> 3) & 7) + 1;
 
 
 
181	}
182
183	c->phys_proc_id = node / nodes;
184}
185
186static int __init numachip_system_init(void)
187{
188	/* Map the LCSR area and set up the apic_icr_write function */
189	switch (numachip_system) {
190	case 1:
191		init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
192		numachip_apic_icr_write = numachip1_apic_icr_write;
193		break;
194	case 2:
195		init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE);
196		numachip_apic_icr_write = numachip2_apic_icr_write;
197		break;
198	default:
199		return 0;
200	}
201
202	x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
203	x86_init.pci.arch_init = pci_numachip_init;
204
205	return 0;
206}
207early_initcall(numachip_system_init);
208
209static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
210{
211	if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
212	    (strncmp(oem_table_id, "NCONNECT", 8) != 0))
213		return 0;
214
215	numachip_system = 1;
216
217	return 1;
 
 
218}
219
220static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
221{
222	if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
223	    (strncmp(oem_table_id, "NCONECT2", 8) != 0))
224		return 0;
225
226	numachip_system = 2;
227
228	return 1;
229}
230
231/* APIC IPIs are queued */
232static void numachip_apic_wait_icr_idle(void)
233{
 
234}
235
236/* APIC NMI IPIs are queued */
237static u32 numachip_safe_apic_wait_icr_idle(void)
238{
239	return 0;
240}
241
242static const struct apic apic_numachip1 __refconst = {
243	.name				= "NumaConnect system",
244	.probe				= numachip1_probe,
245	.acpi_madt_oem_check		= numachip1_acpi_madt_oem_check,
246	.apic_id_valid			= numachip_apic_id_valid,
247	.apic_id_registered		= numachip_apic_id_registered,
248
249	.irq_delivery_mode		= dest_Fixed,
250	.irq_dest_mode			= 0, /* physical */
251
252	.disable_esr			= 0,
253	.dest_logical			= 0,
254	.check_apicid_used		= NULL,
255
256	.init_apic_ldr			= flat_init_apic_ldr,
257
258	.ioapic_phys_id_map		= NULL,
259	.setup_apic_routing		= NULL,
260	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
261	.apicid_to_cpu_present		= NULL,
262	.check_phys_apicid_present	= default_check_phys_apicid_present,
263	.phys_pkg_id			= numachip_phys_pkg_id,
264
265	.get_apic_id			= numachip1_get_apic_id,
266	.set_apic_id			= numachip1_set_apic_id,
267
268	.calc_dest_apicid		= apic_default_calc_apicid,
 
269
270	.send_IPI			= numachip_send_IPI_one,
271	.send_IPI_mask			= numachip_send_IPI_mask,
272	.send_IPI_mask_allbutself	= numachip_send_IPI_mask_allbutself,
273	.send_IPI_allbutself		= numachip_send_IPI_allbutself,
274	.send_IPI_all			= numachip_send_IPI_all,
275	.send_IPI_self			= numachip_send_IPI_self,
276
277	.wakeup_secondary_cpu		= numachip_wakeup_secondary,
278	.inquire_remote_apic		= NULL, /* REMRD not supported */
 
 
 
 
279
280	.read				= native_apic_mem_read,
281	.write				= native_apic_mem_write,
282	.eoi_write			= native_apic_mem_write,
283	.icr_read			= native_apic_icr_read,
284	.icr_write			= native_apic_icr_write,
285	.wait_icr_idle			= numachip_apic_wait_icr_idle,
286	.safe_wait_icr_idle		= numachip_safe_apic_wait_icr_idle,
287};
288
289apic_driver(apic_numachip1);
290
291static const struct apic apic_numachip2 __refconst = {
292	.name				= "NumaConnect2 system",
293	.probe				= numachip2_probe,
294	.acpi_madt_oem_check		= numachip2_acpi_madt_oem_check,
295	.apic_id_valid			= numachip_apic_id_valid,
296	.apic_id_registered		= numachip_apic_id_registered,
297
298	.irq_delivery_mode		= dest_Fixed,
299	.irq_dest_mode			= 0, /* physical */
300
 
301	.disable_esr			= 0,
302	.dest_logical			= 0,
303	.check_apicid_used		= NULL,
 
304
 
305	.init_apic_ldr			= flat_init_apic_ldr,
306
307	.ioapic_phys_id_map		= NULL,
308	.setup_apic_routing		= NULL,
 
309	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
310	.apicid_to_cpu_present		= NULL,
 
311	.check_phys_apicid_present	= default_check_phys_apicid_present,
 
312	.phys_pkg_id			= numachip_phys_pkg_id,
 
313
314	.get_apic_id			= numachip2_get_apic_id,
315	.set_apic_id			= numachip2_set_apic_id,
 
316
317	.calc_dest_apicid		= apic_default_calc_apicid,
 
318
319	.send_IPI			= numachip_send_IPI_one,
320	.send_IPI_mask			= numachip_send_IPI_mask,
321	.send_IPI_mask_allbutself	= numachip_send_IPI_mask_allbutself,
322	.send_IPI_allbutself		= numachip_send_IPI_allbutself,
323	.send_IPI_all			= numachip_send_IPI_all,
324	.send_IPI_self			= numachip_send_IPI_self,
325
326	.wakeup_secondary_cpu		= numachip_wakeup_secondary,
 
 
 
 
327	.inquire_remote_apic		= NULL, /* REMRD not supported */
328
329	.read				= native_apic_mem_read,
330	.write				= native_apic_mem_write,
331	.eoi_write			= native_apic_mem_write,
332	.icr_read			= native_apic_icr_read,
333	.icr_write			= native_apic_icr_write,
334	.wait_icr_idle			= numachip_apic_wait_icr_idle,
335	.safe_wait_icr_idle		= numachip_safe_apic_wait_icr_idle,
336};
 
337
338apic_driver(apic_numachip2);

  1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Numascale NumaConnect-Specific APIC Code
  7 *
  8 * Copyright (C) 2011 Numascale AS. All rights reserved.
  9 *
 10 * Send feedback to <support@numascale.com>
 11 *
 12 */
 13
 14#include <linux/errno.h>
 15#include <linux/threads.h>
 16#include <linux/cpumask.h>
 17#include <linux/string.h>
 18#include <linux/kernel.h>
 19#include <linux/module.h>
 20#include <linux/ctype.h>
 21#include <linux/init.h>
 22#include <linux/hardirq.h>
 23#include <linux/delay.h>
 24
 
 25#include <asm/numachip/numachip_csr.h>
 26#include <asm/smp.h>
 27#include <asm/apic.h>
 28#include <asm/ipi.h>
 29#include <asm/apic_flat_64.h>
 30
 31static int numachip_system __read_mostly;
 
 
 32
 33static struct apic apic_numachip __read_mostly;
 
 
 
 34
 35static unsigned int get_apic_id(unsigned long x)
 36{
 37	unsigned long value;
 38	unsigned int id;
 39
 40	rdmsrl(MSR_FAM10H_NODE_ID, value);
 41	id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U);
 
 
 42
 43	return id;
 44}
 45
 46static unsigned long set_apic_id(unsigned int id)
 
 
 
 
 
 47{
 48	unsigned long x;
 49
 50	x = ((id & 0xffU) << 24);
 51	return x;
 52}
 53
 54static unsigned int read_xapic_id(void)
 55{
 56	return get_apic_id(apic_read(APIC_ID));
 57}
 58
 59static int numachip_apic_id_valid(int apicid)
 60{
 61	/* Trust what bootloader passes in MADT */
 62	return 1;
 63}
 64
 65static int numachip_apic_id_registered(void)
 66{
 67	return physid_isset(read_xapic_id(), phys_cpu_present_map);
 68}
 69
 70static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
 71{
 72	return initial_apic_id >> index_msb;
 73}
 74
 75static const struct cpumask *numachip_target_cpus(void)
 76{
 77	return cpu_online_mask;
 78}
 79
 80static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask)
 81{
 82	cpumask_clear(retmask);
 83	cpumask_set_cpu(cpu, retmask);
 84}
 85
 86static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 87{
 88	union numachip_csr_g3_ext_irq_gen int_gen;
 89
 90	int_gen.s._destination_apic_id = phys_apicid;
 91	int_gen.s._vector = 0;
 92	int_gen.s._msgtype = APIC_DM_INIT >> 8;
 93	int_gen.s._index = 0;
 94
 95	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
 96
 97	int_gen.s._msgtype = APIC_DM_STARTUP >> 8;
 98	int_gen.s._vector = start_rip >> 12;
 99
100	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
101
102	atomic_set(&init_deasserted, 1);
103	return 0;
104}
105
106static void numachip_send_IPI_one(int cpu, int vector)
107{
108	union numachip_csr_g3_ext_irq_gen int_gen;
109	int apicid = per_cpu(x86_cpu_to_apicid, cpu);
110
111	int_gen.s._destination_apic_id = apicid;
112	int_gen.s._vector = vector;
113	int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;
114	int_gen.s._index = 0;
115
116	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
117}
118
119static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
120{
121	unsigned int cpu;
122
123	for_each_cpu(cpu, mask)
124		numachip_send_IPI_one(cpu, vector);
125}
126
127static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
128						int vector)
129{
130	unsigned int this_cpu = smp_processor_id();
131	unsigned int cpu;
132
133	for_each_cpu(cpu, mask) {
134		if (cpu != this_cpu)
135			numachip_send_IPI_one(cpu, vector);
136	}
137}
138
139static void numachip_send_IPI_allbutself(int vector)
140{
141	unsigned int this_cpu = smp_processor_id();
142	unsigned int cpu;
143
144	for_each_online_cpu(cpu) {
145		if (cpu != this_cpu)
146			numachip_send_IPI_one(cpu, vector);
147	}
148}
149
150static void numachip_send_IPI_all(int vector)
151{
152	numachip_send_IPI_mask(cpu_online_mask, vector);
153}
154
155static void numachip_send_IPI_self(int vector)
156{
157	__default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
158}
159
160static unsigned int numachip_cpu_mask_to_apicid(const struct cpumask *cpumask)
161{
162	int cpu;
 
163
164	/*
165	 * We're using fixed IRQ delivery, can only return one phys APIC ID.
166	 * May as well be the first.
167	 */
168	cpu = cpumask_first(cpumask);
169	if (likely((unsigned)cpu < nr_cpu_ids))
170		return per_cpu(x86_cpu_to_apicid, cpu);
171
172	return BAD_APICID;
173}
174
175static unsigned int
176numachip_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
177				const struct cpumask *andmask)
178{
179	int cpu;
 
 
 
180
181	/*
182	 * We're using fixed IRQ delivery, can only return one phys APIC ID.
183	 * May as well be the first.
184	 */
185	for_each_cpu_and(cpu, cpumask, andmask) {
186		if (cpumask_test_cpu(cpu, cpu_online_mask))
187			break;
188	}
189	return per_cpu(x86_cpu_to_apicid, cpu);
 
190}
191
192static int __init numachip_probe(void)
193{
194	return apic == &apic_numachip;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
195}
 
196
197static void __init map_csrs(void)
198{
199	printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n",
200		NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1);
201	init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
 
 
202
203	printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n",
204		NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1);
205	init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
206}
207
208static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
209{
 
 
 
 
 
 
 
 
210
211	if (c->phys_proc_id != node) {
212		c->phys_proc_id = node;
213		per_cpu(cpu_llc_id, smp_processor_id()) = node;
214	}
215}
216
217static int __init numachip_system_init(void)
 
218{
219	unsigned int val;
 
220
221	if (!numachip_system)
222		return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
223
224	x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
 
 
 
 
 
225
226	map_csrs();
 
227
228	val = read_lcsr(CSR_G0_NODE_IDS);
229	printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val);
230
231	return 0;
232}
233early_initcall(numachip_system_init);
 
 
 
234
235static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
236{
237	if (!strncmp(oem_id, "NUMASC", 6)) {
238		numachip_system = 1;
239		return 1;
240	}
241
242	return 0;
243}
 
 
 
 
 
 
244
245static struct apic apic_numachip __refconst = {
246
247	.name				= "NumaConnect system",
248	.probe				= numachip_probe,
249	.acpi_madt_oem_check		= numachip_acpi_madt_oem_check,
 
250	.apic_id_valid			= numachip_apic_id_valid,
251	.apic_id_registered		= numachip_apic_id_registered,
252
253	.irq_delivery_mode		= dest_Fixed,
254	.irq_dest_mode			= 0, /* physical */
255
256	.target_cpus			= numachip_target_cpus,
257	.disable_esr			= 0,
258	.dest_logical			= 0,
259	.check_apicid_used		= NULL,
260	.check_apicid_present		= NULL,
261
262	.vector_allocation_domain	= numachip_vector_allocation_domain,
263	.init_apic_ldr			= flat_init_apic_ldr,
264
265	.ioapic_phys_id_map		= NULL,
266	.setup_apic_routing		= NULL,
267	.multi_timer_check		= NULL,
268	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
269	.apicid_to_cpu_present		= NULL,
270	.setup_portio_remap		= NULL,
271	.check_phys_apicid_present	= default_check_phys_apicid_present,
272	.enable_apic_mode		= NULL,
273	.phys_pkg_id			= numachip_phys_pkg_id,
274	.mps_oem_check			= NULL,
275
276	.get_apic_id			= get_apic_id,
277	.set_apic_id			= set_apic_id,
278	.apic_id_mask			= 0xffU << 24,
279
280	.cpu_mask_to_apicid		= numachip_cpu_mask_to_apicid,
281	.cpu_mask_to_apicid_and		= numachip_cpu_mask_to_apicid_and,
282
 
283	.send_IPI_mask			= numachip_send_IPI_mask,
284	.send_IPI_mask_allbutself	= numachip_send_IPI_mask_allbutself,
285	.send_IPI_allbutself		= numachip_send_IPI_allbutself,
286	.send_IPI_all			= numachip_send_IPI_all,
287	.send_IPI_self			= numachip_send_IPI_self,
288
289	.wakeup_secondary_cpu		= numachip_wakeup_secondary,
290	.trampoline_phys_low		= DEFAULT_TRAMPOLINE_PHYS_LOW,
291	.trampoline_phys_high		= DEFAULT_TRAMPOLINE_PHYS_HIGH,
292	.wait_for_init_deassert		= NULL,
293	.smp_callin_clear_local_apic	= NULL,
294	.inquire_remote_apic		= NULL, /* REMRD not supported */
295
296	.read				= native_apic_mem_read,
297	.write				= native_apic_mem_write,
298	.eoi_write			= native_apic_mem_write,
299	.icr_read			= native_apic_icr_read,
300	.icr_write			= native_apic_icr_write,
301	.wait_icr_idle			= native_apic_wait_icr_idle,
302	.safe_wait_icr_idle		= native_safe_apic_wait_icr_idle,
303};
304apic_driver(apic_numachip);
305