1/*
  2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
  3 *
  4 *   This program is free software; you can redistribute it and/or
  5 *   modify it under the terms of the GNU General Public License
  6 *   as published by the Free Software Foundation, version 2.
  7 *
  8 *   This program is distributed in the hope that it will be useful, but
  9 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 10 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 11 *   NON INFRINGEMENT.  See the GNU General Public License for
 12 *   more details.
 13 *
 14 * These routines make two important assumptions:
 15 *
 16 * 1. atomic_t is really an int and can be freely cast back and forth
 17 *    (validated in __init_atomic_per_cpu).
 18 *
 19 * 2. userspace uses sys_cmpxchg() for all atomic operations, thus using
 20 *    the same locking convention that all the kernel atomic routines use.
 21 */
 22
 23#ifndef _ASM_TILE_FUTEX_H
 24#define _ASM_TILE_FUTEX_H
 25
 26#ifndef __ASSEMBLY__
 27
 28#include <linux/futex.h>
 29#include <linux/uaccess.h>
 30#include <linux/errno.h>
 31#include <asm/atomic.h>
 32
 33/*
 34 * Support macros for futex operations.  Do not use these macros directly.
 35 * They assume "ret", "val", "oparg", and "uaddr" in the lexical context.
 36 * __futex_cmpxchg() additionally assumes "oldval".
 37 */
 38
 39#ifdef __tilegx__
 40
 41#define __futex_asm(OP) \
 42	asm("1: {" #OP " %1, %3, %4; movei %0, 0 }\n"		\
 43	    ".pushsection .fixup,\"ax\"\n"			\
 44	    "0: { movei %0, %5; j 9f }\n"			\
 45	    ".section __ex_table,\"a\"\n"			\
 46	    ".quad 1b, 0b\n"					\
 47	    ".popsection\n"					\
 48	    "9:"						\
 49	    : "=r" (ret), "=r" (val), "+m" (*(uaddr))		\
 50	    : "r" (uaddr), "r" (oparg), "i" (-EFAULT))
 51
 52#define __futex_set() __futex_asm(exch4)
 53#define __futex_add() __futex_asm(fetchadd4)
 54#define __futex_or() __futex_asm(fetchor4)
 55#define __futex_andn() ({ oparg = ~oparg; __futex_asm(fetchand4); })
 56#define __futex_cmpxchg() \
 57	({ __insn_mtspr(SPR_CMPEXCH_VALUE, oldval); __futex_asm(cmpexch4); })
 58
 59#define __futex_xor()						\
 60	({							\
 61		u32 oldval, n = oparg;				\
 62		if ((ret = __get_user(oldval, uaddr)) == 0) {	\
 63			do {					\
 64				oparg = oldval ^ n;		\
 65				__futex_cmpxchg();		\
 66			} while (ret == 0 && oldval != val);	\
 67		}						\
 68	})
 69
 70/* No need to prefetch, since the atomic ops go to the home cache anyway. */
 71#define __futex_prolog()
 72
 73#else
 74
 75#define __futex_call(FN)						\
 76	{								\
 77		struct __get_user gu = FN((u32 __force *)uaddr, lock, oparg); \
 78		val = gu.val;						\
 79		ret = gu.err;						\
 80	}
 81
 82#define __futex_set() __futex_call(__atomic_xchg)
 83#define __futex_add() __futex_call(__atomic_xchg_add)
 84#define __futex_or() __futex_call(__atomic_or)
 85#define __futex_andn() __futex_call(__atomic_andn)
 86#define __futex_xor() __futex_call(__atomic_xor)
 87
 88#define __futex_cmpxchg()						\
 89	{								\
 90		struct __get_user gu = __atomic_cmpxchg((u32 __force *)uaddr, \
 91							lock, oldval, oparg); \
 92		val = gu.val;						\
 93		ret = gu.err;						\
 94	}
 95
 96/*
 97 * Find the lock pointer for the atomic calls to use, and issue a
 98 * prefetch to the user address to bring it into cache.  Similar to
 99 * __atomic_setup(), but we can't do a read into the L1 since it might
100 * fault; instead we do a prefetch into the L2.
101 */
102#define __futex_prolog()					\
103	int *lock;						\
104	__insn_prefetch(uaddr);					\
105	lock = __atomic_hashed_lock((int __force *)uaddr)
106#endif
107
108static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
109{
110	int op = (encoded_op >> 28) & 7;
111	int cmp = (encoded_op >> 24) & 15;
112	int oparg = (encoded_op << 8) >> 20;
113	int cmparg = (encoded_op << 20) >> 20;
114	int uninitialized_var(val), ret;
115
116	__futex_prolog();
117
118	/* The 32-bit futex code makes this assumption, so validate it here. */
119	BUILD_BUG_ON(sizeof(atomic_t) != sizeof(int));
120
121	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
122		oparg = 1 << oparg;
123
124	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
125		return -EFAULT;
126
127	pagefault_disable();
128	switch (op) {
129	case FUTEX_OP_SET:
130		__futex_set();
131		break;
132	case FUTEX_OP_ADD:
133		__futex_add();
134		break;
135	case FUTEX_OP_OR:
136		__futex_or();
137		break;
138	case FUTEX_OP_ANDN:
139		__futex_andn();
140		break;
141	case FUTEX_OP_XOR:
142		__futex_xor();
143		break;
144	default:
145		ret = -ENOSYS;
146		break;
147	}
148	pagefault_enable();
149
150	if (!ret) {
151		switch (cmp) {
152		case FUTEX_OP_CMP_EQ:
153			ret = (val == cmparg);
154			break;
155		case FUTEX_OP_CMP_NE:
156			ret = (val != cmparg);
157			break;
158		case FUTEX_OP_CMP_LT:
159			ret = (val < cmparg);
160			break;
161		case FUTEX_OP_CMP_GE:
162			ret = (val >= cmparg);
163			break;
164		case FUTEX_OP_CMP_LE:
165			ret = (val <= cmparg);
166			break;
167		case FUTEX_OP_CMP_GT:
168			ret = (val > cmparg);
169			break;
170		default:
171			ret = -ENOSYS;
172		}
173	}
174	return ret;
175}
176
177static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
178						u32 oldval, u32 oparg)
179{
180	int ret, val;
181
182	__futex_prolog();
183
184	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
185		return -EFAULT;
186
187	__futex_cmpxchg();
188
189	*uval = val;
190	return ret;
191}
192
193#endif /* !__ASSEMBLY__ */
194
195#endif /* _ASM_TILE_FUTEX_H */