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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2017 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SLI_DEFS_H__
29#define __CVMX_SLI_DEFS_H__
30
31#include <uapi/asm/bitfield.h>
32
33#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
34static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
35{
36 switch (cvmx_get_octeon_family()) {
37 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
38 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
39 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
40 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
41 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
42 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
43 return 0x0000000000003CB0ull;
44 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
45 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
46 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
47 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
48 return 0x0000000000003CB0ull;
49 /* Else, fall through */
50 default:
51 return 0x0000000000023CB0ull;
52 }
53}
54
55
56union cvmx_sli_ctl_portx {
57 uint64_t u64;
58 struct cvmx_sli_ctl_portx_s {
59 __BITFIELD_FIELD(uint64_t reserved_22_63:42,
60 __BITFIELD_FIELD(uint64_t intd:1,
61 __BITFIELD_FIELD(uint64_t intc:1,
62 __BITFIELD_FIELD(uint64_t intb:1,
63 __BITFIELD_FIELD(uint64_t inta:1,
64 __BITFIELD_FIELD(uint64_t dis_port:1,
65 __BITFIELD_FIELD(uint64_t waitl_com:1,
66 __BITFIELD_FIELD(uint64_t intd_map:2,
67 __BITFIELD_FIELD(uint64_t intc_map:2,
68 __BITFIELD_FIELD(uint64_t intb_map:2,
69 __BITFIELD_FIELD(uint64_t inta_map:2,
70 __BITFIELD_FIELD(uint64_t ctlp_ro:1,
71 __BITFIELD_FIELD(uint64_t reserved_6_6:1,
72 __BITFIELD_FIELD(uint64_t ptlp_ro:1,
73 __BITFIELD_FIELD(uint64_t reserved_1_4:4,
74 __BITFIELD_FIELD(uint64_t wait_com:1,
75 ;))))))))))))))))
76 } s;
77};
78
79union cvmx_sli_mem_access_ctl {
80 uint64_t u64;
81 struct cvmx_sli_mem_access_ctl_s {
82 __BITFIELD_FIELD(uint64_t reserved_14_63:50,
83 __BITFIELD_FIELD(uint64_t max_word:4,
84 __BITFIELD_FIELD(uint64_t timer:10,
85 ;)))
86 } s;
87};
88
89union cvmx_sli_s2m_portx_ctl {
90 uint64_t u64;
91 struct cvmx_sli_s2m_portx_ctl_s {
92 __BITFIELD_FIELD(uint64_t reserved_5_63:59,
93 __BITFIELD_FIELD(uint64_t wind_d:1,
94 __BITFIELD_FIELD(uint64_t bar0_d:1,
95 __BITFIELD_FIELD(uint64_t mrrs:3,
96 ;))))
97 } s;
98};
99
100union cvmx_sli_mem_access_subidx {
101 uint64_t u64;
102 struct cvmx_sli_mem_access_subidx_s {
103 __BITFIELD_FIELD(uint64_t reserved_43_63:21,
104 __BITFIELD_FIELD(uint64_t zero:1,
105 __BITFIELD_FIELD(uint64_t port:3,
106 __BITFIELD_FIELD(uint64_t nmerge:1,
107 __BITFIELD_FIELD(uint64_t esr:2,
108 __BITFIELD_FIELD(uint64_t esw:2,
109 __BITFIELD_FIELD(uint64_t wtype:2,
110 __BITFIELD_FIELD(uint64_t rtype:2,
111 __BITFIELD_FIELD(uint64_t ba:30,
112 ;)))))))))
113 } s;
114 struct cvmx_sli_mem_access_subidx_cn68xx {
115 __BITFIELD_FIELD(uint64_t reserved_43_63:21,
116 __BITFIELD_FIELD(uint64_t zero:1,
117 __BITFIELD_FIELD(uint64_t port:3,
118 __BITFIELD_FIELD(uint64_t nmerge:1,
119 __BITFIELD_FIELD(uint64_t esr:2,
120 __BITFIELD_FIELD(uint64_t esw:2,
121 __BITFIELD_FIELD(uint64_t wtype:2,
122 __BITFIELD_FIELD(uint64_t rtype:2,
123 __BITFIELD_FIELD(uint64_t ba:28,
124 __BITFIELD_FIELD(uint64_t reserved_0_1:2,
125 ;))))))))))
126 } cn68xx;
127};
128
129#endif
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SLI_DEFS_H__
29#define __CVMX_SLI_DEFS_H__
30
31#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
32#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
33#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
34#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
35#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
36#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
37#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
38#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
39#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
40#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
41#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
42#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
43#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
44#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
45#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
46#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
47#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
48#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
49#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
50#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
51#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
52#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
53#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
54#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
55#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
56#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
57#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
58#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
59#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
60#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
61#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
62#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
63#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
64#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
65#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
66#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
67#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
68#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
69#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
70#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
71#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
72#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
73#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
74#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
75#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
76#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
77#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
78#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
79#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
80#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
81#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
82#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
83#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
84#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
85#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
86#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
87#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
88#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
89#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
90#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
91#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
92#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
93#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
94#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
95#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
96#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
97#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
98#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
99#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
100#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
101#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
102#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
103#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
104#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
105#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
106#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
107#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
108#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
109#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
110#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
111#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
112#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
113#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
114#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
115#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
116#define CVMX_SLI_STATE1 (0x0000000000000620ull)
117#define CVMX_SLI_STATE2 (0x0000000000000630ull)
118#define CVMX_SLI_STATE3 (0x0000000000000640ull)
119#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
120#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
121#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
122#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
123#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
124#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
125#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
126
127union cvmx_sli_bist_status {
128 uint64_t u64;
129 struct cvmx_sli_bist_status_s {
130 uint64_t reserved_32_63:32;
131 uint64_t ncb_req:1;
132 uint64_t n2p0_c:1;
133 uint64_t n2p0_o:1;
134 uint64_t n2p1_c:1;
135 uint64_t n2p1_o:1;
136 uint64_t cpl_p0:1;
137 uint64_t cpl_p1:1;
138 uint64_t reserved_19_24:6;
139 uint64_t p2n0_c0:1;
140 uint64_t p2n0_c1:1;
141 uint64_t p2n0_n:1;
142 uint64_t p2n0_p0:1;
143 uint64_t p2n0_p1:1;
144 uint64_t p2n1_c0:1;
145 uint64_t p2n1_c1:1;
146 uint64_t p2n1_n:1;
147 uint64_t p2n1_p0:1;
148 uint64_t p2n1_p1:1;
149 uint64_t reserved_6_8:3;
150 uint64_t dsi1_1:1;
151 uint64_t dsi1_0:1;
152 uint64_t dsi0_1:1;
153 uint64_t dsi0_0:1;
154 uint64_t msi:1;
155 uint64_t ncb_cmd:1;
156 } s;
157 struct cvmx_sli_bist_status_cn61xx {
158 uint64_t reserved_31_63:33;
159 uint64_t n2p0_c:1;
160 uint64_t n2p0_o:1;
161 uint64_t reserved_27_28:2;
162 uint64_t cpl_p0:1;
163 uint64_t cpl_p1:1;
164 uint64_t reserved_19_24:6;
165 uint64_t p2n0_c0:1;
166 uint64_t p2n0_c1:1;
167 uint64_t p2n0_n:1;
168 uint64_t p2n0_p0:1;
169 uint64_t p2n0_p1:1;
170 uint64_t p2n1_c0:1;
171 uint64_t p2n1_c1:1;
172 uint64_t p2n1_n:1;
173 uint64_t p2n1_p0:1;
174 uint64_t p2n1_p1:1;
175 uint64_t reserved_6_8:3;
176 uint64_t dsi1_1:1;
177 uint64_t dsi1_0:1;
178 uint64_t dsi0_1:1;
179 uint64_t dsi0_0:1;
180 uint64_t msi:1;
181 uint64_t ncb_cmd:1;
182 } cn61xx;
183 struct cvmx_sli_bist_status_cn63xx {
184 uint64_t reserved_31_63:33;
185 uint64_t n2p0_c:1;
186 uint64_t n2p0_o:1;
187 uint64_t n2p1_c:1;
188 uint64_t n2p1_o:1;
189 uint64_t cpl_p0:1;
190 uint64_t cpl_p1:1;
191 uint64_t reserved_19_24:6;
192 uint64_t p2n0_c0:1;
193 uint64_t p2n0_c1:1;
194 uint64_t p2n0_n:1;
195 uint64_t p2n0_p0:1;
196 uint64_t p2n0_p1:1;
197 uint64_t p2n1_c0:1;
198 uint64_t p2n1_c1:1;
199 uint64_t p2n1_n:1;
200 uint64_t p2n1_p0:1;
201 uint64_t p2n1_p1:1;
202 uint64_t reserved_6_8:3;
203 uint64_t dsi1_1:1;
204 uint64_t dsi1_0:1;
205 uint64_t dsi0_1:1;
206 uint64_t dsi0_0:1;
207 uint64_t msi:1;
208 uint64_t ncb_cmd:1;
209 } cn63xx;
210 struct cvmx_sli_bist_status_cn63xx cn63xxp1;
211 struct cvmx_sli_bist_status_cn61xx cn66xx;
212 struct cvmx_sli_bist_status_s cn68xx;
213 struct cvmx_sli_bist_status_s cn68xxp1;
214};
215
216union cvmx_sli_ctl_portx {
217 uint64_t u64;
218 struct cvmx_sli_ctl_portx_s {
219 uint64_t reserved_22_63:42;
220 uint64_t intd:1;
221 uint64_t intc:1;
222 uint64_t intb:1;
223 uint64_t inta:1;
224 uint64_t dis_port:1;
225 uint64_t waitl_com:1;
226 uint64_t intd_map:2;
227 uint64_t intc_map:2;
228 uint64_t intb_map:2;
229 uint64_t inta_map:2;
230 uint64_t ctlp_ro:1;
231 uint64_t reserved_6_6:1;
232 uint64_t ptlp_ro:1;
233 uint64_t reserved_1_4:4;
234 uint64_t wait_com:1;
235 } s;
236 struct cvmx_sli_ctl_portx_s cn61xx;
237 struct cvmx_sli_ctl_portx_s cn63xx;
238 struct cvmx_sli_ctl_portx_s cn63xxp1;
239 struct cvmx_sli_ctl_portx_s cn66xx;
240 struct cvmx_sli_ctl_portx_s cn68xx;
241 struct cvmx_sli_ctl_portx_s cn68xxp1;
242};
243
244union cvmx_sli_ctl_status {
245 uint64_t u64;
246 struct cvmx_sli_ctl_status_s {
247 uint64_t reserved_20_63:44;
248 uint64_t p1_ntags:6;
249 uint64_t p0_ntags:6;
250 uint64_t chip_rev:8;
251 } s;
252 struct cvmx_sli_ctl_status_cn61xx {
253 uint64_t reserved_14_63:50;
254 uint64_t p0_ntags:6;
255 uint64_t chip_rev:8;
256 } cn61xx;
257 struct cvmx_sli_ctl_status_s cn63xx;
258 struct cvmx_sli_ctl_status_s cn63xxp1;
259 struct cvmx_sli_ctl_status_cn61xx cn66xx;
260 struct cvmx_sli_ctl_status_s cn68xx;
261 struct cvmx_sli_ctl_status_s cn68xxp1;
262};
263
264union cvmx_sli_data_out_cnt {
265 uint64_t u64;
266 struct cvmx_sli_data_out_cnt_s {
267 uint64_t reserved_44_63:20;
268 uint64_t p1_ucnt:16;
269 uint64_t p1_fcnt:6;
270 uint64_t p0_ucnt:16;
271 uint64_t p0_fcnt:6;
272 } s;
273 struct cvmx_sli_data_out_cnt_s cn61xx;
274 struct cvmx_sli_data_out_cnt_s cn63xx;
275 struct cvmx_sli_data_out_cnt_s cn63xxp1;
276 struct cvmx_sli_data_out_cnt_s cn66xx;
277 struct cvmx_sli_data_out_cnt_s cn68xx;
278 struct cvmx_sli_data_out_cnt_s cn68xxp1;
279};
280
281union cvmx_sli_dbg_data {
282 uint64_t u64;
283 struct cvmx_sli_dbg_data_s {
284 uint64_t reserved_18_63:46;
285 uint64_t dsel_ext:1;
286 uint64_t data:17;
287 } s;
288 struct cvmx_sli_dbg_data_s cn61xx;
289 struct cvmx_sli_dbg_data_s cn63xx;
290 struct cvmx_sli_dbg_data_s cn63xxp1;
291 struct cvmx_sli_dbg_data_s cn66xx;
292 struct cvmx_sli_dbg_data_s cn68xx;
293 struct cvmx_sli_dbg_data_s cn68xxp1;
294};
295
296union cvmx_sli_dbg_select {
297 uint64_t u64;
298 struct cvmx_sli_dbg_select_s {
299 uint64_t reserved_33_63:31;
300 uint64_t adbg_sel:1;
301 uint64_t dbg_sel:32;
302 } s;
303 struct cvmx_sli_dbg_select_s cn61xx;
304 struct cvmx_sli_dbg_select_s cn63xx;
305 struct cvmx_sli_dbg_select_s cn63xxp1;
306 struct cvmx_sli_dbg_select_s cn66xx;
307 struct cvmx_sli_dbg_select_s cn68xx;
308 struct cvmx_sli_dbg_select_s cn68xxp1;
309};
310
311union cvmx_sli_dmax_cnt {
312 uint64_t u64;
313 struct cvmx_sli_dmax_cnt_s {
314 uint64_t reserved_32_63:32;
315 uint64_t cnt:32;
316 } s;
317 struct cvmx_sli_dmax_cnt_s cn61xx;
318 struct cvmx_sli_dmax_cnt_s cn63xx;
319 struct cvmx_sli_dmax_cnt_s cn63xxp1;
320 struct cvmx_sli_dmax_cnt_s cn66xx;
321 struct cvmx_sli_dmax_cnt_s cn68xx;
322 struct cvmx_sli_dmax_cnt_s cn68xxp1;
323};
324
325union cvmx_sli_dmax_int_level {
326 uint64_t u64;
327 struct cvmx_sli_dmax_int_level_s {
328 uint64_t time:32;
329 uint64_t cnt:32;
330 } s;
331 struct cvmx_sli_dmax_int_level_s cn61xx;
332 struct cvmx_sli_dmax_int_level_s cn63xx;
333 struct cvmx_sli_dmax_int_level_s cn63xxp1;
334 struct cvmx_sli_dmax_int_level_s cn66xx;
335 struct cvmx_sli_dmax_int_level_s cn68xx;
336 struct cvmx_sli_dmax_int_level_s cn68xxp1;
337};
338
339union cvmx_sli_dmax_tim {
340 uint64_t u64;
341 struct cvmx_sli_dmax_tim_s {
342 uint64_t reserved_32_63:32;
343 uint64_t tim:32;
344 } s;
345 struct cvmx_sli_dmax_tim_s cn61xx;
346 struct cvmx_sli_dmax_tim_s cn63xx;
347 struct cvmx_sli_dmax_tim_s cn63xxp1;
348 struct cvmx_sli_dmax_tim_s cn66xx;
349 struct cvmx_sli_dmax_tim_s cn68xx;
350 struct cvmx_sli_dmax_tim_s cn68xxp1;
351};
352
353union cvmx_sli_int_enb_ciu {
354 uint64_t u64;
355 struct cvmx_sli_int_enb_ciu_s {
356 uint64_t reserved_62_63:2;
357 uint64_t pipe_err:1;
358 uint64_t ill_pad:1;
359 uint64_t sprt3_err:1;
360 uint64_t sprt2_err:1;
361 uint64_t sprt1_err:1;
362 uint64_t sprt0_err:1;
363 uint64_t pins_err:1;
364 uint64_t pop_err:1;
365 uint64_t pdi_err:1;
366 uint64_t pgl_err:1;
367 uint64_t pin_bp:1;
368 uint64_t pout_err:1;
369 uint64_t psldbof:1;
370 uint64_t pidbof:1;
371 uint64_t reserved_38_47:10;
372 uint64_t dtime:2;
373 uint64_t dcnt:2;
374 uint64_t dmafi:2;
375 uint64_t reserved_28_31:4;
376 uint64_t m3_un_wi:1;
377 uint64_t m3_un_b0:1;
378 uint64_t m3_up_wi:1;
379 uint64_t m3_up_b0:1;
380 uint64_t m2_un_wi:1;
381 uint64_t m2_un_b0:1;
382 uint64_t m2_up_wi:1;
383 uint64_t m2_up_b0:1;
384 uint64_t reserved_18_19:2;
385 uint64_t mio_int1:1;
386 uint64_t mio_int0:1;
387 uint64_t m1_un_wi:1;
388 uint64_t m1_un_b0:1;
389 uint64_t m1_up_wi:1;
390 uint64_t m1_up_b0:1;
391 uint64_t m0_un_wi:1;
392 uint64_t m0_un_b0:1;
393 uint64_t m0_up_wi:1;
394 uint64_t m0_up_b0:1;
395 uint64_t reserved_6_7:2;
396 uint64_t ptime:1;
397 uint64_t pcnt:1;
398 uint64_t iob2big:1;
399 uint64_t bar0_to:1;
400 uint64_t reserved_1_1:1;
401 uint64_t rml_to:1;
402 } s;
403 struct cvmx_sli_int_enb_ciu_cn61xx {
404 uint64_t reserved_61_63:3;
405 uint64_t ill_pad:1;
406 uint64_t sprt3_err:1;
407 uint64_t sprt2_err:1;
408 uint64_t sprt1_err:1;
409 uint64_t sprt0_err:1;
410 uint64_t pins_err:1;
411 uint64_t pop_err:1;
412 uint64_t pdi_err:1;
413 uint64_t pgl_err:1;
414 uint64_t pin_bp:1;
415 uint64_t pout_err:1;
416 uint64_t psldbof:1;
417 uint64_t pidbof:1;
418 uint64_t reserved_38_47:10;
419 uint64_t dtime:2;
420 uint64_t dcnt:2;
421 uint64_t dmafi:2;
422 uint64_t reserved_28_31:4;
423 uint64_t m3_un_wi:1;
424 uint64_t m3_un_b0:1;
425 uint64_t m3_up_wi:1;
426 uint64_t m3_up_b0:1;
427 uint64_t m2_un_wi:1;
428 uint64_t m2_un_b0:1;
429 uint64_t m2_up_wi:1;
430 uint64_t m2_up_b0:1;
431 uint64_t reserved_18_19:2;
432 uint64_t mio_int1:1;
433 uint64_t mio_int0:1;
434 uint64_t m1_un_wi:1;
435 uint64_t m1_un_b0:1;
436 uint64_t m1_up_wi:1;
437 uint64_t m1_up_b0:1;
438 uint64_t m0_un_wi:1;
439 uint64_t m0_un_b0:1;
440 uint64_t m0_up_wi:1;
441 uint64_t m0_up_b0:1;
442 uint64_t reserved_6_7:2;
443 uint64_t ptime:1;
444 uint64_t pcnt:1;
445 uint64_t iob2big:1;
446 uint64_t bar0_to:1;
447 uint64_t reserved_1_1:1;
448 uint64_t rml_to:1;
449 } cn61xx;
450 struct cvmx_sli_int_enb_ciu_cn63xx {
451 uint64_t reserved_61_63:3;
452 uint64_t ill_pad:1;
453 uint64_t reserved_58_59:2;
454 uint64_t sprt1_err:1;
455 uint64_t sprt0_err:1;
456 uint64_t pins_err:1;
457 uint64_t pop_err:1;
458 uint64_t pdi_err:1;
459 uint64_t pgl_err:1;
460 uint64_t pin_bp:1;
461 uint64_t pout_err:1;
462 uint64_t psldbof:1;
463 uint64_t pidbof:1;
464 uint64_t reserved_38_47:10;
465 uint64_t dtime:2;
466 uint64_t dcnt:2;
467 uint64_t dmafi:2;
468 uint64_t reserved_18_31:14;
469 uint64_t mio_int1:1;
470 uint64_t mio_int0:1;
471 uint64_t m1_un_wi:1;
472 uint64_t m1_un_b0:1;
473 uint64_t m1_up_wi:1;
474 uint64_t m1_up_b0:1;
475 uint64_t m0_un_wi:1;
476 uint64_t m0_un_b0:1;
477 uint64_t m0_up_wi:1;
478 uint64_t m0_up_b0:1;
479 uint64_t reserved_6_7:2;
480 uint64_t ptime:1;
481 uint64_t pcnt:1;
482 uint64_t iob2big:1;
483 uint64_t bar0_to:1;
484 uint64_t reserved_1_1:1;
485 uint64_t rml_to:1;
486 } cn63xx;
487 struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
488 struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
489 struct cvmx_sli_int_enb_ciu_cn68xx {
490 uint64_t reserved_62_63:2;
491 uint64_t pipe_err:1;
492 uint64_t ill_pad:1;
493 uint64_t reserved_58_59:2;
494 uint64_t sprt1_err:1;
495 uint64_t sprt0_err:1;
496 uint64_t pins_err:1;
497 uint64_t pop_err:1;
498 uint64_t pdi_err:1;
499 uint64_t pgl_err:1;
500 uint64_t reserved_51_51:1;
501 uint64_t pout_err:1;
502 uint64_t psldbof:1;
503 uint64_t pidbof:1;
504 uint64_t reserved_38_47:10;
505 uint64_t dtime:2;
506 uint64_t dcnt:2;
507 uint64_t dmafi:2;
508 uint64_t reserved_18_31:14;
509 uint64_t mio_int1:1;
510 uint64_t mio_int0:1;
511 uint64_t m1_un_wi:1;
512 uint64_t m1_un_b0:1;
513 uint64_t m1_up_wi:1;
514 uint64_t m1_up_b0:1;
515 uint64_t m0_un_wi:1;
516 uint64_t m0_un_b0:1;
517 uint64_t m0_up_wi:1;
518 uint64_t m0_up_b0:1;
519 uint64_t reserved_6_7:2;
520 uint64_t ptime:1;
521 uint64_t pcnt:1;
522 uint64_t iob2big:1;
523 uint64_t bar0_to:1;
524 uint64_t reserved_1_1:1;
525 uint64_t rml_to:1;
526 } cn68xx;
527 struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
528};
529
530union cvmx_sli_int_enb_portx {
531 uint64_t u64;
532 struct cvmx_sli_int_enb_portx_s {
533 uint64_t reserved_62_63:2;
534 uint64_t pipe_err:1;
535 uint64_t ill_pad:1;
536 uint64_t sprt3_err:1;
537 uint64_t sprt2_err:1;
538 uint64_t sprt1_err:1;
539 uint64_t sprt0_err:1;
540 uint64_t pins_err:1;
541 uint64_t pop_err:1;
542 uint64_t pdi_err:1;
543 uint64_t pgl_err:1;
544 uint64_t pin_bp:1;
545 uint64_t pout_err:1;
546 uint64_t psldbof:1;
547 uint64_t pidbof:1;
548 uint64_t reserved_38_47:10;
549 uint64_t dtime:2;
550 uint64_t dcnt:2;
551 uint64_t dmafi:2;
552 uint64_t reserved_28_31:4;
553 uint64_t m3_un_wi:1;
554 uint64_t m3_un_b0:1;
555 uint64_t m3_up_wi:1;
556 uint64_t m3_up_b0:1;
557 uint64_t m2_un_wi:1;
558 uint64_t m2_un_b0:1;
559 uint64_t m2_up_wi:1;
560 uint64_t m2_up_b0:1;
561 uint64_t mac1_int:1;
562 uint64_t mac0_int:1;
563 uint64_t mio_int1:1;
564 uint64_t mio_int0:1;
565 uint64_t m1_un_wi:1;
566 uint64_t m1_un_b0:1;
567 uint64_t m1_up_wi:1;
568 uint64_t m1_up_b0:1;
569 uint64_t m0_un_wi:1;
570 uint64_t m0_un_b0:1;
571 uint64_t m0_up_wi:1;
572 uint64_t m0_up_b0:1;
573 uint64_t reserved_6_7:2;
574 uint64_t ptime:1;
575 uint64_t pcnt:1;
576 uint64_t iob2big:1;
577 uint64_t bar0_to:1;
578 uint64_t reserved_1_1:1;
579 uint64_t rml_to:1;
580 } s;
581 struct cvmx_sli_int_enb_portx_cn61xx {
582 uint64_t reserved_61_63:3;
583 uint64_t ill_pad:1;
584 uint64_t sprt3_err:1;
585 uint64_t sprt2_err:1;
586 uint64_t sprt1_err:1;
587 uint64_t sprt0_err:1;
588 uint64_t pins_err:1;
589 uint64_t pop_err:1;
590 uint64_t pdi_err:1;
591 uint64_t pgl_err:1;
592 uint64_t pin_bp:1;
593 uint64_t pout_err:1;
594 uint64_t psldbof:1;
595 uint64_t pidbof:1;
596 uint64_t reserved_38_47:10;
597 uint64_t dtime:2;
598 uint64_t dcnt:2;
599 uint64_t dmafi:2;
600 uint64_t reserved_28_31:4;
601 uint64_t m3_un_wi:1;
602 uint64_t m3_un_b0:1;
603 uint64_t m3_up_wi:1;
604 uint64_t m3_up_b0:1;
605 uint64_t m2_un_wi:1;
606 uint64_t m2_un_b0:1;
607 uint64_t m2_up_wi:1;
608 uint64_t m2_up_b0:1;
609 uint64_t mac1_int:1;
610 uint64_t mac0_int:1;
611 uint64_t mio_int1:1;
612 uint64_t mio_int0:1;
613 uint64_t m1_un_wi:1;
614 uint64_t m1_un_b0:1;
615 uint64_t m1_up_wi:1;
616 uint64_t m1_up_b0:1;
617 uint64_t m0_un_wi:1;
618 uint64_t m0_un_b0:1;
619 uint64_t m0_up_wi:1;
620 uint64_t m0_up_b0:1;
621 uint64_t reserved_6_7:2;
622 uint64_t ptime:1;
623 uint64_t pcnt:1;
624 uint64_t iob2big:1;
625 uint64_t bar0_to:1;
626 uint64_t reserved_1_1:1;
627 uint64_t rml_to:1;
628 } cn61xx;
629 struct cvmx_sli_int_enb_portx_cn63xx {
630 uint64_t reserved_61_63:3;
631 uint64_t ill_pad:1;
632 uint64_t reserved_58_59:2;
633 uint64_t sprt1_err:1;
634 uint64_t sprt0_err:1;
635 uint64_t pins_err:1;
636 uint64_t pop_err:1;
637 uint64_t pdi_err:1;
638 uint64_t pgl_err:1;
639 uint64_t pin_bp:1;
640 uint64_t pout_err:1;
641 uint64_t psldbof:1;
642 uint64_t pidbof:1;
643 uint64_t reserved_38_47:10;
644 uint64_t dtime:2;
645 uint64_t dcnt:2;
646 uint64_t dmafi:2;
647 uint64_t reserved_20_31:12;
648 uint64_t mac1_int:1;
649 uint64_t mac0_int:1;
650 uint64_t mio_int1:1;
651 uint64_t mio_int0:1;
652 uint64_t m1_un_wi:1;
653 uint64_t m1_un_b0:1;
654 uint64_t m1_up_wi:1;
655 uint64_t m1_up_b0:1;
656 uint64_t m0_un_wi:1;
657 uint64_t m0_un_b0:1;
658 uint64_t m0_up_wi:1;
659 uint64_t m0_up_b0:1;
660 uint64_t reserved_6_7:2;
661 uint64_t ptime:1;
662 uint64_t pcnt:1;
663 uint64_t iob2big:1;
664 uint64_t bar0_to:1;
665 uint64_t reserved_1_1:1;
666 uint64_t rml_to:1;
667 } cn63xx;
668 struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
669 struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
670 struct cvmx_sli_int_enb_portx_cn68xx {
671 uint64_t reserved_62_63:2;
672 uint64_t pipe_err:1;
673 uint64_t ill_pad:1;
674 uint64_t reserved_58_59:2;
675 uint64_t sprt1_err:1;
676 uint64_t sprt0_err:1;
677 uint64_t pins_err:1;
678 uint64_t pop_err:1;
679 uint64_t pdi_err:1;
680 uint64_t pgl_err:1;
681 uint64_t reserved_51_51:1;
682 uint64_t pout_err:1;
683 uint64_t psldbof:1;
684 uint64_t pidbof:1;
685 uint64_t reserved_38_47:10;
686 uint64_t dtime:2;
687 uint64_t dcnt:2;
688 uint64_t dmafi:2;
689 uint64_t reserved_20_31:12;
690 uint64_t mac1_int:1;
691 uint64_t mac0_int:1;
692 uint64_t mio_int1:1;
693 uint64_t mio_int0:1;
694 uint64_t m1_un_wi:1;
695 uint64_t m1_un_b0:1;
696 uint64_t m1_up_wi:1;
697 uint64_t m1_up_b0:1;
698 uint64_t m0_un_wi:1;
699 uint64_t m0_un_b0:1;
700 uint64_t m0_up_wi:1;
701 uint64_t m0_up_b0:1;
702 uint64_t reserved_6_7:2;
703 uint64_t ptime:1;
704 uint64_t pcnt:1;
705 uint64_t iob2big:1;
706 uint64_t bar0_to:1;
707 uint64_t reserved_1_1:1;
708 uint64_t rml_to:1;
709 } cn68xx;
710 struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
711};
712
713union cvmx_sli_int_sum {
714 uint64_t u64;
715 struct cvmx_sli_int_sum_s {
716 uint64_t reserved_62_63:2;
717 uint64_t pipe_err:1;
718 uint64_t ill_pad:1;
719 uint64_t sprt3_err:1;
720 uint64_t sprt2_err:1;
721 uint64_t sprt1_err:1;
722 uint64_t sprt0_err:1;
723 uint64_t pins_err:1;
724 uint64_t pop_err:1;
725 uint64_t pdi_err:1;
726 uint64_t pgl_err:1;
727 uint64_t pin_bp:1;
728 uint64_t pout_err:1;
729 uint64_t psldbof:1;
730 uint64_t pidbof:1;
731 uint64_t reserved_38_47:10;
732 uint64_t dtime:2;
733 uint64_t dcnt:2;
734 uint64_t dmafi:2;
735 uint64_t reserved_28_31:4;
736 uint64_t m3_un_wi:1;
737 uint64_t m3_un_b0:1;
738 uint64_t m3_up_wi:1;
739 uint64_t m3_up_b0:1;
740 uint64_t m2_un_wi:1;
741 uint64_t m2_un_b0:1;
742 uint64_t m2_up_wi:1;
743 uint64_t m2_up_b0:1;
744 uint64_t mac1_int:1;
745 uint64_t mac0_int:1;
746 uint64_t mio_int1:1;
747 uint64_t mio_int0:1;
748 uint64_t m1_un_wi:1;
749 uint64_t m1_un_b0:1;
750 uint64_t m1_up_wi:1;
751 uint64_t m1_up_b0:1;
752 uint64_t m0_un_wi:1;
753 uint64_t m0_un_b0:1;
754 uint64_t m0_up_wi:1;
755 uint64_t m0_up_b0:1;
756 uint64_t reserved_6_7:2;
757 uint64_t ptime:1;
758 uint64_t pcnt:1;
759 uint64_t iob2big:1;
760 uint64_t bar0_to:1;
761 uint64_t reserved_1_1:1;
762 uint64_t rml_to:1;
763 } s;
764 struct cvmx_sli_int_sum_cn61xx {
765 uint64_t reserved_61_63:3;
766 uint64_t ill_pad:1;
767 uint64_t sprt3_err:1;
768 uint64_t sprt2_err:1;
769 uint64_t sprt1_err:1;
770 uint64_t sprt0_err:1;
771 uint64_t pins_err:1;
772 uint64_t pop_err:1;
773 uint64_t pdi_err:1;
774 uint64_t pgl_err:1;
775 uint64_t pin_bp:1;
776 uint64_t pout_err:1;
777 uint64_t psldbof:1;
778 uint64_t pidbof:1;
779 uint64_t reserved_38_47:10;
780 uint64_t dtime:2;
781 uint64_t dcnt:2;
782 uint64_t dmafi:2;
783 uint64_t reserved_28_31:4;
784 uint64_t m3_un_wi:1;
785 uint64_t m3_un_b0:1;
786 uint64_t m3_up_wi:1;
787 uint64_t m3_up_b0:1;
788 uint64_t m2_un_wi:1;
789 uint64_t m2_un_b0:1;
790 uint64_t m2_up_wi:1;
791 uint64_t m2_up_b0:1;
792 uint64_t mac1_int:1;
793 uint64_t mac0_int:1;
794 uint64_t mio_int1:1;
795 uint64_t mio_int0:1;
796 uint64_t m1_un_wi:1;
797 uint64_t m1_un_b0:1;
798 uint64_t m1_up_wi:1;
799 uint64_t m1_up_b0:1;
800 uint64_t m0_un_wi:1;
801 uint64_t m0_un_b0:1;
802 uint64_t m0_up_wi:1;
803 uint64_t m0_up_b0:1;
804 uint64_t reserved_6_7:2;
805 uint64_t ptime:1;
806 uint64_t pcnt:1;
807 uint64_t iob2big:1;
808 uint64_t bar0_to:1;
809 uint64_t reserved_1_1:1;
810 uint64_t rml_to:1;
811 } cn61xx;
812 struct cvmx_sli_int_sum_cn63xx {
813 uint64_t reserved_61_63:3;
814 uint64_t ill_pad:1;
815 uint64_t reserved_58_59:2;
816 uint64_t sprt1_err:1;
817 uint64_t sprt0_err:1;
818 uint64_t pins_err:1;
819 uint64_t pop_err:1;
820 uint64_t pdi_err:1;
821 uint64_t pgl_err:1;
822 uint64_t pin_bp:1;
823 uint64_t pout_err:1;
824 uint64_t psldbof:1;
825 uint64_t pidbof:1;
826 uint64_t reserved_38_47:10;
827 uint64_t dtime:2;
828 uint64_t dcnt:2;
829 uint64_t dmafi:2;
830 uint64_t reserved_20_31:12;
831 uint64_t mac1_int:1;
832 uint64_t mac0_int:1;
833 uint64_t mio_int1:1;
834 uint64_t mio_int0:1;
835 uint64_t m1_un_wi:1;
836 uint64_t m1_un_b0:1;
837 uint64_t m1_up_wi:1;
838 uint64_t m1_up_b0:1;
839 uint64_t m0_un_wi:1;
840 uint64_t m0_un_b0:1;
841 uint64_t m0_up_wi:1;
842 uint64_t m0_up_b0:1;
843 uint64_t reserved_6_7:2;
844 uint64_t ptime:1;
845 uint64_t pcnt:1;
846 uint64_t iob2big:1;
847 uint64_t bar0_to:1;
848 uint64_t reserved_1_1:1;
849 uint64_t rml_to:1;
850 } cn63xx;
851 struct cvmx_sli_int_sum_cn63xx cn63xxp1;
852 struct cvmx_sli_int_sum_cn61xx cn66xx;
853 struct cvmx_sli_int_sum_cn68xx {
854 uint64_t reserved_62_63:2;
855 uint64_t pipe_err:1;
856 uint64_t ill_pad:1;
857 uint64_t reserved_58_59:2;
858 uint64_t sprt1_err:1;
859 uint64_t sprt0_err:1;
860 uint64_t pins_err:1;
861 uint64_t pop_err:1;
862 uint64_t pdi_err:1;
863 uint64_t pgl_err:1;
864 uint64_t reserved_51_51:1;
865 uint64_t pout_err:1;
866 uint64_t psldbof:1;
867 uint64_t pidbof:1;
868 uint64_t reserved_38_47:10;
869 uint64_t dtime:2;
870 uint64_t dcnt:2;
871 uint64_t dmafi:2;
872 uint64_t reserved_20_31:12;
873 uint64_t mac1_int:1;
874 uint64_t mac0_int:1;
875 uint64_t mio_int1:1;
876 uint64_t mio_int0:1;
877 uint64_t m1_un_wi:1;
878 uint64_t m1_un_b0:1;
879 uint64_t m1_up_wi:1;
880 uint64_t m1_up_b0:1;
881 uint64_t m0_un_wi:1;
882 uint64_t m0_un_b0:1;
883 uint64_t m0_up_wi:1;
884 uint64_t m0_up_b0:1;
885 uint64_t reserved_6_7:2;
886 uint64_t ptime:1;
887 uint64_t pcnt:1;
888 uint64_t iob2big:1;
889 uint64_t bar0_to:1;
890 uint64_t reserved_1_1:1;
891 uint64_t rml_to:1;
892 } cn68xx;
893 struct cvmx_sli_int_sum_cn68xx cn68xxp1;
894};
895
896union cvmx_sli_last_win_rdata0 {
897 uint64_t u64;
898 struct cvmx_sli_last_win_rdata0_s {
899 uint64_t data:64;
900 } s;
901 struct cvmx_sli_last_win_rdata0_s cn61xx;
902 struct cvmx_sli_last_win_rdata0_s cn63xx;
903 struct cvmx_sli_last_win_rdata0_s cn63xxp1;
904 struct cvmx_sli_last_win_rdata0_s cn66xx;
905 struct cvmx_sli_last_win_rdata0_s cn68xx;
906 struct cvmx_sli_last_win_rdata0_s cn68xxp1;
907};
908
909union cvmx_sli_last_win_rdata1 {
910 uint64_t u64;
911 struct cvmx_sli_last_win_rdata1_s {
912 uint64_t data:64;
913 } s;
914 struct cvmx_sli_last_win_rdata1_s cn61xx;
915 struct cvmx_sli_last_win_rdata1_s cn63xx;
916 struct cvmx_sli_last_win_rdata1_s cn63xxp1;
917 struct cvmx_sli_last_win_rdata1_s cn66xx;
918 struct cvmx_sli_last_win_rdata1_s cn68xx;
919 struct cvmx_sli_last_win_rdata1_s cn68xxp1;
920};
921
922union cvmx_sli_last_win_rdata2 {
923 uint64_t u64;
924 struct cvmx_sli_last_win_rdata2_s {
925 uint64_t data:64;
926 } s;
927 struct cvmx_sli_last_win_rdata2_s cn61xx;
928 struct cvmx_sli_last_win_rdata2_s cn66xx;
929};
930
931union cvmx_sli_last_win_rdata3 {
932 uint64_t u64;
933 struct cvmx_sli_last_win_rdata3_s {
934 uint64_t data:64;
935 } s;
936 struct cvmx_sli_last_win_rdata3_s cn61xx;
937 struct cvmx_sli_last_win_rdata3_s cn66xx;
938};
939
940union cvmx_sli_mac_credit_cnt {
941 uint64_t u64;
942 struct cvmx_sli_mac_credit_cnt_s {
943 uint64_t reserved_54_63:10;
944 uint64_t p1_c_d:1;
945 uint64_t p1_n_d:1;
946 uint64_t p1_p_d:1;
947 uint64_t p0_c_d:1;
948 uint64_t p0_n_d:1;
949 uint64_t p0_p_d:1;
950 uint64_t p1_ccnt:8;
951 uint64_t p1_ncnt:8;
952 uint64_t p1_pcnt:8;
953 uint64_t p0_ccnt:8;
954 uint64_t p0_ncnt:8;
955 uint64_t p0_pcnt:8;
956 } s;
957 struct cvmx_sli_mac_credit_cnt_s cn61xx;
958 struct cvmx_sli_mac_credit_cnt_s cn63xx;
959 struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
960 uint64_t reserved_48_63:16;
961 uint64_t p1_ccnt:8;
962 uint64_t p1_ncnt:8;
963 uint64_t p1_pcnt:8;
964 uint64_t p0_ccnt:8;
965 uint64_t p0_ncnt:8;
966 uint64_t p0_pcnt:8;
967 } cn63xxp1;
968 struct cvmx_sli_mac_credit_cnt_s cn66xx;
969 struct cvmx_sli_mac_credit_cnt_s cn68xx;
970 struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
971};
972
973union cvmx_sli_mac_credit_cnt2 {
974 uint64_t u64;
975 struct cvmx_sli_mac_credit_cnt2_s {
976 uint64_t reserved_54_63:10;
977 uint64_t p3_c_d:1;
978 uint64_t p3_n_d:1;
979 uint64_t p3_p_d:1;
980 uint64_t p2_c_d:1;
981 uint64_t p2_n_d:1;
982 uint64_t p2_p_d:1;
983 uint64_t p3_ccnt:8;
984 uint64_t p3_ncnt:8;
985 uint64_t p3_pcnt:8;
986 uint64_t p2_ccnt:8;
987 uint64_t p2_ncnt:8;
988 uint64_t p2_pcnt:8;
989 } s;
990 struct cvmx_sli_mac_credit_cnt2_s cn61xx;
991 struct cvmx_sli_mac_credit_cnt2_s cn66xx;
992};
993
994union cvmx_sli_mac_number {
995 uint64_t u64;
996 struct cvmx_sli_mac_number_s {
997 uint64_t reserved_9_63:55;
998 uint64_t a_mode:1;
999 uint64_t num:8;
1000 } s;
1001 struct cvmx_sli_mac_number_s cn61xx;
1002 struct cvmx_sli_mac_number_cn63xx {
1003 uint64_t reserved_8_63:56;
1004 uint64_t num:8;
1005 } cn63xx;
1006 struct cvmx_sli_mac_number_s cn66xx;
1007 struct cvmx_sli_mac_number_cn63xx cn68xx;
1008 struct cvmx_sli_mac_number_cn63xx cn68xxp1;
1009};
1010
1011union cvmx_sli_mem_access_ctl {
1012 uint64_t u64;
1013 struct cvmx_sli_mem_access_ctl_s {
1014 uint64_t reserved_14_63:50;
1015 uint64_t max_word:4;
1016 uint64_t timer:10;
1017 } s;
1018 struct cvmx_sli_mem_access_ctl_s cn61xx;
1019 struct cvmx_sli_mem_access_ctl_s cn63xx;
1020 struct cvmx_sli_mem_access_ctl_s cn63xxp1;
1021 struct cvmx_sli_mem_access_ctl_s cn66xx;
1022 struct cvmx_sli_mem_access_ctl_s cn68xx;
1023 struct cvmx_sli_mem_access_ctl_s cn68xxp1;
1024};
1025
1026union cvmx_sli_mem_access_subidx {
1027 uint64_t u64;
1028 struct cvmx_sli_mem_access_subidx_s {
1029 uint64_t reserved_43_63:21;
1030 uint64_t zero:1;
1031 uint64_t port:3;
1032 uint64_t nmerge:1;
1033 uint64_t esr:2;
1034 uint64_t esw:2;
1035 uint64_t wtype:2;
1036 uint64_t rtype:2;
1037 uint64_t reserved_0_29:30;
1038 } s;
1039 struct cvmx_sli_mem_access_subidx_cn61xx {
1040 uint64_t reserved_43_63:21;
1041 uint64_t zero:1;
1042 uint64_t port:3;
1043 uint64_t nmerge:1;
1044 uint64_t esr:2;
1045 uint64_t esw:2;
1046 uint64_t wtype:2;
1047 uint64_t rtype:2;
1048 uint64_t ba:30;
1049 } cn61xx;
1050 struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
1051 struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
1052 struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
1053 struct cvmx_sli_mem_access_subidx_cn68xx {
1054 uint64_t reserved_43_63:21;
1055 uint64_t zero:1;
1056 uint64_t port:3;
1057 uint64_t nmerge:1;
1058 uint64_t esr:2;
1059 uint64_t esw:2;
1060 uint64_t wtype:2;
1061 uint64_t rtype:2;
1062 uint64_t ba:28;
1063 uint64_t reserved_0_1:2;
1064 } cn68xx;
1065 struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
1066};
1067
1068union cvmx_sli_msi_enb0 {
1069 uint64_t u64;
1070 struct cvmx_sli_msi_enb0_s {
1071 uint64_t enb:64;
1072 } s;
1073 struct cvmx_sli_msi_enb0_s cn61xx;
1074 struct cvmx_sli_msi_enb0_s cn63xx;
1075 struct cvmx_sli_msi_enb0_s cn63xxp1;
1076 struct cvmx_sli_msi_enb0_s cn66xx;
1077 struct cvmx_sli_msi_enb0_s cn68xx;
1078 struct cvmx_sli_msi_enb0_s cn68xxp1;
1079};
1080
1081union cvmx_sli_msi_enb1 {
1082 uint64_t u64;
1083 struct cvmx_sli_msi_enb1_s {
1084 uint64_t enb:64;
1085 } s;
1086 struct cvmx_sli_msi_enb1_s cn61xx;
1087 struct cvmx_sli_msi_enb1_s cn63xx;
1088 struct cvmx_sli_msi_enb1_s cn63xxp1;
1089 struct cvmx_sli_msi_enb1_s cn66xx;
1090 struct cvmx_sli_msi_enb1_s cn68xx;
1091 struct cvmx_sli_msi_enb1_s cn68xxp1;
1092};
1093
1094union cvmx_sli_msi_enb2 {
1095 uint64_t u64;
1096 struct cvmx_sli_msi_enb2_s {
1097 uint64_t enb:64;
1098 } s;
1099 struct cvmx_sli_msi_enb2_s cn61xx;
1100 struct cvmx_sli_msi_enb2_s cn63xx;
1101 struct cvmx_sli_msi_enb2_s cn63xxp1;
1102 struct cvmx_sli_msi_enb2_s cn66xx;
1103 struct cvmx_sli_msi_enb2_s cn68xx;
1104 struct cvmx_sli_msi_enb2_s cn68xxp1;
1105};
1106
1107union cvmx_sli_msi_enb3 {
1108 uint64_t u64;
1109 struct cvmx_sli_msi_enb3_s {
1110 uint64_t enb:64;
1111 } s;
1112 struct cvmx_sli_msi_enb3_s cn61xx;
1113 struct cvmx_sli_msi_enb3_s cn63xx;
1114 struct cvmx_sli_msi_enb3_s cn63xxp1;
1115 struct cvmx_sli_msi_enb3_s cn66xx;
1116 struct cvmx_sli_msi_enb3_s cn68xx;
1117 struct cvmx_sli_msi_enb3_s cn68xxp1;
1118};
1119
1120union cvmx_sli_msi_rcv0 {
1121 uint64_t u64;
1122 struct cvmx_sli_msi_rcv0_s {
1123 uint64_t intr:64;
1124 } s;
1125 struct cvmx_sli_msi_rcv0_s cn61xx;
1126 struct cvmx_sli_msi_rcv0_s cn63xx;
1127 struct cvmx_sli_msi_rcv0_s cn63xxp1;
1128 struct cvmx_sli_msi_rcv0_s cn66xx;
1129 struct cvmx_sli_msi_rcv0_s cn68xx;
1130 struct cvmx_sli_msi_rcv0_s cn68xxp1;
1131};
1132
1133union cvmx_sli_msi_rcv1 {
1134 uint64_t u64;
1135 struct cvmx_sli_msi_rcv1_s {
1136 uint64_t intr:64;
1137 } s;
1138 struct cvmx_sli_msi_rcv1_s cn61xx;
1139 struct cvmx_sli_msi_rcv1_s cn63xx;
1140 struct cvmx_sli_msi_rcv1_s cn63xxp1;
1141 struct cvmx_sli_msi_rcv1_s cn66xx;
1142 struct cvmx_sli_msi_rcv1_s cn68xx;
1143 struct cvmx_sli_msi_rcv1_s cn68xxp1;
1144};
1145
1146union cvmx_sli_msi_rcv2 {
1147 uint64_t u64;
1148 struct cvmx_sli_msi_rcv2_s {
1149 uint64_t intr:64;
1150 } s;
1151 struct cvmx_sli_msi_rcv2_s cn61xx;
1152 struct cvmx_sli_msi_rcv2_s cn63xx;
1153 struct cvmx_sli_msi_rcv2_s cn63xxp1;
1154 struct cvmx_sli_msi_rcv2_s cn66xx;
1155 struct cvmx_sli_msi_rcv2_s cn68xx;
1156 struct cvmx_sli_msi_rcv2_s cn68xxp1;
1157};
1158
1159union cvmx_sli_msi_rcv3 {
1160 uint64_t u64;
1161 struct cvmx_sli_msi_rcv3_s {
1162 uint64_t intr:64;
1163 } s;
1164 struct cvmx_sli_msi_rcv3_s cn61xx;
1165 struct cvmx_sli_msi_rcv3_s cn63xx;
1166 struct cvmx_sli_msi_rcv3_s cn63xxp1;
1167 struct cvmx_sli_msi_rcv3_s cn66xx;
1168 struct cvmx_sli_msi_rcv3_s cn68xx;
1169 struct cvmx_sli_msi_rcv3_s cn68xxp1;
1170};
1171
1172union cvmx_sli_msi_rd_map {
1173 uint64_t u64;
1174 struct cvmx_sli_msi_rd_map_s {
1175 uint64_t reserved_16_63:48;
1176 uint64_t rd_int:8;
1177 uint64_t msi_int:8;
1178 } s;
1179 struct cvmx_sli_msi_rd_map_s cn61xx;
1180 struct cvmx_sli_msi_rd_map_s cn63xx;
1181 struct cvmx_sli_msi_rd_map_s cn63xxp1;
1182 struct cvmx_sli_msi_rd_map_s cn66xx;
1183 struct cvmx_sli_msi_rd_map_s cn68xx;
1184 struct cvmx_sli_msi_rd_map_s cn68xxp1;
1185};
1186
1187union cvmx_sli_msi_w1c_enb0 {
1188 uint64_t u64;
1189 struct cvmx_sli_msi_w1c_enb0_s {
1190 uint64_t clr:64;
1191 } s;
1192 struct cvmx_sli_msi_w1c_enb0_s cn61xx;
1193 struct cvmx_sli_msi_w1c_enb0_s cn63xx;
1194 struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
1195 struct cvmx_sli_msi_w1c_enb0_s cn66xx;
1196 struct cvmx_sli_msi_w1c_enb0_s cn68xx;
1197 struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
1198};
1199
1200union cvmx_sli_msi_w1c_enb1 {
1201 uint64_t u64;
1202 struct cvmx_sli_msi_w1c_enb1_s {
1203 uint64_t clr:64;
1204 } s;
1205 struct cvmx_sli_msi_w1c_enb1_s cn61xx;
1206 struct cvmx_sli_msi_w1c_enb1_s cn63xx;
1207 struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
1208 struct cvmx_sli_msi_w1c_enb1_s cn66xx;
1209 struct cvmx_sli_msi_w1c_enb1_s cn68xx;
1210 struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
1211};
1212
1213union cvmx_sli_msi_w1c_enb2 {
1214 uint64_t u64;
1215 struct cvmx_sli_msi_w1c_enb2_s {
1216 uint64_t clr:64;
1217 } s;
1218 struct cvmx_sli_msi_w1c_enb2_s cn61xx;
1219 struct cvmx_sli_msi_w1c_enb2_s cn63xx;
1220 struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
1221 struct cvmx_sli_msi_w1c_enb2_s cn66xx;
1222 struct cvmx_sli_msi_w1c_enb2_s cn68xx;
1223 struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
1224};
1225
1226union cvmx_sli_msi_w1c_enb3 {
1227 uint64_t u64;
1228 struct cvmx_sli_msi_w1c_enb3_s {
1229 uint64_t clr:64;
1230 } s;
1231 struct cvmx_sli_msi_w1c_enb3_s cn61xx;
1232 struct cvmx_sli_msi_w1c_enb3_s cn63xx;
1233 struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
1234 struct cvmx_sli_msi_w1c_enb3_s cn66xx;
1235 struct cvmx_sli_msi_w1c_enb3_s cn68xx;
1236 struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
1237};
1238
1239union cvmx_sli_msi_w1s_enb0 {
1240 uint64_t u64;
1241 struct cvmx_sli_msi_w1s_enb0_s {
1242 uint64_t set:64;
1243 } s;
1244 struct cvmx_sli_msi_w1s_enb0_s cn61xx;
1245 struct cvmx_sli_msi_w1s_enb0_s cn63xx;
1246 struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
1247 struct cvmx_sli_msi_w1s_enb0_s cn66xx;
1248 struct cvmx_sli_msi_w1s_enb0_s cn68xx;
1249 struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
1250};
1251
1252union cvmx_sli_msi_w1s_enb1 {
1253 uint64_t u64;
1254 struct cvmx_sli_msi_w1s_enb1_s {
1255 uint64_t set:64;
1256 } s;
1257 struct cvmx_sli_msi_w1s_enb1_s cn61xx;
1258 struct cvmx_sli_msi_w1s_enb1_s cn63xx;
1259 struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
1260 struct cvmx_sli_msi_w1s_enb1_s cn66xx;
1261 struct cvmx_sli_msi_w1s_enb1_s cn68xx;
1262 struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
1263};
1264
1265union cvmx_sli_msi_w1s_enb2 {
1266 uint64_t u64;
1267 struct cvmx_sli_msi_w1s_enb2_s {
1268 uint64_t set:64;
1269 } s;
1270 struct cvmx_sli_msi_w1s_enb2_s cn61xx;
1271 struct cvmx_sli_msi_w1s_enb2_s cn63xx;
1272 struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
1273 struct cvmx_sli_msi_w1s_enb2_s cn66xx;
1274 struct cvmx_sli_msi_w1s_enb2_s cn68xx;
1275 struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
1276};
1277
1278union cvmx_sli_msi_w1s_enb3 {
1279 uint64_t u64;
1280 struct cvmx_sli_msi_w1s_enb3_s {
1281 uint64_t set:64;
1282 } s;
1283 struct cvmx_sli_msi_w1s_enb3_s cn61xx;
1284 struct cvmx_sli_msi_w1s_enb3_s cn63xx;
1285 struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
1286 struct cvmx_sli_msi_w1s_enb3_s cn66xx;
1287 struct cvmx_sli_msi_w1s_enb3_s cn68xx;
1288 struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
1289};
1290
1291union cvmx_sli_msi_wr_map {
1292 uint64_t u64;
1293 struct cvmx_sli_msi_wr_map_s {
1294 uint64_t reserved_16_63:48;
1295 uint64_t ciu_int:8;
1296 uint64_t msi_int:8;
1297 } s;
1298 struct cvmx_sli_msi_wr_map_s cn61xx;
1299 struct cvmx_sli_msi_wr_map_s cn63xx;
1300 struct cvmx_sli_msi_wr_map_s cn63xxp1;
1301 struct cvmx_sli_msi_wr_map_s cn66xx;
1302 struct cvmx_sli_msi_wr_map_s cn68xx;
1303 struct cvmx_sli_msi_wr_map_s cn68xxp1;
1304};
1305
1306union cvmx_sli_pcie_msi_rcv {
1307 uint64_t u64;
1308 struct cvmx_sli_pcie_msi_rcv_s {
1309 uint64_t reserved_8_63:56;
1310 uint64_t intr:8;
1311 } s;
1312 struct cvmx_sli_pcie_msi_rcv_s cn61xx;
1313 struct cvmx_sli_pcie_msi_rcv_s cn63xx;
1314 struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
1315 struct cvmx_sli_pcie_msi_rcv_s cn66xx;
1316 struct cvmx_sli_pcie_msi_rcv_s cn68xx;
1317 struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
1318};
1319
1320union cvmx_sli_pcie_msi_rcv_b1 {
1321 uint64_t u64;
1322 struct cvmx_sli_pcie_msi_rcv_b1_s {
1323 uint64_t reserved_16_63:48;
1324 uint64_t intr:8;
1325 uint64_t reserved_0_7:8;
1326 } s;
1327 struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
1328 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
1329 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
1330 struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
1331 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
1332 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
1333};
1334
1335union cvmx_sli_pcie_msi_rcv_b2 {
1336 uint64_t u64;
1337 struct cvmx_sli_pcie_msi_rcv_b2_s {
1338 uint64_t reserved_24_63:40;
1339 uint64_t intr:8;
1340 uint64_t reserved_0_15:16;
1341 } s;
1342 struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
1343 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
1344 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
1345 struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
1346 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
1347 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
1348};
1349
1350union cvmx_sli_pcie_msi_rcv_b3 {
1351 uint64_t u64;
1352 struct cvmx_sli_pcie_msi_rcv_b3_s {
1353 uint64_t reserved_32_63:32;
1354 uint64_t intr:8;
1355 uint64_t reserved_0_23:24;
1356 } s;
1357 struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
1358 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
1359 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
1360 struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
1361 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
1362 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
1363};
1364
1365union cvmx_sli_pktx_cnts {
1366 uint64_t u64;
1367 struct cvmx_sli_pktx_cnts_s {
1368 uint64_t reserved_54_63:10;
1369 uint64_t timer:22;
1370 uint64_t cnt:32;
1371 } s;
1372 struct cvmx_sli_pktx_cnts_s cn61xx;
1373 struct cvmx_sli_pktx_cnts_s cn63xx;
1374 struct cvmx_sli_pktx_cnts_s cn63xxp1;
1375 struct cvmx_sli_pktx_cnts_s cn66xx;
1376 struct cvmx_sli_pktx_cnts_s cn68xx;
1377 struct cvmx_sli_pktx_cnts_s cn68xxp1;
1378};
1379
1380union cvmx_sli_pktx_in_bp {
1381 uint64_t u64;
1382 struct cvmx_sli_pktx_in_bp_s {
1383 uint64_t wmark:32;
1384 uint64_t cnt:32;
1385 } s;
1386 struct cvmx_sli_pktx_in_bp_s cn61xx;
1387 struct cvmx_sli_pktx_in_bp_s cn63xx;
1388 struct cvmx_sli_pktx_in_bp_s cn63xxp1;
1389 struct cvmx_sli_pktx_in_bp_s cn66xx;
1390};
1391
1392union cvmx_sli_pktx_instr_baddr {
1393 uint64_t u64;
1394 struct cvmx_sli_pktx_instr_baddr_s {
1395 uint64_t addr:61;
1396 uint64_t reserved_0_2:3;
1397 } s;
1398 struct cvmx_sli_pktx_instr_baddr_s cn61xx;
1399 struct cvmx_sli_pktx_instr_baddr_s cn63xx;
1400 struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
1401 struct cvmx_sli_pktx_instr_baddr_s cn66xx;
1402 struct cvmx_sli_pktx_instr_baddr_s cn68xx;
1403 struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
1404};
1405
1406union cvmx_sli_pktx_instr_baoff_dbell {
1407 uint64_t u64;
1408 struct cvmx_sli_pktx_instr_baoff_dbell_s {
1409 uint64_t aoff:32;
1410 uint64_t dbell:32;
1411 } s;
1412 struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
1413 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
1414 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
1415 struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
1416 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
1417 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
1418};
1419
1420union cvmx_sli_pktx_instr_fifo_rsize {
1421 uint64_t u64;
1422 struct cvmx_sli_pktx_instr_fifo_rsize_s {
1423 uint64_t max:9;
1424 uint64_t rrp:9;
1425 uint64_t wrp:9;
1426 uint64_t fcnt:5;
1427 uint64_t rsize:32;
1428 } s;
1429 struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
1430 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
1431 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
1432 struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
1433 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
1434 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
1435};
1436
1437union cvmx_sli_pktx_instr_header {
1438 uint64_t u64;
1439 struct cvmx_sli_pktx_instr_header_s {
1440 uint64_t reserved_44_63:20;
1441 uint64_t pbp:1;
1442 uint64_t reserved_38_42:5;
1443 uint64_t rparmode:2;
1444 uint64_t reserved_35_35:1;
1445 uint64_t rskp_len:7;
1446 uint64_t rngrpext:2;
1447 uint64_t rnqos:1;
1448 uint64_t rngrp:1;
1449 uint64_t rntt:1;
1450 uint64_t rntag:1;
1451 uint64_t use_ihdr:1;
1452 uint64_t reserved_16_20:5;
1453 uint64_t par_mode:2;
1454 uint64_t reserved_13_13:1;
1455 uint64_t skp_len:7;
1456 uint64_t ngrpext:2;
1457 uint64_t nqos:1;
1458 uint64_t ngrp:1;
1459 uint64_t ntt:1;
1460 uint64_t ntag:1;
1461 } s;
1462 struct cvmx_sli_pktx_instr_header_cn61xx {
1463 uint64_t reserved_44_63:20;
1464 uint64_t pbp:1;
1465 uint64_t reserved_38_42:5;
1466 uint64_t rparmode:2;
1467 uint64_t reserved_35_35:1;
1468 uint64_t rskp_len:7;
1469 uint64_t reserved_26_27:2;
1470 uint64_t rnqos:1;
1471 uint64_t rngrp:1;
1472 uint64_t rntt:1;
1473 uint64_t rntag:1;
1474 uint64_t use_ihdr:1;
1475 uint64_t reserved_16_20:5;
1476 uint64_t par_mode:2;
1477 uint64_t reserved_13_13:1;
1478 uint64_t skp_len:7;
1479 uint64_t reserved_4_5:2;
1480 uint64_t nqos:1;
1481 uint64_t ngrp:1;
1482 uint64_t ntt:1;
1483 uint64_t ntag:1;
1484 } cn61xx;
1485 struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
1486 struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
1487 struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
1488 struct cvmx_sli_pktx_instr_header_s cn68xx;
1489 struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
1490};
1491
1492union cvmx_sli_pktx_out_size {
1493 uint64_t u64;
1494 struct cvmx_sli_pktx_out_size_s {
1495 uint64_t reserved_23_63:41;
1496 uint64_t isize:7;
1497 uint64_t bsize:16;
1498 } s;
1499 struct cvmx_sli_pktx_out_size_s cn61xx;
1500 struct cvmx_sli_pktx_out_size_s cn63xx;
1501 struct cvmx_sli_pktx_out_size_s cn63xxp1;
1502 struct cvmx_sli_pktx_out_size_s cn66xx;
1503 struct cvmx_sli_pktx_out_size_s cn68xx;
1504 struct cvmx_sli_pktx_out_size_s cn68xxp1;
1505};
1506
1507union cvmx_sli_pktx_slist_baddr {
1508 uint64_t u64;
1509 struct cvmx_sli_pktx_slist_baddr_s {
1510 uint64_t addr:60;
1511 uint64_t reserved_0_3:4;
1512 } s;
1513 struct cvmx_sli_pktx_slist_baddr_s cn61xx;
1514 struct cvmx_sli_pktx_slist_baddr_s cn63xx;
1515 struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
1516 struct cvmx_sli_pktx_slist_baddr_s cn66xx;
1517 struct cvmx_sli_pktx_slist_baddr_s cn68xx;
1518 struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
1519};
1520
1521union cvmx_sli_pktx_slist_baoff_dbell {
1522 uint64_t u64;
1523 struct cvmx_sli_pktx_slist_baoff_dbell_s {
1524 uint64_t aoff:32;
1525 uint64_t dbell:32;
1526 } s;
1527 struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
1528 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
1529 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
1530 struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
1531 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
1532 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
1533};
1534
1535union cvmx_sli_pktx_slist_fifo_rsize {
1536 uint64_t u64;
1537 struct cvmx_sli_pktx_slist_fifo_rsize_s {
1538 uint64_t reserved_32_63:32;
1539 uint64_t rsize:32;
1540 } s;
1541 struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
1542 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
1543 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
1544 struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
1545 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
1546 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
1547};
1548
1549union cvmx_sli_pkt_cnt_int {
1550 uint64_t u64;
1551 struct cvmx_sli_pkt_cnt_int_s {
1552 uint64_t reserved_32_63:32;
1553 uint64_t port:32;
1554 } s;
1555 struct cvmx_sli_pkt_cnt_int_s cn61xx;
1556 struct cvmx_sli_pkt_cnt_int_s cn63xx;
1557 struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
1558 struct cvmx_sli_pkt_cnt_int_s cn66xx;
1559 struct cvmx_sli_pkt_cnt_int_s cn68xx;
1560 struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
1561};
1562
1563union cvmx_sli_pkt_cnt_int_enb {
1564 uint64_t u64;
1565 struct cvmx_sli_pkt_cnt_int_enb_s {
1566 uint64_t reserved_32_63:32;
1567 uint64_t port:32;
1568 } s;
1569 struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
1570 struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
1571 struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
1572 struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
1573 struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
1574 struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
1575};
1576
1577union cvmx_sli_pkt_ctl {
1578 uint64_t u64;
1579 struct cvmx_sli_pkt_ctl_s {
1580 uint64_t reserved_5_63:59;
1581 uint64_t ring_en:1;
1582 uint64_t pkt_bp:4;
1583 } s;
1584 struct cvmx_sli_pkt_ctl_s cn61xx;
1585 struct cvmx_sli_pkt_ctl_s cn63xx;
1586 struct cvmx_sli_pkt_ctl_s cn63xxp1;
1587 struct cvmx_sli_pkt_ctl_s cn66xx;
1588 struct cvmx_sli_pkt_ctl_s cn68xx;
1589 struct cvmx_sli_pkt_ctl_s cn68xxp1;
1590};
1591
1592union cvmx_sli_pkt_data_out_es {
1593 uint64_t u64;
1594 struct cvmx_sli_pkt_data_out_es_s {
1595 uint64_t es:64;
1596 } s;
1597 struct cvmx_sli_pkt_data_out_es_s cn61xx;
1598 struct cvmx_sli_pkt_data_out_es_s cn63xx;
1599 struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
1600 struct cvmx_sli_pkt_data_out_es_s cn66xx;
1601 struct cvmx_sli_pkt_data_out_es_s cn68xx;
1602 struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
1603};
1604
1605union cvmx_sli_pkt_data_out_ns {
1606 uint64_t u64;
1607 struct cvmx_sli_pkt_data_out_ns_s {
1608 uint64_t reserved_32_63:32;
1609 uint64_t nsr:32;
1610 } s;
1611 struct cvmx_sli_pkt_data_out_ns_s cn61xx;
1612 struct cvmx_sli_pkt_data_out_ns_s cn63xx;
1613 struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
1614 struct cvmx_sli_pkt_data_out_ns_s cn66xx;
1615 struct cvmx_sli_pkt_data_out_ns_s cn68xx;
1616 struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
1617};
1618
1619union cvmx_sli_pkt_data_out_ror {
1620 uint64_t u64;
1621 struct cvmx_sli_pkt_data_out_ror_s {
1622 uint64_t reserved_32_63:32;
1623 uint64_t ror:32;
1624 } s;
1625 struct cvmx_sli_pkt_data_out_ror_s cn61xx;
1626 struct cvmx_sli_pkt_data_out_ror_s cn63xx;
1627 struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
1628 struct cvmx_sli_pkt_data_out_ror_s cn66xx;
1629 struct cvmx_sli_pkt_data_out_ror_s cn68xx;
1630 struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
1631};
1632
1633union cvmx_sli_pkt_dpaddr {
1634 uint64_t u64;
1635 struct cvmx_sli_pkt_dpaddr_s {
1636 uint64_t reserved_32_63:32;
1637 uint64_t dptr:32;
1638 } s;
1639 struct cvmx_sli_pkt_dpaddr_s cn61xx;
1640 struct cvmx_sli_pkt_dpaddr_s cn63xx;
1641 struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
1642 struct cvmx_sli_pkt_dpaddr_s cn66xx;
1643 struct cvmx_sli_pkt_dpaddr_s cn68xx;
1644 struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
1645};
1646
1647union cvmx_sli_pkt_in_bp {
1648 uint64_t u64;
1649 struct cvmx_sli_pkt_in_bp_s {
1650 uint64_t reserved_32_63:32;
1651 uint64_t bp:32;
1652 } s;
1653 struct cvmx_sli_pkt_in_bp_s cn61xx;
1654 struct cvmx_sli_pkt_in_bp_s cn63xx;
1655 struct cvmx_sli_pkt_in_bp_s cn63xxp1;
1656 struct cvmx_sli_pkt_in_bp_s cn66xx;
1657};
1658
1659union cvmx_sli_pkt_in_donex_cnts {
1660 uint64_t u64;
1661 struct cvmx_sli_pkt_in_donex_cnts_s {
1662 uint64_t reserved_32_63:32;
1663 uint64_t cnt:32;
1664 } s;
1665 struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
1666 struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
1667 struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
1668 struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
1669 struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
1670 struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
1671};
1672
1673union cvmx_sli_pkt_in_instr_counts {
1674 uint64_t u64;
1675 struct cvmx_sli_pkt_in_instr_counts_s {
1676 uint64_t wr_cnt:32;
1677 uint64_t rd_cnt:32;
1678 } s;
1679 struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
1680 struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
1681 struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
1682 struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
1683 struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
1684 struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
1685};
1686
1687union cvmx_sli_pkt_in_pcie_port {
1688 uint64_t u64;
1689 struct cvmx_sli_pkt_in_pcie_port_s {
1690 uint64_t pp:64;
1691 } s;
1692 struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
1693 struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
1694 struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
1695 struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
1696 struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
1697 struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
1698};
1699
1700union cvmx_sli_pkt_input_control {
1701 uint64_t u64;
1702 struct cvmx_sli_pkt_input_control_s {
1703 uint64_t prd_erst:1;
1704 uint64_t prd_rds:7;
1705 uint64_t gii_erst:1;
1706 uint64_t gii_rds:7;
1707 uint64_t reserved_41_47:7;
1708 uint64_t prc_idle:1;
1709 uint64_t reserved_24_39:16;
1710 uint64_t pin_rst:1;
1711 uint64_t pkt_rr:1;
1712 uint64_t pbp_dhi:13;
1713 uint64_t d_nsr:1;
1714 uint64_t d_esr:2;
1715 uint64_t d_ror:1;
1716 uint64_t use_csr:1;
1717 uint64_t nsr:1;
1718 uint64_t esr:2;
1719 uint64_t ror:1;
1720 } s;
1721 struct cvmx_sli_pkt_input_control_s cn61xx;
1722 struct cvmx_sli_pkt_input_control_cn63xx {
1723 uint64_t reserved_23_63:41;
1724 uint64_t pkt_rr:1;
1725 uint64_t pbp_dhi:13;
1726 uint64_t d_nsr:1;
1727 uint64_t d_esr:2;
1728 uint64_t d_ror:1;
1729 uint64_t use_csr:1;
1730 uint64_t nsr:1;
1731 uint64_t esr:2;
1732 uint64_t ror:1;
1733 } cn63xx;
1734 struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
1735 struct cvmx_sli_pkt_input_control_s cn66xx;
1736 struct cvmx_sli_pkt_input_control_s cn68xx;
1737 struct cvmx_sli_pkt_input_control_s cn68xxp1;
1738};
1739
1740union cvmx_sli_pkt_instr_enb {
1741 uint64_t u64;
1742 struct cvmx_sli_pkt_instr_enb_s {
1743 uint64_t reserved_32_63:32;
1744 uint64_t enb:32;
1745 } s;
1746 struct cvmx_sli_pkt_instr_enb_s cn61xx;
1747 struct cvmx_sli_pkt_instr_enb_s cn63xx;
1748 struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
1749 struct cvmx_sli_pkt_instr_enb_s cn66xx;
1750 struct cvmx_sli_pkt_instr_enb_s cn68xx;
1751 struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
1752};
1753
1754union cvmx_sli_pkt_instr_rd_size {
1755 uint64_t u64;
1756 struct cvmx_sli_pkt_instr_rd_size_s {
1757 uint64_t rdsize:64;
1758 } s;
1759 struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
1760 struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
1761 struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
1762 struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
1763 struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
1764 struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
1765};
1766
1767union cvmx_sli_pkt_instr_size {
1768 uint64_t u64;
1769 struct cvmx_sli_pkt_instr_size_s {
1770 uint64_t reserved_32_63:32;
1771 uint64_t is_64b:32;
1772 } s;
1773 struct cvmx_sli_pkt_instr_size_s cn61xx;
1774 struct cvmx_sli_pkt_instr_size_s cn63xx;
1775 struct cvmx_sli_pkt_instr_size_s cn63xxp1;
1776 struct cvmx_sli_pkt_instr_size_s cn66xx;
1777 struct cvmx_sli_pkt_instr_size_s cn68xx;
1778 struct cvmx_sli_pkt_instr_size_s cn68xxp1;
1779};
1780
1781union cvmx_sli_pkt_int_levels {
1782 uint64_t u64;
1783 struct cvmx_sli_pkt_int_levels_s {
1784 uint64_t reserved_54_63:10;
1785 uint64_t time:22;
1786 uint64_t cnt:32;
1787 } s;
1788 struct cvmx_sli_pkt_int_levels_s cn61xx;
1789 struct cvmx_sli_pkt_int_levels_s cn63xx;
1790 struct cvmx_sli_pkt_int_levels_s cn63xxp1;
1791 struct cvmx_sli_pkt_int_levels_s cn66xx;
1792 struct cvmx_sli_pkt_int_levels_s cn68xx;
1793 struct cvmx_sli_pkt_int_levels_s cn68xxp1;
1794};
1795
1796union cvmx_sli_pkt_iptr {
1797 uint64_t u64;
1798 struct cvmx_sli_pkt_iptr_s {
1799 uint64_t reserved_32_63:32;
1800 uint64_t iptr:32;
1801 } s;
1802 struct cvmx_sli_pkt_iptr_s cn61xx;
1803 struct cvmx_sli_pkt_iptr_s cn63xx;
1804 struct cvmx_sli_pkt_iptr_s cn63xxp1;
1805 struct cvmx_sli_pkt_iptr_s cn66xx;
1806 struct cvmx_sli_pkt_iptr_s cn68xx;
1807 struct cvmx_sli_pkt_iptr_s cn68xxp1;
1808};
1809
1810union cvmx_sli_pkt_out_bmode {
1811 uint64_t u64;
1812 struct cvmx_sli_pkt_out_bmode_s {
1813 uint64_t reserved_32_63:32;
1814 uint64_t bmode:32;
1815 } s;
1816 struct cvmx_sli_pkt_out_bmode_s cn61xx;
1817 struct cvmx_sli_pkt_out_bmode_s cn63xx;
1818 struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
1819 struct cvmx_sli_pkt_out_bmode_s cn66xx;
1820 struct cvmx_sli_pkt_out_bmode_s cn68xx;
1821 struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
1822};
1823
1824union cvmx_sli_pkt_out_bp_en {
1825 uint64_t u64;
1826 struct cvmx_sli_pkt_out_bp_en_s {
1827 uint64_t reserved_32_63:32;
1828 uint64_t bp_en:32;
1829 } s;
1830 struct cvmx_sli_pkt_out_bp_en_s cn68xx;
1831 struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
1832};
1833
1834union cvmx_sli_pkt_out_enb {
1835 uint64_t u64;
1836 struct cvmx_sli_pkt_out_enb_s {
1837 uint64_t reserved_32_63:32;
1838 uint64_t enb:32;
1839 } s;
1840 struct cvmx_sli_pkt_out_enb_s cn61xx;
1841 struct cvmx_sli_pkt_out_enb_s cn63xx;
1842 struct cvmx_sli_pkt_out_enb_s cn63xxp1;
1843 struct cvmx_sli_pkt_out_enb_s cn66xx;
1844 struct cvmx_sli_pkt_out_enb_s cn68xx;
1845 struct cvmx_sli_pkt_out_enb_s cn68xxp1;
1846};
1847
1848union cvmx_sli_pkt_output_wmark {
1849 uint64_t u64;
1850 struct cvmx_sli_pkt_output_wmark_s {
1851 uint64_t reserved_32_63:32;
1852 uint64_t wmark:32;
1853 } s;
1854 struct cvmx_sli_pkt_output_wmark_s cn61xx;
1855 struct cvmx_sli_pkt_output_wmark_s cn63xx;
1856 struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
1857 struct cvmx_sli_pkt_output_wmark_s cn66xx;
1858 struct cvmx_sli_pkt_output_wmark_s cn68xx;
1859 struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
1860};
1861
1862union cvmx_sli_pkt_pcie_port {
1863 uint64_t u64;
1864 struct cvmx_sli_pkt_pcie_port_s {
1865 uint64_t pp:64;
1866 } s;
1867 struct cvmx_sli_pkt_pcie_port_s cn61xx;
1868 struct cvmx_sli_pkt_pcie_port_s cn63xx;
1869 struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
1870 struct cvmx_sli_pkt_pcie_port_s cn66xx;
1871 struct cvmx_sli_pkt_pcie_port_s cn68xx;
1872 struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
1873};
1874
1875union cvmx_sli_pkt_port_in_rst {
1876 uint64_t u64;
1877 struct cvmx_sli_pkt_port_in_rst_s {
1878 uint64_t in_rst:32;
1879 uint64_t out_rst:32;
1880 } s;
1881 struct cvmx_sli_pkt_port_in_rst_s cn61xx;
1882 struct cvmx_sli_pkt_port_in_rst_s cn63xx;
1883 struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
1884 struct cvmx_sli_pkt_port_in_rst_s cn66xx;
1885 struct cvmx_sli_pkt_port_in_rst_s cn68xx;
1886 struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
1887};
1888
1889union cvmx_sli_pkt_slist_es {
1890 uint64_t u64;
1891 struct cvmx_sli_pkt_slist_es_s {
1892 uint64_t es:64;
1893 } s;
1894 struct cvmx_sli_pkt_slist_es_s cn61xx;
1895 struct cvmx_sli_pkt_slist_es_s cn63xx;
1896 struct cvmx_sli_pkt_slist_es_s cn63xxp1;
1897 struct cvmx_sli_pkt_slist_es_s cn66xx;
1898 struct cvmx_sli_pkt_slist_es_s cn68xx;
1899 struct cvmx_sli_pkt_slist_es_s cn68xxp1;
1900};
1901
1902union cvmx_sli_pkt_slist_ns {
1903 uint64_t u64;
1904 struct cvmx_sli_pkt_slist_ns_s {
1905 uint64_t reserved_32_63:32;
1906 uint64_t nsr:32;
1907 } s;
1908 struct cvmx_sli_pkt_slist_ns_s cn61xx;
1909 struct cvmx_sli_pkt_slist_ns_s cn63xx;
1910 struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
1911 struct cvmx_sli_pkt_slist_ns_s cn66xx;
1912 struct cvmx_sli_pkt_slist_ns_s cn68xx;
1913 struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
1914};
1915
1916union cvmx_sli_pkt_slist_ror {
1917 uint64_t u64;
1918 struct cvmx_sli_pkt_slist_ror_s {
1919 uint64_t reserved_32_63:32;
1920 uint64_t ror:32;
1921 } s;
1922 struct cvmx_sli_pkt_slist_ror_s cn61xx;
1923 struct cvmx_sli_pkt_slist_ror_s cn63xx;
1924 struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
1925 struct cvmx_sli_pkt_slist_ror_s cn66xx;
1926 struct cvmx_sli_pkt_slist_ror_s cn68xx;
1927 struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
1928};
1929
1930union cvmx_sli_pkt_time_int {
1931 uint64_t u64;
1932 struct cvmx_sli_pkt_time_int_s {
1933 uint64_t reserved_32_63:32;
1934 uint64_t port:32;
1935 } s;
1936 struct cvmx_sli_pkt_time_int_s cn61xx;
1937 struct cvmx_sli_pkt_time_int_s cn63xx;
1938 struct cvmx_sli_pkt_time_int_s cn63xxp1;
1939 struct cvmx_sli_pkt_time_int_s cn66xx;
1940 struct cvmx_sli_pkt_time_int_s cn68xx;
1941 struct cvmx_sli_pkt_time_int_s cn68xxp1;
1942};
1943
1944union cvmx_sli_pkt_time_int_enb {
1945 uint64_t u64;
1946 struct cvmx_sli_pkt_time_int_enb_s {
1947 uint64_t reserved_32_63:32;
1948 uint64_t port:32;
1949 } s;
1950 struct cvmx_sli_pkt_time_int_enb_s cn61xx;
1951 struct cvmx_sli_pkt_time_int_enb_s cn63xx;
1952 struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
1953 struct cvmx_sli_pkt_time_int_enb_s cn66xx;
1954 struct cvmx_sli_pkt_time_int_enb_s cn68xx;
1955 struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
1956};
1957
1958union cvmx_sli_portx_pkind {
1959 uint64_t u64;
1960 struct cvmx_sli_portx_pkind_s {
1961 uint64_t reserved_25_63:39;
1962 uint64_t rpk_enb:1;
1963 uint64_t reserved_22_23:2;
1964 uint64_t pkindr:6;
1965 uint64_t reserved_14_15:2;
1966 uint64_t bpkind:6;
1967 uint64_t reserved_6_7:2;
1968 uint64_t pkind:6;
1969 } s;
1970 struct cvmx_sli_portx_pkind_s cn68xx;
1971 struct cvmx_sli_portx_pkind_cn68xxp1 {
1972 uint64_t reserved_14_63:50;
1973 uint64_t bpkind:6;
1974 uint64_t reserved_6_7:2;
1975 uint64_t pkind:6;
1976 } cn68xxp1;
1977};
1978
1979union cvmx_sli_s2m_portx_ctl {
1980 uint64_t u64;
1981 struct cvmx_sli_s2m_portx_ctl_s {
1982 uint64_t reserved_5_63:59;
1983 uint64_t wind_d:1;
1984 uint64_t bar0_d:1;
1985 uint64_t mrrs:3;
1986 } s;
1987 struct cvmx_sli_s2m_portx_ctl_s cn61xx;
1988 struct cvmx_sli_s2m_portx_ctl_s cn63xx;
1989 struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
1990 struct cvmx_sli_s2m_portx_ctl_s cn66xx;
1991 struct cvmx_sli_s2m_portx_ctl_s cn68xx;
1992 struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
1993};
1994
1995union cvmx_sli_scratch_1 {
1996 uint64_t u64;
1997 struct cvmx_sli_scratch_1_s {
1998 uint64_t data:64;
1999 } s;
2000 struct cvmx_sli_scratch_1_s cn61xx;
2001 struct cvmx_sli_scratch_1_s cn63xx;
2002 struct cvmx_sli_scratch_1_s cn63xxp1;
2003 struct cvmx_sli_scratch_1_s cn66xx;
2004 struct cvmx_sli_scratch_1_s cn68xx;
2005 struct cvmx_sli_scratch_1_s cn68xxp1;
2006};
2007
2008union cvmx_sli_scratch_2 {
2009 uint64_t u64;
2010 struct cvmx_sli_scratch_2_s {
2011 uint64_t data:64;
2012 } s;
2013 struct cvmx_sli_scratch_2_s cn61xx;
2014 struct cvmx_sli_scratch_2_s cn63xx;
2015 struct cvmx_sli_scratch_2_s cn63xxp1;
2016 struct cvmx_sli_scratch_2_s cn66xx;
2017 struct cvmx_sli_scratch_2_s cn68xx;
2018 struct cvmx_sli_scratch_2_s cn68xxp1;
2019};
2020
2021union cvmx_sli_state1 {
2022 uint64_t u64;
2023 struct cvmx_sli_state1_s {
2024 uint64_t cpl1:12;
2025 uint64_t cpl0:12;
2026 uint64_t arb:1;
2027 uint64_t csr:39;
2028 } s;
2029 struct cvmx_sli_state1_s cn61xx;
2030 struct cvmx_sli_state1_s cn63xx;
2031 struct cvmx_sli_state1_s cn63xxp1;
2032 struct cvmx_sli_state1_s cn66xx;
2033 struct cvmx_sli_state1_s cn68xx;
2034 struct cvmx_sli_state1_s cn68xxp1;
2035};
2036
2037union cvmx_sli_state2 {
2038 uint64_t u64;
2039 struct cvmx_sli_state2_s {
2040 uint64_t reserved_56_63:8;
2041 uint64_t nnp1:8;
2042 uint64_t reserved_47_47:1;
2043 uint64_t rac:1;
2044 uint64_t csm1:15;
2045 uint64_t csm0:15;
2046 uint64_t nnp0:8;
2047 uint64_t nnd:8;
2048 } s;
2049 struct cvmx_sli_state2_s cn61xx;
2050 struct cvmx_sli_state2_s cn63xx;
2051 struct cvmx_sli_state2_s cn63xxp1;
2052 struct cvmx_sli_state2_s cn66xx;
2053 struct cvmx_sli_state2_s cn68xx;
2054 struct cvmx_sli_state2_s cn68xxp1;
2055};
2056
2057union cvmx_sli_state3 {
2058 uint64_t u64;
2059 struct cvmx_sli_state3_s {
2060 uint64_t reserved_56_63:8;
2061 uint64_t psm1:15;
2062 uint64_t psm0:15;
2063 uint64_t nsm1:13;
2064 uint64_t nsm0:13;
2065 } s;
2066 struct cvmx_sli_state3_s cn61xx;
2067 struct cvmx_sli_state3_s cn63xx;
2068 struct cvmx_sli_state3_s cn63xxp1;
2069 struct cvmx_sli_state3_s cn66xx;
2070 struct cvmx_sli_state3_s cn68xx;
2071 struct cvmx_sli_state3_s cn68xxp1;
2072};
2073
2074union cvmx_sli_tx_pipe {
2075 uint64_t u64;
2076 struct cvmx_sli_tx_pipe_s {
2077 uint64_t reserved_24_63:40;
2078 uint64_t nump:8;
2079 uint64_t reserved_7_15:9;
2080 uint64_t base:7;
2081 } s;
2082 struct cvmx_sli_tx_pipe_s cn68xx;
2083 struct cvmx_sli_tx_pipe_s cn68xxp1;
2084};
2085
2086union cvmx_sli_win_rd_addr {
2087 uint64_t u64;
2088 struct cvmx_sli_win_rd_addr_s {
2089 uint64_t reserved_51_63:13;
2090 uint64_t ld_cmd:2;
2091 uint64_t iobit:1;
2092 uint64_t rd_addr:48;
2093 } s;
2094 struct cvmx_sli_win_rd_addr_s cn61xx;
2095 struct cvmx_sli_win_rd_addr_s cn63xx;
2096 struct cvmx_sli_win_rd_addr_s cn63xxp1;
2097 struct cvmx_sli_win_rd_addr_s cn66xx;
2098 struct cvmx_sli_win_rd_addr_s cn68xx;
2099 struct cvmx_sli_win_rd_addr_s cn68xxp1;
2100};
2101
2102union cvmx_sli_win_rd_data {
2103 uint64_t u64;
2104 struct cvmx_sli_win_rd_data_s {
2105 uint64_t rd_data:64;
2106 } s;
2107 struct cvmx_sli_win_rd_data_s cn61xx;
2108 struct cvmx_sli_win_rd_data_s cn63xx;
2109 struct cvmx_sli_win_rd_data_s cn63xxp1;
2110 struct cvmx_sli_win_rd_data_s cn66xx;
2111 struct cvmx_sli_win_rd_data_s cn68xx;
2112 struct cvmx_sli_win_rd_data_s cn68xxp1;
2113};
2114
2115union cvmx_sli_win_wr_addr {
2116 uint64_t u64;
2117 struct cvmx_sli_win_wr_addr_s {
2118 uint64_t reserved_49_63:15;
2119 uint64_t iobit:1;
2120 uint64_t wr_addr:45;
2121 uint64_t reserved_0_2:3;
2122 } s;
2123 struct cvmx_sli_win_wr_addr_s cn61xx;
2124 struct cvmx_sli_win_wr_addr_s cn63xx;
2125 struct cvmx_sli_win_wr_addr_s cn63xxp1;
2126 struct cvmx_sli_win_wr_addr_s cn66xx;
2127 struct cvmx_sli_win_wr_addr_s cn68xx;
2128 struct cvmx_sli_win_wr_addr_s cn68xxp1;
2129};
2130
2131union cvmx_sli_win_wr_data {
2132 uint64_t u64;
2133 struct cvmx_sli_win_wr_data_s {
2134 uint64_t wr_data:64;
2135 } s;
2136 struct cvmx_sli_win_wr_data_s cn61xx;
2137 struct cvmx_sli_win_wr_data_s cn63xx;
2138 struct cvmx_sli_win_wr_data_s cn63xxp1;
2139 struct cvmx_sli_win_wr_data_s cn66xx;
2140 struct cvmx_sli_win_wr_data_s cn68xx;
2141 struct cvmx_sli_win_wr_data_s cn68xxp1;
2142};
2143
2144union cvmx_sli_win_wr_mask {
2145 uint64_t u64;
2146 struct cvmx_sli_win_wr_mask_s {
2147 uint64_t reserved_8_63:56;
2148 uint64_t wr_mask:8;
2149 } s;
2150 struct cvmx_sli_win_wr_mask_s cn61xx;
2151 struct cvmx_sli_win_wr_mask_s cn63xx;
2152 struct cvmx_sli_win_wr_mask_s cn63xxp1;
2153 struct cvmx_sli_win_wr_mask_s cn66xx;
2154 struct cvmx_sli_win_wr_mask_s cn68xx;
2155 struct cvmx_sli_win_wr_mask_s cn68xxp1;
2156};
2157
2158union cvmx_sli_window_ctl {
2159 uint64_t u64;
2160 struct cvmx_sli_window_ctl_s {
2161 uint64_t reserved_32_63:32;
2162 uint64_t time:32;
2163 } s;
2164 struct cvmx_sli_window_ctl_s cn61xx;
2165 struct cvmx_sli_window_ctl_s cn63xx;
2166 struct cvmx_sli_window_ctl_s cn63xxp1;
2167 struct cvmx_sli_window_ctl_s cn66xx;
2168 struct cvmx_sli_window_ctl_s cn68xx;
2169 struct cvmx_sli_window_ctl_s cn68xxp1;
2170};
2171
2172#endif