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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * pci.c - Low-Level PCI Access in IA-64
4 *
5 * Derived from bios32.c of i386 tree.
6 *
7 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Bjorn Helgaas <bjorn.helgaas@hp.com>
10 * Copyright (C) 2004 Silicon Graphics, Inc.
11 *
12 * Note: Above list of copyright holders is incomplete...
13 */
14
15#include <linux/acpi.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/pci-acpi.h>
20#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/memblock.h>
25#include <linux/export.h>
26
27#include <asm/page.h>
28#include <asm/io.h>
29#include <asm/sal.h>
30#include <asm/smp.h>
31#include <asm/irq.h>
32#include <asm/hw_irq.h>
33
34/*
35 * Low-level SAL-based PCI configuration access functions. Note that SAL
36 * calls are already serialized (via sal_lock), so we don't need another
37 * synchronization mechanism here.
38 */
39
40#define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
41 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
42
43/* SAL 3.2 adds support for extended config space. */
44
45#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
46 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
47
48int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
49 int reg, int len, u32 *value)
50{
51 u64 addr, data = 0;
52 int mode, result;
53
54 if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
55 return -EINVAL;
56
57 if ((seg | reg) <= 255) {
58 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
59 mode = 0;
60 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
61 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
62 mode = 1;
63 } else {
64 return -EINVAL;
65 }
66
67 result = ia64_sal_pci_config_read(addr, mode, len, &data);
68 if (result != 0)
69 return -EINVAL;
70
71 *value = (u32) data;
72 return 0;
73}
74
75int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
76 int reg, int len, u32 value)
77{
78 u64 addr;
79 int mode, result;
80
81 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
82 return -EINVAL;
83
84 if ((seg | reg) <= 255) {
85 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
86 mode = 0;
87 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
88 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
89 mode = 1;
90 } else {
91 return -EINVAL;
92 }
93 result = ia64_sal_pci_config_write(addr, mode, len, value);
94 if (result != 0)
95 return -EINVAL;
96 return 0;
97}
98
99static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
100 int size, u32 *value)
101{
102 return raw_pci_read(pci_domain_nr(bus), bus->number,
103 devfn, where, size, value);
104}
105
106static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
107 int size, u32 value)
108{
109 return raw_pci_write(pci_domain_nr(bus), bus->number,
110 devfn, where, size, value);
111}
112
113struct pci_ops pci_root_ops = {
114 .read = pci_read,
115 .write = pci_write,
116};
117
118struct pci_root_info {
119 struct acpi_pci_root_info common;
120 struct pci_controller controller;
121 struct list_head io_resources;
122};
123
124static unsigned int new_space(u64 phys_base, int sparse)
125{
126 u64 mmio_base;
127 int i;
128
129 if (phys_base == 0)
130 return 0; /* legacy I/O port space */
131
132 mmio_base = (u64) ioremap(phys_base, 0);
133 for (i = 0; i < num_io_spaces; i++)
134 if (io_space[i].mmio_base == mmio_base &&
135 io_space[i].sparse == sparse)
136 return i;
137
138 if (num_io_spaces == MAX_IO_SPACES) {
139 pr_err("PCI: Too many IO port spaces "
140 "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
141 return ~0;
142 }
143
144 i = num_io_spaces++;
145 io_space[i].mmio_base = mmio_base;
146 io_space[i].sparse = sparse;
147
148 return i;
149}
150
151static int add_io_space(struct device *dev, struct pci_root_info *info,
152 struct resource_entry *entry)
153{
154 struct resource_entry *iospace;
155 struct resource *resource, *res = entry->res;
156 char *name;
157 unsigned long base, min, max, base_port;
158 unsigned int sparse = 0, space_nr, len;
159
160 len = strlen(info->common.name) + 32;
161 iospace = resource_list_create_entry(NULL, len);
162 if (!iospace) {
163 dev_err(dev, "PCI: No memory for %s I/O port space\n",
164 info->common.name);
165 return -ENOMEM;
166 }
167
168 if (res->flags & IORESOURCE_IO_SPARSE)
169 sparse = 1;
170 space_nr = new_space(entry->offset, sparse);
171 if (space_nr == ~0)
172 goto free_resource;
173
174 name = (char *)(iospace + 1);
175 min = res->start - entry->offset;
176 max = res->end - entry->offset;
177 base = __pa(io_space[space_nr].mmio_base);
178 base_port = IO_SPACE_BASE(space_nr);
179 snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->common.name,
180 base_port + min, base_port + max);
181
182 /*
183 * The SDM guarantees the legacy 0-64K space is sparse, but if the
184 * mapping is done by the processor (not the bridge), ACPI may not
185 * mark it as sparse.
186 */
187 if (space_nr == 0)
188 sparse = 1;
189
190 resource = iospace->res;
191 resource->name = name;
192 resource->flags = IORESOURCE_MEM;
193 resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
194 resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
195 if (insert_resource(&iomem_resource, resource)) {
196 dev_err(dev,
197 "can't allocate host bridge io space resource %pR\n",
198 resource);
199 goto free_resource;
200 }
201
202 entry->offset = base_port;
203 res->start = min + base_port;
204 res->end = max + base_port;
205 resource_list_add_tail(iospace, &info->io_resources);
206
207 return 0;
208
209free_resource:
210 resource_list_free_entry(iospace);
211 return -ENOSPC;
212}
213
214/*
215 * An IO port or MMIO resource assigned to a PCI host bridge may be
216 * consumed by the host bridge itself or available to its child
217 * bus/devices. The ACPI specification defines a bit (Producer/Consumer)
218 * to tell whether the resource is consumed by the host bridge itself,
219 * but firmware hasn't used that bit consistently, so we can't rely on it.
220 *
221 * On x86 and IA64 platforms, all IO port and MMIO resources are assumed
222 * to be available to child bus/devices except one special case:
223 * IO port [0xCF8-0xCFF] is consumed by the host bridge itself
224 * to access PCI configuration space.
225 *
226 * So explicitly filter out PCI CFG IO ports[0xCF8-0xCFF].
227 */
228static bool resource_is_pcicfg_ioport(struct resource *res)
229{
230 return (res->flags & IORESOURCE_IO) &&
231 res->start == 0xCF8 && res->end == 0xCFF;
232}
233
234static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
235{
236 struct device *dev = &ci->bridge->dev;
237 struct pci_root_info *info;
238 struct resource *res;
239 struct resource_entry *entry, *tmp;
240 int status;
241
242 status = acpi_pci_probe_root_resources(ci);
243 if (status > 0) {
244 info = container_of(ci, struct pci_root_info, common);
245 resource_list_for_each_entry_safe(entry, tmp, &ci->resources) {
246 res = entry->res;
247 if (res->flags & IORESOURCE_MEM) {
248 /*
249 * HP's firmware has a hack to work around a
250 * Windows bug. Ignore these tiny memory ranges.
251 */
252 if (resource_size(res) <= 16) {
253 resource_list_del(entry);
254 insert_resource(&iomem_resource,
255 entry->res);
256 resource_list_add_tail(entry,
257 &info->io_resources);
258 }
259 } else if (res->flags & IORESOURCE_IO) {
260 if (resource_is_pcicfg_ioport(entry->res))
261 resource_list_destroy_entry(entry);
262 else if (add_io_space(dev, info, entry))
263 resource_list_destroy_entry(entry);
264 }
265 }
266 }
267
268 return status;
269}
270
271static void pci_acpi_root_release_info(struct acpi_pci_root_info *ci)
272{
273 struct pci_root_info *info;
274 struct resource_entry *entry, *tmp;
275
276 info = container_of(ci, struct pci_root_info, common);
277 resource_list_for_each_entry_safe(entry, tmp, &info->io_resources) {
278 release_resource(entry->res);
279 resource_list_destroy_entry(entry);
280 }
281 kfree(info);
282}
283
284static struct acpi_pci_root_ops pci_acpi_root_ops = {
285 .pci_ops = &pci_root_ops,
286 .release_info = pci_acpi_root_release_info,
287 .prepare_resources = pci_acpi_root_prepare_resources,
288};
289
290struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
291{
292 struct acpi_device *device = root->device;
293 struct pci_root_info *info;
294
295 info = kzalloc(sizeof(*info), GFP_KERNEL);
296 if (!info) {
297 dev_err(&device->dev,
298 "pci_bus %04x:%02x: ignored (out of memory)\n",
299 root->segment, (int)root->secondary.start);
300 return NULL;
301 }
302
303 info->controller.segment = root->segment;
304 info->controller.companion = device;
305 info->controller.node = acpi_get_node(device->handle);
306 INIT_LIST_HEAD(&info->io_resources);
307 return acpi_pci_root_create(root, &pci_acpi_root_ops,
308 &info->common, &info->controller);
309}
310
311int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
312{
313 /*
314 * We pass NULL as parent to pci_create_root_bus(), so if it is not NULL
315 * here, pci_create_root_bus() has been called by someone else and
316 * sysdata is likely to be different from what we expect. Let it go in
317 * that case.
318 */
319 if (!bridge->dev.parent) {
320 struct pci_controller *controller = bridge->bus->sysdata;
321 ACPI_COMPANION_SET(&bridge->dev, controller->companion);
322 }
323 return 0;
324}
325
326void pcibios_fixup_device_resources(struct pci_dev *dev)
327{
328 int idx;
329
330 if (!dev->bus)
331 return;
332
333 for (idx = 0; idx < PCI_BRIDGE_RESOURCES; idx++) {
334 struct resource *r = &dev->resource[idx];
335
336 if (!r->flags || r->parent || !r->start)
337 continue;
338
339 pci_claim_resource(dev, idx);
340 }
341}
342EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
343
344static void pcibios_fixup_bridge_resources(struct pci_dev *dev)
345{
346 int idx;
347
348 if (!dev->bus)
349 return;
350
351 for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
352 struct resource *r = &dev->resource[idx];
353
354 if (!r->flags || r->parent || !r->start)
355 continue;
356
357 pci_claim_bridge_resource(dev, idx);
358 }
359}
360
361/*
362 * Called after each bus is probed, but before its children are examined.
363 */
364void pcibios_fixup_bus(struct pci_bus *b)
365{
366 struct pci_dev *dev;
367
368 if (b->self) {
369 pci_read_bridge_bases(b);
370 pcibios_fixup_bridge_resources(b->self);
371 }
372 list_for_each_entry(dev, &b->devices, bus_list)
373 pcibios_fixup_device_resources(dev);
374}
375
376void pcibios_add_bus(struct pci_bus *bus)
377{
378 acpi_pci_add_bus(bus);
379}
380
381void pcibios_remove_bus(struct pci_bus *bus)
382{
383 acpi_pci_remove_bus(bus);
384}
385
386void pcibios_set_master (struct pci_dev *dev)
387{
388 /* No special bus mastering setup handling */
389}
390
391int
392pcibios_enable_device (struct pci_dev *dev, int mask)
393{
394 int ret;
395
396 ret = pci_enable_resources(dev, mask);
397 if (ret < 0)
398 return ret;
399
400 if (!pci_dev_msi_enabled(dev))
401 return acpi_pci_irq_enable(dev);
402 return 0;
403}
404
405void
406pcibios_disable_device (struct pci_dev *dev)
407{
408 BUG_ON(atomic_read(&dev->enable_cnt));
409 if (!pci_dev_msi_enabled(dev))
410 acpi_pci_irq_disable(dev);
411}
412
413/**
414 * pci_get_legacy_mem - generic legacy mem routine
415 * @bus: bus to get legacy memory base address for
416 *
417 * Find the base of legacy memory for @bus. This is typically the first
418 * megabyte of bus address space for @bus or is simply 0 on platforms whose
419 * chipsets support legacy I/O and memory routing. Returns the base address
420 * or an error pointer if an error occurred.
421 *
422 * This is the ia64 generic version of this routine. Other platforms
423 * are free to override it with a machine vector.
424 */
425char *pci_get_legacy_mem(struct pci_bus *bus)
426{
427 return (char *)__IA64_UNCACHED_OFFSET;
428}
429
430/**
431 * pci_mmap_legacy_page_range - map legacy memory space to userland
432 * @bus: bus whose legacy space we're mapping
433 * @vma: vma passed in by mmap
434 *
435 * Map legacy memory space for this device back to userspace using a machine
436 * vector to get the base address.
437 */
438int
439pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
440 enum pci_mmap_state mmap_state)
441{
442 unsigned long size = vma->vm_end - vma->vm_start;
443 pgprot_t prot;
444 char *addr;
445
446 /* We only support mmap'ing of legacy memory space */
447 if (mmap_state != pci_mmap_mem)
448 return -ENOSYS;
449
450 /*
451 * Avoid attribute aliasing. See Documentation/ia64/aliasing.rst
452 * for more details.
453 */
454 if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
455 return -EINVAL;
456 prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
457 vma->vm_page_prot);
458
459 addr = pci_get_legacy_mem(bus);
460 if (IS_ERR(addr))
461 return PTR_ERR(addr);
462
463 vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
464 vma->vm_page_prot = prot;
465
466 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
467 size, vma->vm_page_prot))
468 return -EAGAIN;
469
470 return 0;
471}
472
473/**
474 * pci_legacy_read - read from legacy I/O space
475 * @bus: bus to read
476 * @port: legacy port value
477 * @val: caller allocated storage for returned value
478 * @size: number of bytes to read
479 *
480 * Simply reads @size bytes from @port and puts the result in @val.
481 *
482 * Again, this (and the write routine) are generic versions that can be
483 * overridden by the platform. This is necessary on platforms that don't
484 * support legacy I/O routing or that hard fail on legacy I/O timeouts.
485 */
486int pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
487{
488 int ret = size;
489
490 switch (size) {
491 case 1:
492 *val = inb(port);
493 break;
494 case 2:
495 *val = inw(port);
496 break;
497 case 4:
498 *val = inl(port);
499 break;
500 default:
501 ret = -EINVAL;
502 break;
503 }
504
505 return ret;
506}
507
508/**
509 * pci_legacy_write - perform a legacy I/O write
510 * @bus: bus pointer
511 * @port: port to write
512 * @val: value to write
513 * @size: number of bytes to write from @val
514 *
515 * Simply writes @size bytes of @val to @port.
516 */
517int pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
518{
519 int ret = size;
520
521 switch (size) {
522 case 1:
523 outb(val, port);
524 break;
525 case 2:
526 outw(val, port);
527 break;
528 case 4:
529 outl(val, port);
530 break;
531 default:
532 ret = -EINVAL;
533 break;
534 }
535
536 return ret;
537}
538
539/**
540 * set_pci_cacheline_size - determine cacheline size for PCI devices
541 *
542 * We want to use the line-size of the outer-most cache. We assume
543 * that this line-size is the same for all CPUs.
544 *
545 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
546 */
547static void __init set_pci_dfl_cacheline_size(void)
548{
549 unsigned long levels, unique_caches;
550 long status;
551 pal_cache_config_info_t cci;
552
553 status = ia64_pal_cache_summary(&levels, &unique_caches);
554 if (status != 0) {
555 pr_err("%s: ia64_pal_cache_summary() failed "
556 "(status=%ld)\n", __func__, status);
557 return;
558 }
559
560 status = ia64_pal_cache_config_info(levels - 1,
561 /* cache_type (data_or_unified)= */ 2, &cci);
562 if (status != 0) {
563 pr_err("%s: ia64_pal_cache_config_info() failed "
564 "(status=%ld)\n", __func__, status);
565 return;
566 }
567 pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
568}
569
570static int __init pcibios_init(void)
571{
572 set_pci_dfl_cacheline_size();
573 return 0;
574}
575
576subsys_initcall(pcibios_init);
1/*
2 * pci.c - Low-Level PCI Access in IA-64
3 *
4 * Derived from bios32.c of i386 tree.
5 *
6 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn.helgaas@hp.com>
9 * Copyright (C) 2004 Silicon Graphics, Inc.
10 *
11 * Note: Above list of copyright holders is incomplete...
12 */
13
14#include <linux/acpi.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/bootmem.h>
23#include <linux/export.h>
24
25#include <asm/machvec.h>
26#include <asm/page.h>
27#include <asm/io.h>
28#include <asm/sal.h>
29#include <asm/smp.h>
30#include <asm/irq.h>
31#include <asm/hw_irq.h>
32
33/*
34 * Low-level SAL-based PCI configuration access functions. Note that SAL
35 * calls are already serialized (via sal_lock), so we don't need another
36 * synchronization mechanism here.
37 */
38
39#define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
40 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
41
42/* SAL 3.2 adds support for extended config space. */
43
44#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
45 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
46
47int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
48 int reg, int len, u32 *value)
49{
50 u64 addr, data = 0;
51 int mode, result;
52
53 if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
54 return -EINVAL;
55
56 if ((seg | reg) <= 255) {
57 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
58 mode = 0;
59 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
60 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
61 mode = 1;
62 } else {
63 return -EINVAL;
64 }
65
66 result = ia64_sal_pci_config_read(addr, mode, len, &data);
67 if (result != 0)
68 return -EINVAL;
69
70 *value = (u32) data;
71 return 0;
72}
73
74int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
75 int reg, int len, u32 value)
76{
77 u64 addr;
78 int mode, result;
79
80 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
81 return -EINVAL;
82
83 if ((seg | reg) <= 255) {
84 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
85 mode = 0;
86 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
87 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
88 mode = 1;
89 } else {
90 return -EINVAL;
91 }
92 result = ia64_sal_pci_config_write(addr, mode, len, value);
93 if (result != 0)
94 return -EINVAL;
95 return 0;
96}
97
98static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
99 int size, u32 *value)
100{
101 return raw_pci_read(pci_domain_nr(bus), bus->number,
102 devfn, where, size, value);
103}
104
105static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
106 int size, u32 value)
107{
108 return raw_pci_write(pci_domain_nr(bus), bus->number,
109 devfn, where, size, value);
110}
111
112struct pci_ops pci_root_ops = {
113 .read = pci_read,
114 .write = pci_write,
115};
116
117/* Called by ACPI when it finds a new root bus. */
118
119static struct pci_controller * __devinit
120alloc_pci_controller (int seg)
121{
122 struct pci_controller *controller;
123
124 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
125 if (!controller)
126 return NULL;
127
128 controller->segment = seg;
129 controller->node = -1;
130 return controller;
131}
132
133struct pci_root_info {
134 struct acpi_device *bridge;
135 struct pci_controller *controller;
136 struct list_head resources;
137 char *name;
138};
139
140static unsigned int
141new_space (u64 phys_base, int sparse)
142{
143 u64 mmio_base;
144 int i;
145
146 if (phys_base == 0)
147 return 0; /* legacy I/O port space */
148
149 mmio_base = (u64) ioremap(phys_base, 0);
150 for (i = 0; i < num_io_spaces; i++)
151 if (io_space[i].mmio_base == mmio_base &&
152 io_space[i].sparse == sparse)
153 return i;
154
155 if (num_io_spaces == MAX_IO_SPACES) {
156 printk(KERN_ERR "PCI: Too many IO port spaces "
157 "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
158 return ~0;
159 }
160
161 i = num_io_spaces++;
162 io_space[i].mmio_base = mmio_base;
163 io_space[i].sparse = sparse;
164
165 return i;
166}
167
168static u64 __devinit
169add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
170{
171 struct resource *resource;
172 char *name;
173 unsigned long base, min, max, base_port;
174 unsigned int sparse = 0, space_nr, len;
175
176 resource = kzalloc(sizeof(*resource), GFP_KERNEL);
177 if (!resource) {
178 printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
179 info->name);
180 goto out;
181 }
182
183 len = strlen(info->name) + 32;
184 name = kzalloc(len, GFP_KERNEL);
185 if (!name) {
186 printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
187 info->name);
188 goto free_resource;
189 }
190
191 min = addr->minimum;
192 max = min + addr->address_length - 1;
193 if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
194 sparse = 1;
195
196 space_nr = new_space(addr->translation_offset, sparse);
197 if (space_nr == ~0)
198 goto free_name;
199
200 base = __pa(io_space[space_nr].mmio_base);
201 base_port = IO_SPACE_BASE(space_nr);
202 snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
203 base_port + min, base_port + max);
204
205 /*
206 * The SDM guarantees the legacy 0-64K space is sparse, but if the
207 * mapping is done by the processor (not the bridge), ACPI may not
208 * mark it as sparse.
209 */
210 if (space_nr == 0)
211 sparse = 1;
212
213 resource->name = name;
214 resource->flags = IORESOURCE_MEM;
215 resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
216 resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
217 insert_resource(&iomem_resource, resource);
218
219 return base_port;
220
221free_name:
222 kfree(name);
223free_resource:
224 kfree(resource);
225out:
226 return ~0;
227}
228
229static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
230 struct acpi_resource_address64 *addr)
231{
232 acpi_status status;
233
234 /*
235 * We're only interested in _CRS descriptors that are
236 * - address space descriptors for memory or I/O space
237 * - non-zero size
238 * - producers, i.e., the address space is routed downstream,
239 * not consumed by the bridge itself
240 */
241 status = acpi_resource_to_address64(resource, addr);
242 if (ACPI_SUCCESS(status) &&
243 (addr->resource_type == ACPI_MEMORY_RANGE ||
244 addr->resource_type == ACPI_IO_RANGE) &&
245 addr->address_length &&
246 addr->producer_consumer == ACPI_PRODUCER)
247 return AE_OK;
248
249 return AE_ERROR;
250}
251
252static acpi_status __devinit
253count_window (struct acpi_resource *resource, void *data)
254{
255 unsigned int *windows = (unsigned int *) data;
256 struct acpi_resource_address64 addr;
257 acpi_status status;
258
259 status = resource_to_window(resource, &addr);
260 if (ACPI_SUCCESS(status))
261 (*windows)++;
262
263 return AE_OK;
264}
265
266static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
267{
268 struct pci_root_info *info = data;
269 struct pci_window *window;
270 struct acpi_resource_address64 addr;
271 acpi_status status;
272 unsigned long flags, offset = 0;
273 struct resource *root;
274
275 /* Return AE_OK for non-window resources to keep scanning for more */
276 status = resource_to_window(res, &addr);
277 if (!ACPI_SUCCESS(status))
278 return AE_OK;
279
280 if (addr.resource_type == ACPI_MEMORY_RANGE) {
281 flags = IORESOURCE_MEM;
282 root = &iomem_resource;
283 offset = addr.translation_offset;
284 } else if (addr.resource_type == ACPI_IO_RANGE) {
285 flags = IORESOURCE_IO;
286 root = &ioport_resource;
287 offset = add_io_space(info, &addr);
288 if (offset == ~0)
289 return AE_OK;
290 } else
291 return AE_OK;
292
293 window = &info->controller->window[info->controller->windows++];
294 window->resource.name = info->name;
295 window->resource.flags = flags;
296 window->resource.start = addr.minimum + offset;
297 window->resource.end = window->resource.start + addr.address_length - 1;
298 window->resource.child = NULL;
299 window->offset = offset;
300
301 if (insert_resource(root, &window->resource)) {
302 dev_err(&info->bridge->dev,
303 "can't allocate host bridge window %pR\n",
304 &window->resource);
305 } else {
306 if (offset)
307 dev_info(&info->bridge->dev, "host bridge window %pR "
308 "(PCI address [%#llx-%#llx])\n",
309 &window->resource,
310 window->resource.start - offset,
311 window->resource.end - offset);
312 else
313 dev_info(&info->bridge->dev,
314 "host bridge window %pR\n",
315 &window->resource);
316 }
317
318 /* HP's firmware has a hack to work around a Windows bug.
319 * Ignore these tiny memory ranges */
320 if (!((window->resource.flags & IORESOURCE_MEM) &&
321 (window->resource.end - window->resource.start < 16)))
322 pci_add_resource_offset(&info->resources, &window->resource,
323 window->offset);
324
325 return AE_OK;
326}
327
328struct pci_bus * __devinit
329pci_acpi_scan_root(struct acpi_pci_root *root)
330{
331 struct acpi_device *device = root->device;
332 int domain = root->segment;
333 int bus = root->secondary.start;
334 struct pci_controller *controller;
335 unsigned int windows = 0;
336 struct pci_root_info info;
337 struct pci_bus *pbus;
338 char *name;
339 int pxm;
340
341 controller = alloc_pci_controller(domain);
342 if (!controller)
343 goto out1;
344
345 controller->acpi_handle = device->handle;
346
347 pxm = acpi_get_pxm(controller->acpi_handle);
348#ifdef CONFIG_NUMA
349 if (pxm >= 0)
350 controller->node = pxm_to_node(pxm);
351#endif
352
353 INIT_LIST_HEAD(&info.resources);
354 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
355 &windows);
356 if (windows) {
357 controller->window =
358 kmalloc_node(sizeof(*controller->window) * windows,
359 GFP_KERNEL, controller->node);
360 if (!controller->window)
361 goto out2;
362
363 name = kmalloc(16, GFP_KERNEL);
364 if (!name)
365 goto out3;
366
367 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
368 info.bridge = device;
369 info.controller = controller;
370 info.name = name;
371 acpi_walk_resources(device->handle, METHOD_NAME__CRS,
372 add_window, &info);
373 }
374 /*
375 * See arch/x86/pci/acpi.c.
376 * The desired pci bus might already be scanned in a quirk. We
377 * should handle the case here, but it appears that IA64 hasn't
378 * such quirk. So we just ignore the case now.
379 */
380 pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller,
381 &info.resources);
382 if (!pbus) {
383 pci_free_resource_list(&info.resources);
384 return NULL;
385 }
386
387 pbus->subordinate = pci_scan_child_bus(pbus);
388 return pbus;
389
390out3:
391 kfree(controller->window);
392out2:
393 kfree(controller);
394out1:
395 return NULL;
396}
397
398static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
399{
400 unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
401 struct resource *devr = &dev->resource[idx], *busr;
402
403 if (!dev->bus)
404 return 0;
405
406 pci_bus_for_each_resource(dev->bus, busr, i) {
407 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
408 continue;
409 if ((devr->start) && (devr->start >= busr->start) &&
410 (devr->end <= busr->end))
411 return 1;
412 }
413 return 0;
414}
415
416static void __devinit
417pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
418{
419 int i;
420
421 for (i = start; i < limit; i++) {
422 if (!dev->resource[i].flags)
423 continue;
424 if ((is_valid_resource(dev, i)))
425 pci_claim_resource(dev, i);
426 }
427}
428
429void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
430{
431 pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
432}
433EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
434
435static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
436{
437 pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
438}
439
440/*
441 * Called after each bus is probed, but before its children are examined.
442 */
443void __devinit
444pcibios_fixup_bus (struct pci_bus *b)
445{
446 struct pci_dev *dev;
447
448 if (b->self) {
449 pci_read_bridge_bases(b);
450 pcibios_fixup_bridge_resources(b->self);
451 }
452 list_for_each_entry(dev, &b->devices, bus_list)
453 pcibios_fixup_device_resources(dev);
454 platform_pci_fixup_bus(b);
455}
456
457void pcibios_set_master (struct pci_dev *dev)
458{
459 /* No special bus mastering setup handling */
460}
461
462void __devinit
463pcibios_update_irq (struct pci_dev *dev, int irq)
464{
465 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
466
467 /* ??? FIXME -- record old value for shutdown. */
468}
469
470int
471pcibios_enable_device (struct pci_dev *dev, int mask)
472{
473 int ret;
474
475 ret = pci_enable_resources(dev, mask);
476 if (ret < 0)
477 return ret;
478
479 if (!dev->msi_enabled)
480 return acpi_pci_irq_enable(dev);
481 return 0;
482}
483
484void
485pcibios_disable_device (struct pci_dev *dev)
486{
487 BUG_ON(atomic_read(&dev->enable_cnt));
488 if (!dev->msi_enabled)
489 acpi_pci_irq_disable(dev);
490}
491
492resource_size_t
493pcibios_align_resource (void *data, const struct resource *res,
494 resource_size_t size, resource_size_t align)
495{
496 return res->start;
497}
498
499/*
500 * PCI BIOS setup, always defaults to SAL interface
501 */
502char * __init
503pcibios_setup (char *str)
504{
505 return str;
506}
507
508int
509pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
510 enum pci_mmap_state mmap_state, int write_combine)
511{
512 unsigned long size = vma->vm_end - vma->vm_start;
513 pgprot_t prot;
514
515 /*
516 * I/O space cannot be accessed via normal processor loads and
517 * stores on this platform.
518 */
519 if (mmap_state == pci_mmap_io)
520 /*
521 * XXX we could relax this for I/O spaces for which ACPI
522 * indicates that the space is 1-to-1 mapped. But at the
523 * moment, we don't support multiple PCI address spaces and
524 * the legacy I/O space is not 1-to-1 mapped, so this is moot.
525 */
526 return -EINVAL;
527
528 if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
529 return -EINVAL;
530
531 prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
532 vma->vm_page_prot);
533
534 /*
535 * If the user requested WC, the kernel uses UC or WC for this region,
536 * and the chipset supports WC, we can use WC. Otherwise, we have to
537 * use the same attribute the kernel uses.
538 */
539 if (write_combine &&
540 ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC ||
541 (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) &&
542 efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
543 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
544 else
545 vma->vm_page_prot = prot;
546
547 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
548 vma->vm_end - vma->vm_start, vma->vm_page_prot))
549 return -EAGAIN;
550
551 return 0;
552}
553
554/**
555 * ia64_pci_get_legacy_mem - generic legacy mem routine
556 * @bus: bus to get legacy memory base address for
557 *
558 * Find the base of legacy memory for @bus. This is typically the first
559 * megabyte of bus address space for @bus or is simply 0 on platforms whose
560 * chipsets support legacy I/O and memory routing. Returns the base address
561 * or an error pointer if an error occurred.
562 *
563 * This is the ia64 generic version of this routine. Other platforms
564 * are free to override it with a machine vector.
565 */
566char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
567{
568 return (char *)__IA64_UNCACHED_OFFSET;
569}
570
571/**
572 * pci_mmap_legacy_page_range - map legacy memory space to userland
573 * @bus: bus whose legacy space we're mapping
574 * @vma: vma passed in by mmap
575 *
576 * Map legacy memory space for this device back to userspace using a machine
577 * vector to get the base address.
578 */
579int
580pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
581 enum pci_mmap_state mmap_state)
582{
583 unsigned long size = vma->vm_end - vma->vm_start;
584 pgprot_t prot;
585 char *addr;
586
587 /* We only support mmap'ing of legacy memory space */
588 if (mmap_state != pci_mmap_mem)
589 return -ENOSYS;
590
591 /*
592 * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt
593 * for more details.
594 */
595 if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
596 return -EINVAL;
597 prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
598 vma->vm_page_prot);
599
600 addr = pci_get_legacy_mem(bus);
601 if (IS_ERR(addr))
602 return PTR_ERR(addr);
603
604 vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
605 vma->vm_page_prot = prot;
606
607 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
608 size, vma->vm_page_prot))
609 return -EAGAIN;
610
611 return 0;
612}
613
614/**
615 * ia64_pci_legacy_read - read from legacy I/O space
616 * @bus: bus to read
617 * @port: legacy port value
618 * @val: caller allocated storage for returned value
619 * @size: number of bytes to read
620 *
621 * Simply reads @size bytes from @port and puts the result in @val.
622 *
623 * Again, this (and the write routine) are generic versions that can be
624 * overridden by the platform. This is necessary on platforms that don't
625 * support legacy I/O routing or that hard fail on legacy I/O timeouts.
626 */
627int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
628{
629 int ret = size;
630
631 switch (size) {
632 case 1:
633 *val = inb(port);
634 break;
635 case 2:
636 *val = inw(port);
637 break;
638 case 4:
639 *val = inl(port);
640 break;
641 default:
642 ret = -EINVAL;
643 break;
644 }
645
646 return ret;
647}
648
649/**
650 * ia64_pci_legacy_write - perform a legacy I/O write
651 * @bus: bus pointer
652 * @port: port to write
653 * @val: value to write
654 * @size: number of bytes to write from @val
655 *
656 * Simply writes @size bytes of @val to @port.
657 */
658int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
659{
660 int ret = size;
661
662 switch (size) {
663 case 1:
664 outb(val, port);
665 break;
666 case 2:
667 outw(val, port);
668 break;
669 case 4:
670 outl(val, port);
671 break;
672 default:
673 ret = -EINVAL;
674 break;
675 }
676
677 return ret;
678}
679
680/**
681 * set_pci_cacheline_size - determine cacheline size for PCI devices
682 *
683 * We want to use the line-size of the outer-most cache. We assume
684 * that this line-size is the same for all CPUs.
685 *
686 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
687 */
688static void __init set_pci_dfl_cacheline_size(void)
689{
690 unsigned long levels, unique_caches;
691 long status;
692 pal_cache_config_info_t cci;
693
694 status = ia64_pal_cache_summary(&levels, &unique_caches);
695 if (status != 0) {
696 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
697 "(status=%ld)\n", __func__, status);
698 return;
699 }
700
701 status = ia64_pal_cache_config_info(levels - 1,
702 /* cache_type (data_or_unified)= */ 2, &cci);
703 if (status != 0) {
704 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
705 "(status=%ld)\n", __func__, status);
706 return;
707 }
708 pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
709}
710
711u64 ia64_dma_get_required_mask(struct device *dev)
712{
713 u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT);
714 u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT));
715 u64 mask;
716
717 if (!high_totalram) {
718 /* convert to mask just covering totalram */
719 low_totalram = (1 << (fls(low_totalram) - 1));
720 low_totalram += low_totalram - 1;
721 mask = low_totalram;
722 } else {
723 high_totalram = (1 << (fls(high_totalram) - 1));
724 high_totalram += high_totalram - 1;
725 mask = (((u64)high_totalram) << 32) + 0xffffffff;
726 }
727 return mask;
728}
729EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask);
730
731u64 dma_get_required_mask(struct device *dev)
732{
733 return platform_dma_get_required_mask(dev);
734}
735EXPORT_SYMBOL_GPL(dma_get_required_mask);
736
737static int __init pcibios_init(void)
738{
739 set_pci_dfl_cacheline_size();
740 return 0;
741}
742
743subsys_initcall(pcibios_init);