Loading...
Note: File does not exist in v3.5.6.
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Freescale lpuart serial port driver
4 *
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 */
7
8#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
9#define SUPPORT_SYSRQ
10#endif
11
12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/dma-mapping.h>
15#include <linux/dmaengine.h>
16#include <linux/dmapool.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/of_dma.h>
23#include <linux/serial_core.h>
24#include <linux/slab.h>
25#include <linux/tty_flip.h>
26
27/* All registers are 8-bit width */
28#define UARTBDH 0x00
29#define UARTBDL 0x01
30#define UARTCR1 0x02
31#define UARTCR2 0x03
32#define UARTSR1 0x04
33#define UARTCR3 0x06
34#define UARTDR 0x07
35#define UARTCR4 0x0a
36#define UARTCR5 0x0b
37#define UARTMODEM 0x0d
38#define UARTPFIFO 0x10
39#define UARTCFIFO 0x11
40#define UARTSFIFO 0x12
41#define UARTTWFIFO 0x13
42#define UARTTCFIFO 0x14
43#define UARTRWFIFO 0x15
44
45#define UARTBDH_LBKDIE 0x80
46#define UARTBDH_RXEDGIE 0x40
47#define UARTBDH_SBR_MASK 0x1f
48
49#define UARTCR1_LOOPS 0x80
50#define UARTCR1_RSRC 0x20
51#define UARTCR1_M 0x10
52#define UARTCR1_WAKE 0x08
53#define UARTCR1_ILT 0x04
54#define UARTCR1_PE 0x02
55#define UARTCR1_PT 0x01
56
57#define UARTCR2_TIE 0x80
58#define UARTCR2_TCIE 0x40
59#define UARTCR2_RIE 0x20
60#define UARTCR2_ILIE 0x10
61#define UARTCR2_TE 0x08
62#define UARTCR2_RE 0x04
63#define UARTCR2_RWU 0x02
64#define UARTCR2_SBK 0x01
65
66#define UARTSR1_TDRE 0x80
67#define UARTSR1_TC 0x40
68#define UARTSR1_RDRF 0x20
69#define UARTSR1_IDLE 0x10
70#define UARTSR1_OR 0x08
71#define UARTSR1_NF 0x04
72#define UARTSR1_FE 0x02
73#define UARTSR1_PE 0x01
74
75#define UARTCR3_R8 0x80
76#define UARTCR3_T8 0x40
77#define UARTCR3_TXDIR 0x20
78#define UARTCR3_TXINV 0x10
79#define UARTCR3_ORIE 0x08
80#define UARTCR3_NEIE 0x04
81#define UARTCR3_FEIE 0x02
82#define UARTCR3_PEIE 0x01
83
84#define UARTCR4_MAEN1 0x80
85#define UARTCR4_MAEN2 0x40
86#define UARTCR4_M10 0x20
87#define UARTCR4_BRFA_MASK 0x1f
88#define UARTCR4_BRFA_OFF 0
89
90#define UARTCR5_TDMAS 0x80
91#define UARTCR5_RDMAS 0x20
92
93#define UARTMODEM_RXRTSE 0x08
94#define UARTMODEM_TXRTSPOL 0x04
95#define UARTMODEM_TXRTSE 0x02
96#define UARTMODEM_TXCTSE 0x01
97
98#define UARTPFIFO_TXFE 0x80
99#define UARTPFIFO_FIFOSIZE_MASK 0x7
100#define UARTPFIFO_TXSIZE_OFF 4
101#define UARTPFIFO_RXFE 0x08
102#define UARTPFIFO_RXSIZE_OFF 0
103
104#define UARTCFIFO_TXFLUSH 0x80
105#define UARTCFIFO_RXFLUSH 0x40
106#define UARTCFIFO_RXOFE 0x04
107#define UARTCFIFO_TXOFE 0x02
108#define UARTCFIFO_RXUFE 0x01
109
110#define UARTSFIFO_TXEMPT 0x80
111#define UARTSFIFO_RXEMPT 0x40
112#define UARTSFIFO_RXOF 0x04
113#define UARTSFIFO_TXOF 0x02
114#define UARTSFIFO_RXUF 0x01
115
116/* 32-bit register definition */
117#define UARTBAUD 0x00
118#define UARTSTAT 0x04
119#define UARTCTRL 0x08
120#define UARTDATA 0x0C
121#define UARTMATCH 0x10
122#define UARTMODIR 0x14
123#define UARTFIFO 0x18
124#define UARTWATER 0x1c
125
126#define UARTBAUD_MAEN1 0x80000000
127#define UARTBAUD_MAEN2 0x40000000
128#define UARTBAUD_M10 0x20000000
129#define UARTBAUD_TDMAE 0x00800000
130#define UARTBAUD_RDMAE 0x00200000
131#define UARTBAUD_MATCFG 0x00400000
132#define UARTBAUD_BOTHEDGE 0x00020000
133#define UARTBAUD_RESYNCDIS 0x00010000
134#define UARTBAUD_LBKDIE 0x00008000
135#define UARTBAUD_RXEDGIE 0x00004000
136#define UARTBAUD_SBNS 0x00002000
137#define UARTBAUD_SBR 0x00000000
138#define UARTBAUD_SBR_MASK 0x1fff
139#define UARTBAUD_OSR_MASK 0x1f
140#define UARTBAUD_OSR_SHIFT 24
141
142#define UARTSTAT_LBKDIF 0x80000000
143#define UARTSTAT_RXEDGIF 0x40000000
144#define UARTSTAT_MSBF 0x20000000
145#define UARTSTAT_RXINV 0x10000000
146#define UARTSTAT_RWUID 0x08000000
147#define UARTSTAT_BRK13 0x04000000
148#define UARTSTAT_LBKDE 0x02000000
149#define UARTSTAT_RAF 0x01000000
150#define UARTSTAT_TDRE 0x00800000
151#define UARTSTAT_TC 0x00400000
152#define UARTSTAT_RDRF 0x00200000
153#define UARTSTAT_IDLE 0x00100000
154#define UARTSTAT_OR 0x00080000
155#define UARTSTAT_NF 0x00040000
156#define UARTSTAT_FE 0x00020000
157#define UARTSTAT_PE 0x00010000
158#define UARTSTAT_MA1F 0x00008000
159#define UARTSTAT_M21F 0x00004000
160
161#define UARTCTRL_R8T9 0x80000000
162#define UARTCTRL_R9T8 0x40000000
163#define UARTCTRL_TXDIR 0x20000000
164#define UARTCTRL_TXINV 0x10000000
165#define UARTCTRL_ORIE 0x08000000
166#define UARTCTRL_NEIE 0x04000000
167#define UARTCTRL_FEIE 0x02000000
168#define UARTCTRL_PEIE 0x01000000
169#define UARTCTRL_TIE 0x00800000
170#define UARTCTRL_TCIE 0x00400000
171#define UARTCTRL_RIE 0x00200000
172#define UARTCTRL_ILIE 0x00100000
173#define UARTCTRL_TE 0x00080000
174#define UARTCTRL_RE 0x00040000
175#define UARTCTRL_RWU 0x00020000
176#define UARTCTRL_SBK 0x00010000
177#define UARTCTRL_MA1IE 0x00008000
178#define UARTCTRL_MA2IE 0x00004000
179#define UARTCTRL_IDLECFG 0x00000100
180#define UARTCTRL_LOOPS 0x00000080
181#define UARTCTRL_DOZEEN 0x00000040
182#define UARTCTRL_RSRC 0x00000020
183#define UARTCTRL_M 0x00000010
184#define UARTCTRL_WAKE 0x00000008
185#define UARTCTRL_ILT 0x00000004
186#define UARTCTRL_PE 0x00000002
187#define UARTCTRL_PT 0x00000001
188
189#define UARTDATA_NOISY 0x00008000
190#define UARTDATA_PARITYE 0x00004000
191#define UARTDATA_FRETSC 0x00002000
192#define UARTDATA_RXEMPT 0x00001000
193#define UARTDATA_IDLINE 0x00000800
194#define UARTDATA_MASK 0x3ff
195
196#define UARTMODIR_IREN 0x00020000
197#define UARTMODIR_TXCTSSRC 0x00000020
198#define UARTMODIR_TXCTSC 0x00000010
199#define UARTMODIR_RXRTSE 0x00000008
200#define UARTMODIR_TXRTSPOL 0x00000004
201#define UARTMODIR_TXRTSE 0x00000002
202#define UARTMODIR_TXCTSE 0x00000001
203
204#define UARTFIFO_TXEMPT 0x00800000
205#define UARTFIFO_RXEMPT 0x00400000
206#define UARTFIFO_TXOF 0x00020000
207#define UARTFIFO_RXUF 0x00010000
208#define UARTFIFO_TXFLUSH 0x00008000
209#define UARTFIFO_RXFLUSH 0x00004000
210#define UARTFIFO_TXOFE 0x00000200
211#define UARTFIFO_RXUFE 0x00000100
212#define UARTFIFO_TXFE 0x00000080
213#define UARTFIFO_FIFOSIZE_MASK 0x7
214#define UARTFIFO_TXSIZE_OFF 4
215#define UARTFIFO_RXFE 0x00000008
216#define UARTFIFO_RXSIZE_OFF 0
217#define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
218
219#define UARTWATER_COUNT_MASK 0xff
220#define UARTWATER_TXCNT_OFF 8
221#define UARTWATER_RXCNT_OFF 24
222#define UARTWATER_WATER_MASK 0xff
223#define UARTWATER_TXWATER_OFF 0
224#define UARTWATER_RXWATER_OFF 16
225
226/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
227#define DMA_RX_TIMEOUT (10)
228
229#define DRIVER_NAME "fsl-lpuart"
230#define DEV_NAME "ttyLP"
231#define UART_NR 6
232
233/* IMX lpuart has four extra unused regs located at the beginning */
234#define IMX_REG_OFF 0x10
235
236static DEFINE_IDA(fsl_lpuart_ida);
237
238enum lpuart_type {
239 VF610_LPUART,
240 LS1021A_LPUART,
241 IMX7ULP_LPUART,
242 IMX8QXP_LPUART,
243};
244
245struct lpuart_port {
246 struct uart_port port;
247 enum lpuart_type devtype;
248 struct clk *ipg_clk;
249 struct clk *baud_clk;
250 unsigned int txfifo_size;
251 unsigned int rxfifo_size;
252
253 bool lpuart_dma_tx_use;
254 bool lpuart_dma_rx_use;
255 struct dma_chan *dma_tx_chan;
256 struct dma_chan *dma_rx_chan;
257 struct dma_async_tx_descriptor *dma_tx_desc;
258 struct dma_async_tx_descriptor *dma_rx_desc;
259 dma_cookie_t dma_tx_cookie;
260 dma_cookie_t dma_rx_cookie;
261 unsigned int dma_tx_bytes;
262 unsigned int dma_rx_bytes;
263 bool dma_tx_in_progress;
264 unsigned int dma_rx_timeout;
265 struct timer_list lpuart_timer;
266 struct scatterlist rx_sgl, tx_sgl[2];
267 struct circ_buf rx_ring;
268 int rx_dma_rng_buf_len;
269 unsigned int dma_tx_nents;
270 wait_queue_head_t dma_wait;
271};
272
273struct lpuart_soc_data {
274 enum lpuart_type devtype;
275 char iotype;
276 u8 reg_off;
277};
278
279static const struct lpuart_soc_data vf_data = {
280 .devtype = VF610_LPUART,
281 .iotype = UPIO_MEM,
282};
283
284static const struct lpuart_soc_data ls_data = {
285 .devtype = LS1021A_LPUART,
286 .iotype = UPIO_MEM32BE,
287};
288
289static struct lpuart_soc_data imx7ulp_data = {
290 .devtype = IMX7ULP_LPUART,
291 .iotype = UPIO_MEM32,
292 .reg_off = IMX_REG_OFF,
293};
294
295static struct lpuart_soc_data imx8qxp_data = {
296 .devtype = IMX8QXP_LPUART,
297 .iotype = UPIO_MEM32,
298 .reg_off = IMX_REG_OFF,
299};
300
301static const struct of_device_id lpuart_dt_ids[] = {
302 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
303 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, },
304 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
305 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
306 { /* sentinel */ }
307};
308MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
309
310/* Forward declare this for the dma callbacks*/
311static void lpuart_dma_tx_complete(void *arg);
312
313static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
314{
315 return sport->devtype == IMX8QXP_LPUART;
316}
317
318static inline u32 lpuart32_read(struct uart_port *port, u32 off)
319{
320 switch (port->iotype) {
321 case UPIO_MEM32:
322 return readl(port->membase + off);
323 case UPIO_MEM32BE:
324 return ioread32be(port->membase + off);
325 default:
326 return 0;
327 }
328}
329
330static inline void lpuart32_write(struct uart_port *port, u32 val,
331 u32 off)
332{
333 switch (port->iotype) {
334 case UPIO_MEM32:
335 writel(val, port->membase + off);
336 break;
337 case UPIO_MEM32BE:
338 iowrite32be(val, port->membase + off);
339 break;
340 }
341}
342
343static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
344{
345 int ret = 0;
346
347 if (is_en) {
348 ret = clk_prepare_enable(sport->ipg_clk);
349 if (ret)
350 return ret;
351
352 ret = clk_prepare_enable(sport->baud_clk);
353 if (ret) {
354 clk_disable_unprepare(sport->ipg_clk);
355 return ret;
356 }
357 } else {
358 clk_disable_unprepare(sport->baud_clk);
359 clk_disable_unprepare(sport->ipg_clk);
360 }
361
362 return 0;
363}
364
365static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
366{
367 if (is_imx8qxp_lpuart(sport))
368 return clk_get_rate(sport->baud_clk);
369
370 return clk_get_rate(sport->ipg_clk);
371}
372
373#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
374#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
375
376static void lpuart_stop_tx(struct uart_port *port)
377{
378 unsigned char temp;
379
380 temp = readb(port->membase + UARTCR2);
381 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
382 writeb(temp, port->membase + UARTCR2);
383}
384
385static void lpuart32_stop_tx(struct uart_port *port)
386{
387 unsigned long temp;
388
389 temp = lpuart32_read(port, UARTCTRL);
390 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
391 lpuart32_write(port, temp, UARTCTRL);
392}
393
394static void lpuart_stop_rx(struct uart_port *port)
395{
396 unsigned char temp;
397
398 temp = readb(port->membase + UARTCR2);
399 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
400}
401
402static void lpuart32_stop_rx(struct uart_port *port)
403{
404 unsigned long temp;
405
406 temp = lpuart32_read(port, UARTCTRL);
407 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
408}
409
410static void lpuart_dma_tx(struct lpuart_port *sport)
411{
412 struct circ_buf *xmit = &sport->port.state->xmit;
413 struct scatterlist *sgl = sport->tx_sgl;
414 struct device *dev = sport->port.dev;
415 int ret;
416
417 if (sport->dma_tx_in_progress)
418 return;
419
420 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
421
422 if (xmit->tail < xmit->head || xmit->head == 0) {
423 sport->dma_tx_nents = 1;
424 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
425 } else {
426 sport->dma_tx_nents = 2;
427 sg_init_table(sgl, 2);
428 sg_set_buf(sgl, xmit->buf + xmit->tail,
429 UART_XMIT_SIZE - xmit->tail);
430 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
431 }
432
433 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
434 if (!ret) {
435 dev_err(dev, "DMA mapping error for TX.\n");
436 return;
437 }
438
439 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
440 sport->dma_tx_nents,
441 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
442 if (!sport->dma_tx_desc) {
443 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
444 dev_err(dev, "Cannot prepare TX slave DMA!\n");
445 return;
446 }
447
448 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
449 sport->dma_tx_desc->callback_param = sport;
450 sport->dma_tx_in_progress = true;
451 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
452 dma_async_issue_pending(sport->dma_tx_chan);
453}
454
455static bool lpuart_stopped_or_empty(struct uart_port *port)
456{
457 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
458}
459
460static void lpuart_dma_tx_complete(void *arg)
461{
462 struct lpuart_port *sport = arg;
463 struct scatterlist *sgl = &sport->tx_sgl[0];
464 struct circ_buf *xmit = &sport->port.state->xmit;
465 unsigned long flags;
466
467 spin_lock_irqsave(&sport->port.lock, flags);
468
469 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
470
471 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
472
473 sport->port.icount.tx += sport->dma_tx_bytes;
474 sport->dma_tx_in_progress = false;
475 spin_unlock_irqrestore(&sport->port.lock, flags);
476
477 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
478 uart_write_wakeup(&sport->port);
479
480 if (waitqueue_active(&sport->dma_wait)) {
481 wake_up(&sport->dma_wait);
482 return;
483 }
484
485 spin_lock_irqsave(&sport->port.lock, flags);
486
487 if (!lpuart_stopped_or_empty(&sport->port))
488 lpuart_dma_tx(sport);
489
490 spin_unlock_irqrestore(&sport->port.lock, flags);
491}
492
493static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
494{
495 switch (sport->port.iotype) {
496 case UPIO_MEM32:
497 return sport->port.mapbase + UARTDATA;
498 case UPIO_MEM32BE:
499 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
500 }
501 return sport->port.mapbase + UARTDR;
502}
503
504static int lpuart_dma_tx_request(struct uart_port *port)
505{
506 struct lpuart_port *sport = container_of(port,
507 struct lpuart_port, port);
508 struct dma_slave_config dma_tx_sconfig = {};
509 int ret;
510
511 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
512 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
513 dma_tx_sconfig.dst_maxburst = 1;
514 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
515 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
516
517 if (ret) {
518 dev_err(sport->port.dev,
519 "DMA slave config failed, err = %d\n", ret);
520 return ret;
521 }
522
523 return 0;
524}
525
526static bool lpuart_is_32(struct lpuart_port *sport)
527{
528 return sport->port.iotype == UPIO_MEM32 ||
529 sport->port.iotype == UPIO_MEM32BE;
530}
531
532static void lpuart_flush_buffer(struct uart_port *port)
533{
534 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
535 u32 val;
536
537 if (sport->lpuart_dma_tx_use) {
538 if (sport->dma_tx_in_progress) {
539 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
540 sport->dma_tx_nents, DMA_TO_DEVICE);
541 sport->dma_tx_in_progress = false;
542 }
543 dmaengine_terminate_all(sport->dma_tx_chan);
544 }
545
546 if (lpuart_is_32(sport)) {
547 val = lpuart32_read(&sport->port, UARTFIFO);
548 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
549 lpuart32_write(&sport->port, val, UARTFIFO);
550 } else {
551 val = readb(sport->port.membase + UARTCFIFO);
552 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
553 writeb(val, sport->port.membase + UARTCFIFO);
554 }
555}
556
557static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
558 u8 bit)
559{
560 while (!(readb(port->membase + offset) & bit))
561 cpu_relax();
562}
563
564static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
565 u32 bit)
566{
567 while (!(lpuart32_read(port, offset) & bit))
568 cpu_relax();
569}
570
571#if defined(CONFIG_CONSOLE_POLL)
572
573static int lpuart_poll_init(struct uart_port *port)
574{
575 struct lpuart_port *sport = container_of(port,
576 struct lpuart_port, port);
577 unsigned long flags;
578 unsigned char temp;
579
580 sport->port.fifosize = 0;
581
582 spin_lock_irqsave(&sport->port.lock, flags);
583 /* Disable Rx & Tx */
584 writeb(0, sport->port.membase + UARTCR2);
585
586 temp = readb(sport->port.membase + UARTPFIFO);
587 /* Enable Rx and Tx FIFO */
588 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
589 sport->port.membase + UARTPFIFO);
590
591 /* flush Tx and Rx FIFO */
592 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
593 sport->port.membase + UARTCFIFO);
594
595 /* explicitly clear RDRF */
596 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
597 readb(sport->port.membase + UARTDR);
598 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
599 }
600
601 writeb(0, sport->port.membase + UARTTWFIFO);
602 writeb(1, sport->port.membase + UARTRWFIFO);
603
604 /* Enable Rx and Tx */
605 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
606 spin_unlock_irqrestore(&sport->port.lock, flags);
607
608 return 0;
609}
610
611static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
612{
613 /* drain */
614 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
615 writeb(c, port->membase + UARTDR);
616}
617
618static int lpuart_poll_get_char(struct uart_port *port)
619{
620 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
621 return NO_POLL_CHAR;
622
623 return readb(port->membase + UARTDR);
624}
625
626static int lpuart32_poll_init(struct uart_port *port)
627{
628 unsigned long flags;
629 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
630 u32 temp;
631
632 sport->port.fifosize = 0;
633
634 spin_lock_irqsave(&sport->port.lock, flags);
635
636 /* Disable Rx & Tx */
637 lpuart32_write(&sport->port, UARTCTRL, 0);
638
639 temp = lpuart32_read(&sport->port, UARTFIFO);
640
641 /* Enable Rx and Tx FIFO */
642 lpuart32_write(&sport->port, UARTFIFO,
643 temp | UARTFIFO_RXFE | UARTFIFO_TXFE);
644
645 /* flush Tx and Rx FIFO */
646 lpuart32_write(&sport->port, UARTFIFO,
647 UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH);
648
649 /* explicitly clear RDRF */
650 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
651 lpuart32_read(&sport->port, UARTDATA);
652 lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF);
653 }
654
655 /* Enable Rx and Tx */
656 lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE | UARTCTRL_TE);
657 spin_unlock_irqrestore(&sport->port.lock, flags);
658
659 return 0;
660}
661
662static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
663{
664 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
665 lpuart32_write(port, UARTDATA, c);
666}
667
668static int lpuart32_poll_get_char(struct uart_port *port)
669{
670 if (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF))
671 return NO_POLL_CHAR;
672
673 return lpuart32_read(port, UARTDATA);
674}
675#endif
676
677static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
678{
679 struct circ_buf *xmit = &sport->port.state->xmit;
680
681 if (sport->port.x_char) {
682 writeb(sport->port.x_char, sport->port.membase + UARTDR);
683 sport->port.icount.tx++;
684 sport->port.x_char = 0;
685 return;
686 }
687
688 if (lpuart_stopped_or_empty(&sport->port)) {
689 lpuart_stop_tx(&sport->port);
690 return;
691 }
692
693 while (!uart_circ_empty(xmit) &&
694 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
695 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
696 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
697 sport->port.icount.tx++;
698 }
699
700 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
701 uart_write_wakeup(&sport->port);
702
703 if (uart_circ_empty(xmit))
704 lpuart_stop_tx(&sport->port);
705}
706
707static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
708{
709 struct circ_buf *xmit = &sport->port.state->xmit;
710 unsigned long txcnt;
711
712 if (sport->port.x_char) {
713 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
714 sport->port.icount.tx++;
715 sport->port.x_char = 0;
716 return;
717 }
718
719 if (lpuart_stopped_or_empty(&sport->port)) {
720 lpuart32_stop_tx(&sport->port);
721 return;
722 }
723
724 txcnt = lpuart32_read(&sport->port, UARTWATER);
725 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
726 txcnt &= UARTWATER_COUNT_MASK;
727 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
728 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
729 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
730 sport->port.icount.tx++;
731 txcnt = lpuart32_read(&sport->port, UARTWATER);
732 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
733 txcnt &= UARTWATER_COUNT_MASK;
734 }
735
736 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
737 uart_write_wakeup(&sport->port);
738
739 if (uart_circ_empty(xmit))
740 lpuart32_stop_tx(&sport->port);
741}
742
743static void lpuart_start_tx(struct uart_port *port)
744{
745 struct lpuart_port *sport = container_of(port,
746 struct lpuart_port, port);
747 unsigned char temp;
748
749 temp = readb(port->membase + UARTCR2);
750 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
751
752 if (sport->lpuart_dma_tx_use) {
753 if (!lpuart_stopped_or_empty(port))
754 lpuart_dma_tx(sport);
755 } else {
756 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
757 lpuart_transmit_buffer(sport);
758 }
759}
760
761static void lpuart32_start_tx(struct uart_port *port)
762{
763 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
764 unsigned long temp;
765
766 if (sport->lpuart_dma_tx_use) {
767 if (!lpuart_stopped_or_empty(port))
768 lpuart_dma_tx(sport);
769 } else {
770 temp = lpuart32_read(port, UARTCTRL);
771 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
772
773 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
774 lpuart32_transmit_buffer(sport);
775 }
776}
777
778/* return TIOCSER_TEMT when transmitter is not busy */
779static unsigned int lpuart_tx_empty(struct uart_port *port)
780{
781 struct lpuart_port *sport = container_of(port,
782 struct lpuart_port, port);
783 unsigned char sr1 = readb(port->membase + UARTSR1);
784 unsigned char sfifo = readb(port->membase + UARTSFIFO);
785
786 if (sport->dma_tx_in_progress)
787 return 0;
788
789 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
790 return TIOCSER_TEMT;
791
792 return 0;
793}
794
795static unsigned int lpuart32_tx_empty(struct uart_port *port)
796{
797 struct lpuart_port *sport = container_of(port,
798 struct lpuart_port, port);
799 unsigned long stat = lpuart32_read(port, UARTSTAT);
800 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
801
802 if (sport->dma_tx_in_progress)
803 return 0;
804
805 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
806 return TIOCSER_TEMT;
807
808 return 0;
809}
810
811static void lpuart_txint(struct lpuart_port *sport)
812{
813 unsigned long flags;
814
815 spin_lock_irqsave(&sport->port.lock, flags);
816 lpuart_transmit_buffer(sport);
817 spin_unlock_irqrestore(&sport->port.lock, flags);
818}
819
820static void lpuart_rxint(struct lpuart_port *sport)
821{
822 unsigned int flg, ignored = 0, overrun = 0;
823 struct tty_port *port = &sport->port.state->port;
824 unsigned long flags;
825 unsigned char rx, sr;
826
827 spin_lock_irqsave(&sport->port.lock, flags);
828
829 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
830 flg = TTY_NORMAL;
831 sport->port.icount.rx++;
832 /*
833 * to clear the FE, OR, NF, FE, PE flags,
834 * read SR1 then read DR
835 */
836 sr = readb(sport->port.membase + UARTSR1);
837 rx = readb(sport->port.membase + UARTDR);
838
839 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
840 continue;
841
842 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
843 if (sr & UARTSR1_PE)
844 sport->port.icount.parity++;
845 else if (sr & UARTSR1_FE)
846 sport->port.icount.frame++;
847
848 if (sr & UARTSR1_OR)
849 overrun++;
850
851 if (sr & sport->port.ignore_status_mask) {
852 if (++ignored > 100)
853 goto out;
854 continue;
855 }
856
857 sr &= sport->port.read_status_mask;
858
859 if (sr & UARTSR1_PE)
860 flg = TTY_PARITY;
861 else if (sr & UARTSR1_FE)
862 flg = TTY_FRAME;
863
864 if (sr & UARTSR1_OR)
865 flg = TTY_OVERRUN;
866
867#ifdef SUPPORT_SYSRQ
868 sport->port.sysrq = 0;
869#endif
870 }
871
872 tty_insert_flip_char(port, rx, flg);
873 }
874
875out:
876 if (overrun) {
877 sport->port.icount.overrun += overrun;
878
879 /*
880 * Overruns cause FIFO pointers to become missaligned.
881 * Flushing the receive FIFO reinitializes the pointers.
882 */
883 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
884 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
885 }
886
887 spin_unlock_irqrestore(&sport->port.lock, flags);
888
889 tty_flip_buffer_push(port);
890}
891
892static void lpuart32_txint(struct lpuart_port *sport)
893{
894 unsigned long flags;
895
896 spin_lock_irqsave(&sport->port.lock, flags);
897 lpuart32_transmit_buffer(sport);
898 spin_unlock_irqrestore(&sport->port.lock, flags);
899}
900
901static void lpuart32_rxint(struct lpuart_port *sport)
902{
903 unsigned int flg, ignored = 0;
904 struct tty_port *port = &sport->port.state->port;
905 unsigned long flags;
906 unsigned long rx, sr;
907
908 spin_lock_irqsave(&sport->port.lock, flags);
909
910 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
911 flg = TTY_NORMAL;
912 sport->port.icount.rx++;
913 /*
914 * to clear the FE, OR, NF, FE, PE flags,
915 * read STAT then read DATA reg
916 */
917 sr = lpuart32_read(&sport->port, UARTSTAT);
918 rx = lpuart32_read(&sport->port, UARTDATA);
919 rx &= 0x3ff;
920
921 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
922 continue;
923
924 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
925 if (sr & UARTSTAT_PE)
926 sport->port.icount.parity++;
927 else if (sr & UARTSTAT_FE)
928 sport->port.icount.frame++;
929
930 if (sr & UARTSTAT_OR)
931 sport->port.icount.overrun++;
932
933 if (sr & sport->port.ignore_status_mask) {
934 if (++ignored > 100)
935 goto out;
936 continue;
937 }
938
939 sr &= sport->port.read_status_mask;
940
941 if (sr & UARTSTAT_PE)
942 flg = TTY_PARITY;
943 else if (sr & UARTSTAT_FE)
944 flg = TTY_FRAME;
945
946 if (sr & UARTSTAT_OR)
947 flg = TTY_OVERRUN;
948
949#ifdef SUPPORT_SYSRQ
950 sport->port.sysrq = 0;
951#endif
952 }
953
954 tty_insert_flip_char(port, rx, flg);
955 }
956
957out:
958 spin_unlock_irqrestore(&sport->port.lock, flags);
959
960 tty_flip_buffer_push(port);
961}
962
963static irqreturn_t lpuart_int(int irq, void *dev_id)
964{
965 struct lpuart_port *sport = dev_id;
966 unsigned char sts;
967
968 sts = readb(sport->port.membase + UARTSR1);
969
970 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
971 lpuart_rxint(sport);
972
973 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
974 lpuart_txint(sport);
975
976 return IRQ_HANDLED;
977}
978
979static irqreturn_t lpuart32_int(int irq, void *dev_id)
980{
981 struct lpuart_port *sport = dev_id;
982 unsigned long sts, rxcount;
983
984 sts = lpuart32_read(&sport->port, UARTSTAT);
985 rxcount = lpuart32_read(&sport->port, UARTWATER);
986 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
987
988 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
989 lpuart32_rxint(sport);
990
991 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
992 lpuart32_txint(sport);
993
994 lpuart32_write(&sport->port, sts, UARTSTAT);
995 return IRQ_HANDLED;
996}
997
998static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
999{
1000 struct tty_port *port = &sport->port.state->port;
1001 struct dma_tx_state state;
1002 enum dma_status dmastat;
1003 struct circ_buf *ring = &sport->rx_ring;
1004 unsigned long flags;
1005 int count = 0;
1006
1007 if (lpuart_is_32(sport)) {
1008 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1009
1010 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1011 /* Read DR to clear the error flags */
1012 lpuart32_read(&sport->port, UARTDATA);
1013
1014 if (sr & UARTSTAT_PE)
1015 sport->port.icount.parity++;
1016 else if (sr & UARTSTAT_FE)
1017 sport->port.icount.frame++;
1018 }
1019 } else {
1020 unsigned char sr = readb(sport->port.membase + UARTSR1);
1021
1022 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1023 unsigned char cr2;
1024
1025 /* Disable receiver during this operation... */
1026 cr2 = readb(sport->port.membase + UARTCR2);
1027 cr2 &= ~UARTCR2_RE;
1028 writeb(cr2, sport->port.membase + UARTCR2);
1029
1030 /* Read DR to clear the error flags */
1031 readb(sport->port.membase + UARTDR);
1032
1033 if (sr & UARTSR1_PE)
1034 sport->port.icount.parity++;
1035 else if (sr & UARTSR1_FE)
1036 sport->port.icount.frame++;
1037 /*
1038 * At this point parity/framing error is
1039 * cleared However, since the DMA already read
1040 * the data register and we had to read it
1041 * again after reading the status register to
1042 * properly clear the flags, the FIFO actually
1043 * underflowed... This requires a clearing of
1044 * the FIFO...
1045 */
1046 if (readb(sport->port.membase + UARTSFIFO) &
1047 UARTSFIFO_RXUF) {
1048 writeb(UARTSFIFO_RXUF,
1049 sport->port.membase + UARTSFIFO);
1050 writeb(UARTCFIFO_RXFLUSH,
1051 sport->port.membase + UARTCFIFO);
1052 }
1053
1054 cr2 |= UARTCR2_RE;
1055 writeb(cr2, sport->port.membase + UARTCR2);
1056 }
1057 }
1058
1059 async_tx_ack(sport->dma_rx_desc);
1060
1061 spin_lock_irqsave(&sport->port.lock, flags);
1062
1063 dmastat = dmaengine_tx_status(sport->dma_rx_chan,
1064 sport->dma_rx_cookie,
1065 &state);
1066
1067 if (dmastat == DMA_ERROR) {
1068 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1069 spin_unlock_irqrestore(&sport->port.lock, flags);
1070 return;
1071 }
1072
1073 /* CPU claims ownership of RX DMA buffer */
1074 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1075
1076 /*
1077 * ring->head points to the end of data already written by the DMA.
1078 * ring->tail points to the beginning of data to be read by the
1079 * framework.
1080 * The current transfer size should not be larger than the dma buffer
1081 * length.
1082 */
1083 ring->head = sport->rx_sgl.length - state.residue;
1084 BUG_ON(ring->head > sport->rx_sgl.length);
1085 /*
1086 * At this point ring->head may point to the first byte right after the
1087 * last byte of the dma buffer:
1088 * 0 <= ring->head <= sport->rx_sgl.length
1089 *
1090 * However ring->tail must always points inside the dma buffer:
1091 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1092 *
1093 * Since we use a ring buffer, we have to handle the case
1094 * where head is lower than tail. In such a case, we first read from
1095 * tail to the end of the buffer then reset tail.
1096 */
1097 if (ring->head < ring->tail) {
1098 count = sport->rx_sgl.length - ring->tail;
1099
1100 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1101 ring->tail = 0;
1102 sport->port.icount.rx += count;
1103 }
1104
1105 /* Finally we read data from tail to head */
1106 if (ring->tail < ring->head) {
1107 count = ring->head - ring->tail;
1108 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1109 /* Wrap ring->head if needed */
1110 if (ring->head >= sport->rx_sgl.length)
1111 ring->head = 0;
1112 ring->tail = ring->head;
1113 sport->port.icount.rx += count;
1114 }
1115
1116 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
1117 DMA_FROM_DEVICE);
1118
1119 spin_unlock_irqrestore(&sport->port.lock, flags);
1120
1121 tty_flip_buffer_push(port);
1122 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1123}
1124
1125static void lpuart_dma_rx_complete(void *arg)
1126{
1127 struct lpuart_port *sport = arg;
1128
1129 lpuart_copy_rx_to_tty(sport);
1130}
1131
1132static void lpuart_timer_func(struct timer_list *t)
1133{
1134 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1135
1136 lpuart_copy_rx_to_tty(sport);
1137}
1138
1139static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1140{
1141 struct dma_slave_config dma_rx_sconfig = {};
1142 struct circ_buf *ring = &sport->rx_ring;
1143 int ret, nent;
1144 int bits, baud;
1145 struct tty_port *port = &sport->port.state->port;
1146 struct tty_struct *tty = port->tty;
1147 struct ktermios *termios = &tty->termios;
1148
1149 baud = tty_get_baud_rate(tty);
1150
1151 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1152 if (termios->c_cflag & PARENB)
1153 bits++;
1154
1155 /*
1156 * Calculate length of one DMA buffer size to keep latency below
1157 * 10ms at any baud rate.
1158 */
1159 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1160 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1161 if (sport->rx_dma_rng_buf_len < 16)
1162 sport->rx_dma_rng_buf_len = 16;
1163
1164 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1165 if (!ring->buf)
1166 return -ENOMEM;
1167
1168 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1169 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1170
1171 if (!nent) {
1172 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1173 return -EINVAL;
1174 }
1175
1176 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1177 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1178 dma_rx_sconfig.src_maxburst = 1;
1179 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1180 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1181
1182 if (ret < 0) {
1183 dev_err(sport->port.dev,
1184 "DMA Rx slave config failed, err = %d\n", ret);
1185 return ret;
1186 }
1187
1188 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
1189 sg_dma_address(&sport->rx_sgl),
1190 sport->rx_sgl.length,
1191 sport->rx_sgl.length / 2,
1192 DMA_DEV_TO_MEM,
1193 DMA_PREP_INTERRUPT);
1194 if (!sport->dma_rx_desc) {
1195 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1196 return -EFAULT;
1197 }
1198
1199 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1200 sport->dma_rx_desc->callback_param = sport;
1201 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1202 dma_async_issue_pending(sport->dma_rx_chan);
1203
1204 if (lpuart_is_32(sport)) {
1205 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1206
1207 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1208 } else {
1209 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1210 sport->port.membase + UARTCR5);
1211 }
1212
1213 return 0;
1214}
1215
1216static void lpuart_dma_rx_free(struct uart_port *port)
1217{
1218 struct lpuart_port *sport = container_of(port,
1219 struct lpuart_port, port);
1220
1221 if (sport->dma_rx_chan)
1222 dmaengine_terminate_all(sport->dma_rx_chan);
1223
1224 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1225 kfree(sport->rx_ring.buf);
1226 sport->rx_ring.tail = 0;
1227 sport->rx_ring.head = 0;
1228 sport->dma_rx_desc = NULL;
1229 sport->dma_rx_cookie = -EINVAL;
1230}
1231
1232static int lpuart_config_rs485(struct uart_port *port,
1233 struct serial_rs485 *rs485)
1234{
1235 struct lpuart_port *sport = container_of(port,
1236 struct lpuart_port, port);
1237
1238 u8 modem = readb(sport->port.membase + UARTMODEM) &
1239 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1240 writeb(modem, sport->port.membase + UARTMODEM);
1241
1242 /* clear unsupported configurations */
1243 rs485->delay_rts_before_send = 0;
1244 rs485->delay_rts_after_send = 0;
1245 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1246
1247 if (rs485->flags & SER_RS485_ENABLED) {
1248 /* Enable auto RS-485 RTS mode */
1249 modem |= UARTMODEM_TXRTSE;
1250
1251 /*
1252 * RTS needs to be logic HIGH either during transer _or_ after
1253 * transfer, other variants are not supported by the hardware.
1254 */
1255
1256 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1257 SER_RS485_RTS_AFTER_SEND)))
1258 rs485->flags |= SER_RS485_RTS_ON_SEND;
1259
1260 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1261 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1262 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1263
1264 /*
1265 * The hardware defaults to RTS logic HIGH while transfer.
1266 * Switch polarity in case RTS shall be logic HIGH
1267 * after transfer.
1268 * Note: UART is assumed to be active high.
1269 */
1270 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1271 modem &= ~UARTMODEM_TXRTSPOL;
1272 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1273 modem |= UARTMODEM_TXRTSPOL;
1274 }
1275
1276 /* Store the new configuration */
1277 sport->port.rs485 = *rs485;
1278
1279 writeb(modem, sport->port.membase + UARTMODEM);
1280 return 0;
1281}
1282
1283static unsigned int lpuart_get_mctrl(struct uart_port *port)
1284{
1285 unsigned int temp = 0;
1286 unsigned char reg;
1287
1288 reg = readb(port->membase + UARTMODEM);
1289 if (reg & UARTMODEM_TXCTSE)
1290 temp |= TIOCM_CTS;
1291
1292 if (reg & UARTMODEM_RXRTSE)
1293 temp |= TIOCM_RTS;
1294
1295 return temp;
1296}
1297
1298static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1299{
1300 unsigned int temp = 0;
1301 unsigned long reg;
1302
1303 reg = lpuart32_read(port, UARTMODIR);
1304 if (reg & UARTMODIR_TXCTSE)
1305 temp |= TIOCM_CTS;
1306
1307 if (reg & UARTMODIR_RXRTSE)
1308 temp |= TIOCM_RTS;
1309
1310 return temp;
1311}
1312
1313static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1314{
1315 unsigned char temp;
1316 struct lpuart_port *sport = container_of(port,
1317 struct lpuart_port, port);
1318
1319 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1320 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1321 temp = readb(sport->port.membase + UARTMODEM) &
1322 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1323
1324 if (mctrl & TIOCM_RTS)
1325 temp |= UARTMODEM_RXRTSE;
1326
1327 if (mctrl & TIOCM_CTS)
1328 temp |= UARTMODEM_TXCTSE;
1329
1330 writeb(temp, port->membase + UARTMODEM);
1331 }
1332}
1333
1334static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1335{
1336 unsigned long temp;
1337
1338 temp = lpuart32_read(port, UARTMODIR) &
1339 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1340
1341 if (mctrl & TIOCM_RTS)
1342 temp |= UARTMODIR_RXRTSE;
1343
1344 if (mctrl & TIOCM_CTS)
1345 temp |= UARTMODIR_TXCTSE;
1346
1347 lpuart32_write(port, temp, UARTMODIR);
1348}
1349
1350static void lpuart_break_ctl(struct uart_port *port, int break_state)
1351{
1352 unsigned char temp;
1353
1354 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1355
1356 if (break_state != 0)
1357 temp |= UARTCR2_SBK;
1358
1359 writeb(temp, port->membase + UARTCR2);
1360}
1361
1362static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1363{
1364 unsigned long temp;
1365
1366 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1367
1368 if (break_state != 0)
1369 temp |= UARTCTRL_SBK;
1370
1371 lpuart32_write(port, temp, UARTCTRL);
1372}
1373
1374static void lpuart_setup_watermark(struct lpuart_port *sport)
1375{
1376 unsigned char val, cr2;
1377 unsigned char cr2_saved;
1378
1379 cr2 = readb(sport->port.membase + UARTCR2);
1380 cr2_saved = cr2;
1381 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1382 UARTCR2_RIE | UARTCR2_RE);
1383 writeb(cr2, sport->port.membase + UARTCR2);
1384
1385 val = readb(sport->port.membase + UARTPFIFO);
1386 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1387 sport->port.membase + UARTPFIFO);
1388
1389 /* flush Tx and Rx FIFO */
1390 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1391 sport->port.membase + UARTCFIFO);
1392
1393 /* explicitly clear RDRF */
1394 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1395 readb(sport->port.membase + UARTDR);
1396 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1397 }
1398
1399 writeb(0, sport->port.membase + UARTTWFIFO);
1400 writeb(1, sport->port.membase + UARTRWFIFO);
1401
1402 /* Restore cr2 */
1403 writeb(cr2_saved, sport->port.membase + UARTCR2);
1404}
1405
1406static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1407{
1408 unsigned char cr2;
1409
1410 lpuart_setup_watermark(sport);
1411
1412 cr2 = readb(sport->port.membase + UARTCR2);
1413 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1414 writeb(cr2, sport->port.membase + UARTCR2);
1415}
1416
1417static void lpuart32_setup_watermark(struct lpuart_port *sport)
1418{
1419 unsigned long val, ctrl;
1420 unsigned long ctrl_saved;
1421
1422 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1423 ctrl_saved = ctrl;
1424 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1425 UARTCTRL_RIE | UARTCTRL_RE);
1426 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1427
1428 /* enable FIFO mode */
1429 val = lpuart32_read(&sport->port, UARTFIFO);
1430 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1431 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1432 lpuart32_write(&sport->port, val, UARTFIFO);
1433
1434 /* set the watermark */
1435 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1436 lpuart32_write(&sport->port, val, UARTWATER);
1437
1438 /* Restore cr2 */
1439 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1440}
1441
1442static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1443{
1444 u32 temp;
1445
1446 lpuart32_setup_watermark(sport);
1447
1448 temp = lpuart32_read(&sport->port, UARTCTRL);
1449 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1450 lpuart32_write(&sport->port, temp, UARTCTRL);
1451}
1452
1453static void rx_dma_timer_init(struct lpuart_port *sport)
1454{
1455 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1456 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1457 add_timer(&sport->lpuart_timer);
1458}
1459
1460static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1461{
1462 u32 uartbaud;
1463
1464 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
1465 init_waitqueue_head(&sport->dma_wait);
1466 sport->lpuart_dma_tx_use = true;
1467 if (lpuart_is_32(sport)) {
1468 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1469 lpuart32_write(&sport->port,
1470 uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1471 } else {
1472 writeb(readb(sport->port.membase + UARTCR5) |
1473 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1474 }
1475 } else {
1476 sport->lpuart_dma_tx_use = false;
1477 }
1478}
1479
1480static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1481{
1482 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1483 /* set Rx DMA timeout */
1484 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1485 if (!sport->dma_rx_timeout)
1486 sport->dma_rx_timeout = 1;
1487
1488 sport->lpuart_dma_rx_use = true;
1489 rx_dma_timer_init(sport);
1490 } else {
1491 sport->lpuart_dma_rx_use = false;
1492 }
1493}
1494
1495static int lpuart_startup(struct uart_port *port)
1496{
1497 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1498 unsigned long flags;
1499 unsigned char temp;
1500
1501 /* determine FIFO size and enable FIFO mode */
1502 temp = readb(sport->port.membase + UARTPFIFO);
1503
1504 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1505 UARTPFIFO_FIFOSIZE_MASK);
1506 sport->port.fifosize = sport->txfifo_size;
1507
1508 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1509 UARTPFIFO_FIFOSIZE_MASK);
1510
1511 spin_lock_irqsave(&sport->port.lock, flags);
1512
1513 lpuart_setup_watermark_enable(sport);
1514
1515 lpuart_rx_dma_startup(sport);
1516 lpuart_tx_dma_startup(sport);
1517
1518 spin_unlock_irqrestore(&sport->port.lock, flags);
1519
1520 return 0;
1521}
1522
1523static void lpuart32_configure(struct lpuart_port *sport)
1524{
1525 unsigned long temp;
1526
1527 if (sport->lpuart_dma_rx_use) {
1528 /* RXWATER must be 0 */
1529 temp = lpuart32_read(&sport->port, UARTWATER);
1530 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1531 lpuart32_write(&sport->port, temp, UARTWATER);
1532 }
1533 temp = lpuart32_read(&sport->port, UARTCTRL);
1534 if (!sport->lpuart_dma_rx_use)
1535 temp |= UARTCTRL_RIE;
1536 if (!sport->lpuart_dma_tx_use)
1537 temp |= UARTCTRL_TIE;
1538 lpuart32_write(&sport->port, temp, UARTCTRL);
1539}
1540
1541static int lpuart32_startup(struct uart_port *port)
1542{
1543 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1544 unsigned long flags;
1545 unsigned long temp;
1546
1547 /* determine FIFO size */
1548 temp = lpuart32_read(&sport->port, UARTFIFO);
1549
1550 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1551 UARTFIFO_FIFOSIZE_MASK);
1552 sport->port.fifosize = sport->txfifo_size;
1553
1554 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1555 UARTFIFO_FIFOSIZE_MASK);
1556
1557 spin_lock_irqsave(&sport->port.lock, flags);
1558
1559 lpuart32_setup_watermark_enable(sport);
1560
1561
1562 lpuart_rx_dma_startup(sport);
1563 lpuart_tx_dma_startup(sport);
1564
1565 lpuart32_configure(sport);
1566
1567 spin_unlock_irqrestore(&sport->port.lock, flags);
1568 return 0;
1569}
1570
1571static void lpuart_dma_shutdown(struct lpuart_port *sport)
1572{
1573 if (sport->lpuart_dma_rx_use) {
1574 del_timer_sync(&sport->lpuart_timer);
1575 lpuart_dma_rx_free(&sport->port);
1576 }
1577
1578 if (sport->lpuart_dma_tx_use) {
1579 if (wait_event_interruptible(sport->dma_wait,
1580 !sport->dma_tx_in_progress) != false) {
1581 sport->dma_tx_in_progress = false;
1582 dmaengine_terminate_all(sport->dma_tx_chan);
1583 }
1584 }
1585}
1586
1587static void lpuart_shutdown(struct uart_port *port)
1588{
1589 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1590 unsigned char temp;
1591 unsigned long flags;
1592
1593 spin_lock_irqsave(&port->lock, flags);
1594
1595 /* disable Rx/Tx and interrupts */
1596 temp = readb(port->membase + UARTCR2);
1597 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1598 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1599 writeb(temp, port->membase + UARTCR2);
1600
1601 spin_unlock_irqrestore(&port->lock, flags);
1602
1603 lpuart_dma_shutdown(sport);
1604}
1605
1606static void lpuart32_shutdown(struct uart_port *port)
1607{
1608 struct lpuart_port *sport =
1609 container_of(port, struct lpuart_port, port);
1610 unsigned long temp;
1611 unsigned long flags;
1612
1613 spin_lock_irqsave(&port->lock, flags);
1614
1615 /* disable Rx/Tx and interrupts */
1616 temp = lpuart32_read(port, UARTCTRL);
1617 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1618 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1619 lpuart32_write(port, temp, UARTCTRL);
1620
1621 spin_unlock_irqrestore(&port->lock, flags);
1622
1623 lpuart_dma_shutdown(sport);
1624}
1625
1626static void
1627lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1628 struct ktermios *old)
1629{
1630 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1631 unsigned long flags;
1632 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1633 unsigned int baud;
1634 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1635 unsigned int sbr, brfa;
1636
1637 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1638 old_cr2 = readb(sport->port.membase + UARTCR2);
1639 cr3 = readb(sport->port.membase + UARTCR3);
1640 cr4 = readb(sport->port.membase + UARTCR4);
1641 bdh = readb(sport->port.membase + UARTBDH);
1642 modem = readb(sport->port.membase + UARTMODEM);
1643 /*
1644 * only support CS8 and CS7, and for CS7 must enable PE.
1645 * supported mode:
1646 * - (7,e/o,1)
1647 * - (8,n,1)
1648 * - (8,m/s,1)
1649 * - (8,e/o,1)
1650 */
1651 while ((termios->c_cflag & CSIZE) != CS8 &&
1652 (termios->c_cflag & CSIZE) != CS7) {
1653 termios->c_cflag &= ~CSIZE;
1654 termios->c_cflag |= old_csize;
1655 old_csize = CS8;
1656 }
1657
1658 if ((termios->c_cflag & CSIZE) == CS8 ||
1659 (termios->c_cflag & CSIZE) == CS7)
1660 cr1 = old_cr1 & ~UARTCR1_M;
1661
1662 if (termios->c_cflag & CMSPAR) {
1663 if ((termios->c_cflag & CSIZE) != CS8) {
1664 termios->c_cflag &= ~CSIZE;
1665 termios->c_cflag |= CS8;
1666 }
1667 cr1 |= UARTCR1_M;
1668 }
1669
1670 /*
1671 * When auto RS-485 RTS mode is enabled,
1672 * hardware flow control need to be disabled.
1673 */
1674 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1675 termios->c_cflag &= ~CRTSCTS;
1676
1677 if (termios->c_cflag & CRTSCTS)
1678 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1679 else
1680 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1681
1682 termios->c_cflag &= ~CSTOPB;
1683
1684 /* parity must be enabled when CS7 to match 8-bits format */
1685 if ((termios->c_cflag & CSIZE) == CS7)
1686 termios->c_cflag |= PARENB;
1687
1688 if (termios->c_cflag & PARENB) {
1689 if (termios->c_cflag & CMSPAR) {
1690 cr1 &= ~UARTCR1_PE;
1691 if (termios->c_cflag & PARODD)
1692 cr3 |= UARTCR3_T8;
1693 else
1694 cr3 &= ~UARTCR3_T8;
1695 } else {
1696 cr1 |= UARTCR1_PE;
1697 if ((termios->c_cflag & CSIZE) == CS8)
1698 cr1 |= UARTCR1_M;
1699 if (termios->c_cflag & PARODD)
1700 cr1 |= UARTCR1_PT;
1701 else
1702 cr1 &= ~UARTCR1_PT;
1703 }
1704 } else {
1705 cr1 &= ~UARTCR1_PE;
1706 }
1707
1708 /* ask the core to calculate the divisor */
1709 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1710
1711 /*
1712 * Need to update the Ring buffer length according to the selected
1713 * baud rate and restart Rx DMA path.
1714 *
1715 * Since timer function acqures sport->port.lock, need to stop before
1716 * acquring same lock because otherwise del_timer_sync() can deadlock.
1717 */
1718 if (old && sport->lpuart_dma_rx_use) {
1719 del_timer_sync(&sport->lpuart_timer);
1720 lpuart_dma_rx_free(&sport->port);
1721 }
1722
1723 spin_lock_irqsave(&sport->port.lock, flags);
1724
1725 sport->port.read_status_mask = 0;
1726 if (termios->c_iflag & INPCK)
1727 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1728 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1729 sport->port.read_status_mask |= UARTSR1_FE;
1730
1731 /* characters to ignore */
1732 sport->port.ignore_status_mask = 0;
1733 if (termios->c_iflag & IGNPAR)
1734 sport->port.ignore_status_mask |= UARTSR1_PE;
1735 if (termios->c_iflag & IGNBRK) {
1736 sport->port.ignore_status_mask |= UARTSR1_FE;
1737 /*
1738 * if we're ignoring parity and break indicators,
1739 * ignore overruns too (for real raw support).
1740 */
1741 if (termios->c_iflag & IGNPAR)
1742 sport->port.ignore_status_mask |= UARTSR1_OR;
1743 }
1744
1745 /* update the per-port timeout */
1746 uart_update_timeout(port, termios->c_cflag, baud);
1747
1748 /* wait transmit engin complete */
1749 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1750
1751 /* disable transmit and receive */
1752 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1753 sport->port.membase + UARTCR2);
1754
1755 sbr = sport->port.uartclk / (16 * baud);
1756 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1757 bdh &= ~UARTBDH_SBR_MASK;
1758 bdh |= (sbr >> 8) & 0x1F;
1759 cr4 &= ~UARTCR4_BRFA_MASK;
1760 brfa &= UARTCR4_BRFA_MASK;
1761 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1762 writeb(bdh, sport->port.membase + UARTBDH);
1763 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1764 writeb(cr3, sport->port.membase + UARTCR3);
1765 writeb(cr1, sport->port.membase + UARTCR1);
1766 writeb(modem, sport->port.membase + UARTMODEM);
1767
1768 /* restore control register */
1769 writeb(old_cr2, sport->port.membase + UARTCR2);
1770
1771 if (old && sport->lpuart_dma_rx_use) {
1772 if (!lpuart_start_rx_dma(sport))
1773 rx_dma_timer_init(sport);
1774 else
1775 sport->lpuart_dma_rx_use = false;
1776 }
1777
1778 spin_unlock_irqrestore(&sport->port.lock, flags);
1779}
1780
1781static void
1782lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
1783{
1784 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1785 u32 clk = sport->port.uartclk;
1786
1787 /*
1788 * The idea is to use the best OSR (over-sampling rate) possible.
1789 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1790 * Loop to find the best OSR value possible, one that generates minimum
1791 * baud_diff iterate through the rest of the supported values of OSR.
1792 *
1793 * Calculation Formula:
1794 * Baud Rate = baud clock / ((OSR+1) × SBR)
1795 */
1796 baud_diff = baudrate;
1797 osr = 0;
1798 sbr = 0;
1799
1800 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1801 /* calculate the temporary sbr value */
1802 tmp_sbr = (clk / (baudrate * tmp_osr));
1803 if (tmp_sbr == 0)
1804 tmp_sbr = 1;
1805
1806 /*
1807 * calculate the baud rate difference based on the temporary
1808 * osr and sbr values
1809 */
1810 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1811
1812 /* select best values between sbr and sbr+1 */
1813 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1814 if (tmp_diff > (baudrate - tmp)) {
1815 tmp_diff = baudrate - tmp;
1816 tmp_sbr++;
1817 }
1818
1819 if (tmp_diff <= baud_diff) {
1820 baud_diff = tmp_diff;
1821 osr = tmp_osr;
1822 sbr = tmp_sbr;
1823
1824 if (!baud_diff)
1825 break;
1826 }
1827 }
1828
1829 /* handle buadrate outside acceptable rate */
1830 if (baud_diff > ((baudrate / 100) * 3))
1831 dev_warn(sport->port.dev,
1832 "unacceptable baud rate difference of more than 3%%\n");
1833
1834 tmp = lpuart32_read(&sport->port, UARTBAUD);
1835
1836 if ((osr > 3) && (osr < 8))
1837 tmp |= UARTBAUD_BOTHEDGE;
1838
1839 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1840 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
1841
1842 tmp &= ~UARTBAUD_SBR_MASK;
1843 tmp |= sbr & UARTBAUD_SBR_MASK;
1844
1845 if (!sport->lpuart_dma_rx_use)
1846 tmp &= ~UARTBAUD_RDMAE;
1847 if (!sport->lpuart_dma_tx_use)
1848 tmp &= ~UARTBAUD_TDMAE;
1849
1850 lpuart32_write(&sport->port, tmp, UARTBAUD);
1851}
1852
1853static void
1854lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1855 struct ktermios *old)
1856{
1857 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1858 unsigned long flags;
1859 unsigned long ctrl, old_ctrl, modem;
1860 unsigned int baud;
1861 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1862
1863 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1864 modem = lpuart32_read(&sport->port, UARTMODIR);
1865 /*
1866 * only support CS8 and CS7, and for CS7 must enable PE.
1867 * supported mode:
1868 * - (7,e/o,1)
1869 * - (8,n,1)
1870 * - (8,m/s,1)
1871 * - (8,e/o,1)
1872 */
1873 while ((termios->c_cflag & CSIZE) != CS8 &&
1874 (termios->c_cflag & CSIZE) != CS7) {
1875 termios->c_cflag &= ~CSIZE;
1876 termios->c_cflag |= old_csize;
1877 old_csize = CS8;
1878 }
1879
1880 if ((termios->c_cflag & CSIZE) == CS8 ||
1881 (termios->c_cflag & CSIZE) == CS7)
1882 ctrl = old_ctrl & ~UARTCTRL_M;
1883
1884 if (termios->c_cflag & CMSPAR) {
1885 if ((termios->c_cflag & CSIZE) != CS8) {
1886 termios->c_cflag &= ~CSIZE;
1887 termios->c_cflag |= CS8;
1888 }
1889 ctrl |= UARTCTRL_M;
1890 }
1891
1892 if (termios->c_cflag & CRTSCTS) {
1893 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1894 } else {
1895 termios->c_cflag &= ~CRTSCTS;
1896 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1897 }
1898
1899 if (termios->c_cflag & CSTOPB)
1900 termios->c_cflag &= ~CSTOPB;
1901
1902 /* parity must be enabled when CS7 to match 8-bits format */
1903 if ((termios->c_cflag & CSIZE) == CS7)
1904 termios->c_cflag |= PARENB;
1905
1906 if ((termios->c_cflag & PARENB)) {
1907 if (termios->c_cflag & CMSPAR) {
1908 ctrl &= ~UARTCTRL_PE;
1909 ctrl |= UARTCTRL_M;
1910 } else {
1911 ctrl |= UARTCTRL_PE;
1912 if ((termios->c_cflag & CSIZE) == CS8)
1913 ctrl |= UARTCTRL_M;
1914 if (termios->c_cflag & PARODD)
1915 ctrl |= UARTCTRL_PT;
1916 else
1917 ctrl &= ~UARTCTRL_PT;
1918 }
1919 } else {
1920 ctrl &= ~UARTCTRL_PE;
1921 }
1922
1923 /* ask the core to calculate the divisor */
1924 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1925
1926 /*
1927 * Need to update the Ring buffer length according to the selected
1928 * baud rate and restart Rx DMA path.
1929 *
1930 * Since timer function acqures sport->port.lock, need to stop before
1931 * acquring same lock because otherwise del_timer_sync() can deadlock.
1932 */
1933 if (old && sport->lpuart_dma_rx_use) {
1934 del_timer_sync(&sport->lpuart_timer);
1935 lpuart_dma_rx_free(&sport->port);
1936 }
1937
1938 spin_lock_irqsave(&sport->port.lock, flags);
1939
1940 sport->port.read_status_mask = 0;
1941 if (termios->c_iflag & INPCK)
1942 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
1943 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1944 sport->port.read_status_mask |= UARTSTAT_FE;
1945
1946 /* characters to ignore */
1947 sport->port.ignore_status_mask = 0;
1948 if (termios->c_iflag & IGNPAR)
1949 sport->port.ignore_status_mask |= UARTSTAT_PE;
1950 if (termios->c_iflag & IGNBRK) {
1951 sport->port.ignore_status_mask |= UARTSTAT_FE;
1952 /*
1953 * if we're ignoring parity and break indicators,
1954 * ignore overruns too (for real raw support).
1955 */
1956 if (termios->c_iflag & IGNPAR)
1957 sport->port.ignore_status_mask |= UARTSTAT_OR;
1958 }
1959
1960 /* update the per-port timeout */
1961 uart_update_timeout(port, termios->c_cflag, baud);
1962
1963 /* wait transmit engin complete */
1964 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
1965
1966 /* disable transmit and receive */
1967 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1968 UARTCTRL);
1969
1970 lpuart32_serial_setbrg(sport, baud);
1971 lpuart32_write(&sport->port, modem, UARTMODIR);
1972 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1973 /* restore control register */
1974
1975 if (old && sport->lpuart_dma_rx_use) {
1976 if (!lpuart_start_rx_dma(sport))
1977 rx_dma_timer_init(sport);
1978 else
1979 sport->lpuart_dma_rx_use = false;
1980 }
1981
1982 spin_unlock_irqrestore(&sport->port.lock, flags);
1983}
1984
1985static const char *lpuart_type(struct uart_port *port)
1986{
1987 return "FSL_LPUART";
1988}
1989
1990static void lpuart_release_port(struct uart_port *port)
1991{
1992 /* nothing to do */
1993}
1994
1995static int lpuart_request_port(struct uart_port *port)
1996{
1997 return 0;
1998}
1999
2000/* configure/autoconfigure the port */
2001static void lpuart_config_port(struct uart_port *port, int flags)
2002{
2003 if (flags & UART_CONFIG_TYPE)
2004 port->type = PORT_LPUART;
2005}
2006
2007static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2008{
2009 int ret = 0;
2010
2011 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2012 ret = -EINVAL;
2013 if (port->irq != ser->irq)
2014 ret = -EINVAL;
2015 if (ser->io_type != UPIO_MEM)
2016 ret = -EINVAL;
2017 if (port->uartclk / 16 != ser->baud_base)
2018 ret = -EINVAL;
2019 if (port->iobase != ser->port)
2020 ret = -EINVAL;
2021 if (ser->hub6 != 0)
2022 ret = -EINVAL;
2023 return ret;
2024}
2025
2026static const struct uart_ops lpuart_pops = {
2027 .tx_empty = lpuart_tx_empty,
2028 .set_mctrl = lpuart_set_mctrl,
2029 .get_mctrl = lpuart_get_mctrl,
2030 .stop_tx = lpuart_stop_tx,
2031 .start_tx = lpuart_start_tx,
2032 .stop_rx = lpuart_stop_rx,
2033 .break_ctl = lpuart_break_ctl,
2034 .startup = lpuart_startup,
2035 .shutdown = lpuart_shutdown,
2036 .set_termios = lpuart_set_termios,
2037 .type = lpuart_type,
2038 .request_port = lpuart_request_port,
2039 .release_port = lpuart_release_port,
2040 .config_port = lpuart_config_port,
2041 .verify_port = lpuart_verify_port,
2042 .flush_buffer = lpuart_flush_buffer,
2043#if defined(CONFIG_CONSOLE_POLL)
2044 .poll_init = lpuart_poll_init,
2045 .poll_get_char = lpuart_poll_get_char,
2046 .poll_put_char = lpuart_poll_put_char,
2047#endif
2048};
2049
2050static const struct uart_ops lpuart32_pops = {
2051 .tx_empty = lpuart32_tx_empty,
2052 .set_mctrl = lpuart32_set_mctrl,
2053 .get_mctrl = lpuart32_get_mctrl,
2054 .stop_tx = lpuart32_stop_tx,
2055 .start_tx = lpuart32_start_tx,
2056 .stop_rx = lpuart32_stop_rx,
2057 .break_ctl = lpuart32_break_ctl,
2058 .startup = lpuart32_startup,
2059 .shutdown = lpuart32_shutdown,
2060 .set_termios = lpuart32_set_termios,
2061 .type = lpuart_type,
2062 .request_port = lpuart_request_port,
2063 .release_port = lpuart_release_port,
2064 .config_port = lpuart_config_port,
2065 .verify_port = lpuart_verify_port,
2066 .flush_buffer = lpuart_flush_buffer,
2067#if defined(CONFIG_CONSOLE_POLL)
2068 .poll_init = lpuart32_poll_init,
2069 .poll_get_char = lpuart32_poll_get_char,
2070 .poll_put_char = lpuart32_poll_put_char,
2071#endif
2072};
2073
2074static struct lpuart_port *lpuart_ports[UART_NR];
2075
2076#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2077static void lpuart_console_putchar(struct uart_port *port, int ch)
2078{
2079 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2080 writeb(ch, port->membase + UARTDR);
2081}
2082
2083static void lpuart32_console_putchar(struct uart_port *port, int ch)
2084{
2085 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2086 lpuart32_write(port, ch, UARTDATA);
2087}
2088
2089static void
2090lpuart_console_write(struct console *co, const char *s, unsigned int count)
2091{
2092 struct lpuart_port *sport = lpuart_ports[co->index];
2093 unsigned char old_cr2, cr2;
2094 unsigned long flags;
2095 int locked = 1;
2096
2097 if (sport->port.sysrq || oops_in_progress)
2098 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2099 else
2100 spin_lock_irqsave(&sport->port.lock, flags);
2101
2102 /* first save CR2 and then disable interrupts */
2103 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2104 cr2 |= UARTCR2_TE | UARTCR2_RE;
2105 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2106 writeb(cr2, sport->port.membase + UARTCR2);
2107
2108 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2109
2110 /* wait for transmitter finish complete and restore CR2 */
2111 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2112
2113 writeb(old_cr2, sport->port.membase + UARTCR2);
2114
2115 if (locked)
2116 spin_unlock_irqrestore(&sport->port.lock, flags);
2117}
2118
2119static void
2120lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2121{
2122 struct lpuart_port *sport = lpuart_ports[co->index];
2123 unsigned long old_cr, cr;
2124 unsigned long flags;
2125 int locked = 1;
2126
2127 if (sport->port.sysrq || oops_in_progress)
2128 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2129 else
2130 spin_lock_irqsave(&sport->port.lock, flags);
2131
2132 /* first save CR2 and then disable interrupts */
2133 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2134 cr |= UARTCTRL_TE | UARTCTRL_RE;
2135 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2136 lpuart32_write(&sport->port, cr, UARTCTRL);
2137
2138 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2139
2140 /* wait for transmitter finish complete and restore CR2 */
2141 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2142
2143 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2144
2145 if (locked)
2146 spin_unlock_irqrestore(&sport->port.lock, flags);
2147}
2148
2149/*
2150 * if the port was already initialised (eg, by a boot loader),
2151 * try to determine the current setup.
2152 */
2153static void __init
2154lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2155 int *parity, int *bits)
2156{
2157 unsigned char cr, bdh, bdl, brfa;
2158 unsigned int sbr, uartclk, baud_raw;
2159
2160 cr = readb(sport->port.membase + UARTCR2);
2161 cr &= UARTCR2_TE | UARTCR2_RE;
2162 if (!cr)
2163 return;
2164
2165 /* ok, the port was enabled */
2166
2167 cr = readb(sport->port.membase + UARTCR1);
2168
2169 *parity = 'n';
2170 if (cr & UARTCR1_PE) {
2171 if (cr & UARTCR1_PT)
2172 *parity = 'o';
2173 else
2174 *parity = 'e';
2175 }
2176
2177 if (cr & UARTCR1_M)
2178 *bits = 9;
2179 else
2180 *bits = 8;
2181
2182 bdh = readb(sport->port.membase + UARTBDH);
2183 bdh &= UARTBDH_SBR_MASK;
2184 bdl = readb(sport->port.membase + UARTBDL);
2185 sbr = bdh;
2186 sbr <<= 8;
2187 sbr |= bdl;
2188 brfa = readb(sport->port.membase + UARTCR4);
2189 brfa &= UARTCR4_BRFA_MASK;
2190
2191 uartclk = lpuart_get_baud_clk_rate(sport);
2192 /*
2193 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2194 */
2195 baud_raw = uartclk / (16 * (sbr + brfa / 32));
2196
2197 if (*baud != baud_raw)
2198 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2199 "from %d to %d\n", baud_raw, *baud);
2200}
2201
2202static void __init
2203lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2204 int *parity, int *bits)
2205{
2206 unsigned long cr, bd;
2207 unsigned int sbr, uartclk, baud_raw;
2208
2209 cr = lpuart32_read(&sport->port, UARTCTRL);
2210 cr &= UARTCTRL_TE | UARTCTRL_RE;
2211 if (!cr)
2212 return;
2213
2214 /* ok, the port was enabled */
2215
2216 cr = lpuart32_read(&sport->port, UARTCTRL);
2217
2218 *parity = 'n';
2219 if (cr & UARTCTRL_PE) {
2220 if (cr & UARTCTRL_PT)
2221 *parity = 'o';
2222 else
2223 *parity = 'e';
2224 }
2225
2226 if (cr & UARTCTRL_M)
2227 *bits = 9;
2228 else
2229 *bits = 8;
2230
2231 bd = lpuart32_read(&sport->port, UARTBAUD);
2232 bd &= UARTBAUD_SBR_MASK;
2233 sbr = bd;
2234 uartclk = lpuart_get_baud_clk_rate(sport);
2235 /*
2236 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2237 */
2238 baud_raw = uartclk / (16 * sbr);
2239
2240 if (*baud != baud_raw)
2241 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2242 "from %d to %d\n", baud_raw, *baud);
2243}
2244
2245static int __init lpuart_console_setup(struct console *co, char *options)
2246{
2247 struct lpuart_port *sport;
2248 int baud = 115200;
2249 int bits = 8;
2250 int parity = 'n';
2251 int flow = 'n';
2252
2253 /*
2254 * check whether an invalid uart number has been specified, and
2255 * if so, search for the first available port that does have
2256 * console support.
2257 */
2258 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2259 co->index = 0;
2260
2261 sport = lpuart_ports[co->index];
2262 if (sport == NULL)
2263 return -ENODEV;
2264
2265 if (options)
2266 uart_parse_options(options, &baud, &parity, &bits, &flow);
2267 else
2268 if (lpuart_is_32(sport))
2269 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2270 else
2271 lpuart_console_get_options(sport, &baud, &parity, &bits);
2272
2273 if (lpuart_is_32(sport))
2274 lpuart32_setup_watermark(sport);
2275 else
2276 lpuart_setup_watermark(sport);
2277
2278 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2279}
2280
2281static struct uart_driver lpuart_reg;
2282static struct console lpuart_console = {
2283 .name = DEV_NAME,
2284 .write = lpuart_console_write,
2285 .device = uart_console_device,
2286 .setup = lpuart_console_setup,
2287 .flags = CON_PRINTBUFFER,
2288 .index = -1,
2289 .data = &lpuart_reg,
2290};
2291
2292static struct console lpuart32_console = {
2293 .name = DEV_NAME,
2294 .write = lpuart32_console_write,
2295 .device = uart_console_device,
2296 .setup = lpuart_console_setup,
2297 .flags = CON_PRINTBUFFER,
2298 .index = -1,
2299 .data = &lpuart_reg,
2300};
2301
2302static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2303{
2304 struct earlycon_device *dev = con->data;
2305
2306 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2307}
2308
2309static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2310{
2311 struct earlycon_device *dev = con->data;
2312
2313 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2314}
2315
2316static int __init lpuart_early_console_setup(struct earlycon_device *device,
2317 const char *opt)
2318{
2319 if (!device->port.membase)
2320 return -ENODEV;
2321
2322 device->con->write = lpuart_early_write;
2323 return 0;
2324}
2325
2326static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2327 const char *opt)
2328{
2329 if (!device->port.membase)
2330 return -ENODEV;
2331
2332 device->port.iotype = UPIO_MEM32BE;
2333 device->con->write = lpuart32_early_write;
2334 return 0;
2335}
2336
2337static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2338 const char *opt)
2339{
2340 if (!device->port.membase)
2341 return -ENODEV;
2342
2343 device->port.iotype = UPIO_MEM32;
2344 device->port.membase += IMX_REG_OFF;
2345 device->con->write = lpuart32_early_write;
2346
2347 return 0;
2348}
2349OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2350OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2351OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2352OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2353EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2354EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2355
2356#define LPUART_CONSOLE (&lpuart_console)
2357#define LPUART32_CONSOLE (&lpuart32_console)
2358#else
2359#define LPUART_CONSOLE NULL
2360#define LPUART32_CONSOLE NULL
2361#endif
2362
2363static struct uart_driver lpuart_reg = {
2364 .owner = THIS_MODULE,
2365 .driver_name = DRIVER_NAME,
2366 .dev_name = DEV_NAME,
2367 .nr = ARRAY_SIZE(lpuart_ports),
2368 .cons = LPUART_CONSOLE,
2369};
2370
2371static int lpuart_probe(struct platform_device *pdev)
2372{
2373 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2374 &pdev->dev);
2375 const struct lpuart_soc_data *sdata = of_id->data;
2376 struct device_node *np = pdev->dev.of_node;
2377 struct lpuart_port *sport;
2378 struct resource *res;
2379 int ret;
2380
2381 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2382 if (!sport)
2383 return -ENOMEM;
2384
2385 ret = of_alias_get_id(np, "serial");
2386 if (ret < 0) {
2387 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2388 if (ret < 0) {
2389 dev_err(&pdev->dev, "port line is full, add device failed\n");
2390 return ret;
2391 }
2392 }
2393 if (ret >= ARRAY_SIZE(lpuart_ports)) {
2394 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2395 return -EINVAL;
2396 }
2397 sport->port.line = ret;
2398 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2399 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2400 if (IS_ERR(sport->port.membase))
2401 return PTR_ERR(sport->port.membase);
2402
2403 sport->port.membase += sdata->reg_off;
2404 sport->port.mapbase = res->start;
2405 sport->port.dev = &pdev->dev;
2406 sport->port.type = PORT_LPUART;
2407 sport->devtype = sdata->devtype;
2408 ret = platform_get_irq(pdev, 0);
2409 if (ret < 0)
2410 return ret;
2411 sport->port.irq = ret;
2412 sport->port.iotype = sdata->iotype;
2413 if (lpuart_is_32(sport))
2414 sport->port.ops = &lpuart32_pops;
2415 else
2416 sport->port.ops = &lpuart_pops;
2417 sport->port.flags = UPF_BOOT_AUTOCONF;
2418
2419 sport->port.rs485_config = lpuart_config_rs485;
2420
2421 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2422 if (IS_ERR(sport->ipg_clk)) {
2423 ret = PTR_ERR(sport->ipg_clk);
2424 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2425 return ret;
2426 }
2427
2428 sport->baud_clk = NULL;
2429 if (is_imx8qxp_lpuart(sport)) {
2430 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2431 if (IS_ERR(sport->baud_clk)) {
2432 ret = PTR_ERR(sport->baud_clk);
2433 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2434 return ret;
2435 }
2436 }
2437
2438 ret = lpuart_enable_clks(sport);
2439 if (ret)
2440 return ret;
2441 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2442
2443 lpuart_ports[sport->port.line] = sport;
2444
2445 platform_set_drvdata(pdev, &sport->port);
2446
2447 if (lpuart_is_32(sport)) {
2448 lpuart_reg.cons = LPUART32_CONSOLE;
2449 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2450 DRIVER_NAME, sport);
2451 } else {
2452 lpuart_reg.cons = LPUART_CONSOLE;
2453 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2454 DRIVER_NAME, sport);
2455 }
2456
2457 if (ret)
2458 goto failed_irq_request;
2459
2460 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2461 if (ret)
2462 goto failed_attach_port;
2463
2464 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2465
2466 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2467 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2468
2469 if (sport->port.rs485.delay_rts_before_send ||
2470 sport->port.rs485.delay_rts_after_send)
2471 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2472
2473 lpuart_config_rs485(&sport->port, &sport->port.rs485);
2474
2475 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2476 if (!sport->dma_tx_chan)
2477 dev_info(sport->port.dev, "DMA tx channel request failed, "
2478 "operating without tx DMA\n");
2479
2480 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2481 if (!sport->dma_rx_chan)
2482 dev_info(sport->port.dev, "DMA rx channel request failed, "
2483 "operating without rx DMA\n");
2484
2485 return 0;
2486
2487failed_attach_port:
2488failed_irq_request:
2489 lpuart_disable_clks(sport);
2490 return ret;
2491}
2492
2493static int lpuart_remove(struct platform_device *pdev)
2494{
2495 struct lpuart_port *sport = platform_get_drvdata(pdev);
2496
2497 uart_remove_one_port(&lpuart_reg, &sport->port);
2498
2499 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2500
2501 lpuart_disable_clks(sport);
2502
2503 if (sport->dma_tx_chan)
2504 dma_release_channel(sport->dma_tx_chan);
2505
2506 if (sport->dma_rx_chan)
2507 dma_release_channel(sport->dma_rx_chan);
2508
2509 return 0;
2510}
2511
2512#ifdef CONFIG_PM_SLEEP
2513static int lpuart_suspend(struct device *dev)
2514{
2515 struct lpuart_port *sport = dev_get_drvdata(dev);
2516 unsigned long temp;
2517 bool irq_wake;
2518
2519 if (lpuart_is_32(sport)) {
2520 /* disable Rx/Tx and interrupts */
2521 temp = lpuart32_read(&sport->port, UARTCTRL);
2522 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2523 lpuart32_write(&sport->port, temp, UARTCTRL);
2524 } else {
2525 /* disable Rx/Tx and interrupts */
2526 temp = readb(sport->port.membase + UARTCR2);
2527 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2528 writeb(temp, sport->port.membase + UARTCR2);
2529 }
2530
2531 uart_suspend_port(&lpuart_reg, &sport->port);
2532
2533 /* uart_suspend_port() might set wakeup flag */
2534 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2535
2536 if (sport->lpuart_dma_rx_use) {
2537 /*
2538 * EDMA driver during suspend will forcefully release any
2539 * non-idle DMA channels. If port wakeup is enabled or if port
2540 * is console port or 'no_console_suspend' is set the Rx DMA
2541 * cannot resume as as expected, hence gracefully release the
2542 * Rx DMA path before suspend and start Rx DMA path on resume.
2543 */
2544 if (irq_wake) {
2545 del_timer_sync(&sport->lpuart_timer);
2546 lpuart_dma_rx_free(&sport->port);
2547 }
2548
2549 /* Disable Rx DMA to use UART port as wakeup source */
2550 if (lpuart_is_32(sport)) {
2551 temp = lpuart32_read(&sport->port, UARTBAUD);
2552 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2553 UARTBAUD);
2554 } else {
2555 writeb(readb(sport->port.membase + UARTCR5) &
2556 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2557 }
2558 }
2559
2560 if (sport->lpuart_dma_tx_use) {
2561 sport->dma_tx_in_progress = false;
2562 dmaengine_terminate_all(sport->dma_tx_chan);
2563 }
2564
2565 if (sport->port.suspended && !irq_wake)
2566 lpuart_disable_clks(sport);
2567
2568 return 0;
2569}
2570
2571static int lpuart_resume(struct device *dev)
2572{
2573 struct lpuart_port *sport = dev_get_drvdata(dev);
2574 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2575
2576 if (sport->port.suspended && !irq_wake)
2577 lpuart_enable_clks(sport);
2578
2579 if (lpuart_is_32(sport))
2580 lpuart32_setup_watermark_enable(sport);
2581 else
2582 lpuart_setup_watermark_enable(sport);
2583
2584 if (sport->lpuart_dma_rx_use) {
2585 if (irq_wake) {
2586 if (!lpuart_start_rx_dma(sport))
2587 rx_dma_timer_init(sport);
2588 else
2589 sport->lpuart_dma_rx_use = false;
2590 }
2591 }
2592
2593 lpuart_tx_dma_startup(sport);
2594
2595 if (lpuart_is_32(sport))
2596 lpuart32_configure(sport);
2597
2598 uart_resume_port(&lpuart_reg, &sport->port);
2599
2600 return 0;
2601}
2602#endif
2603
2604static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2605
2606static struct platform_driver lpuart_driver = {
2607 .probe = lpuart_probe,
2608 .remove = lpuart_remove,
2609 .driver = {
2610 .name = "fsl-lpuart",
2611 .of_match_table = lpuart_dt_ids,
2612 .pm = &lpuart_pm_ops,
2613 },
2614};
2615
2616static int __init lpuart_serial_init(void)
2617{
2618 int ret = uart_register_driver(&lpuart_reg);
2619
2620 if (ret)
2621 return ret;
2622
2623 ret = platform_driver_register(&lpuart_driver);
2624 if (ret)
2625 uart_unregister_driver(&lpuart_reg);
2626
2627 return ret;
2628}
2629
2630static void __exit lpuart_serial_exit(void)
2631{
2632 ida_destroy(&fsl_lpuart_ida);
2633 platform_driver_unregister(&lpuart_driver);
2634 uart_unregister_driver(&lpuart_reg);
2635}
2636
2637module_init(lpuart_serial_init);
2638module_exit(lpuart_serial_exit);
2639
2640MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2641MODULE_LICENSE("GPL v2");