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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Express I/O Virtualization (IOV) support
4 * Address Translation Service 1.0
5 * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
6 * PASID support added by Joerg Roedel <joerg.roedel@amd.com>
7 *
8 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
9 * Copyright (C) 2011 Advanced Micro Devices,
10 */
11
12#include <linux/export.h>
13#include <linux/pci-ats.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16
17#include "pci.h"
18
19void pci_ats_init(struct pci_dev *dev)
20{
21 int pos;
22
23 if (pci_ats_disabled())
24 return;
25
26 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
27 if (!pos)
28 return;
29
30 dev->ats_cap = pos;
31}
32
33/**
34 * pci_enable_ats - enable the ATS capability
35 * @dev: the PCI device
36 * @ps: the IOMMU page shift
37 *
38 * Returns 0 on success, or negative on failure.
39 */
40int pci_enable_ats(struct pci_dev *dev, int ps)
41{
42 u16 ctrl;
43 struct pci_dev *pdev;
44
45 if (!dev->ats_cap)
46 return -EINVAL;
47
48 if (WARN_ON(dev->ats_enabled))
49 return -EBUSY;
50
51 if (ps < PCI_ATS_MIN_STU)
52 return -EINVAL;
53
54 /*
55 * Note that enabling ATS on a VF fails unless it's already enabled
56 * with the same STU on the PF.
57 */
58 ctrl = PCI_ATS_CTRL_ENABLE;
59 if (dev->is_virtfn) {
60 pdev = pci_physfn(dev);
61 if (pdev->ats_stu != ps)
62 return -EINVAL;
63
64 atomic_inc(&pdev->ats_ref_cnt); /* count enabled VFs */
65 } else {
66 dev->ats_stu = ps;
67 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
68 }
69 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
70
71 dev->ats_enabled = 1;
72 return 0;
73}
74EXPORT_SYMBOL_GPL(pci_enable_ats);
75
76/**
77 * pci_disable_ats - disable the ATS capability
78 * @dev: the PCI device
79 */
80void pci_disable_ats(struct pci_dev *dev)
81{
82 struct pci_dev *pdev;
83 u16 ctrl;
84
85 if (WARN_ON(!dev->ats_enabled))
86 return;
87
88 if (atomic_read(&dev->ats_ref_cnt))
89 return; /* VFs still enabled */
90
91 if (dev->is_virtfn) {
92 pdev = pci_physfn(dev);
93 atomic_dec(&pdev->ats_ref_cnt);
94 }
95
96 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
97 ctrl &= ~PCI_ATS_CTRL_ENABLE;
98 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
99
100 dev->ats_enabled = 0;
101}
102EXPORT_SYMBOL_GPL(pci_disable_ats);
103
104void pci_restore_ats_state(struct pci_dev *dev)
105{
106 u16 ctrl;
107
108 if (!dev->ats_enabled)
109 return;
110
111 ctrl = PCI_ATS_CTRL_ENABLE;
112 if (!dev->is_virtfn)
113 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
114 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
115}
116EXPORT_SYMBOL_GPL(pci_restore_ats_state);
117
118/**
119 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
120 * @dev: the PCI device
121 *
122 * Returns the queue depth on success, or negative on failure.
123 *
124 * The ATS spec uses 0 in the Invalidate Queue Depth field to
125 * indicate that the function can accept 32 Invalidate Request.
126 * But here we use the `real' values (i.e. 1~32) for the Queue
127 * Depth; and 0 indicates the function shares the Queue with
128 * other functions (doesn't exclusively own a Queue).
129 */
130int pci_ats_queue_depth(struct pci_dev *dev)
131{
132 u16 cap;
133
134 if (!dev->ats_cap)
135 return -EINVAL;
136
137 if (dev->is_virtfn)
138 return 0;
139
140 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
141 return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
142}
143EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
144
145/**
146 * pci_ats_page_aligned - Return Page Aligned Request bit status.
147 * @pdev: the PCI device
148 *
149 * Returns 1, if the Untranslated Addresses generated by the device
150 * are always aligned or 0 otherwise.
151 *
152 * Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
153 * is set, it indicates the Untranslated Addresses generated by the
154 * device are always aligned to a 4096 byte boundary.
155 */
156int pci_ats_page_aligned(struct pci_dev *pdev)
157{
158 u16 cap;
159
160 if (!pdev->ats_cap)
161 return 0;
162
163 pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
164
165 if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
166 return 1;
167
168 return 0;
169}
170EXPORT_SYMBOL_GPL(pci_ats_page_aligned);
171
172#ifdef CONFIG_PCI_PRI
173/**
174 * pci_enable_pri - Enable PRI capability
175 * @ pdev: PCI device structure
176 *
177 * Returns 0 on success, negative value on error
178 */
179int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
180{
181 u16 control, status;
182 u32 max_requests;
183 int pos;
184
185 if (WARN_ON(pdev->pri_enabled))
186 return -EBUSY;
187
188 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
189 if (!pos)
190 return -EINVAL;
191
192 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
193 if (!(status & PCI_PRI_STATUS_STOPPED))
194 return -EBUSY;
195
196 pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
197 reqs = min(max_requests, reqs);
198 pdev->pri_reqs_alloc = reqs;
199 pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
200
201 control = PCI_PRI_CTRL_ENABLE;
202 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
203
204 pdev->pri_enabled = 1;
205
206 return 0;
207}
208EXPORT_SYMBOL_GPL(pci_enable_pri);
209
210/**
211 * pci_disable_pri - Disable PRI capability
212 * @pdev: PCI device structure
213 *
214 * Only clears the enabled-bit, regardless of its former value
215 */
216void pci_disable_pri(struct pci_dev *pdev)
217{
218 u16 control;
219 int pos;
220
221 if (WARN_ON(!pdev->pri_enabled))
222 return;
223
224 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
225 if (!pos)
226 return;
227
228 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
229 control &= ~PCI_PRI_CTRL_ENABLE;
230 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
231
232 pdev->pri_enabled = 0;
233}
234EXPORT_SYMBOL_GPL(pci_disable_pri);
235
236/**
237 * pci_restore_pri_state - Restore PRI
238 * @pdev: PCI device structure
239 */
240void pci_restore_pri_state(struct pci_dev *pdev)
241{
242 u16 control = PCI_PRI_CTRL_ENABLE;
243 u32 reqs = pdev->pri_reqs_alloc;
244 int pos;
245
246 if (!pdev->pri_enabled)
247 return;
248
249 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
250 if (!pos)
251 return;
252
253 pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
254 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
255}
256EXPORT_SYMBOL_GPL(pci_restore_pri_state);
257
258/**
259 * pci_reset_pri - Resets device's PRI state
260 * @pdev: PCI device structure
261 *
262 * The PRI capability must be disabled before this function is called.
263 * Returns 0 on success, negative value on error.
264 */
265int pci_reset_pri(struct pci_dev *pdev)
266{
267 u16 control;
268 int pos;
269
270 if (WARN_ON(pdev->pri_enabled))
271 return -EBUSY;
272
273 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
274 if (!pos)
275 return -EINVAL;
276
277 control = PCI_PRI_CTRL_RESET;
278 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
279
280 return 0;
281}
282EXPORT_SYMBOL_GPL(pci_reset_pri);
283#endif /* CONFIG_PCI_PRI */
284
285#ifdef CONFIG_PCI_PASID
286/**
287 * pci_enable_pasid - Enable the PASID capability
288 * @pdev: PCI device structure
289 * @features: Features to enable
290 *
291 * Returns 0 on success, negative value on error. This function checks
292 * whether the features are actually supported by the device and returns
293 * an error if not.
294 */
295int pci_enable_pasid(struct pci_dev *pdev, int features)
296{
297 u16 control, supported;
298 int pos;
299
300 if (WARN_ON(pdev->pasid_enabled))
301 return -EBUSY;
302
303 if (!pdev->eetlp_prefix_path)
304 return -EINVAL;
305
306 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
307 if (!pos)
308 return -EINVAL;
309
310 pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
311 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
312
313 /* User wants to enable anything unsupported? */
314 if ((supported & features) != features)
315 return -EINVAL;
316
317 control = PCI_PASID_CTRL_ENABLE | features;
318 pdev->pasid_features = features;
319
320 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
321
322 pdev->pasid_enabled = 1;
323
324 return 0;
325}
326EXPORT_SYMBOL_GPL(pci_enable_pasid);
327
328/**
329 * pci_disable_pasid - Disable the PASID capability
330 * @pdev: PCI device structure
331 */
332void pci_disable_pasid(struct pci_dev *pdev)
333{
334 u16 control = 0;
335 int pos;
336
337 if (WARN_ON(!pdev->pasid_enabled))
338 return;
339
340 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
341 if (!pos)
342 return;
343
344 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
345
346 pdev->pasid_enabled = 0;
347}
348EXPORT_SYMBOL_GPL(pci_disable_pasid);
349
350/**
351 * pci_restore_pasid_state - Restore PASID capabilities
352 * @pdev: PCI device structure
353 */
354void pci_restore_pasid_state(struct pci_dev *pdev)
355{
356 u16 control;
357 int pos;
358
359 if (!pdev->pasid_enabled)
360 return;
361
362 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
363 if (!pos)
364 return;
365
366 control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
367 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
368}
369EXPORT_SYMBOL_GPL(pci_restore_pasid_state);
370
371/**
372 * pci_pasid_features - Check which PASID features are supported
373 * @pdev: PCI device structure
374 *
375 * Returns a negative value when no PASI capability is present.
376 * Otherwise is returns a bitmask with supported features. Current
377 * features reported are:
378 * PCI_PASID_CAP_EXEC - Execute permission supported
379 * PCI_PASID_CAP_PRIV - Privileged mode supported
380 */
381int pci_pasid_features(struct pci_dev *pdev)
382{
383 u16 supported;
384 int pos;
385
386 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
387 if (!pos)
388 return -EINVAL;
389
390 pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
391
392 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
393
394 return supported;
395}
396EXPORT_SYMBOL_GPL(pci_pasid_features);
397
398/**
399 * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
400 * status.
401 * @pdev: PCI device structure
402 *
403 * Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
404 *
405 * Even though the PRG response PASID status is read from PRI Status
406 * Register, since this API will mainly be used by PASID users, this
407 * function is defined within #ifdef CONFIG_PCI_PASID instead of
408 * CONFIG_PCI_PRI.
409 */
410int pci_prg_resp_pasid_required(struct pci_dev *pdev)
411{
412 u16 status;
413 int pos;
414
415 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
416 if (!pos)
417 return 0;
418
419 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
420
421 if (status & PCI_PRI_STATUS_PASID)
422 return 1;
423
424 return 0;
425}
426EXPORT_SYMBOL_GPL(pci_prg_resp_pasid_required);
427
428#define PASID_NUMBER_SHIFT 8
429#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
430/**
431 * pci_max_pasid - Get maximum number of PASIDs supported by device
432 * @pdev: PCI device structure
433 *
434 * Returns negative value when PASID capability is not present.
435 * Otherwise it returns the number of supported PASIDs.
436 */
437int pci_max_pasids(struct pci_dev *pdev)
438{
439 u16 supported;
440 int pos;
441
442 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
443 if (!pos)
444 return -EINVAL;
445
446 pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
447
448 supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
449
450 return (1 << supported);
451}
452EXPORT_SYMBOL_GPL(pci_max_pasids);
453#endif /* CONFIG_PCI_PASID */
1/*
2 * drivers/pci/ats.c
3 *
4 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
5 * Copyright (C) 2011 Advanced Micro Devices,
6 *
7 * PCI Express I/O Virtualization (IOV) support.
8 * Address Translation Service 1.0
9 * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
10 * PASID support added by Joerg Roedel <joerg.roedel@amd.com>
11 */
12
13#include <linux/export.h>
14#include <linux/pci-ats.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17
18#include "pci.h"
19
20static int ats_alloc_one(struct pci_dev *dev, int ps)
21{
22 int pos;
23 u16 cap;
24 struct pci_ats *ats;
25
26 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
27 if (!pos)
28 return -ENODEV;
29
30 ats = kzalloc(sizeof(*ats), GFP_KERNEL);
31 if (!ats)
32 return -ENOMEM;
33
34 ats->pos = pos;
35 ats->stu = ps;
36 pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
37 ats->qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
38 PCI_ATS_MAX_QDEP;
39 dev->ats = ats;
40
41 return 0;
42}
43
44static void ats_free_one(struct pci_dev *dev)
45{
46 kfree(dev->ats);
47 dev->ats = NULL;
48}
49
50/**
51 * pci_enable_ats - enable the ATS capability
52 * @dev: the PCI device
53 * @ps: the IOMMU page shift
54 *
55 * Returns 0 on success, or negative on failure.
56 */
57int pci_enable_ats(struct pci_dev *dev, int ps)
58{
59 int rc;
60 u16 ctrl;
61
62 BUG_ON(dev->ats && dev->ats->is_enabled);
63
64 if (ps < PCI_ATS_MIN_STU)
65 return -EINVAL;
66
67 if (dev->is_physfn || dev->is_virtfn) {
68 struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
69
70 mutex_lock(&pdev->sriov->lock);
71 if (pdev->ats)
72 rc = pdev->ats->stu == ps ? 0 : -EINVAL;
73 else
74 rc = ats_alloc_one(pdev, ps);
75
76 if (!rc)
77 pdev->ats->ref_cnt++;
78 mutex_unlock(&pdev->sriov->lock);
79 if (rc)
80 return rc;
81 }
82
83 if (!dev->is_physfn) {
84 rc = ats_alloc_one(dev, ps);
85 if (rc)
86 return rc;
87 }
88
89 ctrl = PCI_ATS_CTRL_ENABLE;
90 if (!dev->is_virtfn)
91 ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU);
92 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
93
94 dev->ats->is_enabled = 1;
95
96 return 0;
97}
98EXPORT_SYMBOL_GPL(pci_enable_ats);
99
100/**
101 * pci_disable_ats - disable the ATS capability
102 * @dev: the PCI device
103 */
104void pci_disable_ats(struct pci_dev *dev)
105{
106 u16 ctrl;
107
108 BUG_ON(!dev->ats || !dev->ats->is_enabled);
109
110 pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl);
111 ctrl &= ~PCI_ATS_CTRL_ENABLE;
112 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
113
114 dev->ats->is_enabled = 0;
115
116 if (dev->is_physfn || dev->is_virtfn) {
117 struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
118
119 mutex_lock(&pdev->sriov->lock);
120 pdev->ats->ref_cnt--;
121 if (!pdev->ats->ref_cnt)
122 ats_free_one(pdev);
123 mutex_unlock(&pdev->sriov->lock);
124 }
125
126 if (!dev->is_physfn)
127 ats_free_one(dev);
128}
129EXPORT_SYMBOL_GPL(pci_disable_ats);
130
131void pci_restore_ats_state(struct pci_dev *dev)
132{
133 u16 ctrl;
134
135 if (!pci_ats_enabled(dev))
136 return;
137 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS))
138 BUG();
139
140 ctrl = PCI_ATS_CTRL_ENABLE;
141 if (!dev->is_virtfn)
142 ctrl |= PCI_ATS_CTRL_STU(dev->ats->stu - PCI_ATS_MIN_STU);
143
144 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
145}
146EXPORT_SYMBOL_GPL(pci_restore_ats_state);
147
148/**
149 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
150 * @dev: the PCI device
151 *
152 * Returns the queue depth on success, or negative on failure.
153 *
154 * The ATS spec uses 0 in the Invalidate Queue Depth field to
155 * indicate that the function can accept 32 Invalidate Request.
156 * But here we use the `real' values (i.e. 1~32) for the Queue
157 * Depth; and 0 indicates the function shares the Queue with
158 * other functions (doesn't exclusively own a Queue).
159 */
160int pci_ats_queue_depth(struct pci_dev *dev)
161{
162 int pos;
163 u16 cap;
164
165 if (dev->is_virtfn)
166 return 0;
167
168 if (dev->ats)
169 return dev->ats->qdep;
170
171 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
172 if (!pos)
173 return -ENODEV;
174
175 pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
176
177 return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
178 PCI_ATS_MAX_QDEP;
179}
180EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
181
182#ifdef CONFIG_PCI_PRI
183/**
184 * pci_enable_pri - Enable PRI capability
185 * @ pdev: PCI device structure
186 *
187 * Returns 0 on success, negative value on error
188 */
189int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
190{
191 u16 control, status;
192 u32 max_requests;
193 int pos;
194
195 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
196 if (!pos)
197 return -EINVAL;
198
199 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
200 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
201 if ((control & PCI_PRI_CTRL_ENABLE) ||
202 !(status & PCI_PRI_STATUS_STOPPED))
203 return -EBUSY;
204
205 pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
206 reqs = min(max_requests, reqs);
207 pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
208
209 control |= PCI_PRI_CTRL_ENABLE;
210 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
211
212 return 0;
213}
214EXPORT_SYMBOL_GPL(pci_enable_pri);
215
216/**
217 * pci_disable_pri - Disable PRI capability
218 * @pdev: PCI device structure
219 *
220 * Only clears the enabled-bit, regardless of its former value
221 */
222void pci_disable_pri(struct pci_dev *pdev)
223{
224 u16 control;
225 int pos;
226
227 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
228 if (!pos)
229 return;
230
231 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
232 control &= ~PCI_PRI_CTRL_ENABLE;
233 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
234}
235EXPORT_SYMBOL_GPL(pci_disable_pri);
236
237/**
238 * pci_pri_enabled - Checks if PRI capability is enabled
239 * @pdev: PCI device structure
240 *
241 * Returns true if PRI is enabled on the device, false otherwise
242 */
243bool pci_pri_enabled(struct pci_dev *pdev)
244{
245 u16 control;
246 int pos;
247
248 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
249 if (!pos)
250 return false;
251
252 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
253
254 return (control & PCI_PRI_CTRL_ENABLE) ? true : false;
255}
256EXPORT_SYMBOL_GPL(pci_pri_enabled);
257
258/**
259 * pci_reset_pri - Resets device's PRI state
260 * @pdev: PCI device structure
261 *
262 * The PRI capability must be disabled before this function is called.
263 * Returns 0 on success, negative value on error.
264 */
265int pci_reset_pri(struct pci_dev *pdev)
266{
267 u16 control;
268 int pos;
269
270 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
271 if (!pos)
272 return -EINVAL;
273
274 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
275 if (control & PCI_PRI_CTRL_ENABLE)
276 return -EBUSY;
277
278 control |= PCI_PRI_CTRL_RESET;
279
280 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
281
282 return 0;
283}
284EXPORT_SYMBOL_GPL(pci_reset_pri);
285
286/**
287 * pci_pri_stopped - Checks whether the PRI capability is stopped
288 * @pdev: PCI device structure
289 *
290 * Returns true if the PRI capability on the device is disabled and the
291 * device has no outstanding PRI requests, false otherwise. The device
292 * indicates this via the STOPPED bit in the status register of the
293 * capability.
294 * The device internal state can be cleared by resetting the PRI state
295 * with pci_reset_pri(). This can force the capability into the STOPPED
296 * state.
297 */
298bool pci_pri_stopped(struct pci_dev *pdev)
299{
300 u16 control, status;
301 int pos;
302
303 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
304 if (!pos)
305 return true;
306
307 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
308 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
309
310 if (control & PCI_PRI_CTRL_ENABLE)
311 return false;
312
313 return (status & PCI_PRI_STATUS_STOPPED) ? true : false;
314}
315EXPORT_SYMBOL_GPL(pci_pri_stopped);
316
317/**
318 * pci_pri_status - Request PRI status of a device
319 * @pdev: PCI device structure
320 *
321 * Returns negative value on failure, status on success. The status can
322 * be checked against status-bits. Supported bits are currently:
323 * PCI_PRI_STATUS_RF: Response failure
324 * PCI_PRI_STATUS_UPRGI: Unexpected Page Request Group Index
325 * PCI_PRI_STATUS_STOPPED: PRI has stopped
326 */
327int pci_pri_status(struct pci_dev *pdev)
328{
329 u16 status, control;
330 int pos;
331
332 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
333 if (!pos)
334 return -EINVAL;
335
336 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
337 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
338
339 /* Stopped bit is undefined when enable == 1, so clear it */
340 if (control & PCI_PRI_CTRL_ENABLE)
341 status &= ~PCI_PRI_STATUS_STOPPED;
342
343 return status;
344}
345EXPORT_SYMBOL_GPL(pci_pri_status);
346#endif /* CONFIG_PCI_PRI */
347
348#ifdef CONFIG_PCI_PASID
349/**
350 * pci_enable_pasid - Enable the PASID capability
351 * @pdev: PCI device structure
352 * @features: Features to enable
353 *
354 * Returns 0 on success, negative value on error. This function checks
355 * whether the features are actually supported by the device and returns
356 * an error if not.
357 */
358int pci_enable_pasid(struct pci_dev *pdev, int features)
359{
360 u16 control, supported;
361 int pos;
362
363 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
364 if (!pos)
365 return -EINVAL;
366
367 pci_read_config_word(pdev, pos + PCI_PASID_CTRL, &control);
368 pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
369
370 if (control & PCI_PASID_CTRL_ENABLE)
371 return -EINVAL;
372
373 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
374
375 /* User wants to enable anything unsupported? */
376 if ((supported & features) != features)
377 return -EINVAL;
378
379 control = PCI_PASID_CTRL_ENABLE | features;
380
381 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
382
383 return 0;
384}
385EXPORT_SYMBOL_GPL(pci_enable_pasid);
386
387/**
388 * pci_disable_pasid - Disable the PASID capability
389 * @pdev: PCI device structure
390 *
391 */
392void pci_disable_pasid(struct pci_dev *pdev)
393{
394 u16 control = 0;
395 int pos;
396
397 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
398 if (!pos)
399 return;
400
401 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
402}
403EXPORT_SYMBOL_GPL(pci_disable_pasid);
404
405/**
406 * pci_pasid_features - Check which PASID features are supported
407 * @pdev: PCI device structure
408 *
409 * Returns a negative value when no PASI capability is present.
410 * Otherwise is returns a bitmask with supported features. Current
411 * features reported are:
412 * PCI_PASID_CAP_EXEC - Execute permission supported
413 * PCI_PASID_CAP_PRIV - Priviledged mode supported
414 */
415int pci_pasid_features(struct pci_dev *pdev)
416{
417 u16 supported;
418 int pos;
419
420 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
421 if (!pos)
422 return -EINVAL;
423
424 pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
425
426 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
427
428 return supported;
429}
430EXPORT_SYMBOL_GPL(pci_pasid_features);
431
432#define PASID_NUMBER_SHIFT 8
433#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
434/**
435 * pci_max_pasid - Get maximum number of PASIDs supported by device
436 * @pdev: PCI device structure
437 *
438 * Returns negative value when PASID capability is not present.
439 * Otherwise it returns the numer of supported PASIDs.
440 */
441int pci_max_pasids(struct pci_dev *pdev)
442{
443 u16 supported;
444 int pos;
445
446 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
447 if (!pos)
448 return -EINVAL;
449
450 pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
451
452 supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
453
454 return (1 << supported);
455}
456EXPORT_SYMBOL_GPL(pci_max_pasids);
457#endif /* CONFIG_PCI_PASID */