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1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/hpet.h>
7#include <linux/cpu.h>
8#include <linux/irq.h>
9
10#include <asm/hpet.h>
11#include <asm/time.h>
12
13#undef pr_fmt
14#define pr_fmt(fmt) "hpet: " fmt
15
16enum hpet_mode {
17 HPET_MODE_UNUSED,
18 HPET_MODE_LEGACY,
19 HPET_MODE_CLOCKEVT,
20 HPET_MODE_DEVICE,
21};
22
23struct hpet_channel {
24 struct clock_event_device evt;
25 unsigned int num;
26 unsigned int cpu;
27 unsigned int irq;
28 unsigned int in_use;
29 enum hpet_mode mode;
30 unsigned int boot_cfg;
31 char name[10];
32};
33
34struct hpet_base {
35 unsigned int nr_channels;
36 unsigned int nr_clockevents;
37 unsigned int boot_cfg;
38 struct hpet_channel *channels;
39};
40
41#define HPET_MASK CLOCKSOURCE_MASK(32)
42
43#define HPET_MIN_CYCLES 128
44#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
45
46/*
47 * HPET address is set in acpi/boot.c, when an ACPI entry exists
48 */
49unsigned long hpet_address;
50u8 hpet_blockid; /* OS timer block num */
51bool hpet_msi_disable;
52
53#ifdef CONFIG_PCI_MSI
54static DEFINE_PER_CPU(struct hpet_channel *, cpu_hpet_channel);
55static struct irq_domain *hpet_domain;
56#endif
57
58static void __iomem *hpet_virt_address;
59
60static struct hpet_base hpet_base;
61
62static bool hpet_legacy_int_enabled;
63static unsigned long hpet_freq;
64
65bool boot_hpet_disable;
66bool hpet_force_user;
67static bool hpet_verbose;
68
69static inline
70struct hpet_channel *clockevent_to_channel(struct clock_event_device *evt)
71{
72 return container_of(evt, struct hpet_channel, evt);
73}
74
75inline unsigned int hpet_readl(unsigned int a)
76{
77 return readl(hpet_virt_address + a);
78}
79
80static inline void hpet_writel(unsigned int d, unsigned int a)
81{
82 writel(d, hpet_virt_address + a);
83}
84
85static inline void hpet_set_mapping(void)
86{
87 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
88}
89
90static inline void hpet_clear_mapping(void)
91{
92 iounmap(hpet_virt_address);
93 hpet_virt_address = NULL;
94}
95
96/*
97 * HPET command line enable / disable
98 */
99static int __init hpet_setup(char *str)
100{
101 while (str) {
102 char *next = strchr(str, ',');
103
104 if (next)
105 *next++ = 0;
106 if (!strncmp("disable", str, 7))
107 boot_hpet_disable = true;
108 if (!strncmp("force", str, 5))
109 hpet_force_user = true;
110 if (!strncmp("verbose", str, 7))
111 hpet_verbose = true;
112 str = next;
113 }
114 return 1;
115}
116__setup("hpet=", hpet_setup);
117
118static int __init disable_hpet(char *str)
119{
120 boot_hpet_disable = true;
121 return 1;
122}
123__setup("nohpet", disable_hpet);
124
125static inline int is_hpet_capable(void)
126{
127 return !boot_hpet_disable && hpet_address;
128}
129
130/**
131 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
132 */
133int is_hpet_enabled(void)
134{
135 return is_hpet_capable() && hpet_legacy_int_enabled;
136}
137EXPORT_SYMBOL_GPL(is_hpet_enabled);
138
139static void _hpet_print_config(const char *function, int line)
140{
141 u32 i, id, period, cfg, status, channels, l, h;
142
143 pr_info("%s(%d):\n", function, line);
144
145 id = hpet_readl(HPET_ID);
146 period = hpet_readl(HPET_PERIOD);
147 pr_info("ID: 0x%x, PERIOD: 0x%x\n", id, period);
148
149 cfg = hpet_readl(HPET_CFG);
150 status = hpet_readl(HPET_STATUS);
151 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status);
152
153 l = hpet_readl(HPET_COUNTER);
154 h = hpet_readl(HPET_COUNTER+4);
155 pr_info("COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
156
157 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
158
159 for (i = 0; i < channels; i++) {
160 l = hpet_readl(HPET_Tn_CFG(i));
161 h = hpet_readl(HPET_Tn_CFG(i)+4);
162 pr_info("T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", i, l, h);
163
164 l = hpet_readl(HPET_Tn_CMP(i));
165 h = hpet_readl(HPET_Tn_CMP(i)+4);
166 pr_info("T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", i, l, h);
167
168 l = hpet_readl(HPET_Tn_ROUTE(i));
169 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
170 pr_info("T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", i, l, h);
171 }
172}
173
174#define hpet_print_config() \
175do { \
176 if (hpet_verbose) \
177 _hpet_print_config(__func__, __LINE__); \
178} while (0)
179
180/*
181 * When the HPET driver (/dev/hpet) is enabled, we need to reserve
182 * timer 0 and timer 1 in case of RTC emulation.
183 */
184#ifdef CONFIG_HPET
185
186static void __init hpet_reserve_platform_timers(void)
187{
188 struct hpet_data hd;
189 unsigned int i;
190
191 memset(&hd, 0, sizeof(hd));
192 hd.hd_phys_address = hpet_address;
193 hd.hd_address = hpet_virt_address;
194 hd.hd_nirqs = hpet_base.nr_channels;
195
196 /*
197 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
198 * is wrong for i8259!) not the output IRQ. Many BIOS writers
199 * don't bother configuring *any* comparator interrupts.
200 */
201 hd.hd_irq[0] = HPET_LEGACY_8254;
202 hd.hd_irq[1] = HPET_LEGACY_RTC;
203
204 for (i = 0; i < hpet_base.nr_channels; i++) {
205 struct hpet_channel *hc = hpet_base.channels + i;
206
207 if (i >= 2)
208 hd.hd_irq[i] = hc->irq;
209
210 switch (hc->mode) {
211 case HPET_MODE_UNUSED:
212 case HPET_MODE_DEVICE:
213 hc->mode = HPET_MODE_DEVICE;
214 break;
215 case HPET_MODE_CLOCKEVT:
216 case HPET_MODE_LEGACY:
217 hpet_reserve_timer(&hd, hc->num);
218 break;
219 }
220 }
221
222 hpet_alloc(&hd);
223}
224
225static void __init hpet_select_device_channel(void)
226{
227 int i;
228
229 for (i = 0; i < hpet_base.nr_channels; i++) {
230 struct hpet_channel *hc = hpet_base.channels + i;
231
232 /* Associate the first unused channel to /dev/hpet */
233 if (hc->mode == HPET_MODE_UNUSED) {
234 hc->mode = HPET_MODE_DEVICE;
235 return;
236 }
237 }
238}
239
240#else
241static inline void hpet_reserve_platform_timers(void) { }
242static inline void hpet_select_device_channel(void) {}
243#endif
244
245/* Common HPET functions */
246static void hpet_stop_counter(void)
247{
248 u32 cfg = hpet_readl(HPET_CFG);
249
250 cfg &= ~HPET_CFG_ENABLE;
251 hpet_writel(cfg, HPET_CFG);
252}
253
254static void hpet_reset_counter(void)
255{
256 hpet_writel(0, HPET_COUNTER);
257 hpet_writel(0, HPET_COUNTER + 4);
258}
259
260static void hpet_start_counter(void)
261{
262 unsigned int cfg = hpet_readl(HPET_CFG);
263
264 cfg |= HPET_CFG_ENABLE;
265 hpet_writel(cfg, HPET_CFG);
266}
267
268static void hpet_restart_counter(void)
269{
270 hpet_stop_counter();
271 hpet_reset_counter();
272 hpet_start_counter();
273}
274
275static void hpet_resume_device(void)
276{
277 force_hpet_resume();
278}
279
280static void hpet_resume_counter(struct clocksource *cs)
281{
282 hpet_resume_device();
283 hpet_restart_counter();
284}
285
286static void hpet_enable_legacy_int(void)
287{
288 unsigned int cfg = hpet_readl(HPET_CFG);
289
290 cfg |= HPET_CFG_LEGACY;
291 hpet_writel(cfg, HPET_CFG);
292 hpet_legacy_int_enabled = true;
293}
294
295static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt)
296{
297 unsigned int channel = clockevent_to_channel(evt)->num;
298 unsigned int cfg, cmp, now;
299 uint64_t delta;
300
301 hpet_stop_counter();
302 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
303 delta >>= evt->shift;
304 now = hpet_readl(HPET_COUNTER);
305 cmp = now + (unsigned int)delta;
306 cfg = hpet_readl(HPET_Tn_CFG(channel));
307 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
308 HPET_TN_32BIT;
309 hpet_writel(cfg, HPET_Tn_CFG(channel));
310 hpet_writel(cmp, HPET_Tn_CMP(channel));
311 udelay(1);
312 /*
313 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
314 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
315 * bit is automatically cleared after the first write.
316 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
317 * Publication # 24674)
318 */
319 hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel));
320 hpet_start_counter();
321 hpet_print_config();
322
323 return 0;
324}
325
326static int hpet_clkevt_set_state_oneshot(struct clock_event_device *evt)
327{
328 unsigned int channel = clockevent_to_channel(evt)->num;
329 unsigned int cfg;
330
331 cfg = hpet_readl(HPET_Tn_CFG(channel));
332 cfg &= ~HPET_TN_PERIODIC;
333 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
334 hpet_writel(cfg, HPET_Tn_CFG(channel));
335
336 return 0;
337}
338
339static int hpet_clkevt_set_state_shutdown(struct clock_event_device *evt)
340{
341 unsigned int channel = clockevent_to_channel(evt)->num;
342 unsigned int cfg;
343
344 cfg = hpet_readl(HPET_Tn_CFG(channel));
345 cfg &= ~HPET_TN_ENABLE;
346 hpet_writel(cfg, HPET_Tn_CFG(channel));
347
348 return 0;
349}
350
351static int hpet_clkevt_legacy_resume(struct clock_event_device *evt)
352{
353 hpet_enable_legacy_int();
354 hpet_print_config();
355 return 0;
356}
357
358static int
359hpet_clkevt_set_next_event(unsigned long delta, struct clock_event_device *evt)
360{
361 unsigned int channel = clockevent_to_channel(evt)->num;
362 u32 cnt;
363 s32 res;
364
365 cnt = hpet_readl(HPET_COUNTER);
366 cnt += (u32) delta;
367 hpet_writel(cnt, HPET_Tn_CMP(channel));
368
369 /*
370 * HPETs are a complete disaster. The compare register is
371 * based on a equal comparison and neither provides a less
372 * than or equal functionality (which would require to take
373 * the wraparound into account) nor a simple count down event
374 * mode. Further the write to the comparator register is
375 * delayed internally up to two HPET clock cycles in certain
376 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
377 * longer delays. We worked around that by reading back the
378 * compare register, but that required another workaround for
379 * ICH9,10 chips where the first readout after write can
380 * return the old stale value. We already had a minimum
381 * programming delta of 5us enforced, but a NMI or SMI hitting
382 * between the counter readout and the comparator write can
383 * move us behind that point easily. Now instead of reading
384 * the compare register back several times, we make the ETIME
385 * decision based on the following: Return ETIME if the
386 * counter value after the write is less than HPET_MIN_CYCLES
387 * away from the event or if the counter is already ahead of
388 * the event. The minimum programming delta for the generic
389 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
390 */
391 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
392
393 return res < HPET_MIN_CYCLES ? -ETIME : 0;
394}
395
396static void hpet_init_clockevent(struct hpet_channel *hc, unsigned int rating)
397{
398 struct clock_event_device *evt = &hc->evt;
399
400 evt->rating = rating;
401 evt->irq = hc->irq;
402 evt->name = hc->name;
403 evt->cpumask = cpumask_of(hc->cpu);
404 evt->set_state_oneshot = hpet_clkevt_set_state_oneshot;
405 evt->set_next_event = hpet_clkevt_set_next_event;
406 evt->set_state_shutdown = hpet_clkevt_set_state_shutdown;
407
408 evt->features = CLOCK_EVT_FEAT_ONESHOT;
409 if (hc->boot_cfg & HPET_TN_PERIODIC) {
410 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
411 evt->set_state_periodic = hpet_clkevt_set_state_periodic;
412 }
413}
414
415static void __init hpet_legacy_clockevent_register(struct hpet_channel *hc)
416{
417 /*
418 * Start HPET with the boot CPU's cpumask and make it global after
419 * the IO_APIC has been initialized.
420 */
421 hc->cpu = boot_cpu_data.cpu_index;
422 strncpy(hc->name, "hpet", sizeof(hc->name));
423 hpet_init_clockevent(hc, 50);
424
425 hc->evt.tick_resume = hpet_clkevt_legacy_resume;
426
427 /*
428 * Legacy horrors and sins from the past. HPET used periodic mode
429 * unconditionally forever on the legacy channel 0. Removing the
430 * below hack and using the conditional in hpet_init_clockevent()
431 * makes at least Qemu and one hardware machine fail to boot.
432 * There are two issues which cause the boot failure:
433 *
434 * #1 After the timer delivery test in IOAPIC and the IOAPIC setup
435 * the next interrupt is not delivered despite the HPET channel
436 * being programmed correctly. Reprogramming the HPET after
437 * switching to IOAPIC makes it work again. After fixing this,
438 * the next issue surfaces:
439 *
440 * #2 Due to the unconditional periodic mode availability the Local
441 * APIC timer calibration can hijack the global clockevents
442 * event handler without causing damage. Using oneshot at this
443 * stage makes if hang because the HPET does not get
444 * reprogrammed due to the handler hijacking. Duh, stupid me!
445 *
446 * Both issues require major surgery and especially the kick HPET
447 * again after enabling IOAPIC results in really nasty hackery.
448 * This 'assume periodic works' magic has survived since HPET
449 * support got added, so it's questionable whether this should be
450 * fixed. Both Qemu and the failing hardware machine support
451 * periodic mode despite the fact that both don't advertise it in
452 * the configuration register and both need that extra kick after
453 * switching to IOAPIC. Seems to be a feature...
454 */
455 hc->evt.features |= CLOCK_EVT_FEAT_PERIODIC;
456 hc->evt.set_state_periodic = hpet_clkevt_set_state_periodic;
457
458 /* Start HPET legacy interrupts */
459 hpet_enable_legacy_int();
460
461 clockevents_config_and_register(&hc->evt, hpet_freq,
462 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
463 global_clock_event = &hc->evt;
464 pr_debug("Clockevent registered\n");
465}
466
467/*
468 * HPET MSI Support
469 */
470#ifdef CONFIG_PCI_MSI
471
472void hpet_msi_unmask(struct irq_data *data)
473{
474 struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
475 unsigned int cfg;
476
477 cfg = hpet_readl(HPET_Tn_CFG(hc->num));
478 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
479 hpet_writel(cfg, HPET_Tn_CFG(hc->num));
480}
481
482void hpet_msi_mask(struct irq_data *data)
483{
484 struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
485 unsigned int cfg;
486
487 cfg = hpet_readl(HPET_Tn_CFG(hc->num));
488 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
489 hpet_writel(cfg, HPET_Tn_CFG(hc->num));
490}
491
492void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg)
493{
494 hpet_writel(msg->data, HPET_Tn_ROUTE(hc->num));
495 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hc->num) + 4);
496}
497
498static int hpet_clkevt_msi_resume(struct clock_event_device *evt)
499{
500 struct hpet_channel *hc = clockevent_to_channel(evt);
501 struct irq_data *data = irq_get_irq_data(hc->irq);
502 struct msi_msg msg;
503
504 /* Restore the MSI msg and unmask the interrupt */
505 irq_chip_compose_msi_msg(data, &msg);
506 hpet_msi_write(hc, &msg);
507 hpet_msi_unmask(data);
508 return 0;
509}
510
511static irqreturn_t hpet_msi_interrupt_handler(int irq, void *data)
512{
513 struct hpet_channel *hc = data;
514 struct clock_event_device *evt = &hc->evt;
515
516 if (!evt->event_handler) {
517 pr_info("Spurious interrupt HPET channel %d\n", hc->num);
518 return IRQ_HANDLED;
519 }
520
521 evt->event_handler(evt);
522 return IRQ_HANDLED;
523}
524
525static int hpet_setup_msi_irq(struct hpet_channel *hc)
526{
527 if (request_irq(hc->irq, hpet_msi_interrupt_handler,
528 IRQF_TIMER | IRQF_NOBALANCING,
529 hc->name, hc))
530 return -1;
531
532 disable_irq(hc->irq);
533 irq_set_affinity(hc->irq, cpumask_of(hc->cpu));
534 enable_irq(hc->irq);
535
536 pr_debug("%s irq %u for MSI\n", hc->name, hc->irq);
537
538 return 0;
539}
540
541/* Invoked from the hotplug callback on @cpu */
542static void init_one_hpet_msi_clockevent(struct hpet_channel *hc, int cpu)
543{
544 struct clock_event_device *evt = &hc->evt;
545
546 hc->cpu = cpu;
547 per_cpu(cpu_hpet_channel, cpu) = hc;
548 hpet_setup_msi_irq(hc);
549
550 hpet_init_clockevent(hc, 110);
551 evt->tick_resume = hpet_clkevt_msi_resume;
552
553 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
554 0x7FFFFFFF);
555}
556
557static struct hpet_channel *hpet_get_unused_clockevent(void)
558{
559 int i;
560
561 for (i = 0; i < hpet_base.nr_channels; i++) {
562 struct hpet_channel *hc = hpet_base.channels + i;
563
564 if (hc->mode != HPET_MODE_CLOCKEVT || hc->in_use)
565 continue;
566 hc->in_use = 1;
567 return hc;
568 }
569 return NULL;
570}
571
572static int hpet_cpuhp_online(unsigned int cpu)
573{
574 struct hpet_channel *hc = hpet_get_unused_clockevent();
575
576 if (hc)
577 init_one_hpet_msi_clockevent(hc, cpu);
578 return 0;
579}
580
581static int hpet_cpuhp_dead(unsigned int cpu)
582{
583 struct hpet_channel *hc = per_cpu(cpu_hpet_channel, cpu);
584
585 if (!hc)
586 return 0;
587 free_irq(hc->irq, hc);
588 hc->in_use = 0;
589 per_cpu(cpu_hpet_channel, cpu) = NULL;
590 return 0;
591}
592
593static void __init hpet_select_clockevents(void)
594{
595 unsigned int i;
596
597 hpet_base.nr_clockevents = 0;
598
599 /* No point if MSI is disabled or CPU has an Always Runing APIC Timer */
600 if (hpet_msi_disable || boot_cpu_has(X86_FEATURE_ARAT))
601 return;
602
603 hpet_print_config();
604
605 hpet_domain = hpet_create_irq_domain(hpet_blockid);
606 if (!hpet_domain)
607 return;
608
609 for (i = 0; i < hpet_base.nr_channels; i++) {
610 struct hpet_channel *hc = hpet_base.channels + i;
611 int irq;
612
613 if (hc->mode != HPET_MODE_UNUSED)
614 continue;
615
616 /* Only consider HPET channel with MSI support */
617 if (!(hc->boot_cfg & HPET_TN_FSB_CAP))
618 continue;
619
620 sprintf(hc->name, "hpet%d", i);
621
622 irq = hpet_assign_irq(hpet_domain, hc, hc->num);
623 if (irq <= 0)
624 continue;
625
626 hc->irq = irq;
627 hc->mode = HPET_MODE_CLOCKEVT;
628
629 if (++hpet_base.nr_clockevents == num_possible_cpus())
630 break;
631 }
632
633 pr_info("%d channels of %d reserved for per-cpu timers\n",
634 hpet_base.nr_channels, hpet_base.nr_clockevents);
635}
636
637#else
638
639static inline void hpet_select_clockevents(void) { }
640
641#define hpet_cpuhp_online NULL
642#define hpet_cpuhp_dead NULL
643
644#endif
645
646/*
647 * Clock source related code
648 */
649#if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
650/*
651 * Reading the HPET counter is a very slow operation. If a large number of
652 * CPUs are trying to access the HPET counter simultaneously, it can cause
653 * massive delays and slow down system performance dramatically. This may
654 * happen when HPET is the default clock source instead of TSC. For a
655 * really large system with hundreds of CPUs, the slowdown may be so
656 * severe, that it can actually crash the system because of a NMI watchdog
657 * soft lockup, for example.
658 *
659 * If multiple CPUs are trying to access the HPET counter at the same time,
660 * we don't actually need to read the counter multiple times. Instead, the
661 * other CPUs can use the counter value read by the first CPU in the group.
662 *
663 * This special feature is only enabled on x86-64 systems. It is unlikely
664 * that 32-bit x86 systems will have enough CPUs to require this feature
665 * with its associated locking overhead. We also need 64-bit atomic read.
666 *
667 * The lock and the HPET value are stored together and can be read in a
668 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
669 * is 32 bits in size.
670 */
671union hpet_lock {
672 struct {
673 arch_spinlock_t lock;
674 u32 value;
675 };
676 u64 lockval;
677};
678
679static union hpet_lock hpet __cacheline_aligned = {
680 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
681};
682
683static u64 read_hpet(struct clocksource *cs)
684{
685 unsigned long flags;
686 union hpet_lock old, new;
687
688 BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
689
690 /*
691 * Read HPET directly if in NMI.
692 */
693 if (in_nmi())
694 return (u64)hpet_readl(HPET_COUNTER);
695
696 /*
697 * Read the current state of the lock and HPET value atomically.
698 */
699 old.lockval = READ_ONCE(hpet.lockval);
700
701 if (arch_spin_is_locked(&old.lock))
702 goto contended;
703
704 local_irq_save(flags);
705 if (arch_spin_trylock(&hpet.lock)) {
706 new.value = hpet_readl(HPET_COUNTER);
707 /*
708 * Use WRITE_ONCE() to prevent store tearing.
709 */
710 WRITE_ONCE(hpet.value, new.value);
711 arch_spin_unlock(&hpet.lock);
712 local_irq_restore(flags);
713 return (u64)new.value;
714 }
715 local_irq_restore(flags);
716
717contended:
718 /*
719 * Contended case
720 * --------------
721 * Wait until the HPET value change or the lock is free to indicate
722 * its value is up-to-date.
723 *
724 * It is possible that old.value has already contained the latest
725 * HPET value while the lock holder was in the process of releasing
726 * the lock. Checking for lock state change will enable us to return
727 * the value immediately instead of waiting for the next HPET reader
728 * to come along.
729 */
730 do {
731 cpu_relax();
732 new.lockval = READ_ONCE(hpet.lockval);
733 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
734
735 return (u64)new.value;
736}
737#else
738/*
739 * For UP or 32-bit.
740 */
741static u64 read_hpet(struct clocksource *cs)
742{
743 return (u64)hpet_readl(HPET_COUNTER);
744}
745#endif
746
747static struct clocksource clocksource_hpet = {
748 .name = "hpet",
749 .rating = 250,
750 .read = read_hpet,
751 .mask = HPET_MASK,
752 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
753 .resume = hpet_resume_counter,
754};
755
756/*
757 * AMD SB700 based systems with spread spectrum enabled use a SMM based
758 * HPET emulation to provide proper frequency setting.
759 *
760 * On such systems the SMM code is initialized with the first HPET register
761 * access and takes some time to complete. During this time the config
762 * register reads 0xffffffff. We check for max 1000 loops whether the
763 * config register reads a non-0xffffffff value to make sure that the
764 * HPET is up and running before we proceed any further.
765 *
766 * A counting loop is safe, as the HPET access takes thousands of CPU cycles.
767 *
768 * On non-SB700 based machines this check is only done once and has no
769 * side effects.
770 */
771static bool __init hpet_cfg_working(void)
772{
773 int i;
774
775 for (i = 0; i < 1000; i++) {
776 if (hpet_readl(HPET_CFG) != 0xFFFFFFFF)
777 return true;
778 }
779
780 pr_warn("Config register invalid. Disabling HPET\n");
781 return false;
782}
783
784static bool __init hpet_counting(void)
785{
786 u64 start, now, t1;
787
788 hpet_restart_counter();
789
790 t1 = hpet_readl(HPET_COUNTER);
791 start = rdtsc();
792
793 /*
794 * We don't know the TSC frequency yet, but waiting for
795 * 200000 TSC cycles is safe:
796 * 4 GHz == 50us
797 * 1 GHz == 200us
798 */
799 do {
800 if (t1 != hpet_readl(HPET_COUNTER))
801 return true;
802 now = rdtsc();
803 } while ((now - start) < 200000UL);
804
805 pr_warn("Counter not counting. HPET disabled\n");
806 return false;
807}
808
809/**
810 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
811 */
812int __init hpet_enable(void)
813{
814 u32 hpet_period, cfg, id, irq;
815 unsigned int i, channels;
816 struct hpet_channel *hc;
817 u64 freq;
818
819 if (!is_hpet_capable())
820 return 0;
821
822 hpet_set_mapping();
823 if (!hpet_virt_address)
824 return 0;
825
826 /* Validate that the config register is working */
827 if (!hpet_cfg_working())
828 goto out_nohpet;
829
830 /*
831 * Read the period and check for a sane value:
832 */
833 hpet_period = hpet_readl(HPET_PERIOD);
834 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
835 goto out_nohpet;
836
837 /* The period is a femtoseconds value. Convert it to a frequency. */
838 freq = FSEC_PER_SEC;
839 do_div(freq, hpet_period);
840 hpet_freq = freq;
841
842 /*
843 * Read the HPET ID register to retrieve the IRQ routing
844 * information and the number of channels
845 */
846 id = hpet_readl(HPET_ID);
847 hpet_print_config();
848
849 /* This is the HPET channel number which is zero based */
850 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
851
852 /*
853 * The legacy routing mode needs at least two channels, tick timer
854 * and the rtc emulation channel.
855 */
856 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC) && channels < 2)
857 goto out_nohpet;
858
859 hc = kcalloc(channels, sizeof(*hc), GFP_KERNEL);
860 if (!hc) {
861 pr_warn("Disabling HPET.\n");
862 goto out_nohpet;
863 }
864 hpet_base.channels = hc;
865 hpet_base.nr_channels = channels;
866
867 /* Read, store and sanitize the global configuration */
868 cfg = hpet_readl(HPET_CFG);
869 hpet_base.boot_cfg = cfg;
870 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
871 hpet_writel(cfg, HPET_CFG);
872 if (cfg)
873 pr_warn("Global config: Unknown bits %#x\n", cfg);
874
875 /* Read, store and sanitize the per channel configuration */
876 for (i = 0; i < channels; i++, hc++) {
877 hc->num = i;
878
879 cfg = hpet_readl(HPET_Tn_CFG(i));
880 hc->boot_cfg = cfg;
881 irq = (cfg & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
882 hc->irq = irq;
883
884 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
885 hpet_writel(cfg, HPET_Tn_CFG(i));
886
887 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
888 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
889 | HPET_TN_FSB | HPET_TN_FSB_CAP);
890 if (cfg)
891 pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg);
892 }
893 hpet_print_config();
894
895 /*
896 * Validate that the counter is counting. This needs to be done
897 * after sanitizing the config registers to properly deal with
898 * force enabled HPETs.
899 */
900 if (!hpet_counting())
901 goto out_nohpet;
902
903 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
904
905 if (id & HPET_ID_LEGSUP) {
906 hpet_legacy_clockevent_register(&hpet_base.channels[0]);
907 hpet_base.channels[0].mode = HPET_MODE_LEGACY;
908 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC))
909 hpet_base.channels[1].mode = HPET_MODE_LEGACY;
910 return 1;
911 }
912 return 0;
913
914out_nohpet:
915 kfree(hpet_base.channels);
916 hpet_base.channels = NULL;
917 hpet_base.nr_channels = 0;
918 hpet_clear_mapping();
919 hpet_address = 0;
920 return 0;
921}
922
923/*
924 * The late initialization runs after the PCI quirks have been invoked
925 * which might have detected a system on which the HPET can be enforced.
926 *
927 * Also, the MSI machinery is not working yet when the HPET is initialized
928 * early.
929 *
930 * If the HPET is enabled, then:
931 *
932 * 1) Reserve one channel for /dev/hpet if CONFIG_HPET=y
933 * 2) Reserve up to num_possible_cpus() channels as per CPU clockevents
934 * 3) Setup /dev/hpet if CONFIG_HPET=y
935 * 4) Register hotplug callbacks when clockevents are available
936 */
937static __init int hpet_late_init(void)
938{
939 int ret;
940
941 if (!hpet_address) {
942 if (!force_hpet_address)
943 return -ENODEV;
944
945 hpet_address = force_hpet_address;
946 hpet_enable();
947 }
948
949 if (!hpet_virt_address)
950 return -ENODEV;
951
952 hpet_select_device_channel();
953 hpet_select_clockevents();
954 hpet_reserve_platform_timers();
955 hpet_print_config();
956
957 if (!hpet_base.nr_clockevents)
958 return 0;
959
960 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online",
961 hpet_cpuhp_online, NULL);
962 if (ret)
963 return ret;
964 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL,
965 hpet_cpuhp_dead);
966 if (ret)
967 goto err_cpuhp;
968 return 0;
969
970err_cpuhp:
971 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
972 return ret;
973}
974fs_initcall(hpet_late_init);
975
976void hpet_disable(void)
977{
978 unsigned int i;
979 u32 cfg;
980
981 if (!is_hpet_capable() || !hpet_virt_address)
982 return;
983
984 /* Restore boot configuration with the enable bit cleared */
985 cfg = hpet_base.boot_cfg;
986 cfg &= ~HPET_CFG_ENABLE;
987 hpet_writel(cfg, HPET_CFG);
988
989 /* Restore the channel boot configuration */
990 for (i = 0; i < hpet_base.nr_channels; i++)
991 hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i));
992
993 /* If the HPET was enabled at boot time, reenable it */
994 if (hpet_base.boot_cfg & HPET_CFG_ENABLE)
995 hpet_writel(hpet_base.boot_cfg, HPET_CFG);
996}
997
998#ifdef CONFIG_HPET_EMULATE_RTC
999
1000/*
1001 * HPET in LegacyReplacement mode eats up the RTC interrupt line. When HPET
1002 * is enabled, we support RTC interrupt functionality in software.
1003 *
1004 * RTC has 3 kinds of interrupts:
1005 *
1006 * 1) Update Interrupt - generate an interrupt, every second, when the
1007 * RTC clock is updated
1008 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1009 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1010 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all frequencies in powers of 2)
1011 *
1012 * (1) and (2) above are implemented using polling at a frequency of 64 Hz:
1013 * DEFAULT_RTC_INT_FREQ.
1014 *
1015 * The exact frequency is a tradeoff between accuracy and interrupt overhead.
1016 *
1017 * For (3), we use interrupts at 64 Hz, or the user specified periodic frequency,
1018 * if it's higher.
1019 */
1020#include <linux/mc146818rtc.h>
1021#include <linux/rtc.h>
1022
1023#define DEFAULT_RTC_INT_FREQ 64
1024#define DEFAULT_RTC_SHIFT 6
1025#define RTC_NUM_INTS 1
1026
1027static unsigned long hpet_rtc_flags;
1028static int hpet_prev_update_sec;
1029static struct rtc_time hpet_alarm_time;
1030static unsigned long hpet_pie_count;
1031static u32 hpet_t1_cmp;
1032static u32 hpet_default_delta;
1033static u32 hpet_pie_delta;
1034static unsigned long hpet_pie_limit;
1035
1036static rtc_irq_handler irq_handler;
1037
1038/*
1039 * Check that the HPET counter c1 is ahead of c2
1040 */
1041static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1042{
1043 return (s32)(c2 - c1) < 0;
1044}
1045
1046/*
1047 * Registers a IRQ handler.
1048 */
1049int hpet_register_irq_handler(rtc_irq_handler handler)
1050{
1051 if (!is_hpet_enabled())
1052 return -ENODEV;
1053 if (irq_handler)
1054 return -EBUSY;
1055
1056 irq_handler = handler;
1057
1058 return 0;
1059}
1060EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1061
1062/*
1063 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1064 * and does cleanup.
1065 */
1066void hpet_unregister_irq_handler(rtc_irq_handler handler)
1067{
1068 if (!is_hpet_enabled())
1069 return;
1070
1071 irq_handler = NULL;
1072 hpet_rtc_flags = 0;
1073}
1074EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1075
1076/*
1077 * Channel 1 for RTC emulation. We use one shot mode, as periodic mode
1078 * is not supported by all HPET implementations for channel 1.
1079 *
1080 * hpet_rtc_timer_init() is called when the rtc is initialized.
1081 */
1082int hpet_rtc_timer_init(void)
1083{
1084 unsigned int cfg, cnt, delta;
1085 unsigned long flags;
1086
1087 if (!is_hpet_enabled())
1088 return 0;
1089
1090 if (!hpet_default_delta) {
1091 struct clock_event_device *evt = &hpet_base.channels[0].evt;
1092 uint64_t clc;
1093
1094 clc = (uint64_t) evt->mult * NSEC_PER_SEC;
1095 clc >>= evt->shift + DEFAULT_RTC_SHIFT;
1096 hpet_default_delta = clc;
1097 }
1098
1099 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1100 delta = hpet_default_delta;
1101 else
1102 delta = hpet_pie_delta;
1103
1104 local_irq_save(flags);
1105
1106 cnt = delta + hpet_readl(HPET_COUNTER);
1107 hpet_writel(cnt, HPET_T1_CMP);
1108 hpet_t1_cmp = cnt;
1109
1110 cfg = hpet_readl(HPET_T1_CFG);
1111 cfg &= ~HPET_TN_PERIODIC;
1112 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1113 hpet_writel(cfg, HPET_T1_CFG);
1114
1115 local_irq_restore(flags);
1116
1117 return 1;
1118}
1119EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1120
1121static void hpet_disable_rtc_channel(void)
1122{
1123 u32 cfg = hpet_readl(HPET_T1_CFG);
1124
1125 cfg &= ~HPET_TN_ENABLE;
1126 hpet_writel(cfg, HPET_T1_CFG);
1127}
1128
1129/*
1130 * The functions below are called from rtc driver.
1131 * Return 0 if HPET is not being used.
1132 * Otherwise do the necessary changes and return 1.
1133 */
1134int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1135{
1136 if (!is_hpet_enabled())
1137 return 0;
1138
1139 hpet_rtc_flags &= ~bit_mask;
1140 if (unlikely(!hpet_rtc_flags))
1141 hpet_disable_rtc_channel();
1142
1143 return 1;
1144}
1145EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1146
1147int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1148{
1149 unsigned long oldbits = hpet_rtc_flags;
1150
1151 if (!is_hpet_enabled())
1152 return 0;
1153
1154 hpet_rtc_flags |= bit_mask;
1155
1156 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1157 hpet_prev_update_sec = -1;
1158
1159 if (!oldbits)
1160 hpet_rtc_timer_init();
1161
1162 return 1;
1163}
1164EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1165
1166int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
1167{
1168 if (!is_hpet_enabled())
1169 return 0;
1170
1171 hpet_alarm_time.tm_hour = hrs;
1172 hpet_alarm_time.tm_min = min;
1173 hpet_alarm_time.tm_sec = sec;
1174
1175 return 1;
1176}
1177EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1178
1179int hpet_set_periodic_freq(unsigned long freq)
1180{
1181 uint64_t clc;
1182
1183 if (!is_hpet_enabled())
1184 return 0;
1185
1186 if (freq <= DEFAULT_RTC_INT_FREQ) {
1187 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1188 } else {
1189 struct clock_event_device *evt = &hpet_base.channels[0].evt;
1190
1191 clc = (uint64_t) evt->mult * NSEC_PER_SEC;
1192 do_div(clc, freq);
1193 clc >>= evt->shift;
1194 hpet_pie_delta = clc;
1195 hpet_pie_limit = 0;
1196 }
1197
1198 return 1;
1199}
1200EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1201
1202int hpet_rtc_dropped_irq(void)
1203{
1204 return is_hpet_enabled();
1205}
1206EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1207
1208static void hpet_rtc_timer_reinit(void)
1209{
1210 unsigned int delta;
1211 int lost_ints = -1;
1212
1213 if (unlikely(!hpet_rtc_flags))
1214 hpet_disable_rtc_channel();
1215
1216 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1217 delta = hpet_default_delta;
1218 else
1219 delta = hpet_pie_delta;
1220
1221 /*
1222 * Increment the comparator value until we are ahead of the
1223 * current count.
1224 */
1225 do {
1226 hpet_t1_cmp += delta;
1227 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1228 lost_ints++;
1229 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1230
1231 if (lost_ints) {
1232 if (hpet_rtc_flags & RTC_PIE)
1233 hpet_pie_count += lost_ints;
1234 if (printk_ratelimit())
1235 pr_warn("Lost %d RTC interrupts\n", lost_ints);
1236 }
1237}
1238
1239irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1240{
1241 struct rtc_time curr_time;
1242 unsigned long rtc_int_flag = 0;
1243
1244 hpet_rtc_timer_reinit();
1245 memset(&curr_time, 0, sizeof(struct rtc_time));
1246
1247 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1248 mc146818_get_time(&curr_time);
1249
1250 if (hpet_rtc_flags & RTC_UIE &&
1251 curr_time.tm_sec != hpet_prev_update_sec) {
1252 if (hpet_prev_update_sec >= 0)
1253 rtc_int_flag = RTC_UF;
1254 hpet_prev_update_sec = curr_time.tm_sec;
1255 }
1256
1257 if (hpet_rtc_flags & RTC_PIE && ++hpet_pie_count >= hpet_pie_limit) {
1258 rtc_int_flag |= RTC_PF;
1259 hpet_pie_count = 0;
1260 }
1261
1262 if (hpet_rtc_flags & RTC_AIE &&
1263 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1264 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1265 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1266 rtc_int_flag |= RTC_AF;
1267
1268 if (rtc_int_flag) {
1269 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1270 if (irq_handler)
1271 irq_handler(rtc_int_flag, dev_id);
1272 }
1273 return IRQ_HANDLED;
1274}
1275EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1276#endif
1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/fixmap.h>
16#include <asm/hpet.h>
17#include <asm/time.h>
18
19#define HPET_MASK CLOCKSOURCE_MASK(32)
20
21/* FSEC = 10^-15
22 NSEC = 10^-9 */
23#define FSEC_PER_NSEC 1000000L
24
25#define HPET_DEV_USED_BIT 2
26#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
27#define HPET_DEV_VALID 0x8
28#define HPET_DEV_FSB_CAP 0x1000
29#define HPET_DEV_PERI_CAP 0x2000
30
31#define HPET_MIN_CYCLES 128
32#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
33
34/*
35 * HPET address is set in acpi/boot.c, when an ACPI entry exists
36 */
37unsigned long hpet_address;
38u8 hpet_blockid; /* OS timer block num */
39u8 hpet_msi_disable;
40
41#ifdef CONFIG_PCI_MSI
42static unsigned long hpet_num_timers;
43#endif
44static void __iomem *hpet_virt_address;
45
46struct hpet_dev {
47 struct clock_event_device evt;
48 unsigned int num;
49 int cpu;
50 unsigned int irq;
51 unsigned int flags;
52 char name[10];
53};
54
55inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
56{
57 return container_of(evtdev, struct hpet_dev, evt);
58}
59
60inline unsigned int hpet_readl(unsigned int a)
61{
62 return readl(hpet_virt_address + a);
63}
64
65static inline void hpet_writel(unsigned int d, unsigned int a)
66{
67 writel(d, hpet_virt_address + a);
68}
69
70#ifdef CONFIG_X86_64
71#include <asm/pgtable.h>
72#endif
73
74static inline void hpet_set_mapping(void)
75{
76 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
77#ifdef CONFIG_X86_64
78 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
79#endif
80}
81
82static inline void hpet_clear_mapping(void)
83{
84 iounmap(hpet_virt_address);
85 hpet_virt_address = NULL;
86}
87
88/*
89 * HPET command line enable / disable
90 */
91static int boot_hpet_disable;
92int hpet_force_user;
93static int hpet_verbose;
94
95static int __init hpet_setup(char *str)
96{
97 while (str) {
98 char *next = strchr(str, ',');
99
100 if (next)
101 *next++ = 0;
102 if (!strncmp("disable", str, 7))
103 boot_hpet_disable = 1;
104 if (!strncmp("force", str, 5))
105 hpet_force_user = 1;
106 if (!strncmp("verbose", str, 7))
107 hpet_verbose = 1;
108 str = next;
109 }
110 return 1;
111}
112__setup("hpet=", hpet_setup);
113
114static int __init disable_hpet(char *str)
115{
116 boot_hpet_disable = 1;
117 return 1;
118}
119__setup("nohpet", disable_hpet);
120
121static inline int is_hpet_capable(void)
122{
123 return !boot_hpet_disable && hpet_address;
124}
125
126/*
127 * HPET timer interrupt enable / disable
128 */
129static int hpet_legacy_int_enabled;
130
131/**
132 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
133 */
134int is_hpet_enabled(void)
135{
136 return is_hpet_capable() && hpet_legacy_int_enabled;
137}
138EXPORT_SYMBOL_GPL(is_hpet_enabled);
139
140static void _hpet_print_config(const char *function, int line)
141{
142 u32 i, timers, l, h;
143 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
144 l = hpet_readl(HPET_ID);
145 h = hpet_readl(HPET_PERIOD);
146 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
147 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
148 l = hpet_readl(HPET_CFG);
149 h = hpet_readl(HPET_STATUS);
150 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
151 l = hpet_readl(HPET_COUNTER);
152 h = hpet_readl(HPET_COUNTER+4);
153 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
154
155 for (i = 0; i < timers; i++) {
156 l = hpet_readl(HPET_Tn_CFG(i));
157 h = hpet_readl(HPET_Tn_CFG(i)+4);
158 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
159 i, l, h);
160 l = hpet_readl(HPET_Tn_CMP(i));
161 h = hpet_readl(HPET_Tn_CMP(i)+4);
162 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
163 i, l, h);
164 l = hpet_readl(HPET_Tn_ROUTE(i));
165 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
166 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
167 i, l, h);
168 }
169}
170
171#define hpet_print_config() \
172do { \
173 if (hpet_verbose) \
174 _hpet_print_config(__FUNCTION__, __LINE__); \
175} while (0)
176
177/*
178 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
179 * timer 0 and timer 1 in case of RTC emulation.
180 */
181#ifdef CONFIG_HPET
182
183static void hpet_reserve_msi_timers(struct hpet_data *hd);
184
185static void hpet_reserve_platform_timers(unsigned int id)
186{
187 struct hpet __iomem *hpet = hpet_virt_address;
188 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
189 unsigned int nrtimers, i;
190 struct hpet_data hd;
191
192 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
193
194 memset(&hd, 0, sizeof(hd));
195 hd.hd_phys_address = hpet_address;
196 hd.hd_address = hpet;
197 hd.hd_nirqs = nrtimers;
198 hpet_reserve_timer(&hd, 0);
199
200#ifdef CONFIG_HPET_EMULATE_RTC
201 hpet_reserve_timer(&hd, 1);
202#endif
203
204 /*
205 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
206 * is wrong for i8259!) not the output IRQ. Many BIOS writers
207 * don't bother configuring *any* comparator interrupts.
208 */
209 hd.hd_irq[0] = HPET_LEGACY_8254;
210 hd.hd_irq[1] = HPET_LEGACY_RTC;
211
212 for (i = 2; i < nrtimers; timer++, i++) {
213 hd.hd_irq[i] = (readl(&timer->hpet_config) &
214 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
215 }
216
217 hpet_reserve_msi_timers(&hd);
218
219 hpet_alloc(&hd);
220
221}
222#else
223static void hpet_reserve_platform_timers(unsigned int id) { }
224#endif
225
226/*
227 * Common hpet info
228 */
229static unsigned long hpet_freq;
230
231static void hpet_legacy_set_mode(enum clock_event_mode mode,
232 struct clock_event_device *evt);
233static int hpet_legacy_next_event(unsigned long delta,
234 struct clock_event_device *evt);
235
236/*
237 * The hpet clock event device
238 */
239static struct clock_event_device hpet_clockevent = {
240 .name = "hpet",
241 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
242 .set_mode = hpet_legacy_set_mode,
243 .set_next_event = hpet_legacy_next_event,
244 .irq = 0,
245 .rating = 50,
246};
247
248static void hpet_stop_counter(void)
249{
250 unsigned long cfg = hpet_readl(HPET_CFG);
251 cfg &= ~HPET_CFG_ENABLE;
252 hpet_writel(cfg, HPET_CFG);
253}
254
255static void hpet_reset_counter(void)
256{
257 hpet_writel(0, HPET_COUNTER);
258 hpet_writel(0, HPET_COUNTER + 4);
259}
260
261static void hpet_start_counter(void)
262{
263 unsigned int cfg = hpet_readl(HPET_CFG);
264 cfg |= HPET_CFG_ENABLE;
265 hpet_writel(cfg, HPET_CFG);
266}
267
268static void hpet_restart_counter(void)
269{
270 hpet_stop_counter();
271 hpet_reset_counter();
272 hpet_start_counter();
273}
274
275static void hpet_resume_device(void)
276{
277 force_hpet_resume();
278}
279
280static void hpet_resume_counter(struct clocksource *cs)
281{
282 hpet_resume_device();
283 hpet_restart_counter();
284}
285
286static void hpet_enable_legacy_int(void)
287{
288 unsigned int cfg = hpet_readl(HPET_CFG);
289
290 cfg |= HPET_CFG_LEGACY;
291 hpet_writel(cfg, HPET_CFG);
292 hpet_legacy_int_enabled = 1;
293}
294
295static void hpet_legacy_clockevent_register(void)
296{
297 /* Start HPET legacy interrupts */
298 hpet_enable_legacy_int();
299
300 /*
301 * Start hpet with the boot cpu mask and make it
302 * global after the IO_APIC has been initialized.
303 */
304 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
305 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
306 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
307 global_clock_event = &hpet_clockevent;
308 printk(KERN_DEBUG "hpet clockevent registered\n");
309}
310
311static int hpet_setup_msi_irq(unsigned int irq);
312
313static void hpet_set_mode(enum clock_event_mode mode,
314 struct clock_event_device *evt, int timer)
315{
316 unsigned int cfg, cmp, now;
317 uint64_t delta;
318
319 switch (mode) {
320 case CLOCK_EVT_MODE_PERIODIC:
321 hpet_stop_counter();
322 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
323 delta >>= evt->shift;
324 now = hpet_readl(HPET_COUNTER);
325 cmp = now + (unsigned int) delta;
326 cfg = hpet_readl(HPET_Tn_CFG(timer));
327 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
328 HPET_TN_SETVAL | HPET_TN_32BIT;
329 hpet_writel(cfg, HPET_Tn_CFG(timer));
330 hpet_writel(cmp, HPET_Tn_CMP(timer));
331 udelay(1);
332 /*
333 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
334 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
335 * bit is automatically cleared after the first write.
336 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
337 * Publication # 24674)
338 */
339 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
340 hpet_start_counter();
341 hpet_print_config();
342 break;
343
344 case CLOCK_EVT_MODE_ONESHOT:
345 cfg = hpet_readl(HPET_Tn_CFG(timer));
346 cfg &= ~HPET_TN_PERIODIC;
347 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
348 hpet_writel(cfg, HPET_Tn_CFG(timer));
349 break;
350
351 case CLOCK_EVT_MODE_UNUSED:
352 case CLOCK_EVT_MODE_SHUTDOWN:
353 cfg = hpet_readl(HPET_Tn_CFG(timer));
354 cfg &= ~HPET_TN_ENABLE;
355 hpet_writel(cfg, HPET_Tn_CFG(timer));
356 break;
357
358 case CLOCK_EVT_MODE_RESUME:
359 if (timer == 0) {
360 hpet_enable_legacy_int();
361 } else {
362 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
363 hpet_setup_msi_irq(hdev->irq);
364 disable_irq(hdev->irq);
365 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
366 enable_irq(hdev->irq);
367 }
368 hpet_print_config();
369 break;
370 }
371}
372
373static int hpet_next_event(unsigned long delta,
374 struct clock_event_device *evt, int timer)
375{
376 u32 cnt;
377 s32 res;
378
379 cnt = hpet_readl(HPET_COUNTER);
380 cnt += (u32) delta;
381 hpet_writel(cnt, HPET_Tn_CMP(timer));
382
383 /*
384 * HPETs are a complete disaster. The compare register is
385 * based on a equal comparison and neither provides a less
386 * than or equal functionality (which would require to take
387 * the wraparound into account) nor a simple count down event
388 * mode. Further the write to the comparator register is
389 * delayed internally up to two HPET clock cycles in certain
390 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
391 * longer delays. We worked around that by reading back the
392 * compare register, but that required another workaround for
393 * ICH9,10 chips where the first readout after write can
394 * return the old stale value. We already had a minimum
395 * programming delta of 5us enforced, but a NMI or SMI hitting
396 * between the counter readout and the comparator write can
397 * move us behind that point easily. Now instead of reading
398 * the compare register back several times, we make the ETIME
399 * decision based on the following: Return ETIME if the
400 * counter value after the write is less than HPET_MIN_CYCLES
401 * away from the event or if the counter is already ahead of
402 * the event. The minimum programming delta for the generic
403 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
404 */
405 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
406
407 return res < HPET_MIN_CYCLES ? -ETIME : 0;
408}
409
410static void hpet_legacy_set_mode(enum clock_event_mode mode,
411 struct clock_event_device *evt)
412{
413 hpet_set_mode(mode, evt, 0);
414}
415
416static int hpet_legacy_next_event(unsigned long delta,
417 struct clock_event_device *evt)
418{
419 return hpet_next_event(delta, evt, 0);
420}
421
422/*
423 * HPET MSI Support
424 */
425#ifdef CONFIG_PCI_MSI
426
427static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
428static struct hpet_dev *hpet_devs;
429
430void hpet_msi_unmask(struct irq_data *data)
431{
432 struct hpet_dev *hdev = data->handler_data;
433 unsigned int cfg;
434
435 /* unmask it */
436 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
437 cfg |= HPET_TN_FSB;
438 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
439}
440
441void hpet_msi_mask(struct irq_data *data)
442{
443 struct hpet_dev *hdev = data->handler_data;
444 unsigned int cfg;
445
446 /* mask it */
447 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
448 cfg &= ~HPET_TN_FSB;
449 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
450}
451
452void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
453{
454 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
455 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
456}
457
458void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
459{
460 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
461 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
462 msg->address_hi = 0;
463}
464
465static void hpet_msi_set_mode(enum clock_event_mode mode,
466 struct clock_event_device *evt)
467{
468 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
469 hpet_set_mode(mode, evt, hdev->num);
470}
471
472static int hpet_msi_next_event(unsigned long delta,
473 struct clock_event_device *evt)
474{
475 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
476 return hpet_next_event(delta, evt, hdev->num);
477}
478
479static int hpet_setup_msi_irq(unsigned int irq)
480{
481 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
482 destroy_irq(irq);
483 return -EINVAL;
484 }
485 return 0;
486}
487
488static int hpet_assign_irq(struct hpet_dev *dev)
489{
490 unsigned int irq;
491
492 irq = create_irq_nr(0, -1);
493 if (!irq)
494 return -EINVAL;
495
496 irq_set_handler_data(irq, dev);
497
498 if (hpet_setup_msi_irq(irq))
499 return -EINVAL;
500
501 dev->irq = irq;
502 return 0;
503}
504
505static irqreturn_t hpet_interrupt_handler(int irq, void *data)
506{
507 struct hpet_dev *dev = (struct hpet_dev *)data;
508 struct clock_event_device *hevt = &dev->evt;
509
510 if (!hevt->event_handler) {
511 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
512 dev->num);
513 return IRQ_HANDLED;
514 }
515
516 hevt->event_handler(hevt);
517 return IRQ_HANDLED;
518}
519
520static int hpet_setup_irq(struct hpet_dev *dev)
521{
522
523 if (request_irq(dev->irq, hpet_interrupt_handler,
524 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
525 dev->name, dev))
526 return -1;
527
528 disable_irq(dev->irq);
529 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
530 enable_irq(dev->irq);
531
532 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
533 dev->name, dev->irq);
534
535 return 0;
536}
537
538/* This should be called in specific @cpu */
539static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
540{
541 struct clock_event_device *evt = &hdev->evt;
542
543 WARN_ON(cpu != smp_processor_id());
544 if (!(hdev->flags & HPET_DEV_VALID))
545 return;
546
547 if (hpet_setup_msi_irq(hdev->irq))
548 return;
549
550 hdev->cpu = cpu;
551 per_cpu(cpu_hpet_dev, cpu) = hdev;
552 evt->name = hdev->name;
553 hpet_setup_irq(hdev);
554 evt->irq = hdev->irq;
555
556 evt->rating = 110;
557 evt->features = CLOCK_EVT_FEAT_ONESHOT;
558 if (hdev->flags & HPET_DEV_PERI_CAP)
559 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
560
561 evt->set_mode = hpet_msi_set_mode;
562 evt->set_next_event = hpet_msi_next_event;
563 evt->cpumask = cpumask_of(hdev->cpu);
564
565 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
566 0x7FFFFFFF);
567}
568
569#ifdef CONFIG_HPET
570/* Reserve at least one timer for userspace (/dev/hpet) */
571#define RESERVE_TIMERS 1
572#else
573#define RESERVE_TIMERS 0
574#endif
575
576static void hpet_msi_capability_lookup(unsigned int start_timer)
577{
578 unsigned int id;
579 unsigned int num_timers;
580 unsigned int num_timers_used = 0;
581 int i;
582
583 if (hpet_msi_disable)
584 return;
585
586 if (boot_cpu_has(X86_FEATURE_ARAT))
587 return;
588 id = hpet_readl(HPET_ID);
589
590 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
591 num_timers++; /* Value read out starts from 0 */
592 hpet_print_config();
593
594 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
595 if (!hpet_devs)
596 return;
597
598 hpet_num_timers = num_timers;
599
600 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
601 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
602 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
603
604 /* Only consider HPET timer with MSI support */
605 if (!(cfg & HPET_TN_FSB_CAP))
606 continue;
607
608 hdev->flags = 0;
609 if (cfg & HPET_TN_PERIODIC_CAP)
610 hdev->flags |= HPET_DEV_PERI_CAP;
611 hdev->num = i;
612
613 sprintf(hdev->name, "hpet%d", i);
614 if (hpet_assign_irq(hdev))
615 continue;
616
617 hdev->flags |= HPET_DEV_FSB_CAP;
618 hdev->flags |= HPET_DEV_VALID;
619 num_timers_used++;
620 if (num_timers_used == num_possible_cpus())
621 break;
622 }
623
624 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
625 num_timers, num_timers_used);
626}
627
628#ifdef CONFIG_HPET
629static void hpet_reserve_msi_timers(struct hpet_data *hd)
630{
631 int i;
632
633 if (!hpet_devs)
634 return;
635
636 for (i = 0; i < hpet_num_timers; i++) {
637 struct hpet_dev *hdev = &hpet_devs[i];
638
639 if (!(hdev->flags & HPET_DEV_VALID))
640 continue;
641
642 hd->hd_irq[hdev->num] = hdev->irq;
643 hpet_reserve_timer(hd, hdev->num);
644 }
645}
646#endif
647
648static struct hpet_dev *hpet_get_unused_timer(void)
649{
650 int i;
651
652 if (!hpet_devs)
653 return NULL;
654
655 for (i = 0; i < hpet_num_timers; i++) {
656 struct hpet_dev *hdev = &hpet_devs[i];
657
658 if (!(hdev->flags & HPET_DEV_VALID))
659 continue;
660 if (test_and_set_bit(HPET_DEV_USED_BIT,
661 (unsigned long *)&hdev->flags))
662 continue;
663 return hdev;
664 }
665 return NULL;
666}
667
668struct hpet_work_struct {
669 struct delayed_work work;
670 struct completion complete;
671};
672
673static void hpet_work(struct work_struct *w)
674{
675 struct hpet_dev *hdev;
676 int cpu = smp_processor_id();
677 struct hpet_work_struct *hpet_work;
678
679 hpet_work = container_of(w, struct hpet_work_struct, work.work);
680
681 hdev = hpet_get_unused_timer();
682 if (hdev)
683 init_one_hpet_msi_clockevent(hdev, cpu);
684
685 complete(&hpet_work->complete);
686}
687
688static int hpet_cpuhp_notify(struct notifier_block *n,
689 unsigned long action, void *hcpu)
690{
691 unsigned long cpu = (unsigned long)hcpu;
692 struct hpet_work_struct work;
693 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
694
695 switch (action & 0xf) {
696 case CPU_ONLINE:
697 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
698 init_completion(&work.complete);
699 /* FIXME: add schedule_work_on() */
700 schedule_delayed_work_on(cpu, &work.work, 0);
701 wait_for_completion(&work.complete);
702 destroy_timer_on_stack(&work.work.timer);
703 break;
704 case CPU_DEAD:
705 if (hdev) {
706 free_irq(hdev->irq, hdev);
707 hdev->flags &= ~HPET_DEV_USED;
708 per_cpu(cpu_hpet_dev, cpu) = NULL;
709 }
710 break;
711 }
712 return NOTIFY_OK;
713}
714#else
715
716static int hpet_setup_msi_irq(unsigned int irq)
717{
718 return 0;
719}
720static void hpet_msi_capability_lookup(unsigned int start_timer)
721{
722 return;
723}
724
725#ifdef CONFIG_HPET
726static void hpet_reserve_msi_timers(struct hpet_data *hd)
727{
728 return;
729}
730#endif
731
732static int hpet_cpuhp_notify(struct notifier_block *n,
733 unsigned long action, void *hcpu)
734{
735 return NOTIFY_OK;
736}
737
738#endif
739
740/*
741 * Clock source related code
742 */
743static cycle_t read_hpet(struct clocksource *cs)
744{
745 return (cycle_t)hpet_readl(HPET_COUNTER);
746}
747
748static struct clocksource clocksource_hpet = {
749 .name = "hpet",
750 .rating = 250,
751 .read = read_hpet,
752 .mask = HPET_MASK,
753 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
754 .resume = hpet_resume_counter,
755#ifdef CONFIG_X86_64
756 .archdata = { .vclock_mode = VCLOCK_HPET },
757#endif
758};
759
760static int hpet_clocksource_register(void)
761{
762 u64 start, now;
763 cycle_t t1;
764
765 /* Start the counter */
766 hpet_restart_counter();
767
768 /* Verify whether hpet counter works */
769 t1 = hpet_readl(HPET_COUNTER);
770 rdtscll(start);
771
772 /*
773 * We don't know the TSC frequency yet, but waiting for
774 * 200000 TSC cycles is safe:
775 * 4 GHz == 50us
776 * 1 GHz == 200us
777 */
778 do {
779 rep_nop();
780 rdtscll(now);
781 } while ((now - start) < 200000UL);
782
783 if (t1 == hpet_readl(HPET_COUNTER)) {
784 printk(KERN_WARNING
785 "HPET counter not counting. HPET disabled\n");
786 return -ENODEV;
787 }
788
789 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
790 return 0;
791}
792
793static u32 *hpet_boot_cfg;
794
795/**
796 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
797 */
798int __init hpet_enable(void)
799{
800 u32 hpet_period, cfg, id;
801 u64 freq;
802 unsigned int i, last;
803
804 if (!is_hpet_capable())
805 return 0;
806
807 hpet_set_mapping();
808
809 /*
810 * Read the period and check for a sane value:
811 */
812 hpet_period = hpet_readl(HPET_PERIOD);
813
814 /*
815 * AMD SB700 based systems with spread spectrum enabled use a
816 * SMM based HPET emulation to provide proper frequency
817 * setting. The SMM code is initialized with the first HPET
818 * register access and takes some time to complete. During
819 * this time the config register reads 0xffffffff. We check
820 * for max. 1000 loops whether the config register reads a non
821 * 0xffffffff value to make sure that HPET is up and running
822 * before we go further. A counting loop is safe, as the HPET
823 * access takes thousands of CPU cycles. On non SB700 based
824 * machines this check is only done once and has no side
825 * effects.
826 */
827 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
828 if (i == 1000) {
829 printk(KERN_WARNING
830 "HPET config register value = 0xFFFFFFFF. "
831 "Disabling HPET\n");
832 goto out_nohpet;
833 }
834 }
835
836 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
837 goto out_nohpet;
838
839 /*
840 * The period is a femto seconds value. Convert it to a
841 * frequency.
842 */
843 freq = FSEC_PER_SEC;
844 do_div(freq, hpet_period);
845 hpet_freq = freq;
846
847 /*
848 * Read the HPET ID register to retrieve the IRQ routing
849 * information and the number of channels
850 */
851 id = hpet_readl(HPET_ID);
852 hpet_print_config();
853
854 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
855
856#ifdef CONFIG_HPET_EMULATE_RTC
857 /*
858 * The legacy routing mode needs at least two channels, tick timer
859 * and the rtc emulation channel.
860 */
861 if (!last)
862 goto out_nohpet;
863#endif
864
865 cfg = hpet_readl(HPET_CFG);
866 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
867 GFP_KERNEL);
868 if (hpet_boot_cfg)
869 *hpet_boot_cfg = cfg;
870 else
871 pr_warn("HPET initial state will not be saved\n");
872 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
873 hpet_writel(cfg, HPET_CFG);
874 if (cfg)
875 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
876 cfg);
877
878 for (i = 0; i <= last; ++i) {
879 cfg = hpet_readl(HPET_Tn_CFG(i));
880 if (hpet_boot_cfg)
881 hpet_boot_cfg[i + 1] = cfg;
882 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
883 hpet_writel(cfg, HPET_Tn_CFG(i));
884 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
885 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
886 | HPET_TN_FSB | HPET_TN_FSB_CAP);
887 if (cfg)
888 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
889 cfg, i);
890 }
891 hpet_print_config();
892
893 if (hpet_clocksource_register())
894 goto out_nohpet;
895
896 if (id & HPET_ID_LEGSUP) {
897 hpet_legacy_clockevent_register();
898 return 1;
899 }
900 return 0;
901
902out_nohpet:
903 hpet_clear_mapping();
904 hpet_address = 0;
905 return 0;
906}
907
908/*
909 * Needs to be late, as the reserve_timer code calls kalloc !
910 *
911 * Not a problem on i386 as hpet_enable is called from late_time_init,
912 * but on x86_64 it is necessary !
913 */
914static __init int hpet_late_init(void)
915{
916 int cpu;
917
918 if (boot_hpet_disable)
919 return -ENODEV;
920
921 if (!hpet_address) {
922 if (!force_hpet_address)
923 return -ENODEV;
924
925 hpet_address = force_hpet_address;
926 hpet_enable();
927 }
928
929 if (!hpet_virt_address)
930 return -ENODEV;
931
932 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
933 hpet_msi_capability_lookup(2);
934 else
935 hpet_msi_capability_lookup(0);
936
937 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
938 hpet_print_config();
939
940 if (hpet_msi_disable)
941 return 0;
942
943 if (boot_cpu_has(X86_FEATURE_ARAT))
944 return 0;
945
946 for_each_online_cpu(cpu) {
947 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
948 }
949
950 /* This notifier should be called after workqueue is ready */
951 hotcpu_notifier(hpet_cpuhp_notify, -20);
952
953 return 0;
954}
955fs_initcall(hpet_late_init);
956
957void hpet_disable(void)
958{
959 if (is_hpet_capable() && hpet_virt_address) {
960 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
961
962 if (hpet_boot_cfg)
963 cfg = *hpet_boot_cfg;
964 else if (hpet_legacy_int_enabled) {
965 cfg &= ~HPET_CFG_LEGACY;
966 hpet_legacy_int_enabled = 0;
967 }
968 cfg &= ~HPET_CFG_ENABLE;
969 hpet_writel(cfg, HPET_CFG);
970
971 if (!hpet_boot_cfg)
972 return;
973
974 id = hpet_readl(HPET_ID);
975 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
976
977 for (id = 0; id <= last; ++id)
978 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
979
980 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
981 hpet_writel(*hpet_boot_cfg, HPET_CFG);
982 }
983}
984
985#ifdef CONFIG_HPET_EMULATE_RTC
986
987/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
988 * is enabled, we support RTC interrupt functionality in software.
989 * RTC has 3 kinds of interrupts:
990 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
991 * is updated
992 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
993 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
994 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
995 * (1) and (2) above are implemented using polling at a frequency of
996 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
997 * overhead. (DEFAULT_RTC_INT_FREQ)
998 * For (3), we use interrupts at 64Hz or user specified periodic
999 * frequency, whichever is higher.
1000 */
1001#include <linux/mc146818rtc.h>
1002#include <linux/rtc.h>
1003#include <asm/rtc.h>
1004
1005#define DEFAULT_RTC_INT_FREQ 64
1006#define DEFAULT_RTC_SHIFT 6
1007#define RTC_NUM_INTS 1
1008
1009static unsigned long hpet_rtc_flags;
1010static int hpet_prev_update_sec;
1011static struct rtc_time hpet_alarm_time;
1012static unsigned long hpet_pie_count;
1013static u32 hpet_t1_cmp;
1014static u32 hpet_default_delta;
1015static u32 hpet_pie_delta;
1016static unsigned long hpet_pie_limit;
1017
1018static rtc_irq_handler irq_handler;
1019
1020/*
1021 * Check that the hpet counter c1 is ahead of the c2
1022 */
1023static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1024{
1025 return (s32)(c2 - c1) < 0;
1026}
1027
1028/*
1029 * Registers a IRQ handler.
1030 */
1031int hpet_register_irq_handler(rtc_irq_handler handler)
1032{
1033 if (!is_hpet_enabled())
1034 return -ENODEV;
1035 if (irq_handler)
1036 return -EBUSY;
1037
1038 irq_handler = handler;
1039
1040 return 0;
1041}
1042EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1043
1044/*
1045 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1046 * and does cleanup.
1047 */
1048void hpet_unregister_irq_handler(rtc_irq_handler handler)
1049{
1050 if (!is_hpet_enabled())
1051 return;
1052
1053 irq_handler = NULL;
1054 hpet_rtc_flags = 0;
1055}
1056EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1057
1058/*
1059 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1060 * is not supported by all HPET implementations for timer 1.
1061 *
1062 * hpet_rtc_timer_init() is called when the rtc is initialized.
1063 */
1064int hpet_rtc_timer_init(void)
1065{
1066 unsigned int cfg, cnt, delta;
1067 unsigned long flags;
1068
1069 if (!is_hpet_enabled())
1070 return 0;
1071
1072 if (!hpet_default_delta) {
1073 uint64_t clc;
1074
1075 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1076 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1077 hpet_default_delta = clc;
1078 }
1079
1080 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1081 delta = hpet_default_delta;
1082 else
1083 delta = hpet_pie_delta;
1084
1085 local_irq_save(flags);
1086
1087 cnt = delta + hpet_readl(HPET_COUNTER);
1088 hpet_writel(cnt, HPET_T1_CMP);
1089 hpet_t1_cmp = cnt;
1090
1091 cfg = hpet_readl(HPET_T1_CFG);
1092 cfg &= ~HPET_TN_PERIODIC;
1093 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1094 hpet_writel(cfg, HPET_T1_CFG);
1095
1096 local_irq_restore(flags);
1097
1098 return 1;
1099}
1100EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1101
1102static void hpet_disable_rtc_channel(void)
1103{
1104 unsigned long cfg;
1105 cfg = hpet_readl(HPET_T1_CFG);
1106 cfg &= ~HPET_TN_ENABLE;
1107 hpet_writel(cfg, HPET_T1_CFG);
1108}
1109
1110/*
1111 * The functions below are called from rtc driver.
1112 * Return 0 if HPET is not being used.
1113 * Otherwise do the necessary changes and return 1.
1114 */
1115int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1116{
1117 if (!is_hpet_enabled())
1118 return 0;
1119
1120 hpet_rtc_flags &= ~bit_mask;
1121 if (unlikely(!hpet_rtc_flags))
1122 hpet_disable_rtc_channel();
1123
1124 return 1;
1125}
1126EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1127
1128int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1129{
1130 unsigned long oldbits = hpet_rtc_flags;
1131
1132 if (!is_hpet_enabled())
1133 return 0;
1134
1135 hpet_rtc_flags |= bit_mask;
1136
1137 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1138 hpet_prev_update_sec = -1;
1139
1140 if (!oldbits)
1141 hpet_rtc_timer_init();
1142
1143 return 1;
1144}
1145EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1146
1147int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1148 unsigned char sec)
1149{
1150 if (!is_hpet_enabled())
1151 return 0;
1152
1153 hpet_alarm_time.tm_hour = hrs;
1154 hpet_alarm_time.tm_min = min;
1155 hpet_alarm_time.tm_sec = sec;
1156
1157 return 1;
1158}
1159EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1160
1161int hpet_set_periodic_freq(unsigned long freq)
1162{
1163 uint64_t clc;
1164
1165 if (!is_hpet_enabled())
1166 return 0;
1167
1168 if (freq <= DEFAULT_RTC_INT_FREQ)
1169 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1170 else {
1171 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1172 do_div(clc, freq);
1173 clc >>= hpet_clockevent.shift;
1174 hpet_pie_delta = clc;
1175 hpet_pie_limit = 0;
1176 }
1177 return 1;
1178}
1179EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1180
1181int hpet_rtc_dropped_irq(void)
1182{
1183 return is_hpet_enabled();
1184}
1185EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1186
1187static void hpet_rtc_timer_reinit(void)
1188{
1189 unsigned int delta;
1190 int lost_ints = -1;
1191
1192 if (unlikely(!hpet_rtc_flags))
1193 hpet_disable_rtc_channel();
1194
1195 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1196 delta = hpet_default_delta;
1197 else
1198 delta = hpet_pie_delta;
1199
1200 /*
1201 * Increment the comparator value until we are ahead of the
1202 * current count.
1203 */
1204 do {
1205 hpet_t1_cmp += delta;
1206 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1207 lost_ints++;
1208 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1209
1210 if (lost_ints) {
1211 if (hpet_rtc_flags & RTC_PIE)
1212 hpet_pie_count += lost_ints;
1213 if (printk_ratelimit())
1214 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1215 lost_ints);
1216 }
1217}
1218
1219irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1220{
1221 struct rtc_time curr_time;
1222 unsigned long rtc_int_flag = 0;
1223
1224 hpet_rtc_timer_reinit();
1225 memset(&curr_time, 0, sizeof(struct rtc_time));
1226
1227 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1228 get_rtc_time(&curr_time);
1229
1230 if (hpet_rtc_flags & RTC_UIE &&
1231 curr_time.tm_sec != hpet_prev_update_sec) {
1232 if (hpet_prev_update_sec >= 0)
1233 rtc_int_flag = RTC_UF;
1234 hpet_prev_update_sec = curr_time.tm_sec;
1235 }
1236
1237 if (hpet_rtc_flags & RTC_PIE &&
1238 ++hpet_pie_count >= hpet_pie_limit) {
1239 rtc_int_flag |= RTC_PF;
1240 hpet_pie_count = 0;
1241 }
1242
1243 if (hpet_rtc_flags & RTC_AIE &&
1244 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1245 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1246 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1247 rtc_int_flag |= RTC_AF;
1248
1249 if (rtc_int_flag) {
1250 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1251 if (irq_handler)
1252 irq_handler(rtc_int_flag, dev_id);
1253 }
1254 return IRQ_HANDLED;
1255}
1256EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1257#endif