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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Count register synchronisation.
4 *
5 * All CPUs will have their count registers synchronised to the CPU0 next time
6 * value. This can cause a small timewarp for CPU0. All other CPU's should
7 * not have done anything significant (but they may have had interrupts
8 * enabled briefly - prom_smp_finish() should not be responsible for enabling
9 * interrupts...)
10 */
11
12#include <linux/kernel.h>
13#include <linux/irqflags.h>
14#include <linux/cpumask.h>
15
16#include <asm/r4k-timer.h>
17#include <linux/atomic.h>
18#include <asm/barrier.h>
19#include <asm/mipsregs.h>
20
21static unsigned int initcount = 0;
22static atomic_t count_count_start = ATOMIC_INIT(0);
23static atomic_t count_count_stop = ATOMIC_INIT(0);
24
25#define COUNTON 100
26#define NR_LOOPS 3
27
28void synchronise_count_master(int cpu)
29{
30 int i;
31 unsigned long flags;
32
33 pr_info("Synchronize counters for CPU %u: ", cpu);
34
35 local_irq_save(flags);
36
37 /*
38 * We loop a few times to get a primed instruction cache,
39 * then the last pass is more or less synchronised and
40 * the master and slaves each set their cycle counters to a known
41 * value all at once. This reduces the chance of having random offsets
42 * between the processors, and guarantees that the maximum
43 * delay between the cycle counters is never bigger than
44 * the latency of information-passing (cachelines) between
45 * two CPUs.
46 */
47
48 for (i = 0; i < NR_LOOPS; i++) {
49 /* slaves loop on '!= 2' */
50 while (atomic_read(&count_count_start) != 1)
51 mb();
52 atomic_set(&count_count_stop, 0);
53 smp_wmb();
54
55 /* Let the slave writes its count register */
56 atomic_inc(&count_count_start);
57
58 /* Count will be initialised to current timer */
59 if (i == 1)
60 initcount = read_c0_count();
61
62 /*
63 * Everyone initialises count in the last loop:
64 */
65 if (i == NR_LOOPS-1)
66 write_c0_count(initcount);
67
68 /*
69 * Wait for slave to leave the synchronization point:
70 */
71 while (atomic_read(&count_count_stop) != 1)
72 mb();
73 atomic_set(&count_count_start, 0);
74 smp_wmb();
75 atomic_inc(&count_count_stop);
76 }
77 /* Arrange for an interrupt in a short while */
78 write_c0_compare(read_c0_count() + COUNTON);
79
80 local_irq_restore(flags);
81
82 /*
83 * i386 code reported the skew here, but the
84 * count registers were almost certainly out of sync
85 * so no point in alarming people
86 */
87 pr_cont("done.\n");
88}
89
90void synchronise_count_slave(int cpu)
91{
92 int i;
93
94 /*
95 * Not every cpu is online at the time this gets called,
96 * so we first wait for the master to say everyone is ready
97 */
98
99 for (i = 0; i < NR_LOOPS; i++) {
100 atomic_inc(&count_count_start);
101 while (atomic_read(&count_count_start) != 2)
102 mb();
103
104 /*
105 * Everyone initialises count in the last loop:
106 */
107 if (i == NR_LOOPS-1)
108 write_c0_count(initcount);
109
110 atomic_inc(&count_count_stop);
111 while (atomic_read(&count_count_stop) != 2)
112 mb();
113 }
114 /* Arrange for an interrupt in a short while */
115 write_c0_compare(read_c0_count() + COUNTON);
116}
117#undef NR_LOOPS
1/*
2 * Count register synchronisation.
3 *
4 * All CPUs will have their count registers synchronised to the CPU0 next time
5 * value. This can cause a small timewarp for CPU0. All other CPU's should
6 * not have done anything significant (but they may have had interrupts
7 * enabled briefly - prom_smp_finish() should not be responsible for enabling
8 * interrupts...)
9 *
10 * FIXME: broken for SMTC
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/irqflags.h>
16#include <linux/cpumask.h>
17
18#include <asm/r4k-timer.h>
19#include <linux/atomic.h>
20#include <asm/barrier.h>
21#include <asm/mipsregs.h>
22
23static atomic_t __cpuinitdata count_start_flag = ATOMIC_INIT(0);
24static atomic_t __cpuinitdata count_count_start = ATOMIC_INIT(0);
25static atomic_t __cpuinitdata count_count_stop = ATOMIC_INIT(0);
26static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0);
27
28#define COUNTON 100
29#define NR_LOOPS 5
30
31void __cpuinit synchronise_count_master(void)
32{
33 int i;
34 unsigned long flags;
35 unsigned int initcount;
36 int nslaves;
37
38#ifdef CONFIG_MIPS_MT_SMTC
39 /*
40 * SMTC needs to synchronise per VPE, not per CPU
41 * ignore for now
42 */
43 return;
44#endif
45
46 printk(KERN_INFO "Synchronize counters across %u CPUs: ",
47 num_online_cpus());
48
49 local_irq_save(flags);
50
51 /*
52 * Notify the slaves that it's time to start
53 */
54 atomic_set(&count_reference, read_c0_count());
55 atomic_set(&count_start_flag, 1);
56 smp_wmb();
57
58 /* Count will be initialised to current timer for all CPU's */
59 initcount = read_c0_count();
60
61 /*
62 * We loop a few times to get a primed instruction cache,
63 * then the last pass is more or less synchronised and
64 * the master and slaves each set their cycle counters to a known
65 * value all at once. This reduces the chance of having random offsets
66 * between the processors, and guarantees that the maximum
67 * delay between the cycle counters is never bigger than
68 * the latency of information-passing (cachelines) between
69 * two CPUs.
70 */
71
72 nslaves = num_online_cpus()-1;
73 for (i = 0; i < NR_LOOPS; i++) {
74 /* slaves loop on '!= ncpus' */
75 while (atomic_read(&count_count_start) != nslaves)
76 mb();
77 atomic_set(&count_count_stop, 0);
78 smp_wmb();
79
80 /* this lets the slaves write their count register */
81 atomic_inc(&count_count_start);
82
83 /*
84 * Everyone initialises count in the last loop:
85 */
86 if (i == NR_LOOPS-1)
87 write_c0_count(initcount);
88
89 /*
90 * Wait for all slaves to leave the synchronization point:
91 */
92 while (atomic_read(&count_count_stop) != nslaves)
93 mb();
94 atomic_set(&count_count_start, 0);
95 smp_wmb();
96 atomic_inc(&count_count_stop);
97 }
98 /* Arrange for an interrupt in a short while */
99 write_c0_compare(read_c0_count() + COUNTON);
100
101 local_irq_restore(flags);
102
103 /*
104 * i386 code reported the skew here, but the
105 * count registers were almost certainly out of sync
106 * so no point in alarming people
107 */
108 printk("done.\n");
109}
110
111void __cpuinit synchronise_count_slave(void)
112{
113 int i;
114 unsigned int initcount;
115 int ncpus;
116
117#ifdef CONFIG_MIPS_MT_SMTC
118 /*
119 * SMTC needs to synchronise per VPE, not per CPU
120 * ignore for now
121 */
122 return;
123#endif
124
125 /*
126 * Not every cpu is online at the time this gets called,
127 * so we first wait for the master to say everyone is ready
128 */
129
130 while (!atomic_read(&count_start_flag))
131 mb();
132
133 /* Count will be initialised to next expire for all CPU's */
134 initcount = atomic_read(&count_reference);
135
136 ncpus = num_online_cpus();
137 for (i = 0; i < NR_LOOPS; i++) {
138 atomic_inc(&count_count_start);
139 while (atomic_read(&count_count_start) != ncpus)
140 mb();
141
142 /*
143 * Everyone initialises count in the last loop:
144 */
145 if (i == NR_LOOPS-1)
146 write_c0_count(initcount);
147
148 atomic_inc(&count_count_stop);
149 while (atomic_read(&count_count_stop) != ncpus)
150 mb();
151 }
152 /* Arrange for an interrupt in a short while */
153 write_c0_compare(read_c0_count() + COUNTON);
154}
155#undef NR_LOOPS