1/*
 2 * This file is subject to the terms and conditions of the GNU General Public
 3 * License.  See the file "COPYING" in the main directory of this archive
 4 * for more details.
 5 *
 6 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
 7 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
 8 */
 9#ifndef _ASM_IRQ_H
10#define _ASM_IRQ_H
11
12#include <linux/linkage.h>
13#include <linux/smp.h>
14#include <linux/irqdomain.h>
15
16#include <asm/mipsmtregs.h>
17
18#include <irq.h>
19
20#define IRQ_STACK_SIZE			THREAD_SIZE
21#define IRQ_STACK_START			(IRQ_STACK_SIZE - 16)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
22
23extern void *irq_stack[NR_CPUS];
 
 
24
25/*
26 * The highest address on the IRQ stack contains a dummy frame put down in
27 * genex.S (handle_int & except_vec_vi_handler) which is structured as follows:
28 *
29 *   top ------------
30 *       | task sp  | <- irq_stack[cpu] + IRQ_STACK_START
31 *       ------------
32 *       |          | <- First frame of IRQ context
33 *       ------------
34 *
35 * task sp holds a copy of the task stack pointer where the struct pt_regs
36 * from exception entry can be found.
37 */
38
39static inline bool on_irq_stack(int cpu, unsigned long sp)
40{
41	unsigned long low = (unsigned long)irq_stack[cpu];
42	unsigned long high = low + IRQ_STACK_SIZE;
43
44	return (low <= sp && sp <= high);
 
 
 
45}
46
47#ifdef CONFIG_I8259
48static inline int irq_canonicalize(int irq)
 
 
 
 
 
 
 
49{
50	return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
51}
 
52#else
53#define irq_canonicalize(irq) (irq)	/* Sane hardware, sane code ... */
54#endif
55
56asmlinkage void plat_irq_dispatch(void);
 
 
 
 
 
 
57
58extern void do_IRQ(unsigned int irq);
59
 
 
 
 
 
 
60extern void arch_init_irq(void);
61extern void spurious_interrupt(void);
62
63extern int allocate_irqno(void);
64extern void alloc_legacy_irqno(void);
65extern void free_irqno(unsigned int irq);
66
67/*
68 * Before R2 the timer and performance counter interrupts were both fixed to
69 * IE7.	 Since R2 their number has to be read from the c0_intctl register.
70 */
71#define CP0_LEGACY_COMPARE_IRQ 7
72#define CP0_LEGACY_PERFCNT_IRQ 7
73
74extern int cp0_compare_irq;
75extern int cp0_compare_irq_shift;
76extern int cp0_perfcount_irq;
77extern int cp0_fdc_irq;
78
79extern int get_c0_fdc_int(void);
80
81void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
82				    bool exclude_self);
83#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
84
85#endif /* _ASM_IRQ_H */

  1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
  7 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
  8 */
  9#ifndef _ASM_IRQ_H
 10#define _ASM_IRQ_H
 11
 12#include <linux/linkage.h>
 13#include <linux/smp.h>
 14#include <linux/irqdomain.h>
 15
 16#include <asm/mipsmtregs.h>
 17
 18#include <irq.h>
 19
 20#ifdef CONFIG_I8259
 21static inline int irq_canonicalize(int irq)
 22{
 23	return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
 24}
 25#else
 26#define irq_canonicalize(irq) (irq)	/* Sane hardware, sane code ... */
 27#endif
 28
 29#ifdef CONFIG_MIPS_MT_SMTC
 30
 31struct irqaction;
 32
 33extern unsigned long irq_hwmask[];
 34extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
 35                          unsigned long hwmask);
 36
 37static inline void smtc_im_ack_irq(unsigned int irq)
 38{
 39	if (irq_hwmask[irq] & ST0_IM)
 40		set_c0_status(irq_hwmask[irq] & ST0_IM);
 41}
 42
 43#else
 44
 45static inline void smtc_im_ack_irq(unsigned int irq)
 46{
 47}
 48
 49#endif /* CONFIG_MIPS_MT_SMTC */
 50
 51#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
 52#include <linux/cpumask.h>
 53
 54extern int plat_set_irq_affinity(struct irq_data *d,
 55				 const struct cpumask *affinity, bool force);
 56extern void smtc_forward_irq(struct irq_data *d);
 57
 58/*
 59 * IRQ affinity hook invoked at the beginning of interrupt dispatch
 60 * if option is enabled.
 61 *
 62 * Up through Linux 2.6.22 (at least) cpumask operations are very
 63 * inefficient on MIPS.  Initial prototypes of SMTC IRQ affinity
 64 * used a "fast path" per-IRQ-descriptor cache of affinity information
 65 * to reduce latency.  As there is a project afoot to optimize the
 66 * cpumask implementations, this version is optimistically assuming
 67 * that cpumask.h macro overhead is reasonable during interrupt dispatch.
 
 
 68 */
 69static inline int handle_on_other_cpu(unsigned int irq)
 
 70{
 71	struct irq_data *d = irq_get_irq_data(irq);
 
 72
 73	if (cpumask_test_cpu(smp_processor_id(), d->affinity))
 74		return 0;
 75	smtc_forward_irq(d);
 76	return 1;
 77}
 78
 79#else /* Not doing SMTC affinity */
 80
 81static inline int handle_on_other_cpu(unsigned int irq) { return 0; }
 82
 83#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
 84
 85#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
 86
 87static inline void smtc_im_backstop(unsigned int irq)
 88{
 89	if (irq_hwmask[irq] & 0x0000ff00)
 90		write_c0_tccontext(read_c0_tccontext() &
 91				   ~(irq_hwmask[irq] & 0x0000ff00));
 92}
 93
 94/*
 95 * Clear interrupt mask handling "backstop" if irq_hwmask
 96 * entry so indicates. This implies that the ack() or end()
 97 * functions will take over re-enabling the low-level mask.
 98 * Otherwise it will be done on return from exception.
 99 */
100static inline int smtc_handle_on_other_cpu(unsigned int irq)
101{
102	int ret = handle_on_other_cpu(irq);
103
104	if (!ret)
105		smtc_im_backstop(irq);
106	return ret;
107}
108
109#else
 
 
110
111static inline void smtc_im_backstop(unsigned int irq) { }
112static inline int smtc_handle_on_other_cpu(unsigned int irq)
113{
114	return handle_on_other_cpu(irq);
115}
116
117#endif
118
119extern void do_IRQ(unsigned int irq);
120
121#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
122
123extern void do_IRQ_no_affinity(unsigned int irq);
124
125#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
126
127extern void arch_init_irq(void);
128extern void spurious_interrupt(void);
129
130extern int allocate_irqno(void);
131extern void alloc_legacy_irqno(void);
132extern void free_irqno(unsigned int irq);
133
134/*
135 * Before R2 the timer and performance counter interrupts were both fixed to
136 * IE7.  Since R2 their number has to be read from the c0_intctl register.
137 */
138#define CP0_LEGACY_COMPARE_IRQ 7
139#define CP0_LEGACY_PERFCNT_IRQ 7
140
141extern int cp0_compare_irq;
142extern int cp0_compare_irq_shift;
143extern int cp0_perfcount_irq;
 
 
 
 
 
 
 
144
145#endif /* _ASM_IRQ_H */