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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Cadence UART driver (found in Xilinx Zynq)
4 *
5 * 2011 - 2014 (C) Xilinx Inc.
6 *
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
9 * in the code.
10 */
11
12#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
16#include <linux/platform_device.h>
17#include <linux/serial.h>
18#include <linux/console.h>
19#include <linux/serial_core.h>
20#include <linux/slab.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/clk.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/of.h>
27#include <linux/module.h>
28#include <linux/pm_runtime.h>
29#include <linux/iopoll.h>
30
31#define CDNS_UART_TTY_NAME "ttyPS"
32#define CDNS_UART_NAME "xuartps"
33#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
34#define CDNS_UART_REGISTER_SPACE 0x1000
35#define TX_TIMEOUT 500000
36
37/* Rx Trigger level */
38static int rx_trigger_level = 56;
39static int uartps_major;
40module_param(rx_trigger_level, uint, 0444);
41MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
42
43/* Rx Timeout */
44static int rx_timeout = 10;
45module_param(rx_timeout, uint, 0444);
46MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
47
48/* Register offsets for the UART. */
49#define CDNS_UART_CR 0x00 /* Control Register */
50#define CDNS_UART_MR 0x04 /* Mode Register */
51#define CDNS_UART_IER 0x08 /* Interrupt Enable */
52#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
53#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
54#define CDNS_UART_ISR 0x14 /* Interrupt Status */
55#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
56#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
58#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
59#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
60#define CDNS_UART_SR 0x2C /* Channel Status */
61#define CDNS_UART_FIFO 0x30 /* FIFO */
62#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
63#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
64#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
65#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
66#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
67#define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
68
69/* Control Register Bit Definitions */
70#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
71#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
72#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
73#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
74#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
75#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
76#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
77#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
78#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
79#define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
80#define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
81#define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
82
83/*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92#define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
93
94#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
95#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
96
97#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
98#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
99#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
100#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
101#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
102
103#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
104#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
105#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
106
107/*
108 * Interrupt Registers:
109 * Interrupt control logic uses the interrupt enable register (IER) and the
110 * interrupt disable register (IDR) to set the value of the bits in the
111 * interrupt mask register (IMR). The IMR determines whether to pass an
112 * interrupt to the interrupt status register (ISR).
113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
114 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
115 * Reading either IER or IDR returns 0x00.
116 * All four registers have the same bit definitions.
117 */
118#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
119#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
120#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
121#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
122#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
123#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
124#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
125#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
126#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
127#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
128#define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
129
130 /*
131 * Do not enable parity error interrupt for the following
132 * reason: When parity error interrupt is enabled, each Rx
133 * parity error always results in 2 events. The first one
134 * being parity error interrupt and the second one with a
135 * proper Rx interrupt with the incoming data. Disabling
136 * parity error interrupt ensures better handling of parity
137 * error events. With this change, for a parity error case, we
138 * get a Rx interrupt with parity error set in ISR register
139 * and we still handle parity errors in the desired way.
140 */
141
142#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
143 CDNS_UART_IXR_OVERRUN | \
144 CDNS_UART_IXR_RXTRIG | \
145 CDNS_UART_IXR_TOUT)
146
147/* Goes in read_status_mask for break detection as the HW doesn't do it*/
148#define CDNS_UART_IXR_BRK 0x00002000
149
150#define CDNS_UART_RXBS_SUPPORT BIT(1)
151/*
152 * Modem Control register:
153 * The read/write Modem Control register controls the interface with the modem
154 * or data set, or a peripheral device emulating a modem.
155 */
156#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
157#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
158#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
159
160/*
161 * Channel Status Register:
162 * The channel status register (CSR) is provided to enable the control logic
163 * to monitor the status of bits in the channel interrupt status register,
164 * even if these are masked out by the interrupt mask register.
165 */
166#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
167#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
168#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
169#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
170#define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
171
172/* baud dividers min/max values */
173#define CDNS_UART_BDIV_MIN 4
174#define CDNS_UART_BDIV_MAX 255
175#define CDNS_UART_CD_MAX 65535
176#define UART_AUTOSUSPEND_TIMEOUT 3000
177
178/**
179 * struct cdns_uart - device data
180 * @port: Pointer to the UART port
181 * @uartclk: Reference clock
182 * @pclk: APB clock
183 * @cdns_uart_driver: Pointer to UART driver
184 * @baud: Current baud rate
185 * @id: Port ID
186 * @clk_rate_change_nb: Notifier block for clock changes
187 * @quirks: Flags for RXBS support.
188 */
189struct cdns_uart {
190 struct uart_port *port;
191 struct clk *uartclk;
192 struct clk *pclk;
193 struct uart_driver *cdns_uart_driver;
194 unsigned int baud;
195 int id;
196 struct notifier_block clk_rate_change_nb;
197 u32 quirks;
198 bool cts_override;
199};
200struct cdns_platform_data {
201 u32 quirks;
202};
203#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
204 clk_rate_change_nb)
205
206/**
207 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
208 * @dev_id: Id of the UART port
209 * @isrstatus: The interrupt status register value as read
210 * Return: None
211 */
212static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
213{
214 struct uart_port *port = (struct uart_port *)dev_id;
215 struct cdns_uart *cdns_uart = port->private_data;
216 unsigned int data;
217 unsigned int rxbs_status = 0;
218 unsigned int status_mask;
219 unsigned int framerrprocessed = 0;
220 char status = TTY_NORMAL;
221 bool is_rxbs_support;
222
223 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
224
225 while ((readl(port->membase + CDNS_UART_SR) &
226 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
227 if (is_rxbs_support)
228 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
229 data = readl(port->membase + CDNS_UART_FIFO);
230 port->icount.rx++;
231 /*
232 * There is no hardware break detection in Zynq, so we interpret
233 * framing error with all-zeros data as a break sequence.
234 * Most of the time, there's another non-zero byte at the
235 * end of the sequence.
236 */
237 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
238 if (!data) {
239 port->read_status_mask |= CDNS_UART_IXR_BRK;
240 framerrprocessed = 1;
241 continue;
242 }
243 }
244 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
245 port->icount.brk++;
246 status = TTY_BREAK;
247 if (uart_handle_break(port))
248 continue;
249 }
250
251 isrstatus &= port->read_status_mask;
252 isrstatus &= ~port->ignore_status_mask;
253 status_mask = port->read_status_mask;
254 status_mask &= ~port->ignore_status_mask;
255
256 if (data &&
257 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
258 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
259 port->icount.brk++;
260 if (uart_handle_break(port))
261 continue;
262 }
263
264 if (uart_handle_sysrq_char(port, data))
265 continue;
266
267 if (is_rxbs_support) {
268 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
269 && (status_mask & CDNS_UART_IXR_PARITY)) {
270 port->icount.parity++;
271 status = TTY_PARITY;
272 }
273 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
274 && (status_mask & CDNS_UART_IXR_PARITY)) {
275 port->icount.frame++;
276 status = TTY_FRAME;
277 }
278 } else {
279 if (isrstatus & CDNS_UART_IXR_PARITY) {
280 port->icount.parity++;
281 status = TTY_PARITY;
282 }
283 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
284 !framerrprocessed) {
285 port->icount.frame++;
286 status = TTY_FRAME;
287 }
288 }
289 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
290 port->icount.overrun++;
291 tty_insert_flip_char(&port->state->port, 0,
292 TTY_OVERRUN);
293 }
294 tty_insert_flip_char(&port->state->port, data, status);
295 isrstatus = 0;
296 }
297 spin_unlock(&port->lock);
298 tty_flip_buffer_push(&port->state->port);
299 spin_lock(&port->lock);
300}
301
302/**
303 * cdns_uart_handle_tx - Handle the bytes to be Txed.
304 * @dev_id: Id of the UART port
305 * Return: None
306 */
307static void cdns_uart_handle_tx(void *dev_id)
308{
309 struct uart_port *port = (struct uart_port *)dev_id;
310 unsigned int numbytes;
311
312 if (uart_circ_empty(&port->state->xmit)) {
313 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
314 } else {
315 numbytes = port->fifosize;
316 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
317 !(readl(port->membase + CDNS_UART_SR) &
318 CDNS_UART_SR_TXFULL)) {
319 /*
320 * Get the data from the UART circular buffer
321 * and write it to the cdns_uart's TX_FIFO
322 * register.
323 */
324 writel(
325 port->state->xmit.buf[port->state->xmit.tail],
326 port->membase + CDNS_UART_FIFO);
327
328 port->icount.tx++;
329
330 /*
331 * Adjust the tail of the UART buffer and wrap
332 * the buffer if it reaches limit.
333 */
334 port->state->xmit.tail =
335 (port->state->xmit.tail + 1) &
336 (UART_XMIT_SIZE - 1);
337
338 numbytes--;
339 }
340
341 if (uart_circ_chars_pending(
342 &port->state->xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(port);
344 }
345}
346
347/**
348 * cdns_uart_isr - Interrupt handler
349 * @irq: Irq number
350 * @dev_id: Id of the port
351 *
352 * Return: IRQHANDLED
353 */
354static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
355{
356 struct uart_port *port = (struct uart_port *)dev_id;
357 unsigned int isrstatus;
358
359 spin_lock(&port->lock);
360
361 /* Read the interrupt status register to determine which
362 * interrupt(s) is/are active and clear them.
363 */
364 isrstatus = readl(port->membase + CDNS_UART_ISR);
365 writel(isrstatus, port->membase + CDNS_UART_ISR);
366
367 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
368 cdns_uart_handle_tx(dev_id);
369 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
370 }
371
372 /*
373 * Skip RX processing if RX is disabled as RXEMPTY will never be set
374 * as read bytes will not be removed from the FIFO.
375 */
376 if (isrstatus & CDNS_UART_IXR_RXMASK &&
377 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
378 cdns_uart_handle_rx(dev_id, isrstatus);
379
380 spin_unlock(&port->lock);
381 return IRQ_HANDLED;
382}
383
384/**
385 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
386 * @clk: UART module input clock
387 * @baud: Desired baud rate
388 * @rbdiv: BDIV value (return value)
389 * @rcd: CD value (return value)
390 * @div8: Value for clk_sel bit in mod (return value)
391 * Return: baud rate, requested baud when possible, or actual baud when there
392 * was too much error, zero if no valid divisors are found.
393 *
394 * Formula to obtain baud rate is
395 * baud_tx/rx rate = clk/CD * (BDIV + 1)
396 * input_clk = (Uart User Defined Clock or Apb Clock)
397 * depends on UCLKEN in MR Reg
398 * clk = input_clk or input_clk/8;
399 * depends on CLKS in MR reg
400 * CD and BDIV depends on values in
401 * baud rate generate register
402 * baud rate clock divisor register
403 */
404static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
405 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
406{
407 u32 cd, bdiv;
408 unsigned int calc_baud;
409 unsigned int bestbaud = 0;
410 unsigned int bauderror;
411 unsigned int besterror = ~0;
412
413 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
414 *div8 = 1;
415 clk /= 8;
416 } else {
417 *div8 = 0;
418 }
419
420 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
421 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
422 if (cd < 1 || cd > CDNS_UART_CD_MAX)
423 continue;
424
425 calc_baud = clk / (cd * (bdiv + 1));
426
427 if (baud > calc_baud)
428 bauderror = baud - calc_baud;
429 else
430 bauderror = calc_baud - baud;
431
432 if (besterror > bauderror) {
433 *rbdiv = bdiv;
434 *rcd = cd;
435 bestbaud = calc_baud;
436 besterror = bauderror;
437 }
438 }
439 /* use the values when percent error is acceptable */
440 if (((besterror * 100) / baud) < 3)
441 bestbaud = baud;
442
443 return bestbaud;
444}
445
446/**
447 * cdns_uart_set_baud_rate - Calculate and set the baud rate
448 * @port: Handle to the uart port structure
449 * @baud: Baud rate to set
450 * Return: baud rate, requested baud when possible, or actual baud when there
451 * was too much error, zero if no valid divisors are found.
452 */
453static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
454 unsigned int baud)
455{
456 unsigned int calc_baud;
457 u32 cd = 0, bdiv = 0;
458 u32 mreg;
459 int div8;
460 struct cdns_uart *cdns_uart = port->private_data;
461
462 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
463 &div8);
464
465 /* Write new divisors to hardware */
466 mreg = readl(port->membase + CDNS_UART_MR);
467 if (div8)
468 mreg |= CDNS_UART_MR_CLKSEL;
469 else
470 mreg &= ~CDNS_UART_MR_CLKSEL;
471 writel(mreg, port->membase + CDNS_UART_MR);
472 writel(cd, port->membase + CDNS_UART_BAUDGEN);
473 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
474 cdns_uart->baud = baud;
475
476 return calc_baud;
477}
478
479#ifdef CONFIG_COMMON_CLK
480/**
481 * cdns_uart_clk_notitifer_cb - Clock notifier callback
482 * @nb: Notifier block
483 * @event: Notify event
484 * @data: Notifier data
485 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
486 */
487static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
488 unsigned long event, void *data)
489{
490 u32 ctrl_reg;
491 struct uart_port *port;
492 int locked = 0;
493 struct clk_notifier_data *ndata = data;
494 unsigned long flags = 0;
495 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
496
497 port = cdns_uart->port;
498 if (port->suspended)
499 return NOTIFY_OK;
500
501 switch (event) {
502 case PRE_RATE_CHANGE:
503 {
504 u32 bdiv, cd;
505 int div8;
506
507 /*
508 * Find out if current baud-rate can be achieved with new clock
509 * frequency.
510 */
511 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
512 &bdiv, &cd, &div8)) {
513 dev_warn(port->dev, "clock rate change rejected\n");
514 return NOTIFY_BAD;
515 }
516
517 spin_lock_irqsave(&cdns_uart->port->lock, flags);
518
519 /* Disable the TX and RX to set baud rate */
520 ctrl_reg = readl(port->membase + CDNS_UART_CR);
521 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
522 writel(ctrl_reg, port->membase + CDNS_UART_CR);
523
524 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
525
526 return NOTIFY_OK;
527 }
528 case POST_RATE_CHANGE:
529 /*
530 * Set clk dividers to generate correct baud with new clock
531 * frequency.
532 */
533
534 spin_lock_irqsave(&cdns_uart->port->lock, flags);
535
536 locked = 1;
537 port->uartclk = ndata->new_rate;
538
539 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
540 cdns_uart->baud);
541 /* fall through */
542 case ABORT_RATE_CHANGE:
543 if (!locked)
544 spin_lock_irqsave(&cdns_uart->port->lock, flags);
545
546 /* Set TX/RX Reset */
547 ctrl_reg = readl(port->membase + CDNS_UART_CR);
548 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
549 writel(ctrl_reg, port->membase + CDNS_UART_CR);
550
551 while (readl(port->membase + CDNS_UART_CR) &
552 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
553 cpu_relax();
554
555 /*
556 * Clear the RX disable and TX disable bits and then set the TX
557 * enable bit and RX enable bit to enable the transmitter and
558 * receiver.
559 */
560 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
561 ctrl_reg = readl(port->membase + CDNS_UART_CR);
562 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
563 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
564 writel(ctrl_reg, port->membase + CDNS_UART_CR);
565
566 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
567
568 return NOTIFY_OK;
569 default:
570 return NOTIFY_DONE;
571 }
572}
573#endif
574
575/**
576 * cdns_uart_start_tx - Start transmitting bytes
577 * @port: Handle to the uart port structure
578 */
579static void cdns_uart_start_tx(struct uart_port *port)
580{
581 unsigned int status;
582
583 if (uart_tx_stopped(port))
584 return;
585
586 /*
587 * Set the TX enable bit and clear the TX disable bit to enable the
588 * transmitter.
589 */
590 status = readl(port->membase + CDNS_UART_CR);
591 status &= ~CDNS_UART_CR_TX_DIS;
592 status |= CDNS_UART_CR_TX_EN;
593 writel(status, port->membase + CDNS_UART_CR);
594
595 if (uart_circ_empty(&port->state->xmit))
596 return;
597
598 cdns_uart_handle_tx(port);
599
600 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
601 /* Enable the TX Empty interrupt */
602 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
603}
604
605/**
606 * cdns_uart_stop_tx - Stop TX
607 * @port: Handle to the uart port structure
608 */
609static void cdns_uart_stop_tx(struct uart_port *port)
610{
611 unsigned int regval;
612
613 regval = readl(port->membase + CDNS_UART_CR);
614 regval |= CDNS_UART_CR_TX_DIS;
615 /* Disable the transmitter */
616 writel(regval, port->membase + CDNS_UART_CR);
617}
618
619/**
620 * cdns_uart_stop_rx - Stop RX
621 * @port: Handle to the uart port structure
622 */
623static void cdns_uart_stop_rx(struct uart_port *port)
624{
625 unsigned int regval;
626
627 /* Disable RX IRQs */
628 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
629
630 /* Disable the receiver */
631 regval = readl(port->membase + CDNS_UART_CR);
632 regval |= CDNS_UART_CR_RX_DIS;
633 writel(regval, port->membase + CDNS_UART_CR);
634}
635
636/**
637 * cdns_uart_tx_empty - Check whether TX is empty
638 * @port: Handle to the uart port structure
639 *
640 * Return: TIOCSER_TEMT on success, 0 otherwise
641 */
642static unsigned int cdns_uart_tx_empty(struct uart_port *port)
643{
644 unsigned int status;
645
646 status = readl(port->membase + CDNS_UART_SR) &
647 CDNS_UART_SR_TXEMPTY;
648 return status ? TIOCSER_TEMT : 0;
649}
650
651/**
652 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
653 * transmitting char breaks
654 * @port: Handle to the uart port structure
655 * @ctl: Value based on which start or stop decision is taken
656 */
657static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
658{
659 unsigned int status;
660 unsigned long flags;
661
662 spin_lock_irqsave(&port->lock, flags);
663
664 status = readl(port->membase + CDNS_UART_CR);
665
666 if (ctl == -1)
667 writel(CDNS_UART_CR_STARTBRK | status,
668 port->membase + CDNS_UART_CR);
669 else {
670 if ((status & CDNS_UART_CR_STOPBRK) == 0)
671 writel(CDNS_UART_CR_STOPBRK | status,
672 port->membase + CDNS_UART_CR);
673 }
674 spin_unlock_irqrestore(&port->lock, flags);
675}
676
677/**
678 * cdns_uart_set_termios - termios operations, handling data length, parity,
679 * stop bits, flow control, baud rate
680 * @port: Handle to the uart port structure
681 * @termios: Handle to the input termios structure
682 * @old: Values of the previously saved termios structure
683 */
684static void cdns_uart_set_termios(struct uart_port *port,
685 struct ktermios *termios, struct ktermios *old)
686{
687 unsigned int cval = 0;
688 unsigned int baud, minbaud, maxbaud;
689 unsigned long flags;
690 unsigned int ctrl_reg, mode_reg, val;
691 int err;
692
693 /* Wait for the transmit FIFO to empty before making changes */
694 if (!(readl(port->membase + CDNS_UART_CR) &
695 CDNS_UART_CR_TX_DIS)) {
696 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
697 val, (val & CDNS_UART_SR_TXEMPTY),
698 1000, TX_TIMEOUT);
699 if (err) {
700 dev_err(port->dev, "timed out waiting for tx empty");
701 return;
702 }
703 }
704 spin_lock_irqsave(&port->lock, flags);
705
706 /* Disable the TX and RX to set baud rate */
707 ctrl_reg = readl(port->membase + CDNS_UART_CR);
708 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
709 writel(ctrl_reg, port->membase + CDNS_UART_CR);
710
711 /*
712 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
713 * min and max baud should be calculated here based on port->uartclk.
714 * this way we get a valid baud and can safely call set_baud()
715 */
716 minbaud = port->uartclk /
717 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
718 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
719 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
720 baud = cdns_uart_set_baud_rate(port, baud);
721 if (tty_termios_baud_rate(termios))
722 tty_termios_encode_baud_rate(termios, baud, baud);
723
724 /* Update the per-port timeout. */
725 uart_update_timeout(port, termios->c_cflag, baud);
726
727 /* Set TX/RX Reset */
728 ctrl_reg = readl(port->membase + CDNS_UART_CR);
729 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
730 writel(ctrl_reg, port->membase + CDNS_UART_CR);
731
732 while (readl(port->membase + CDNS_UART_CR) &
733 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
734 cpu_relax();
735
736 /*
737 * Clear the RX disable and TX disable bits and then set the TX enable
738 * bit and RX enable bit to enable the transmitter and receiver.
739 */
740 ctrl_reg = readl(port->membase + CDNS_UART_CR);
741 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
742 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
743 writel(ctrl_reg, port->membase + CDNS_UART_CR);
744
745 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
746
747 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
748 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
749 port->ignore_status_mask = 0;
750
751 if (termios->c_iflag & INPCK)
752 port->read_status_mask |= CDNS_UART_IXR_PARITY |
753 CDNS_UART_IXR_FRAMING;
754
755 if (termios->c_iflag & IGNPAR)
756 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
757 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
758
759 /* ignore all characters if CREAD is not set */
760 if ((termios->c_cflag & CREAD) == 0)
761 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
762 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
763 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
764
765 mode_reg = readl(port->membase + CDNS_UART_MR);
766
767 /* Handling Data Size */
768 switch (termios->c_cflag & CSIZE) {
769 case CS6:
770 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
771 break;
772 case CS7:
773 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
774 break;
775 default:
776 case CS8:
777 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
778 termios->c_cflag &= ~CSIZE;
779 termios->c_cflag |= CS8;
780 break;
781 }
782
783 /* Handling Parity and Stop Bits length */
784 if (termios->c_cflag & CSTOPB)
785 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
786 else
787 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
788
789 if (termios->c_cflag & PARENB) {
790 /* Mark or Space parity */
791 if (termios->c_cflag & CMSPAR) {
792 if (termios->c_cflag & PARODD)
793 cval |= CDNS_UART_MR_PARITY_MARK;
794 else
795 cval |= CDNS_UART_MR_PARITY_SPACE;
796 } else {
797 if (termios->c_cflag & PARODD)
798 cval |= CDNS_UART_MR_PARITY_ODD;
799 else
800 cval |= CDNS_UART_MR_PARITY_EVEN;
801 }
802 } else {
803 cval |= CDNS_UART_MR_PARITY_NONE;
804 }
805 cval |= mode_reg & 1;
806 writel(cval, port->membase + CDNS_UART_MR);
807
808 spin_unlock_irqrestore(&port->lock, flags);
809}
810
811/**
812 * cdns_uart_startup - Called when an application opens a cdns_uart port
813 * @port: Handle to the uart port structure
814 *
815 * Return: 0 on success, negative errno otherwise
816 */
817static int cdns_uart_startup(struct uart_port *port)
818{
819 struct cdns_uart *cdns_uart = port->private_data;
820 bool is_brk_support;
821 int ret;
822 unsigned long flags;
823 unsigned int status = 0;
824
825 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
826
827 spin_lock_irqsave(&port->lock, flags);
828
829 /* Disable the TX and RX */
830 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
831 port->membase + CDNS_UART_CR);
832
833 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
834 * no break chars.
835 */
836 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
837 port->membase + CDNS_UART_CR);
838
839 while (readl(port->membase + CDNS_UART_CR) &
840 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
841 cpu_relax();
842
843 /*
844 * Clear the RX disable bit and then set the RX enable bit to enable
845 * the receiver.
846 */
847 status = readl(port->membase + CDNS_UART_CR);
848 status &= ~CDNS_UART_CR_RX_DIS;
849 status |= CDNS_UART_CR_RX_EN;
850 writel(status, port->membase + CDNS_UART_CR);
851
852 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
853 * no parity.
854 */
855 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
856 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
857 port->membase + CDNS_UART_MR);
858
859 /*
860 * Set the RX FIFO Trigger level to use most of the FIFO, but it
861 * can be tuned with a module parameter
862 */
863 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
864
865 /*
866 * Receive Timeout register is enabled but it
867 * can be tuned with a module parameter
868 */
869 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
870
871 /* Clear out any pending interrupts before enabling them */
872 writel(readl(port->membase + CDNS_UART_ISR),
873 port->membase + CDNS_UART_ISR);
874
875 spin_unlock_irqrestore(&port->lock, flags);
876
877 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
878 if (ret) {
879 dev_err(port->dev, "request_irq '%d' failed with %d\n",
880 port->irq, ret);
881 return ret;
882 }
883
884 /* Set the Interrupt Registers with desired interrupts */
885 if (is_brk_support)
886 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
887 port->membase + CDNS_UART_IER);
888 else
889 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
890
891 return 0;
892}
893
894/**
895 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
896 * @port: Handle to the uart port structure
897 */
898static void cdns_uart_shutdown(struct uart_port *port)
899{
900 int status;
901 unsigned long flags;
902
903 spin_lock_irqsave(&port->lock, flags);
904
905 /* Disable interrupts */
906 status = readl(port->membase + CDNS_UART_IMR);
907 writel(status, port->membase + CDNS_UART_IDR);
908 writel(0xffffffff, port->membase + CDNS_UART_ISR);
909
910 /* Disable the TX and RX */
911 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
912 port->membase + CDNS_UART_CR);
913
914 spin_unlock_irqrestore(&port->lock, flags);
915
916 free_irq(port->irq, port);
917}
918
919/**
920 * cdns_uart_type - Set UART type to cdns_uart port
921 * @port: Handle to the uart port structure
922 *
923 * Return: string on success, NULL otherwise
924 */
925static const char *cdns_uart_type(struct uart_port *port)
926{
927 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
928}
929
930/**
931 * cdns_uart_verify_port - Verify the port params
932 * @port: Handle to the uart port structure
933 * @ser: Handle to the structure whose members are compared
934 *
935 * Return: 0 on success, negative errno otherwise.
936 */
937static int cdns_uart_verify_port(struct uart_port *port,
938 struct serial_struct *ser)
939{
940 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
941 return -EINVAL;
942 if (port->irq != ser->irq)
943 return -EINVAL;
944 if (ser->io_type != UPIO_MEM)
945 return -EINVAL;
946 if (port->iobase != ser->port)
947 return -EINVAL;
948 if (ser->hub6 != 0)
949 return -EINVAL;
950 return 0;
951}
952
953/**
954 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
955 * called when the driver adds a cdns_uart port via
956 * uart_add_one_port()
957 * @port: Handle to the uart port structure
958 *
959 * Return: 0 on success, negative errno otherwise.
960 */
961static int cdns_uart_request_port(struct uart_port *port)
962{
963 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
964 CDNS_UART_NAME)) {
965 return -ENOMEM;
966 }
967
968 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
969 if (!port->membase) {
970 dev_err(port->dev, "Unable to map registers\n");
971 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
972 return -ENOMEM;
973 }
974 return 0;
975}
976
977/**
978 * cdns_uart_release_port - Release UART port
979 * @port: Handle to the uart port structure
980 *
981 * Release the memory region attached to a cdns_uart port. Called when the
982 * driver removes a cdns_uart port via uart_remove_one_port().
983 */
984static void cdns_uart_release_port(struct uart_port *port)
985{
986 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
987 iounmap(port->membase);
988 port->membase = NULL;
989}
990
991/**
992 * cdns_uart_config_port - Configure UART port
993 * @port: Handle to the uart port structure
994 * @flags: If any
995 */
996static void cdns_uart_config_port(struct uart_port *port, int flags)
997{
998 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
999 port->type = PORT_XUARTPS;
1000}
1001
1002/**
1003 * cdns_uart_get_mctrl - Get the modem control state
1004 * @port: Handle to the uart port structure
1005 *
1006 * Return: the modem control state
1007 */
1008static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1009{
1010 struct cdns_uart *cdns_uart_data = port->private_data;
1011
1012 if (cdns_uart_data->cts_override)
1013 return 0;
1014
1015 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1016}
1017
1018static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1019{
1020 u32 val;
1021 u32 mode_reg;
1022 struct cdns_uart *cdns_uart_data = port->private_data;
1023
1024 if (cdns_uart_data->cts_override)
1025 return;
1026
1027 val = readl(port->membase + CDNS_UART_MODEMCR);
1028 mode_reg = readl(port->membase + CDNS_UART_MR);
1029
1030 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1031 CDNS_UART_MODEMCR_FCM);
1032 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1033
1034 if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1035 val |= CDNS_UART_MODEMCR_FCM;
1036 if (mctrl & TIOCM_LOOP)
1037 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1038 else
1039 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1040
1041 writel(val, port->membase + CDNS_UART_MODEMCR);
1042 writel(mode_reg, port->membase + CDNS_UART_MR);
1043}
1044
1045#ifdef CONFIG_CONSOLE_POLL
1046static int cdns_uart_poll_get_char(struct uart_port *port)
1047{
1048 int c;
1049 unsigned long flags;
1050
1051 spin_lock_irqsave(&port->lock, flags);
1052
1053 /* Check if FIFO is empty */
1054 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1055 c = NO_POLL_CHAR;
1056 else /* Read a character */
1057 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1058
1059 spin_unlock_irqrestore(&port->lock, flags);
1060
1061 return c;
1062}
1063
1064static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1065{
1066 unsigned long flags;
1067
1068 spin_lock_irqsave(&port->lock, flags);
1069
1070 /* Wait until FIFO is empty */
1071 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1072 cpu_relax();
1073
1074 /* Write a character */
1075 writel(c, port->membase + CDNS_UART_FIFO);
1076
1077 /* Wait until FIFO is empty */
1078 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1079 cpu_relax();
1080
1081 spin_unlock_irqrestore(&port->lock, flags);
1082}
1083#endif
1084
1085static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1086 unsigned int oldstate)
1087{
1088 switch (state) {
1089 case UART_PM_STATE_OFF:
1090 pm_runtime_mark_last_busy(port->dev);
1091 pm_runtime_put_autosuspend(port->dev);
1092 break;
1093 default:
1094 pm_runtime_get_sync(port->dev);
1095 break;
1096 }
1097}
1098
1099static const struct uart_ops cdns_uart_ops = {
1100 .set_mctrl = cdns_uart_set_mctrl,
1101 .get_mctrl = cdns_uart_get_mctrl,
1102 .start_tx = cdns_uart_start_tx,
1103 .stop_tx = cdns_uart_stop_tx,
1104 .stop_rx = cdns_uart_stop_rx,
1105 .tx_empty = cdns_uart_tx_empty,
1106 .break_ctl = cdns_uart_break_ctl,
1107 .set_termios = cdns_uart_set_termios,
1108 .startup = cdns_uart_startup,
1109 .shutdown = cdns_uart_shutdown,
1110 .pm = cdns_uart_pm,
1111 .type = cdns_uart_type,
1112 .verify_port = cdns_uart_verify_port,
1113 .request_port = cdns_uart_request_port,
1114 .release_port = cdns_uart_release_port,
1115 .config_port = cdns_uart_config_port,
1116#ifdef CONFIG_CONSOLE_POLL
1117 .poll_get_char = cdns_uart_poll_get_char,
1118 .poll_put_char = cdns_uart_poll_put_char,
1119#endif
1120};
1121
1122#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1123/**
1124 * cdns_uart_console_putchar - write the character to the FIFO buffer
1125 * @port: Handle to the uart port structure
1126 * @ch: Character to be written
1127 */
1128static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1129{
1130 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1131 cpu_relax();
1132 writel(ch, port->membase + CDNS_UART_FIFO);
1133}
1134
1135static void cdns_early_write(struct console *con, const char *s,
1136 unsigned n)
1137{
1138 struct earlycon_device *dev = con->data;
1139
1140 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1141}
1142
1143static int __init cdns_early_console_setup(struct earlycon_device *device,
1144 const char *opt)
1145{
1146 struct uart_port *port = &device->port;
1147
1148 if (!port->membase)
1149 return -ENODEV;
1150
1151 /* initialise control register */
1152 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1153 port->membase + CDNS_UART_CR);
1154
1155 /* only set baud if specified on command line - otherwise
1156 * assume it has been initialized by a boot loader.
1157 */
1158 if (port->uartclk && device->baud) {
1159 u32 cd = 0, bdiv = 0;
1160 u32 mr;
1161 int div8;
1162
1163 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1164 &bdiv, &cd, &div8);
1165 mr = CDNS_UART_MR_PARITY_NONE;
1166 if (div8)
1167 mr |= CDNS_UART_MR_CLKSEL;
1168
1169 writel(mr, port->membase + CDNS_UART_MR);
1170 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1171 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1172 }
1173
1174 device->con->write = cdns_early_write;
1175
1176 return 0;
1177}
1178OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1179OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1180OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1181OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1182
1183
1184/* Static pointer to console port */
1185static struct uart_port *console_port;
1186
1187/**
1188 * cdns_uart_console_write - perform write operation
1189 * @co: Console handle
1190 * @s: Pointer to character array
1191 * @count: No of characters
1192 */
1193static void cdns_uart_console_write(struct console *co, const char *s,
1194 unsigned int count)
1195{
1196 struct uart_port *port = console_port;
1197 unsigned long flags = 0;
1198 unsigned int imr, ctrl;
1199 int locked = 1;
1200
1201 if (port->sysrq)
1202 locked = 0;
1203 else if (oops_in_progress)
1204 locked = spin_trylock_irqsave(&port->lock, flags);
1205 else
1206 spin_lock_irqsave(&port->lock, flags);
1207
1208 /* save and disable interrupt */
1209 imr = readl(port->membase + CDNS_UART_IMR);
1210 writel(imr, port->membase + CDNS_UART_IDR);
1211
1212 /*
1213 * Make sure that the tx part is enabled. Set the TX enable bit and
1214 * clear the TX disable bit to enable the transmitter.
1215 */
1216 ctrl = readl(port->membase + CDNS_UART_CR);
1217 ctrl &= ~CDNS_UART_CR_TX_DIS;
1218 ctrl |= CDNS_UART_CR_TX_EN;
1219 writel(ctrl, port->membase + CDNS_UART_CR);
1220
1221 uart_console_write(port, s, count, cdns_uart_console_putchar);
1222 while ((readl(port->membase + CDNS_UART_SR) &
1223 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1224 CDNS_UART_SR_TXEMPTY)
1225 cpu_relax();
1226
1227 /* restore interrupt state */
1228 writel(imr, port->membase + CDNS_UART_IER);
1229
1230 if (locked)
1231 spin_unlock_irqrestore(&port->lock, flags);
1232}
1233
1234/**
1235 * cdns_uart_console_setup - Initialize the uart to default config
1236 * @co: Console handle
1237 * @options: Initial settings of uart
1238 *
1239 * Return: 0 on success, negative errno otherwise.
1240 */
1241static int cdns_uart_console_setup(struct console *co, char *options)
1242{
1243 struct uart_port *port = console_port;
1244
1245 int baud = 9600;
1246 int bits = 8;
1247 int parity = 'n';
1248 int flow = 'n';
1249
1250 if (!port->membase) {
1251 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1252 co->index);
1253 return -ENODEV;
1254 }
1255
1256 if (options)
1257 uart_parse_options(options, &baud, &parity, &bits, &flow);
1258
1259 return uart_set_options(port, co, baud, parity, bits, flow);
1260}
1261#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1262
1263#ifdef CONFIG_PM_SLEEP
1264/**
1265 * cdns_uart_suspend - suspend event
1266 * @device: Pointer to the device structure
1267 *
1268 * Return: 0
1269 */
1270static int cdns_uart_suspend(struct device *device)
1271{
1272 struct uart_port *port = dev_get_drvdata(device);
1273 struct cdns_uart *cdns_uart = port->private_data;
1274 int may_wake;
1275
1276 may_wake = device_may_wakeup(device);
1277
1278 if (console_suspend_enabled && uart_console(port) && may_wake) {
1279 unsigned long flags = 0;
1280
1281 spin_lock_irqsave(&port->lock, flags);
1282 /* Empty the receive FIFO 1st before making changes */
1283 while (!(readl(port->membase + CDNS_UART_SR) &
1284 CDNS_UART_SR_RXEMPTY))
1285 readl(port->membase + CDNS_UART_FIFO);
1286 /* set RX trigger level to 1 */
1287 writel(1, port->membase + CDNS_UART_RXWM);
1288 /* disable RX timeout interrups */
1289 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1290 spin_unlock_irqrestore(&port->lock, flags);
1291 }
1292
1293 /*
1294 * Call the API provided in serial_core.c file which handles
1295 * the suspend.
1296 */
1297 return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1298}
1299
1300/**
1301 * cdns_uart_resume - Resume after a previous suspend
1302 * @device: Pointer to the device structure
1303 *
1304 * Return: 0
1305 */
1306static int cdns_uart_resume(struct device *device)
1307{
1308 struct uart_port *port = dev_get_drvdata(device);
1309 struct cdns_uart *cdns_uart = port->private_data;
1310 unsigned long flags = 0;
1311 u32 ctrl_reg;
1312 int may_wake;
1313
1314 may_wake = device_may_wakeup(device);
1315
1316 if (console_suspend_enabled && uart_console(port) && !may_wake) {
1317 clk_enable(cdns_uart->pclk);
1318 clk_enable(cdns_uart->uartclk);
1319
1320 spin_lock_irqsave(&port->lock, flags);
1321
1322 /* Set TX/RX Reset */
1323 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1324 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1325 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1326 while (readl(port->membase + CDNS_UART_CR) &
1327 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1328 cpu_relax();
1329
1330 /* restore rx timeout value */
1331 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1332 /* Enable Tx/Rx */
1333 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1334 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1335 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1336 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1337
1338 clk_disable(cdns_uart->uartclk);
1339 clk_disable(cdns_uart->pclk);
1340 spin_unlock_irqrestore(&port->lock, flags);
1341 } else {
1342 spin_lock_irqsave(&port->lock, flags);
1343 /* restore original rx trigger level */
1344 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1345 /* enable RX timeout interrupt */
1346 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1347 spin_unlock_irqrestore(&port->lock, flags);
1348 }
1349
1350 return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1351}
1352#endif /* ! CONFIG_PM_SLEEP */
1353static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1354{
1355 struct uart_port *port = dev_get_drvdata(dev);
1356 struct cdns_uart *cdns_uart = port->private_data;
1357
1358 clk_disable(cdns_uart->uartclk);
1359 clk_disable(cdns_uart->pclk);
1360 return 0;
1361};
1362
1363static int __maybe_unused cdns_runtime_resume(struct device *dev)
1364{
1365 struct uart_port *port = dev_get_drvdata(dev);
1366 struct cdns_uart *cdns_uart = port->private_data;
1367
1368 clk_enable(cdns_uart->pclk);
1369 clk_enable(cdns_uart->uartclk);
1370 return 0;
1371};
1372
1373static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1374 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1375 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1376 cdns_runtime_resume, NULL)
1377};
1378
1379static const struct cdns_platform_data zynqmp_uart_def = {
1380 .quirks = CDNS_UART_RXBS_SUPPORT, };
1381
1382/* Match table for of_platform binding */
1383static const struct of_device_id cdns_uart_of_match[] = {
1384 { .compatible = "xlnx,xuartps", },
1385 { .compatible = "cdns,uart-r1p8", },
1386 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1387 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1388 {}
1389};
1390MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1391
1392/*
1393 * Maximum number of instances without alias IDs but if there is alias
1394 * which target "< MAX_UART_INSTANCES" range this ID can't be used.
1395 */
1396#define MAX_UART_INSTANCES 32
1397
1398/* Stores static aliases list */
1399static DECLARE_BITMAP(alias_bitmap, MAX_UART_INSTANCES);
1400static int alias_bitmap_initialized;
1401
1402/* Stores actual bitmap of allocated IDs with alias IDs together */
1403static DECLARE_BITMAP(bitmap, MAX_UART_INSTANCES);
1404/* Protect bitmap operations to have unique IDs */
1405static DEFINE_MUTEX(bitmap_lock);
1406
1407static int cdns_get_id(struct platform_device *pdev)
1408{
1409 int id, ret;
1410
1411 mutex_lock(&bitmap_lock);
1412
1413 /* Alias list is stable that's why get alias bitmap only once */
1414 if (!alias_bitmap_initialized) {
1415 ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
1416 alias_bitmap, MAX_UART_INSTANCES);
1417 if (ret && ret != -EOVERFLOW) {
1418 mutex_unlock(&bitmap_lock);
1419 return ret;
1420 }
1421
1422 alias_bitmap_initialized++;
1423 }
1424
1425 /* Make sure that alias ID is not taken by instance without alias */
1426 bitmap_or(bitmap, bitmap, alias_bitmap, MAX_UART_INSTANCES);
1427
1428 dev_dbg(&pdev->dev, "Alias bitmap: %*pb\n",
1429 MAX_UART_INSTANCES, bitmap);
1430
1431 /* Look for a serialN alias */
1432 id = of_alias_get_id(pdev->dev.of_node, "serial");
1433 if (id < 0) {
1434 dev_warn(&pdev->dev,
1435 "No serial alias passed. Using the first free id\n");
1436
1437 /*
1438 * Start with id 0 and check if there is no serial0 alias
1439 * which points to device which is compatible with this driver.
1440 * If alias exists then try next free position.
1441 */
1442 id = 0;
1443
1444 for (;;) {
1445 dev_info(&pdev->dev, "Checking id %d\n", id);
1446 id = find_next_zero_bit(bitmap, MAX_UART_INSTANCES, id);
1447
1448 /* No free empty instance */
1449 if (id == MAX_UART_INSTANCES) {
1450 dev_err(&pdev->dev, "No free ID\n");
1451 mutex_unlock(&bitmap_lock);
1452 return -EINVAL;
1453 }
1454
1455 dev_dbg(&pdev->dev, "The empty id is %d\n", id);
1456 /* Check if ID is empty */
1457 if (!test_and_set_bit(id, bitmap)) {
1458 /* Break the loop if bit is taken */
1459 dev_dbg(&pdev->dev,
1460 "Selected ID %d allocation passed\n",
1461 id);
1462 break;
1463 }
1464 dev_dbg(&pdev->dev,
1465 "Selected ID %d allocation failed\n", id);
1466 /* if taking bit fails then try next one */
1467 id++;
1468 }
1469 }
1470
1471 mutex_unlock(&bitmap_lock);
1472
1473 return id;
1474}
1475
1476/**
1477 * cdns_uart_probe - Platform driver probe
1478 * @pdev: Pointer to the platform device structure
1479 *
1480 * Return: 0 on success, negative errno otherwise
1481 */
1482static int cdns_uart_probe(struct platform_device *pdev)
1483{
1484 int rc, irq;
1485 struct uart_port *port;
1486 struct resource *res;
1487 struct cdns_uart *cdns_uart_data;
1488 const struct of_device_id *match;
1489 struct uart_driver *cdns_uart_uart_driver;
1490 char *driver_name;
1491#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1492 struct console *cdns_uart_console;
1493#endif
1494
1495 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1496 GFP_KERNEL);
1497 if (!cdns_uart_data)
1498 return -ENOMEM;
1499 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1500 if (!port)
1501 return -ENOMEM;
1502
1503 cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
1504 sizeof(*cdns_uart_uart_driver),
1505 GFP_KERNEL);
1506 if (!cdns_uart_uart_driver)
1507 return -ENOMEM;
1508
1509 cdns_uart_data->id = cdns_get_id(pdev);
1510 if (cdns_uart_data->id < 0)
1511 return cdns_uart_data->id;
1512
1513 /* There is a need to use unique driver name */
1514 driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1515 CDNS_UART_NAME, cdns_uart_data->id);
1516 if (!driver_name) {
1517 rc = -ENOMEM;
1518 goto err_out_id;
1519 }
1520
1521 cdns_uart_uart_driver->owner = THIS_MODULE;
1522 cdns_uart_uart_driver->driver_name = driver_name;
1523 cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1524 cdns_uart_uart_driver->major = uartps_major;
1525 cdns_uart_uart_driver->minor = cdns_uart_data->id;
1526 cdns_uart_uart_driver->nr = 1;
1527
1528#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1529 cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
1530 GFP_KERNEL);
1531 if (!cdns_uart_console) {
1532 rc = -ENOMEM;
1533 goto err_out_id;
1534 }
1535
1536 strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
1537 sizeof(cdns_uart_console->name));
1538 cdns_uart_console->index = cdns_uart_data->id;
1539 cdns_uart_console->write = cdns_uart_console_write;
1540 cdns_uart_console->device = uart_console_device;
1541 cdns_uart_console->setup = cdns_uart_console_setup;
1542 cdns_uart_console->flags = CON_PRINTBUFFER;
1543 cdns_uart_console->data = cdns_uart_uart_driver;
1544 cdns_uart_uart_driver->cons = cdns_uart_console;
1545#endif
1546
1547 rc = uart_register_driver(cdns_uart_uart_driver);
1548 if (rc < 0) {
1549 dev_err(&pdev->dev, "Failed to register driver\n");
1550 goto err_out_id;
1551 }
1552
1553 cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1554
1555 /*
1556 * Setting up proper name_base needs to be done after uart
1557 * registration because tty_driver structure is not filled.
1558 * name_base is 0 by default.
1559 */
1560 cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1561
1562 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1563 if (match && match->data) {
1564 const struct cdns_platform_data *data = match->data;
1565
1566 cdns_uart_data->quirks = data->quirks;
1567 }
1568
1569 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1570 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1571 rc = PTR_ERR(cdns_uart_data->pclk);
1572 goto err_out_unregister_driver;
1573 }
1574
1575 if (IS_ERR(cdns_uart_data->pclk)) {
1576 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1577 if (IS_ERR(cdns_uart_data->pclk)) {
1578 rc = PTR_ERR(cdns_uart_data->pclk);
1579 goto err_out_unregister_driver;
1580 }
1581 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1582 }
1583
1584 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1585 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1586 rc = PTR_ERR(cdns_uart_data->uartclk);
1587 goto err_out_unregister_driver;
1588 }
1589
1590 if (IS_ERR(cdns_uart_data->uartclk)) {
1591 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1592 if (IS_ERR(cdns_uart_data->uartclk)) {
1593 rc = PTR_ERR(cdns_uart_data->uartclk);
1594 goto err_out_unregister_driver;
1595 }
1596 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1597 }
1598
1599 rc = clk_prepare_enable(cdns_uart_data->pclk);
1600 if (rc) {
1601 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1602 goto err_out_unregister_driver;
1603 }
1604 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1605 if (rc) {
1606 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1607 goto err_out_clk_dis_pclk;
1608 }
1609
1610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1611 if (!res) {
1612 rc = -ENODEV;
1613 goto err_out_clk_disable;
1614 }
1615
1616 irq = platform_get_irq(pdev, 0);
1617 if (irq <= 0) {
1618 rc = -ENXIO;
1619 goto err_out_clk_disable;
1620 }
1621
1622#ifdef CONFIG_COMMON_CLK
1623 cdns_uart_data->clk_rate_change_nb.notifier_call =
1624 cdns_uart_clk_notifier_cb;
1625 if (clk_notifier_register(cdns_uart_data->uartclk,
1626 &cdns_uart_data->clk_rate_change_nb))
1627 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1628#endif
1629
1630 /* At this point, we've got an empty uart_port struct, initialize it */
1631 spin_lock_init(&port->lock);
1632 port->type = PORT_UNKNOWN;
1633 port->iotype = UPIO_MEM32;
1634 port->flags = UPF_BOOT_AUTOCONF;
1635 port->ops = &cdns_uart_ops;
1636 port->fifosize = CDNS_UART_FIFO_SIZE;
1637
1638 /*
1639 * Register the port.
1640 * This function also registers this device with the tty layer
1641 * and triggers invocation of the config_port() entry point.
1642 */
1643 port->mapbase = res->start;
1644 port->irq = irq;
1645 port->dev = &pdev->dev;
1646 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1647 port->private_data = cdns_uart_data;
1648 cdns_uart_data->port = port;
1649 platform_set_drvdata(pdev, port);
1650
1651 pm_runtime_use_autosuspend(&pdev->dev);
1652 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1653 pm_runtime_set_active(&pdev->dev);
1654 pm_runtime_enable(&pdev->dev);
1655 device_init_wakeup(port->dev, true);
1656
1657#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1658 /*
1659 * If console hasn't been found yet try to assign this port
1660 * because it is required to be assigned for console setup function.
1661 * If register_console() don't assign value, then console_port pointer
1662 * is cleanup.
1663 */
1664 if (!console_port)
1665 console_port = port;
1666#endif
1667
1668 rc = uart_add_one_port(cdns_uart_uart_driver, port);
1669 if (rc) {
1670 dev_err(&pdev->dev,
1671 "uart_add_one_port() failed; err=%i\n", rc);
1672 goto err_out_pm_disable;
1673 }
1674
1675#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1676 /* This is not port which is used for console that's why clean it up */
1677 if (console_port == port &&
1678 !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
1679 console_port = NULL;
1680#endif
1681
1682 uartps_major = cdns_uart_uart_driver->tty_driver->major;
1683 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1684 "cts-override");
1685 return 0;
1686
1687err_out_pm_disable:
1688 pm_runtime_disable(&pdev->dev);
1689 pm_runtime_set_suspended(&pdev->dev);
1690 pm_runtime_dont_use_autosuspend(&pdev->dev);
1691#ifdef CONFIG_COMMON_CLK
1692 clk_notifier_unregister(cdns_uart_data->uartclk,
1693 &cdns_uart_data->clk_rate_change_nb);
1694#endif
1695err_out_clk_disable:
1696 clk_disable_unprepare(cdns_uart_data->uartclk);
1697err_out_clk_dis_pclk:
1698 clk_disable_unprepare(cdns_uart_data->pclk);
1699err_out_unregister_driver:
1700 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1701err_out_id:
1702 mutex_lock(&bitmap_lock);
1703 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1704 clear_bit(cdns_uart_data->id, bitmap);
1705 mutex_unlock(&bitmap_lock);
1706 return rc;
1707}
1708
1709/**
1710 * cdns_uart_remove - called when the platform driver is unregistered
1711 * @pdev: Pointer to the platform device structure
1712 *
1713 * Return: 0 on success, negative errno otherwise
1714 */
1715static int cdns_uart_remove(struct platform_device *pdev)
1716{
1717 struct uart_port *port = platform_get_drvdata(pdev);
1718 struct cdns_uart *cdns_uart_data = port->private_data;
1719 int rc;
1720
1721 /* Remove the cdns_uart port from the serial core */
1722#ifdef CONFIG_COMMON_CLK
1723 clk_notifier_unregister(cdns_uart_data->uartclk,
1724 &cdns_uart_data->clk_rate_change_nb);
1725#endif
1726 rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1727 port->mapbase = 0;
1728 mutex_lock(&bitmap_lock);
1729 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1730 clear_bit(cdns_uart_data->id, bitmap);
1731 mutex_unlock(&bitmap_lock);
1732 clk_disable_unprepare(cdns_uart_data->uartclk);
1733 clk_disable_unprepare(cdns_uart_data->pclk);
1734 pm_runtime_disable(&pdev->dev);
1735 pm_runtime_set_suspended(&pdev->dev);
1736 pm_runtime_dont_use_autosuspend(&pdev->dev);
1737 device_init_wakeup(&pdev->dev, false);
1738
1739#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1740 if (console_port == port)
1741 console_port = NULL;
1742#endif
1743
1744 /* If this is last instance major number should be initialized */
1745 mutex_lock(&bitmap_lock);
1746 if (bitmap_empty(bitmap, MAX_UART_INSTANCES))
1747 uartps_major = 0;
1748 mutex_unlock(&bitmap_lock);
1749
1750 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1751 return rc;
1752}
1753
1754static struct platform_driver cdns_uart_platform_driver = {
1755 .probe = cdns_uart_probe,
1756 .remove = cdns_uart_remove,
1757 .driver = {
1758 .name = CDNS_UART_NAME,
1759 .of_match_table = cdns_uart_of_match,
1760 .pm = &cdns_uart_dev_pm_ops,
1761 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1762 },
1763};
1764
1765static int __init cdns_uart_init(void)
1766{
1767 /* Register the platform driver */
1768 return platform_driver_register(&cdns_uart_platform_driver);
1769}
1770
1771static void __exit cdns_uart_exit(void)
1772{
1773 /* Unregister the platform driver */
1774 platform_driver_unregister(&cdns_uart_platform_driver);
1775}
1776
1777arch_initcall(cdns_uart_init);
1778module_exit(cdns_uart_exit);
1779
1780MODULE_DESCRIPTION("Driver for Cadence UART");
1781MODULE_AUTHOR("Xilinx Inc.");
1782MODULE_LICENSE("GPL");
1/*
2 * Xilinx PS UART driver
3 *
4 * 2011 - 2013 (C) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 */
13
14#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15#define SUPPORT_SYSRQ
16#endif
17
18#include <linux/platform_device.h>
19#include <linux/serial.h>
20#include <linux/console.h>
21#include <linux/serial_core.h>
22#include <linux/slab.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/clk.h>
26#include <linux/irq.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/module.h>
30
31#define XUARTPS_TTY_NAME "ttyPS"
32#define XUARTPS_NAME "xuartps"
33#define XUARTPS_MAJOR 0 /* use dynamic node allocation */
34#define XUARTPS_MINOR 0 /* works best with devtmpfs */
35#define XUARTPS_NR_PORTS 2
36#define XUARTPS_FIFO_SIZE 64 /* FIFO size */
37#define XUARTPS_REGISTER_SPACE 0xFFF
38
39#define xuartps_readl(offset) ioread32(port->membase + offset)
40#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
41
42/* Rx Trigger level */
43static int rx_trigger_level = 56;
44module_param(rx_trigger_level, uint, S_IRUGO);
45MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46
47/* Rx Timeout */
48static int rx_timeout = 10;
49module_param(rx_timeout, uint, S_IRUGO);
50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51
52/********************************Register Map********************************/
53/** UART
54 *
55 * Register offsets for the UART.
56 *
57 */
58#define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
59#define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
60#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
61#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
62#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
63#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
64#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
65#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
66#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
67#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
68#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
69#define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
70#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
71#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
72#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
73#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
74 Width [15:0] */
75#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
76 Width [7:0] */
77#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
78
79/** Control Register
80 *
81 * The Control register (CR) controls the major functions of the device.
82 *
83 * Control Register Bit Definitions
84 */
85#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
86#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
87#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
88#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
89#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
90#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
91#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
92#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
93#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
94
95/** Mode Register
96 *
97 * The mode register (MR) defines the mode of transfer as well as the data
98 * format. If this register is modified during transmission or reception,
99 * data validity cannot be guaranteed.
100 *
101 * Mode Register Bit Definitions
102 *
103 */
104#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
105#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
106#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
107
108#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
109#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
110
111#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
112#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
113#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
114#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
115#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
116
117#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
118#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
119#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
120
121/** Interrupt Registers
122 *
123 * Interrupt control logic uses the interrupt enable register (IER) and the
124 * interrupt disable register (IDR) to set the value of the bits in the
125 * interrupt mask register (IMR). The IMR determines whether to pass an
126 * interrupt to the interrupt status register (ISR).
127 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
128 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
129 * Reading either IER or IDR returns 0x00.
130 *
131 * All four registers have the same bit definitions.
132 */
133#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
134#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
135#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
136#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
137#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
138#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
139#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
140#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
141#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
142#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
143#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
144
145/* Goes in read_status_mask for break detection as the HW doesn't do it*/
146#define XUARTPS_IXR_BRK 0x80000000
147
148/** Channel Status Register
149 *
150 * The channel status register (CSR) is provided to enable the control logic
151 * to monitor the status of bits in the channel interrupt status register,
152 * even if these are masked out by the interrupt mask register.
153 */
154#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
155#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
156#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
157#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
158
159/* baud dividers min/max values */
160#define XUARTPS_BDIV_MIN 4
161#define XUARTPS_BDIV_MAX 255
162#define XUARTPS_CD_MAX 65535
163
164/**
165 * struct xuartps - device data
166 * @port Pointer to the UART port
167 * @refclk Reference clock
168 * @aperclk APB clock
169 * @baud Current baud rate
170 * @clk_rate_change_nb Notifier block for clock changes
171 */
172struct xuartps {
173 struct uart_port *port;
174 struct clk *refclk;
175 struct clk *aperclk;
176 unsigned int baud;
177 struct notifier_block clk_rate_change_nb;
178};
179#define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb);
180
181/**
182 * xuartps_isr - Interrupt handler
183 * @irq: Irq number
184 * @dev_id: Id of the port
185 *
186 * Returns IRQHANDLED
187 **/
188static irqreturn_t xuartps_isr(int irq, void *dev_id)
189{
190 struct uart_port *port = (struct uart_port *)dev_id;
191 unsigned long flags;
192 unsigned int isrstatus, numbytes;
193 unsigned int data;
194 char status = TTY_NORMAL;
195
196 spin_lock_irqsave(&port->lock, flags);
197
198 /* Read the interrupt status register to determine which
199 * interrupt(s) is/are active.
200 */
201 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
202
203 /*
204 * There is no hardware break detection, so we interpret framing
205 * error with all-zeros data as a break sequence. Most of the time,
206 * there's another non-zero byte at the end of the sequence.
207 */
208
209 if (isrstatus & XUARTPS_IXR_FRAMING) {
210 while (!(xuartps_readl(XUARTPS_SR_OFFSET) &
211 XUARTPS_SR_RXEMPTY)) {
212 if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) {
213 port->read_status_mask |= XUARTPS_IXR_BRK;
214 isrstatus &= ~XUARTPS_IXR_FRAMING;
215 }
216 }
217 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET);
218 }
219
220 /* drop byte with parity error if IGNPAR specified */
221 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
222 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
223
224 isrstatus &= port->read_status_mask;
225 isrstatus &= ~port->ignore_status_mask;
226
227 if ((isrstatus & XUARTPS_IXR_TOUT) ||
228 (isrstatus & XUARTPS_IXR_RXTRIG)) {
229 /* Receive Timeout Interrupt */
230 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
231 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
232 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
233
234 /* Non-NULL byte after BREAK is garbage (99%) */
235 if (data && (port->read_status_mask &
236 XUARTPS_IXR_BRK)) {
237 port->read_status_mask &= ~XUARTPS_IXR_BRK;
238 port->icount.brk++;
239 if (uart_handle_break(port))
240 continue;
241 }
242
243#ifdef SUPPORT_SYSRQ
244 /*
245 * uart_handle_sysrq_char() doesn't work if
246 * spinlocked, for some reason
247 */
248 if (port->sysrq) {
249 spin_unlock(&port->lock);
250 if (uart_handle_sysrq_char(port,
251 (unsigned char)data)) {
252 spin_lock(&port->lock);
253 continue;
254 }
255 spin_lock(&port->lock);
256 }
257#endif
258
259 port->icount.rx++;
260
261 if (isrstatus & XUARTPS_IXR_PARITY) {
262 port->icount.parity++;
263 status = TTY_PARITY;
264 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
265 port->icount.frame++;
266 status = TTY_FRAME;
267 } else if (isrstatus & XUARTPS_IXR_OVERRUN)
268 port->icount.overrun++;
269
270 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN,
271 data, status);
272 }
273 spin_unlock(&port->lock);
274 tty_flip_buffer_push(&port->state->port);
275 spin_lock(&port->lock);
276 }
277
278 /* Dispatch an appropriate handler */
279 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
280 if (uart_circ_empty(&port->state->xmit)) {
281 xuartps_writel(XUARTPS_IXR_TXEMPTY,
282 XUARTPS_IDR_OFFSET);
283 } else {
284 numbytes = port->fifosize;
285 /* Break if no more data available in the UART buffer */
286 while (numbytes--) {
287 if (uart_circ_empty(&port->state->xmit))
288 break;
289 /* Get the data from the UART circular buffer
290 * and write it to the xuartps's TX_FIFO
291 * register.
292 */
293 xuartps_writel(
294 port->state->xmit.buf[port->state->xmit.
295 tail], XUARTPS_FIFO_OFFSET);
296
297 port->icount.tx++;
298
299 /* Adjust the tail of the UART buffer and wrap
300 * the buffer if it reaches limit.
301 */
302 port->state->xmit.tail =
303 (port->state->xmit.tail + 1) & \
304 (UART_XMIT_SIZE - 1);
305 }
306
307 if (uart_circ_chars_pending(
308 &port->state->xmit) < WAKEUP_CHARS)
309 uart_write_wakeup(port);
310 }
311 }
312
313 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
314
315 /* be sure to release the lock and tty before leaving */
316 spin_unlock_irqrestore(&port->lock, flags);
317
318 return IRQ_HANDLED;
319}
320
321/**
322 * xuartps_calc_baud_divs - Calculate baud rate divisors
323 * @clk: UART module input clock
324 * @baud: Desired baud rate
325 * @rbdiv: BDIV value (return value)
326 * @rcd: CD value (return value)
327 * @div8: Value for clk_sel bit in mod (return value)
328 * Returns baud rate, requested baud when possible, or actual baud when there
329 * was too much error, zero if no valid divisors are found.
330 *
331 * Formula to obtain baud rate is
332 * baud_tx/rx rate = clk/CD * (BDIV + 1)
333 * input_clk = (Uart User Defined Clock or Apb Clock)
334 * depends on UCLKEN in MR Reg
335 * clk = input_clk or input_clk/8;
336 * depends on CLKS in MR reg
337 * CD and BDIV depends on values in
338 * baud rate generate register
339 * baud rate clock divisor register
340 */
341static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
342 u32 *rbdiv, u32 *rcd, int *div8)
343{
344 u32 cd, bdiv;
345 unsigned int calc_baud;
346 unsigned int bestbaud = 0;
347 unsigned int bauderror;
348 unsigned int besterror = ~0;
349
350 if (baud < clk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX)) {
351 *div8 = 1;
352 clk /= 8;
353 } else {
354 *div8 = 0;
355 }
356
357 for (bdiv = XUARTPS_BDIV_MIN; bdiv <= XUARTPS_BDIV_MAX; bdiv++) {
358 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
359 if (cd < 1 || cd > XUARTPS_CD_MAX)
360 continue;
361
362 calc_baud = clk / (cd * (bdiv + 1));
363
364 if (baud > calc_baud)
365 bauderror = baud - calc_baud;
366 else
367 bauderror = calc_baud - baud;
368
369 if (besterror > bauderror) {
370 *rbdiv = bdiv;
371 *rcd = cd;
372 bestbaud = calc_baud;
373 besterror = bauderror;
374 }
375 }
376 /* use the values when percent error is acceptable */
377 if (((besterror * 100) / baud) < 3)
378 bestbaud = baud;
379
380 return bestbaud;
381}
382
383/**
384 * xuartps_set_baud_rate - Calculate and set the baud rate
385 * @port: Handle to the uart port structure
386 * @baud: Baud rate to set
387 * Returns baud rate, requested baud when possible, or actual baud when there
388 * was too much error, zero if no valid divisors are found.
389 */
390static unsigned int xuartps_set_baud_rate(struct uart_port *port,
391 unsigned int baud)
392{
393 unsigned int calc_baud;
394 u32 cd = 0, bdiv = 0;
395 u32 mreg;
396 int div8;
397 struct xuartps *xuartps = port->private_data;
398
399 calc_baud = xuartps_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
400 &div8);
401
402 /* Write new divisors to hardware */
403 mreg = xuartps_readl(XUARTPS_MR_OFFSET);
404 if (div8)
405 mreg |= XUARTPS_MR_CLKSEL;
406 else
407 mreg &= ~XUARTPS_MR_CLKSEL;
408 xuartps_writel(mreg, XUARTPS_MR_OFFSET);
409 xuartps_writel(cd, XUARTPS_BAUDGEN_OFFSET);
410 xuartps_writel(bdiv, XUARTPS_BAUDDIV_OFFSET);
411 xuartps->baud = baud;
412
413 return calc_baud;
414}
415
416#ifdef CONFIG_COMMON_CLK
417/**
418 * xuartps_clk_notitifer_cb - Clock notifier callback
419 * @nb: Notifier block
420 * @event: Notify event
421 * @data: Notifier data
422 * Returns NOTIFY_OK on success, NOTIFY_BAD on error.
423 */
424static int xuartps_clk_notifier_cb(struct notifier_block *nb,
425 unsigned long event, void *data)
426{
427 u32 ctrl_reg;
428 struct uart_port *port;
429 int locked = 0;
430 struct clk_notifier_data *ndata = data;
431 unsigned long flags = 0;
432 struct xuartps *xuartps = to_xuartps(nb);
433
434 port = xuartps->port;
435 if (port->suspended)
436 return NOTIFY_OK;
437
438 switch (event) {
439 case PRE_RATE_CHANGE:
440 {
441 u32 bdiv;
442 u32 cd;
443 int div8;
444
445 /*
446 * Find out if current baud-rate can be achieved with new clock
447 * frequency.
448 */
449 if (!xuartps_calc_baud_divs(ndata->new_rate, xuartps->baud,
450 &bdiv, &cd, &div8))
451 return NOTIFY_BAD;
452
453 spin_lock_irqsave(&xuartps->port->lock, flags);
454
455 /* Disable the TX and RX to set baud rate */
456 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
457 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
458 XUARTPS_CR_OFFSET);
459
460 spin_unlock_irqrestore(&xuartps->port->lock, flags);
461
462 return NOTIFY_OK;
463 }
464 case POST_RATE_CHANGE:
465 /*
466 * Set clk dividers to generate correct baud with new clock
467 * frequency.
468 */
469
470 spin_lock_irqsave(&xuartps->port->lock, flags);
471
472 locked = 1;
473 port->uartclk = ndata->new_rate;
474
475 xuartps->baud = xuartps_set_baud_rate(xuartps->port,
476 xuartps->baud);
477 /* fall through */
478 case ABORT_RATE_CHANGE:
479 if (!locked)
480 spin_lock_irqsave(&xuartps->port->lock, flags);
481
482 /* Set TX/RX Reset */
483 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
484 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
485 XUARTPS_CR_OFFSET);
486
487 while (xuartps_readl(XUARTPS_CR_OFFSET) &
488 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
489 cpu_relax();
490
491 /*
492 * Clear the RX disable and TX disable bits and then set the TX
493 * enable bit and RX enable bit to enable the transmitter and
494 * receiver.
495 */
496 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
497 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
498 xuartps_writel(
499 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
500 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
501 XUARTPS_CR_OFFSET);
502
503 spin_unlock_irqrestore(&xuartps->port->lock, flags);
504
505 return NOTIFY_OK;
506 default:
507 return NOTIFY_DONE;
508 }
509}
510#endif
511
512/*----------------------Uart Operations---------------------------*/
513
514/**
515 * xuartps_start_tx - Start transmitting bytes
516 * @port: Handle to the uart port structure
517 *
518 **/
519static void xuartps_start_tx(struct uart_port *port)
520{
521 unsigned int status, numbytes = port->fifosize;
522
523 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
524 return;
525
526 status = xuartps_readl(XUARTPS_CR_OFFSET);
527 /* Set the TX enable bit and clear the TX disable bit to enable the
528 * transmitter.
529 */
530 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
531 XUARTPS_CR_OFFSET);
532
533 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
534 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
535
536 /* Break if no more data available in the UART buffer */
537 if (uart_circ_empty(&port->state->xmit))
538 break;
539
540 /* Get the data from the UART circular buffer and
541 * write it to the xuartps's TX_FIFO register.
542 */
543 xuartps_writel(
544 port->state->xmit.buf[port->state->xmit.tail],
545 XUARTPS_FIFO_OFFSET);
546 port->icount.tx++;
547
548 /* Adjust the tail of the UART buffer and wrap
549 * the buffer if it reaches limit.
550 */
551 port->state->xmit.tail = (port->state->xmit.tail + 1) &
552 (UART_XMIT_SIZE - 1);
553 }
554 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET);
555 /* Enable the TX Empty interrupt */
556 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
557
558 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
559 uart_write_wakeup(port);
560}
561
562/**
563 * xuartps_stop_tx - Stop TX
564 * @port: Handle to the uart port structure
565 *
566 **/
567static void xuartps_stop_tx(struct uart_port *port)
568{
569 unsigned int regval;
570
571 regval = xuartps_readl(XUARTPS_CR_OFFSET);
572 regval |= XUARTPS_CR_TX_DIS;
573 /* Disable the transmitter */
574 xuartps_writel(regval, XUARTPS_CR_OFFSET);
575}
576
577/**
578 * xuartps_stop_rx - Stop RX
579 * @port: Handle to the uart port structure
580 *
581 **/
582static void xuartps_stop_rx(struct uart_port *port)
583{
584 unsigned int regval;
585
586 regval = xuartps_readl(XUARTPS_CR_OFFSET);
587 regval |= XUARTPS_CR_RX_DIS;
588 /* Disable the receiver */
589 xuartps_writel(regval, XUARTPS_CR_OFFSET);
590}
591
592/**
593 * xuartps_tx_empty - Check whether TX is empty
594 * @port: Handle to the uart port structure
595 *
596 * Returns TIOCSER_TEMT on success, 0 otherwise
597 **/
598static unsigned int xuartps_tx_empty(struct uart_port *port)
599{
600 unsigned int status;
601
602 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
603 return status ? TIOCSER_TEMT : 0;
604}
605
606/**
607 * xuartps_break_ctl - Based on the input ctl we have to start or stop
608 * transmitting char breaks
609 * @port: Handle to the uart port structure
610 * @ctl: Value based on which start or stop decision is taken
611 *
612 **/
613static void xuartps_break_ctl(struct uart_port *port, int ctl)
614{
615 unsigned int status;
616 unsigned long flags;
617
618 spin_lock_irqsave(&port->lock, flags);
619
620 status = xuartps_readl(XUARTPS_CR_OFFSET);
621
622 if (ctl == -1)
623 xuartps_writel(XUARTPS_CR_STARTBRK | status,
624 XUARTPS_CR_OFFSET);
625 else {
626 if ((status & XUARTPS_CR_STOPBRK) == 0)
627 xuartps_writel(XUARTPS_CR_STOPBRK | status,
628 XUARTPS_CR_OFFSET);
629 }
630 spin_unlock_irqrestore(&port->lock, flags);
631}
632
633/**
634 * xuartps_set_termios - termios operations, handling data length, parity,
635 * stop bits, flow control, baud rate
636 * @port: Handle to the uart port structure
637 * @termios: Handle to the input termios structure
638 * @old: Values of the previously saved termios structure
639 *
640 **/
641static void xuartps_set_termios(struct uart_port *port,
642 struct ktermios *termios, struct ktermios *old)
643{
644 unsigned int cval = 0;
645 unsigned int baud, minbaud, maxbaud;
646 unsigned long flags;
647 unsigned int ctrl_reg, mode_reg;
648
649 spin_lock_irqsave(&port->lock, flags);
650
651 /* Empty the receive FIFO 1st before making changes */
652 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
653 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
654 xuartps_readl(XUARTPS_FIFO_OFFSET);
655 }
656
657 /* Disable the TX and RX to set baud rate */
658 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
659 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
660 XUARTPS_CR_OFFSET);
661
662 /*
663 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
664 * min and max baud should be calculated here based on port->uartclk.
665 * this way we get a valid baud and can safely call set_baud()
666 */
667 minbaud = port->uartclk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX * 8);
668 maxbaud = port->uartclk / (XUARTPS_BDIV_MIN + 1);
669 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
670 baud = xuartps_set_baud_rate(port, baud);
671 if (tty_termios_baud_rate(termios))
672 tty_termios_encode_baud_rate(termios, baud, baud);
673
674 /*
675 * Update the per-port timeout.
676 */
677 uart_update_timeout(port, termios->c_cflag, baud);
678
679 /* Set TX/RX Reset */
680 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
681 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
682 XUARTPS_CR_OFFSET);
683
684 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
685
686 /* Clear the RX disable and TX disable bits and then set the TX enable
687 * bit and RX enable bit to enable the transmitter and receiver.
688 */
689 xuartps_writel(
690 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
691 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
692 XUARTPS_CR_OFFSET);
693
694 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
695
696 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
697 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
698 port->ignore_status_mask = 0;
699
700 if (termios->c_iflag & INPCK)
701 port->read_status_mask |= XUARTPS_IXR_PARITY |
702 XUARTPS_IXR_FRAMING;
703
704 if (termios->c_iflag & IGNPAR)
705 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
706 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
707
708 /* ignore all characters if CREAD is not set */
709 if ((termios->c_cflag & CREAD) == 0)
710 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
711 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
712 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
713
714 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
715
716 /* Handling Data Size */
717 switch (termios->c_cflag & CSIZE) {
718 case CS6:
719 cval |= XUARTPS_MR_CHARLEN_6_BIT;
720 break;
721 case CS7:
722 cval |= XUARTPS_MR_CHARLEN_7_BIT;
723 break;
724 default:
725 case CS8:
726 cval |= XUARTPS_MR_CHARLEN_8_BIT;
727 termios->c_cflag &= ~CSIZE;
728 termios->c_cflag |= CS8;
729 break;
730 }
731
732 /* Handling Parity and Stop Bits length */
733 if (termios->c_cflag & CSTOPB)
734 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
735 else
736 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
737
738 if (termios->c_cflag & PARENB) {
739 /* Mark or Space parity */
740 if (termios->c_cflag & CMSPAR) {
741 if (termios->c_cflag & PARODD)
742 cval |= XUARTPS_MR_PARITY_MARK;
743 else
744 cval |= XUARTPS_MR_PARITY_SPACE;
745 } else {
746 if (termios->c_cflag & PARODD)
747 cval |= XUARTPS_MR_PARITY_ODD;
748 else
749 cval |= XUARTPS_MR_PARITY_EVEN;
750 }
751 } else {
752 cval |= XUARTPS_MR_PARITY_NONE;
753 }
754 cval |= mode_reg & 1;
755 xuartps_writel(cval, XUARTPS_MR_OFFSET);
756
757 spin_unlock_irqrestore(&port->lock, flags);
758}
759
760/**
761 * xuartps_startup - Called when an application opens a xuartps port
762 * @port: Handle to the uart port structure
763 *
764 * Returns 0 on success, negative error otherwise
765 **/
766static int xuartps_startup(struct uart_port *port)
767{
768 unsigned int retval = 0, status = 0;
769
770 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
771 (void *)port);
772 if (retval)
773 return retval;
774
775 /* Disable the TX and RX */
776 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
777 XUARTPS_CR_OFFSET);
778
779 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
780 * no break chars.
781 */
782 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
783 XUARTPS_CR_OFFSET);
784
785 status = xuartps_readl(XUARTPS_CR_OFFSET);
786
787 /* Clear the RX disable and TX disable bits and then set the TX enable
788 * bit and RX enable bit to enable the transmitter and receiver.
789 */
790 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
791 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
792 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
793
794 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
795 * no parity.
796 */
797 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
798 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
799 XUARTPS_MR_OFFSET);
800
801 /*
802 * Set the RX FIFO Trigger level to use most of the FIFO, but it
803 * can be tuned with a module parameter
804 */
805 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
806
807 /*
808 * Receive Timeout register is enabled but it
809 * can be tuned with a module parameter
810 */
811 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
812
813 /* Clear out any pending interrupts before enabling them */
814 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET);
815
816 /* Set the Interrupt Registers with desired interrupts */
817 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
818 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
819 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
820
821 return retval;
822}
823
824/**
825 * xuartps_shutdown - Called when an application closes a xuartps port
826 * @port: Handle to the uart port structure
827 *
828 **/
829static void xuartps_shutdown(struct uart_port *port)
830{
831 int status;
832
833 /* Disable interrupts */
834 status = xuartps_readl(XUARTPS_IMR_OFFSET);
835 xuartps_writel(status, XUARTPS_IDR_OFFSET);
836
837 /* Disable the TX and RX */
838 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
839 XUARTPS_CR_OFFSET);
840 free_irq(port->irq, port);
841}
842
843/**
844 * xuartps_type - Set UART type to xuartps port
845 * @port: Handle to the uart port structure
846 *
847 * Returns string on success, NULL otherwise
848 **/
849static const char *xuartps_type(struct uart_port *port)
850{
851 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
852}
853
854/**
855 * xuartps_verify_port - Verify the port params
856 * @port: Handle to the uart port structure
857 * @ser: Handle to the structure whose members are compared
858 *
859 * Returns 0 if success otherwise -EINVAL
860 **/
861static int xuartps_verify_port(struct uart_port *port,
862 struct serial_struct *ser)
863{
864 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
865 return -EINVAL;
866 if (port->irq != ser->irq)
867 return -EINVAL;
868 if (ser->io_type != UPIO_MEM)
869 return -EINVAL;
870 if (port->iobase != ser->port)
871 return -EINVAL;
872 if (ser->hub6 != 0)
873 return -EINVAL;
874 return 0;
875}
876
877/**
878 * xuartps_request_port - Claim the memory region attached to xuartps port,
879 * called when the driver adds a xuartps port via
880 * uart_add_one_port()
881 * @port: Handle to the uart port structure
882 *
883 * Returns 0, -ENOMEM if request fails
884 **/
885static int xuartps_request_port(struct uart_port *port)
886{
887 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
888 XUARTPS_NAME)) {
889 return -ENOMEM;
890 }
891
892 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
893 if (!port->membase) {
894 dev_err(port->dev, "Unable to map registers\n");
895 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
896 return -ENOMEM;
897 }
898 return 0;
899}
900
901/**
902 * xuartps_release_port - Release the memory region attached to a xuartps
903 * port, called when the driver removes a xuartps
904 * port via uart_remove_one_port().
905 * @port: Handle to the uart port structure
906 *
907 **/
908static void xuartps_release_port(struct uart_port *port)
909{
910 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
911 iounmap(port->membase);
912 port->membase = NULL;
913}
914
915/**
916 * xuartps_config_port - Configure xuartps, called when the driver adds a
917 * xuartps port
918 * @port: Handle to the uart port structure
919 * @flags: If any
920 *
921 **/
922static void xuartps_config_port(struct uart_port *port, int flags)
923{
924 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
925 port->type = PORT_XUARTPS;
926}
927
928/**
929 * xuartps_get_mctrl - Get the modem control state
930 *
931 * @port: Handle to the uart port structure
932 *
933 * Returns the modem control state
934 *
935 **/
936static unsigned int xuartps_get_mctrl(struct uart_port *port)
937{
938 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
939}
940
941static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
942{
943 /* N/A */
944}
945
946static void xuartps_enable_ms(struct uart_port *port)
947{
948 /* N/A */
949}
950
951#ifdef CONFIG_CONSOLE_POLL
952static int xuartps_poll_get_char(struct uart_port *port)
953{
954 u32 imr;
955 int c;
956
957 /* Disable all interrupts */
958 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
959 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
960
961 /* Check if FIFO is empty */
962 if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)
963 c = NO_POLL_CHAR;
964 else /* Read a character */
965 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET);
966
967 /* Enable interrupts */
968 xuartps_writel(imr, XUARTPS_IER_OFFSET);
969
970 return c;
971}
972
973static void xuartps_poll_put_char(struct uart_port *port, unsigned char c)
974{
975 u32 imr;
976
977 /* Disable all interrupts */
978 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
979 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
980
981 /* Wait until FIFO is empty */
982 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
983 cpu_relax();
984
985 /* Write a character */
986 xuartps_writel(c, XUARTPS_FIFO_OFFSET);
987
988 /* Wait until FIFO is empty */
989 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
990 cpu_relax();
991
992 /* Enable interrupts */
993 xuartps_writel(imr, XUARTPS_IER_OFFSET);
994
995 return;
996}
997#endif
998
999/** The UART operations structure
1000 */
1001static struct uart_ops xuartps_ops = {
1002 .set_mctrl = xuartps_set_mctrl,
1003 .get_mctrl = xuartps_get_mctrl,
1004 .enable_ms = xuartps_enable_ms,
1005
1006 .start_tx = xuartps_start_tx, /* Start transmitting */
1007 .stop_tx = xuartps_stop_tx, /* Stop transmission */
1008 .stop_rx = xuartps_stop_rx, /* Stop reception */
1009 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */
1010 .break_ctl = xuartps_break_ctl, /* Start/stop
1011 * transmitting break
1012 */
1013 .set_termios = xuartps_set_termios, /* Set termios */
1014 .startup = xuartps_startup, /* App opens xuartps */
1015 .shutdown = xuartps_shutdown, /* App closes xuartps */
1016 .type = xuartps_type, /* Set UART type */
1017 .verify_port = xuartps_verify_port, /* Verification of port
1018 * params
1019 */
1020 .request_port = xuartps_request_port, /* Claim resources
1021 * associated with a
1022 * xuartps port
1023 */
1024 .release_port = xuartps_release_port, /* Release resources
1025 * associated with a
1026 * xuartps port
1027 */
1028 .config_port = xuartps_config_port, /* Configure when driver
1029 * adds a xuartps port
1030 */
1031#ifdef CONFIG_CONSOLE_POLL
1032 .poll_get_char = xuartps_poll_get_char,
1033 .poll_put_char = xuartps_poll_put_char,
1034#endif
1035};
1036
1037static struct uart_port xuartps_port[2];
1038
1039/**
1040 * xuartps_get_port - Configure the port from the platform device resource
1041 * info
1042 *
1043 * Returns a pointer to a uart_port or NULL for failure
1044 **/
1045static struct uart_port *xuartps_get_port(void)
1046{
1047 struct uart_port *port;
1048 int id;
1049
1050 /* Find the next unused port */
1051 for (id = 0; id < XUARTPS_NR_PORTS; id++)
1052 if (xuartps_port[id].mapbase == 0)
1053 break;
1054
1055 if (id >= XUARTPS_NR_PORTS)
1056 return NULL;
1057
1058 port = &xuartps_port[id];
1059
1060 /* At this point, we've got an empty uart_port struct, initialize it */
1061 spin_lock_init(&port->lock);
1062 port->membase = NULL;
1063 port->iobase = 1; /* mark port in use */
1064 port->irq = 0;
1065 port->type = PORT_UNKNOWN;
1066 port->iotype = UPIO_MEM32;
1067 port->flags = UPF_BOOT_AUTOCONF;
1068 port->ops = &xuartps_ops;
1069 port->fifosize = XUARTPS_FIFO_SIZE;
1070 port->line = id;
1071 port->dev = NULL;
1072 return port;
1073}
1074
1075/*-----------------------Console driver operations--------------------------*/
1076
1077#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1078/**
1079 * xuartps_console_wait_tx - Wait for the TX to be full
1080 * @port: Handle to the uart port structure
1081 *
1082 **/
1083static void xuartps_console_wait_tx(struct uart_port *port)
1084{
1085 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
1086 != XUARTPS_SR_TXEMPTY)
1087 barrier();
1088}
1089
1090/**
1091 * xuartps_console_putchar - write the character to the FIFO buffer
1092 * @port: Handle to the uart port structure
1093 * @ch: Character to be written
1094 *
1095 **/
1096static void xuartps_console_putchar(struct uart_port *port, int ch)
1097{
1098 xuartps_console_wait_tx(port);
1099 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
1100}
1101
1102/**
1103 * xuartps_console_write - perform write operation
1104 * @port: Handle to the uart port structure
1105 * @s: Pointer to character array
1106 * @count: No of characters
1107 **/
1108static void xuartps_console_write(struct console *co, const char *s,
1109 unsigned int count)
1110{
1111 struct uart_port *port = &xuartps_port[co->index];
1112 unsigned long flags;
1113 unsigned int imr, ctrl;
1114 int locked = 1;
1115
1116 if (oops_in_progress)
1117 locked = spin_trylock_irqsave(&port->lock, flags);
1118 else
1119 spin_lock_irqsave(&port->lock, flags);
1120
1121 /* save and disable interrupt */
1122 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
1123 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
1124
1125 /*
1126 * Make sure that the tx part is enabled. Set the TX enable bit and
1127 * clear the TX disable bit to enable the transmitter.
1128 */
1129 ctrl = xuartps_readl(XUARTPS_CR_OFFSET);
1130 xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
1131 XUARTPS_CR_OFFSET);
1132
1133 uart_console_write(port, s, count, xuartps_console_putchar);
1134 xuartps_console_wait_tx(port);
1135
1136 xuartps_writel(ctrl, XUARTPS_CR_OFFSET);
1137
1138 /* restore interrupt state, it seems like there may be a h/w bug
1139 * in that the interrupt enable register should not need to be
1140 * written based on the data sheet
1141 */
1142 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
1143 xuartps_writel(imr, XUARTPS_IER_OFFSET);
1144
1145 if (locked)
1146 spin_unlock_irqrestore(&port->lock, flags);
1147}
1148
1149/**
1150 * xuartps_console_setup - Initialize the uart to default config
1151 * @co: Console handle
1152 * @options: Initial settings of uart
1153 *
1154 * Returns 0, -ENODEV if no device
1155 **/
1156static int __init xuartps_console_setup(struct console *co, char *options)
1157{
1158 struct uart_port *port = &xuartps_port[co->index];
1159 int baud = 9600;
1160 int bits = 8;
1161 int parity = 'n';
1162 int flow = 'n';
1163
1164 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
1165 return -EINVAL;
1166
1167 if (!port->mapbase) {
1168 pr_debug("console on ttyPS%i not present\n", co->index);
1169 return -ENODEV;
1170 }
1171
1172 if (options)
1173 uart_parse_options(options, &baud, &parity, &bits, &flow);
1174
1175 return uart_set_options(port, co, baud, parity, bits, flow);
1176}
1177
1178static struct uart_driver xuartps_uart_driver;
1179
1180static struct console xuartps_console = {
1181 .name = XUARTPS_TTY_NAME,
1182 .write = xuartps_console_write,
1183 .device = uart_console_device,
1184 .setup = xuartps_console_setup,
1185 .flags = CON_PRINTBUFFER,
1186 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1187 .data = &xuartps_uart_driver,
1188};
1189
1190/**
1191 * xuartps_console_init - Initialization call
1192 *
1193 * Returns 0 on success, negative error otherwise
1194 **/
1195static int __init xuartps_console_init(void)
1196{
1197 register_console(&xuartps_console);
1198 return 0;
1199}
1200
1201console_initcall(xuartps_console_init);
1202
1203#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1204
1205/** Structure Definitions
1206 */
1207static struct uart_driver xuartps_uart_driver = {
1208 .owner = THIS_MODULE, /* Owner */
1209 .driver_name = XUARTPS_NAME, /* Driver name */
1210 .dev_name = XUARTPS_TTY_NAME, /* Node name */
1211 .major = XUARTPS_MAJOR, /* Major number */
1212 .minor = XUARTPS_MINOR, /* Minor number */
1213 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
1214#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1215 .cons = &xuartps_console, /* Console */
1216#endif
1217};
1218
1219#ifdef CONFIG_PM_SLEEP
1220/**
1221 * xuartps_suspend - suspend event
1222 * @device: Pointer to the device structure
1223 *
1224 * Returns 0
1225 */
1226static int xuartps_suspend(struct device *device)
1227{
1228 struct uart_port *port = dev_get_drvdata(device);
1229 struct tty_struct *tty;
1230 struct device *tty_dev;
1231 int may_wake = 0;
1232
1233 /* Get the tty which could be NULL so don't assume it's valid */
1234 tty = tty_port_tty_get(&port->state->port);
1235 if (tty) {
1236 tty_dev = tty->dev;
1237 may_wake = device_may_wakeup(tty_dev);
1238 tty_kref_put(tty);
1239 }
1240
1241 /*
1242 * Call the API provided in serial_core.c file which handles
1243 * the suspend.
1244 */
1245 uart_suspend_port(&xuartps_uart_driver, port);
1246 if (console_suspend_enabled && !may_wake) {
1247 struct xuartps *xuartps = port->private_data;
1248
1249 clk_disable(xuartps->refclk);
1250 clk_disable(xuartps->aperclk);
1251 } else {
1252 unsigned long flags = 0;
1253
1254 spin_lock_irqsave(&port->lock, flags);
1255 /* Empty the receive FIFO 1st before making changes */
1256 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY))
1257 xuartps_readl(XUARTPS_FIFO_OFFSET);
1258 /* set RX trigger level to 1 */
1259 xuartps_writel(1, XUARTPS_RXWM_OFFSET);
1260 /* disable RX timeout interrups */
1261 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IDR_OFFSET);
1262 spin_unlock_irqrestore(&port->lock, flags);
1263 }
1264
1265 return 0;
1266}
1267
1268/**
1269 * xuartps_resume - Resume after a previous suspend
1270 * @device: Pointer to the device structure
1271 *
1272 * Returns 0
1273 */
1274static int xuartps_resume(struct device *device)
1275{
1276 struct uart_port *port = dev_get_drvdata(device);
1277 unsigned long flags = 0;
1278 u32 ctrl_reg;
1279 struct tty_struct *tty;
1280 struct device *tty_dev;
1281 int may_wake = 0;
1282
1283 /* Get the tty which could be NULL so don't assume it's valid */
1284 tty = tty_port_tty_get(&port->state->port);
1285 if (tty) {
1286 tty_dev = tty->dev;
1287 may_wake = device_may_wakeup(tty_dev);
1288 tty_kref_put(tty);
1289 }
1290
1291 if (console_suspend_enabled && !may_wake) {
1292 struct xuartps *xuartps = port->private_data;
1293
1294 clk_enable(xuartps->aperclk);
1295 clk_enable(xuartps->refclk);
1296
1297 spin_lock_irqsave(&port->lock, flags);
1298
1299 /* Set TX/RX Reset */
1300 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
1301 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
1302 XUARTPS_CR_OFFSET);
1303 while (xuartps_readl(XUARTPS_CR_OFFSET) &
1304 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
1305 cpu_relax();
1306
1307 /* restore rx timeout value */
1308 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
1309 /* Enable Tx/Rx */
1310 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
1311 xuartps_writel(
1312 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
1313 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
1314 XUARTPS_CR_OFFSET);
1315
1316 spin_unlock_irqrestore(&port->lock, flags);
1317 } else {
1318 spin_lock_irqsave(&port->lock, flags);
1319 /* restore original rx trigger level */
1320 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
1321 /* enable RX timeout interrupt */
1322 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
1323 spin_unlock_irqrestore(&port->lock, flags);
1324 }
1325
1326 return uart_resume_port(&xuartps_uart_driver, port);
1327}
1328#endif /* ! CONFIG_PM_SLEEP */
1329
1330static SIMPLE_DEV_PM_OPS(xuartps_dev_pm_ops, xuartps_suspend, xuartps_resume);
1331
1332/* ---------------------------------------------------------------------
1333 * Platform bus binding
1334 */
1335/**
1336 * xuartps_probe - Platform driver probe
1337 * @pdev: Pointer to the platform device structure
1338 *
1339 * Returns 0 on success, negative error otherwise
1340 **/
1341static int xuartps_probe(struct platform_device *pdev)
1342{
1343 int rc;
1344 struct uart_port *port;
1345 struct resource *res, *res2;
1346 struct xuartps *xuartps_data;
1347
1348 xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data),
1349 GFP_KERNEL);
1350 if (!xuartps_data)
1351 return -ENOMEM;
1352
1353 xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk");
1354 if (IS_ERR(xuartps_data->aperclk)) {
1355 dev_err(&pdev->dev, "aper_clk clock not found.\n");
1356 return PTR_ERR(xuartps_data->aperclk);
1357 }
1358 xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1359 if (IS_ERR(xuartps_data->refclk)) {
1360 dev_err(&pdev->dev, "ref_clk clock not found.\n");
1361 return PTR_ERR(xuartps_data->refclk);
1362 }
1363
1364 rc = clk_prepare_enable(xuartps_data->aperclk);
1365 if (rc) {
1366 dev_err(&pdev->dev, "Unable to enable APER clock.\n");
1367 return rc;
1368 }
1369 rc = clk_prepare_enable(xuartps_data->refclk);
1370 if (rc) {
1371 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1372 goto err_out_clk_dis_aper;
1373 }
1374
1375 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1376 if (!res) {
1377 rc = -ENODEV;
1378 goto err_out_clk_disable;
1379 }
1380
1381 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1382 if (!res2) {
1383 rc = -ENODEV;
1384 goto err_out_clk_disable;
1385 }
1386
1387#ifdef CONFIG_COMMON_CLK
1388 xuartps_data->clk_rate_change_nb.notifier_call =
1389 xuartps_clk_notifier_cb;
1390 if (clk_notifier_register(xuartps_data->refclk,
1391 &xuartps_data->clk_rate_change_nb))
1392 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1393#endif
1394
1395 /* Initialize the port structure */
1396 port = xuartps_get_port();
1397
1398 if (!port) {
1399 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1400 rc = -ENODEV;
1401 goto err_out_notif_unreg;
1402 } else {
1403 /* Register the port.
1404 * This function also registers this device with the tty layer
1405 * and triggers invocation of the config_port() entry point.
1406 */
1407 port->mapbase = res->start;
1408 port->irq = res2->start;
1409 port->dev = &pdev->dev;
1410 port->uartclk = clk_get_rate(xuartps_data->refclk);
1411 port->private_data = xuartps_data;
1412 xuartps_data->port = port;
1413 platform_set_drvdata(pdev, port);
1414 rc = uart_add_one_port(&xuartps_uart_driver, port);
1415 if (rc) {
1416 dev_err(&pdev->dev,
1417 "uart_add_one_port() failed; err=%i\n", rc);
1418 goto err_out_notif_unreg;
1419 }
1420 return 0;
1421 }
1422
1423err_out_notif_unreg:
1424#ifdef CONFIG_COMMON_CLK
1425 clk_notifier_unregister(xuartps_data->refclk,
1426 &xuartps_data->clk_rate_change_nb);
1427#endif
1428err_out_clk_disable:
1429 clk_disable_unprepare(xuartps_data->refclk);
1430err_out_clk_dis_aper:
1431 clk_disable_unprepare(xuartps_data->aperclk);
1432
1433 return rc;
1434}
1435
1436/**
1437 * xuartps_remove - called when the platform driver is unregistered
1438 * @pdev: Pointer to the platform device structure
1439 *
1440 * Returns 0 on success, negative error otherwise
1441 **/
1442static int xuartps_remove(struct platform_device *pdev)
1443{
1444 struct uart_port *port = platform_get_drvdata(pdev);
1445 struct xuartps *xuartps_data = port->private_data;
1446 int rc;
1447
1448 /* Remove the xuartps port from the serial core */
1449#ifdef CONFIG_COMMON_CLK
1450 clk_notifier_unregister(xuartps_data->refclk,
1451 &xuartps_data->clk_rate_change_nb);
1452#endif
1453 rc = uart_remove_one_port(&xuartps_uart_driver, port);
1454 port->mapbase = 0;
1455 clk_disable_unprepare(xuartps_data->refclk);
1456 clk_disable_unprepare(xuartps_data->aperclk);
1457 return rc;
1458}
1459
1460/* Match table for of_platform binding */
1461static struct of_device_id xuartps_of_match[] = {
1462 { .compatible = "xlnx,xuartps", },
1463 {}
1464};
1465MODULE_DEVICE_TABLE(of, xuartps_of_match);
1466
1467static struct platform_driver xuartps_platform_driver = {
1468 .probe = xuartps_probe, /* Probe method */
1469 .remove = xuartps_remove, /* Detach method */
1470 .driver = {
1471 .owner = THIS_MODULE,
1472 .name = XUARTPS_NAME, /* Driver name */
1473 .of_match_table = xuartps_of_match,
1474 .pm = &xuartps_dev_pm_ops,
1475 },
1476};
1477
1478/* ---------------------------------------------------------------------
1479 * Module Init and Exit
1480 */
1481/**
1482 * xuartps_init - Initial driver registration call
1483 *
1484 * Returns whether the registration was successful or not
1485 **/
1486static int __init xuartps_init(void)
1487{
1488 int retval = 0;
1489
1490 /* Register the xuartps driver with the serial core */
1491 retval = uart_register_driver(&xuartps_uart_driver);
1492 if (retval)
1493 return retval;
1494
1495 /* Register the platform driver */
1496 retval = platform_driver_register(&xuartps_platform_driver);
1497 if (retval)
1498 uart_unregister_driver(&xuartps_uart_driver);
1499
1500 return retval;
1501}
1502
1503/**
1504 * xuartps_exit - Driver unregistration call
1505 **/
1506static void __exit xuartps_exit(void)
1507{
1508 /* The order of unregistration is important. Unregister the
1509 * UART driver before the platform driver crashes the system.
1510 */
1511
1512 /* Unregister the platform driver */
1513 platform_driver_unregister(&xuartps_platform_driver);
1514
1515 /* Unregister the xuartps driver */
1516 uart_unregister_driver(&xuartps_uart_driver);
1517}
1518
1519module_init(xuartps_init);
1520module_exit(xuartps_exit);
1521
1522MODULE_DESCRIPTION("Driver for PS UART");
1523MODULE_AUTHOR("Xilinx Inc.");
1524MODULE_LICENSE("GPL");