Loading...
Note: File does not exist in v5.4.
1/*
2 * MSM 7k/8k High speed uart driver
3 *
4 * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
5 * Copyright (c) 2008 Google Inc.
6 * Modified: Nick Pelly <npelly@google.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 * See the GNU General Public License for more details.
16 *
17 * Has optional support for uart power management independent of linux
18 * suspend/resume:
19 *
20 * RX wakeup.
21 * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
22 * UART RX pin). This should only be used if there is not a wakeup
23 * GPIO on the UART CTS, and the first RX byte is known (for example, with the
24 * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
25 * always be lost. RTS will be asserted even while the UART is off in this mode
26 * of operation. See msm_serial_hs_platform_data.rx_wakeup_irq.
27 */
28
29#include <linux/module.h>
30
31#include <linux/serial.h>
32#include <linux/serial_core.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/slab.h>
36#include <linux/init.h>
37#include <linux/interrupt.h>
38#include <linux/irq.h>
39#include <linux/io.h>
40#include <linux/ioport.h>
41#include <linux/kernel.h>
42#include <linux/timer.h>
43#include <linux/clk.h>
44#include <linux/platform_device.h>
45#include <linux/pm_runtime.h>
46#include <linux/dma-mapping.h>
47#include <linux/dmapool.h>
48#include <linux/wait.h>
49#include <linux/workqueue.h>
50
51#include <linux/atomic.h>
52#include <asm/irq.h>
53
54#include <mach/hardware.h>
55#include <mach/dma.h>
56#include <linux/platform_data/msm_serial_hs.h>
57
58/* HSUART Registers */
59#define UARTDM_MR1_ADDR 0x0
60#define UARTDM_MR2_ADDR 0x4
61
62/* Data Mover result codes */
63#define RSLT_FIFO_CNTR_BMSK (0xE << 28)
64#define RSLT_VLD BIT(1)
65
66/* write only register */
67#define UARTDM_CSR_ADDR 0x8
68#define UARTDM_CSR_115200 0xFF
69#define UARTDM_CSR_57600 0xEE
70#define UARTDM_CSR_38400 0xDD
71#define UARTDM_CSR_28800 0xCC
72#define UARTDM_CSR_19200 0xBB
73#define UARTDM_CSR_14400 0xAA
74#define UARTDM_CSR_9600 0x99
75#define UARTDM_CSR_7200 0x88
76#define UARTDM_CSR_4800 0x77
77#define UARTDM_CSR_3600 0x66
78#define UARTDM_CSR_2400 0x55
79#define UARTDM_CSR_1200 0x44
80#define UARTDM_CSR_600 0x33
81#define UARTDM_CSR_300 0x22
82#define UARTDM_CSR_150 0x11
83#define UARTDM_CSR_75 0x00
84
85/* write only register */
86#define UARTDM_TF_ADDR 0x70
87#define UARTDM_TF2_ADDR 0x74
88#define UARTDM_TF3_ADDR 0x78
89#define UARTDM_TF4_ADDR 0x7C
90
91/* write only register */
92#define UARTDM_CR_ADDR 0x10
93#define UARTDM_IMR_ADDR 0x14
94
95#define UARTDM_IPR_ADDR 0x18
96#define UARTDM_TFWR_ADDR 0x1c
97#define UARTDM_RFWR_ADDR 0x20
98#define UARTDM_HCR_ADDR 0x24
99#define UARTDM_DMRX_ADDR 0x34
100#define UARTDM_IRDA_ADDR 0x38
101#define UARTDM_DMEN_ADDR 0x3c
102
103/* UART_DM_NO_CHARS_FOR_TX */
104#define UARTDM_NCF_TX_ADDR 0x40
105
106#define UARTDM_BADR_ADDR 0x44
107
108#define UARTDM_SIM_CFG_ADDR 0x80
109/* Read Only register */
110#define UARTDM_SR_ADDR 0x8
111
112/* Read Only register */
113#define UARTDM_RF_ADDR 0x70
114#define UARTDM_RF2_ADDR 0x74
115#define UARTDM_RF3_ADDR 0x78
116#define UARTDM_RF4_ADDR 0x7C
117
118/* Read Only register */
119#define UARTDM_MISR_ADDR 0x10
120
121/* Read Only register */
122#define UARTDM_ISR_ADDR 0x14
123#define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
124
125#define UARTDM_RXFS_ADDR 0x50
126
127/* Register field Mask Mapping */
128#define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
129#define UARTDM_SR_OVERRUN_BMSK BIT(4)
130#define UARTDM_SR_TXEMT_BMSK BIT(3)
131#define UARTDM_SR_TXRDY_BMSK BIT(2)
132#define UARTDM_SR_RXRDY_BMSK BIT(0)
133
134#define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
135#define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
136#define UARTDM_CR_TX_EN_BMSK BIT(2)
137#define UARTDM_CR_RX_EN_BMSK BIT(0)
138
139/* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
140#define RESET_RX 0x10
141#define RESET_TX 0x20
142#define RESET_ERROR_STATUS 0x30
143#define RESET_BREAK_INT 0x40
144#define START_BREAK 0x50
145#define STOP_BREAK 0x60
146#define RESET_CTS 0x70
147#define RESET_STALE_INT 0x80
148#define RFR_LOW 0xD0
149#define RFR_HIGH 0xE0
150#define CR_PROTECTION_EN 0x100
151#define STALE_EVENT_ENABLE 0x500
152#define STALE_EVENT_DISABLE 0x600
153#define FORCE_STALE_EVENT 0x400
154#define CLEAR_TX_READY 0x300
155#define RESET_TX_ERROR 0x800
156#define RESET_TX_DONE 0x810
157
158#define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
159#define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
160#define UARTDM_MR1_CTS_CTL_BMSK 0x40
161#define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
162
163#define UARTDM_MR2_ERROR_MODE_BMSK 0x40
164#define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
165
166/* bits per character configuration */
167#define FIVE_BPC (0 << 4)
168#define SIX_BPC (1 << 4)
169#define SEVEN_BPC (2 << 4)
170#define EIGHT_BPC (3 << 4)
171
172#define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
173#define STOP_BIT_ONE (1 << 2)
174#define STOP_BIT_TWO (3 << 2)
175
176#define UARTDM_MR2_PARITY_MODE_BMSK 0x3
177
178/* Parity configuration */
179#define NO_PARITY 0x0
180#define EVEN_PARITY 0x1
181#define ODD_PARITY 0x2
182#define SPACE_PARITY 0x3
183
184#define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
185#define UARTDM_IPR_STALE_LSB_BMSK 0x1f
186
187/* These can be used for both ISR and IMR register */
188#define UARTDM_ISR_TX_READY_BMSK BIT(7)
189#define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
190#define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
191#define UARTDM_ISR_RXLEV_BMSK BIT(4)
192#define UARTDM_ISR_RXSTALE_BMSK BIT(3)
193#define UARTDM_ISR_RXBREAK_BMSK BIT(2)
194#define UARTDM_ISR_RXHUNT_BMSK BIT(1)
195#define UARTDM_ISR_TXLEV_BMSK BIT(0)
196
197/* Field definitions for UART_DM_DMEN*/
198#define UARTDM_TX_DM_EN_BMSK 0x1
199#define UARTDM_RX_DM_EN_BMSK 0x2
200
201#define UART_FIFOSIZE 64
202#define UARTCLK 7372800
203
204/* Rx DMA request states */
205enum flush_reason {
206 FLUSH_NONE,
207 FLUSH_DATA_READY,
208 FLUSH_DATA_INVALID, /* values after this indicate invalid data */
209 FLUSH_IGNORE = FLUSH_DATA_INVALID,
210 FLUSH_STOP,
211 FLUSH_SHUTDOWN,
212};
213
214/* UART clock states */
215enum msm_hs_clk_states_e {
216 MSM_HS_CLK_PORT_OFF, /* port not in use */
217 MSM_HS_CLK_OFF, /* clock disabled */
218 MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */
219 MSM_HS_CLK_ON, /* clock enabled */
220};
221
222/* Track the forced RXSTALE flush during clock off sequence.
223 * These states are only valid during MSM_HS_CLK_REQUEST_OFF */
224enum msm_hs_clk_req_off_state_e {
225 CLK_REQ_OFF_START,
226 CLK_REQ_OFF_RXSTALE_ISSUED,
227 CLK_REQ_OFF_FLUSH_ISSUED,
228 CLK_REQ_OFF_RXSTALE_FLUSHED,
229};
230
231/**
232 * struct msm_hs_tx
233 * @tx_ready_int_en: ok to dma more tx?
234 * @dma_in_flight: tx dma in progress
235 * @xfer: top level DMA command pointer structure
236 * @command_ptr: third level command struct pointer
237 * @command_ptr_ptr: second level command list struct pointer
238 * @mapped_cmd_ptr: DMA view of third level command struct
239 * @mapped_cmd_ptr_ptr: DMA view of second level command list struct
240 * @tx_count: number of bytes to transfer in DMA transfer
241 * @dma_base: DMA view of UART xmit buffer
242 *
243 * This structure describes a single Tx DMA transaction. MSM DMA
244 * commands have two levels of indirection. The top level command
245 * ptr points to a list of command ptr which in turn points to a
246 * single DMA 'command'. In our case each Tx transaction consists
247 * of a single second level pointer pointing to a 'box type' command.
248 */
249struct msm_hs_tx {
250 unsigned int tx_ready_int_en;
251 unsigned int dma_in_flight;
252 struct msm_dmov_cmd xfer;
253 dmov_box *command_ptr;
254 u32 *command_ptr_ptr;
255 dma_addr_t mapped_cmd_ptr;
256 dma_addr_t mapped_cmd_ptr_ptr;
257 int tx_count;
258 dma_addr_t dma_base;
259};
260
261/**
262 * struct msm_hs_rx
263 * @flush: Rx DMA request state
264 * @xfer: top level DMA command pointer structure
265 * @cmdptr_dmaaddr: DMA view of second level command structure
266 * @command_ptr: third level DMA command pointer structure
267 * @command_ptr_ptr: second level DMA command list pointer
268 * @mapped_cmd_ptr: DMA view of the third level command structure
269 * @wait: wait for DMA completion before shutdown
270 * @buffer: destination buffer for RX DMA
271 * @rbuffer: DMA view of buffer
272 * @pool: dma pool out of which coherent rx buffer is allocated
273 * @tty_work: private work-queue for tty flip buffer push task
274 *
275 * This structure describes a single Rx DMA transaction. Rx DMA
276 * transactions use box mode DMA commands.
277 */
278struct msm_hs_rx {
279 enum flush_reason flush;
280 struct msm_dmov_cmd xfer;
281 dma_addr_t cmdptr_dmaaddr;
282 dmov_box *command_ptr;
283 u32 *command_ptr_ptr;
284 dma_addr_t mapped_cmd_ptr;
285 wait_queue_head_t wait;
286 dma_addr_t rbuffer;
287 unsigned char *buffer;
288 struct dma_pool *pool;
289 struct work_struct tty_work;
290};
291
292/**
293 * struct msm_hs_rx_wakeup
294 * @irq: IRQ line to be configured as interrupt source on Rx activity
295 * @ignore: boolean value. 1 = ignore the wakeup interrupt
296 * @rx_to_inject: extra character to be inserted to Rx tty on wakeup
297 * @inject_rx: 1 = insert rx_to_inject. 0 = do not insert extra character
298 *
299 * This is an optional structure required for UART Rx GPIO IRQ based
300 * wakeup from low power state. UART wakeup can be triggered by RX activity
301 * (using a wakeup GPIO on the UART RX pin). This should only be used if
302 * there is not a wakeup GPIO on the UART CTS, and the first RX byte is
303 * known (eg., with the Bluetooth Texas Instruments HCILL protocol),
304 * since the first RX byte will always be lost. RTS will be asserted even
305 * while the UART is clocked off in this mode of operation.
306 */
307struct msm_hs_rx_wakeup {
308 int irq; /* < 0 indicates low power wakeup disabled */
309 unsigned char ignore;
310 unsigned char inject_rx;
311 char rx_to_inject;
312};
313
314/**
315 * struct msm_hs_port
316 * @uport: embedded uart port structure
317 * @imr_reg: shadow value of UARTDM_IMR
318 * @clk: uart input clock handle
319 * @tx: Tx transaction related data structure
320 * @rx: Rx transaction related data structure
321 * @dma_tx_channel: Tx DMA command channel
322 * @dma_rx_channel Rx DMA command channel
323 * @dma_tx_crci: Tx channel rate control interface number
324 * @dma_rx_crci: Rx channel rate control interface number
325 * @clk_off_timer: Timer to poll DMA event completion before clock off
326 * @clk_off_delay: clk_off_timer poll interval
327 * @clk_state: overall clock state
328 * @clk_req_off_state: post flush clock states
329 * @rx_wakeup: optional rx_wakeup feature related data
330 * @exit_lpm_cb: optional callback to exit low power mode
331 *
332 * Low level serial port structure.
333 */
334struct msm_hs_port {
335 struct uart_port uport;
336 unsigned long imr_reg;
337 struct clk *clk;
338 struct msm_hs_tx tx;
339 struct msm_hs_rx rx;
340
341 int dma_tx_channel;
342 int dma_rx_channel;
343 int dma_tx_crci;
344 int dma_rx_crci;
345
346 struct hrtimer clk_off_timer;
347 ktime_t clk_off_delay;
348 enum msm_hs_clk_states_e clk_state;
349 enum msm_hs_clk_req_off_state_e clk_req_off_state;
350
351 struct msm_hs_rx_wakeup rx_wakeup;
352 void (*exit_lpm_cb)(struct uart_port *);
353};
354
355#define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */
356#define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE
357#define UARTDM_RX_BUF_SIZE 512
358
359#define UARTDM_NR 2
360
361static struct msm_hs_port q_uart_port[UARTDM_NR];
362static struct platform_driver msm_serial_hs_platform_driver;
363static struct uart_driver msm_hs_driver;
364static struct uart_ops msm_hs_ops;
365static struct workqueue_struct *msm_hs_workqueue;
366
367#define UARTDM_TO_MSM(uart_port) \
368 container_of((uart_port), struct msm_hs_port, uport)
369
370static unsigned int use_low_power_rx_wakeup(struct msm_hs_port
371 *msm_uport)
372{
373 return (msm_uport->rx_wakeup.irq >= 0);
374}
375
376static unsigned int msm_hs_read(struct uart_port *uport,
377 unsigned int offset)
378{
379 return ioread32(uport->membase + offset);
380}
381
382static void msm_hs_write(struct uart_port *uport, unsigned int offset,
383 unsigned int value)
384{
385 iowrite32(value, uport->membase + offset);
386}
387
388static void msm_hs_release_port(struct uart_port *port)
389{
390 iounmap(port->membase);
391}
392
393static int msm_hs_request_port(struct uart_port *port)
394{
395 port->membase = ioremap(port->mapbase, PAGE_SIZE);
396 if (unlikely(!port->membase))
397 return -ENOMEM;
398
399 /* configure the CR Protection to Enable */
400 msm_hs_write(port, UARTDM_CR_ADDR, CR_PROTECTION_EN);
401 return 0;
402}
403
404static int msm_hs_remove(struct platform_device *pdev)
405{
406
407 struct msm_hs_port *msm_uport;
408 struct device *dev;
409
410 if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
411 printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
412 return -EINVAL;
413 }
414
415 msm_uport = &q_uart_port[pdev->id];
416 dev = msm_uport->uport.dev;
417
418 dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box),
419 DMA_TO_DEVICE);
420 dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
421 msm_uport->rx.rbuffer);
422 dma_pool_destroy(msm_uport->rx.pool);
423
424 dma_unmap_single(dev, msm_uport->rx.cmdptr_dmaaddr, sizeof(u32),
425 DMA_TO_DEVICE);
426 dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr_ptr, sizeof(u32),
427 DMA_TO_DEVICE);
428 dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box),
429 DMA_TO_DEVICE);
430
431 uart_remove_one_port(&msm_hs_driver, &msm_uport->uport);
432 clk_put(msm_uport->clk);
433
434 /* Free the tx resources */
435 kfree(msm_uport->tx.command_ptr);
436 kfree(msm_uport->tx.command_ptr_ptr);
437
438 /* Free the rx resources */
439 kfree(msm_uport->rx.command_ptr);
440 kfree(msm_uport->rx.command_ptr_ptr);
441
442 iounmap(msm_uport->uport.membase);
443
444 return 0;
445}
446
447static int msm_hs_init_clk_locked(struct uart_port *uport)
448{
449 int ret;
450 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
451
452 ret = clk_enable(msm_uport->clk);
453 if (ret) {
454 printk(KERN_ERR "Error could not turn on UART clk\n");
455 return ret;
456 }
457
458 /* Set up the MREG/NREG/DREG/MNDREG */
459 ret = clk_set_rate(msm_uport->clk, uport->uartclk);
460 if (ret) {
461 printk(KERN_WARNING "Error setting clock rate on UART\n");
462 clk_disable(msm_uport->clk);
463 return ret;
464 }
465
466 msm_uport->clk_state = MSM_HS_CLK_ON;
467 return 0;
468}
469
470/* Enable and Disable clocks (Used for power management) */
471static void msm_hs_pm(struct uart_port *uport, unsigned int state,
472 unsigned int oldstate)
473{
474 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
475
476 if (use_low_power_rx_wakeup(msm_uport) ||
477 msm_uport->exit_lpm_cb)
478 return; /* ignore linux PM states,
479 use msm_hs_request_clock API */
480
481 switch (state) {
482 case 0:
483 clk_enable(msm_uport->clk);
484 break;
485 case 3:
486 clk_disable(msm_uport->clk);
487 break;
488 default:
489 dev_err(uport->dev, "msm_serial: Unknown PM state %d\n",
490 state);
491 }
492}
493
494/*
495 * programs the UARTDM_CSR register with correct bit rates
496 *
497 * Interrupts should be disabled before we are called, as
498 * we modify Set Baud rate
499 * Set receive stale interrupt level, dependent on Bit Rate
500 * Goal is to have around 8 ms before indicate stale.
501 * roundup (((Bit Rate * .008) / 10) + 1
502 */
503static void msm_hs_set_bps_locked(struct uart_port *uport,
504 unsigned int bps)
505{
506 unsigned long rxstale;
507 unsigned long data;
508 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
509
510 switch (bps) {
511 case 300:
512 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_75);
513 rxstale = 1;
514 break;
515 case 600:
516 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_150);
517 rxstale = 1;
518 break;
519 case 1200:
520 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_300);
521 rxstale = 1;
522 break;
523 case 2400:
524 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_600);
525 rxstale = 1;
526 break;
527 case 4800:
528 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_1200);
529 rxstale = 1;
530 break;
531 case 9600:
532 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
533 rxstale = 2;
534 break;
535 case 14400:
536 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_3600);
537 rxstale = 3;
538 break;
539 case 19200:
540 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_4800);
541 rxstale = 4;
542 break;
543 case 28800:
544 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_7200);
545 rxstale = 6;
546 break;
547 case 38400:
548 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_9600);
549 rxstale = 8;
550 break;
551 case 57600:
552 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_14400);
553 rxstale = 16;
554 break;
555 case 76800:
556 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_19200);
557 rxstale = 16;
558 break;
559 case 115200:
560 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_28800);
561 rxstale = 31;
562 break;
563 case 230400:
564 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_57600);
565 rxstale = 31;
566 break;
567 case 460800:
568 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
569 rxstale = 31;
570 break;
571 case 4000000:
572 case 3686400:
573 case 3200000:
574 case 3500000:
575 case 3000000:
576 case 2500000:
577 case 1500000:
578 case 1152000:
579 case 1000000:
580 case 921600:
581 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
582 rxstale = 31;
583 break;
584 default:
585 msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
586 /* default to 9600 */
587 bps = 9600;
588 rxstale = 2;
589 break;
590 }
591 if (bps > 460800)
592 uport->uartclk = bps * 16;
593 else
594 uport->uartclk = UARTCLK;
595
596 if (clk_set_rate(msm_uport->clk, uport->uartclk)) {
597 printk(KERN_WARNING "Error setting clock rate on UART\n");
598 return;
599 }
600
601 data = rxstale & UARTDM_IPR_STALE_LSB_BMSK;
602 data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
603
604 msm_hs_write(uport, UARTDM_IPR_ADDR, data);
605}
606
607/*
608 * termios : new ktermios
609 * oldtermios: old ktermios previous setting
610 *
611 * Configure the serial port
612 */
613static void msm_hs_set_termios(struct uart_port *uport,
614 struct ktermios *termios,
615 struct ktermios *oldtermios)
616{
617 unsigned int bps;
618 unsigned long data;
619 unsigned long flags;
620 unsigned int c_cflag = termios->c_cflag;
621 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
622
623 spin_lock_irqsave(&uport->lock, flags);
624 clk_enable(msm_uport->clk);
625
626 /* 300 is the minimum baud support by the driver */
627 bps = uart_get_baud_rate(uport, termios, oldtermios, 200, 4000000);
628
629 /* Temporary remapping 200 BAUD to 3.2 mbps */
630 if (bps == 200)
631 bps = 3200000;
632
633 msm_hs_set_bps_locked(uport, bps);
634
635 data = msm_hs_read(uport, UARTDM_MR2_ADDR);
636 data &= ~UARTDM_MR2_PARITY_MODE_BMSK;
637 /* set parity */
638 if (PARENB == (c_cflag & PARENB)) {
639 if (PARODD == (c_cflag & PARODD))
640 data |= ODD_PARITY;
641 else if (CMSPAR == (c_cflag & CMSPAR))
642 data |= SPACE_PARITY;
643 else
644 data |= EVEN_PARITY;
645 }
646
647 /* Set bits per char */
648 data &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK;
649
650 switch (c_cflag & CSIZE) {
651 case CS5:
652 data |= FIVE_BPC;
653 break;
654 case CS6:
655 data |= SIX_BPC;
656 break;
657 case CS7:
658 data |= SEVEN_BPC;
659 break;
660 default:
661 data |= EIGHT_BPC;
662 break;
663 }
664 /* stop bits */
665 if (c_cflag & CSTOPB) {
666 data |= STOP_BIT_TWO;
667 } else {
668 /* otherwise 1 stop bit */
669 data |= STOP_BIT_ONE;
670 }
671 data |= UARTDM_MR2_ERROR_MODE_BMSK;
672 /* write parity/bits per char/stop bit configuration */
673 msm_hs_write(uport, UARTDM_MR2_ADDR, data);
674
675 /* Configure HW flow control */
676 data = msm_hs_read(uport, UARTDM_MR1_ADDR);
677
678 data &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK);
679
680 if (c_cflag & CRTSCTS) {
681 data |= UARTDM_MR1_CTS_CTL_BMSK;
682 data |= UARTDM_MR1_RX_RDY_CTL_BMSK;
683 }
684
685 msm_hs_write(uport, UARTDM_MR1_ADDR, data);
686
687 uport->ignore_status_mask = termios->c_iflag & INPCK;
688 uport->ignore_status_mask |= termios->c_iflag & IGNPAR;
689 uport->read_status_mask = (termios->c_cflag & CREAD);
690
691 msm_hs_write(uport, UARTDM_IMR_ADDR, 0);
692
693 /* Set Transmit software time out */
694 uart_update_timeout(uport, c_cflag, bps);
695
696 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
697 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
698
699 if (msm_uport->rx.flush == FLUSH_NONE) {
700 msm_uport->rx.flush = FLUSH_IGNORE;
701 msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
702 }
703
704 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
705
706 clk_disable(msm_uport->clk);
707 spin_unlock_irqrestore(&uport->lock, flags);
708}
709
710/*
711 * Standard API, Transmitter
712 * Any character in the transmit shift register is sent
713 */
714static unsigned int msm_hs_tx_empty(struct uart_port *uport)
715{
716 unsigned int data;
717 unsigned int ret = 0;
718 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
719
720 clk_enable(msm_uport->clk);
721
722 data = msm_hs_read(uport, UARTDM_SR_ADDR);
723 if (data & UARTDM_SR_TXEMT_BMSK)
724 ret = TIOCSER_TEMT;
725
726 clk_disable(msm_uport->clk);
727
728 return ret;
729}
730
731/*
732 * Standard API, Stop transmitter.
733 * Any character in the transmit shift register is sent as
734 * well as the current data mover transfer .
735 */
736static void msm_hs_stop_tx_locked(struct uart_port *uport)
737{
738 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
739
740 msm_uport->tx.tx_ready_int_en = 0;
741}
742
743/*
744 * Standard API, Stop receiver as soon as possible.
745 *
746 * Function immediately terminates the operation of the
747 * channel receiver and any incoming characters are lost. None
748 * of the receiver status bits are affected by this command and
749 * characters that are already in the receive FIFO there.
750 */
751static void msm_hs_stop_rx_locked(struct uart_port *uport)
752{
753 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
754 unsigned int data;
755
756 clk_enable(msm_uport->clk);
757
758 /* disable dlink */
759 data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
760 data &= ~UARTDM_RX_DM_EN_BMSK;
761 msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
762
763 /* Disable the receiver */
764 if (msm_uport->rx.flush == FLUSH_NONE)
765 msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
766
767 if (msm_uport->rx.flush != FLUSH_SHUTDOWN)
768 msm_uport->rx.flush = FLUSH_STOP;
769
770 clk_disable(msm_uport->clk);
771}
772
773/* Transmit the next chunk of data */
774static void msm_hs_submit_tx_locked(struct uart_port *uport)
775{
776 int left;
777 int tx_count;
778 dma_addr_t src_addr;
779 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
780 struct msm_hs_tx *tx = &msm_uport->tx;
781 struct circ_buf *tx_buf = &msm_uport->uport.state->xmit;
782
783 if (uart_circ_empty(tx_buf) || uport->state->port.tty->stopped) {
784 msm_hs_stop_tx_locked(uport);
785 return;
786 }
787
788 tx->dma_in_flight = 1;
789
790 tx_count = uart_circ_chars_pending(tx_buf);
791
792 if (UARTDM_TX_BUF_SIZE < tx_count)
793 tx_count = UARTDM_TX_BUF_SIZE;
794
795 left = UART_XMIT_SIZE - tx_buf->tail;
796
797 if (tx_count > left)
798 tx_count = left;
799
800 src_addr = tx->dma_base + tx_buf->tail;
801 dma_sync_single_for_device(uport->dev, src_addr, tx_count,
802 DMA_TO_DEVICE);
803
804 tx->command_ptr->num_rows = (((tx_count + 15) >> 4) << 16) |
805 ((tx_count + 15) >> 4);
806 tx->command_ptr->src_row_addr = src_addr;
807
808 dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr,
809 sizeof(dmov_box), DMA_TO_DEVICE);
810
811 *tx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(tx->mapped_cmd_ptr);
812
813 dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr_ptr,
814 sizeof(u32), DMA_TO_DEVICE);
815
816 /* Save tx_count to use in Callback */
817 tx->tx_count = tx_count;
818 msm_hs_write(uport, UARTDM_NCF_TX_ADDR, tx_count);
819
820 /* Disable the tx_ready interrupt */
821 msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK;
822 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
823 msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer);
824}
825
826/* Start to receive the next chunk of data */
827static void msm_hs_start_rx_locked(struct uart_port *uport)
828{
829 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
830
831 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
832 msm_hs_write(uport, UARTDM_DMRX_ADDR, UARTDM_RX_BUF_SIZE);
833 msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_ENABLE);
834 msm_uport->imr_reg |= UARTDM_ISR_RXLEV_BMSK;
835 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
836
837 msm_uport->rx.flush = FLUSH_NONE;
838 msm_dmov_enqueue_cmd(msm_uport->dma_rx_channel, &msm_uport->rx.xfer);
839
840 /* might have finished RX and be ready to clock off */
841 hrtimer_start(&msm_uport->clk_off_timer, msm_uport->clk_off_delay,
842 HRTIMER_MODE_REL);
843}
844
845/* Enable the transmitter Interrupt */
846static void msm_hs_start_tx_locked(struct uart_port *uport)
847{
848 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
849
850 clk_enable(msm_uport->clk);
851
852 if (msm_uport->exit_lpm_cb)
853 msm_uport->exit_lpm_cb(uport);
854
855 if (msm_uport->tx.tx_ready_int_en == 0) {
856 msm_uport->tx.tx_ready_int_en = 1;
857 msm_hs_submit_tx_locked(uport);
858 }
859
860 clk_disable(msm_uport->clk);
861}
862
863/*
864 * This routine is called when we are done with a DMA transfer
865 *
866 * This routine is registered with Data mover when we set
867 * up a Data Mover transfer. It is called from Data mover ISR
868 * when the DMA transfer is done.
869 */
870static void msm_hs_dmov_tx_callback(struct msm_dmov_cmd *cmd_ptr,
871 unsigned int result,
872 struct msm_dmov_errdata *err)
873{
874 unsigned long flags;
875 struct msm_hs_port *msm_uport;
876
877 /* DMA did not finish properly */
878 WARN_ON((((result & RSLT_FIFO_CNTR_BMSK) >> 28) == 1) &&
879 !(result & RSLT_VLD));
880
881 msm_uport = container_of(cmd_ptr, struct msm_hs_port, tx.xfer);
882
883 spin_lock_irqsave(&msm_uport->uport.lock, flags);
884 clk_enable(msm_uport->clk);
885
886 msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK;
887 msm_hs_write(&msm_uport->uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
888
889 clk_disable(msm_uport->clk);
890 spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
891}
892
893/*
894 * This routine is called when we are done with a DMA transfer or the
895 * a flush has been sent to the data mover driver.
896 *
897 * This routine is registered with Data mover when we set up a Data Mover
898 * transfer. It is called from Data mover ISR when the DMA transfer is done.
899 */
900static void msm_hs_dmov_rx_callback(struct msm_dmov_cmd *cmd_ptr,
901 unsigned int result,
902 struct msm_dmov_errdata *err)
903{
904 int retval;
905 int rx_count;
906 unsigned long status;
907 unsigned int error_f = 0;
908 unsigned long flags;
909 unsigned int flush;
910 struct tty_port *port;
911 struct uart_port *uport;
912 struct msm_hs_port *msm_uport;
913
914 msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer);
915 uport = &msm_uport->uport;
916
917 spin_lock_irqsave(&uport->lock, flags);
918 clk_enable(msm_uport->clk);
919
920 port = &uport->state->port;
921
922 msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
923
924 status = msm_hs_read(uport, UARTDM_SR_ADDR);
925
926 /* overflow is not connect to data in a FIFO */
927 if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) &&
928 (uport->read_status_mask & CREAD))) {
929 tty_insert_flip_char(port, 0, TTY_OVERRUN);
930 uport->icount.buf_overrun++;
931 error_f = 1;
932 }
933
934 if (!(uport->ignore_status_mask & INPCK))
935 status = status & ~(UARTDM_SR_PAR_FRAME_BMSK);
936
937 if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) {
938 /* Can not tell difference between parity & frame error */
939 uport->icount.parity++;
940 error_f = 1;
941 if (uport->ignore_status_mask & IGNPAR)
942 tty_insert_flip_char(port, 0, TTY_PARITY);
943 }
944
945 if (error_f)
946 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
947
948 if (msm_uport->clk_req_off_state == CLK_REQ_OFF_FLUSH_ISSUED)
949 msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_FLUSHED;
950
951 flush = msm_uport->rx.flush;
952 if (flush == FLUSH_IGNORE)
953 msm_hs_start_rx_locked(uport);
954 if (flush == FLUSH_STOP)
955 msm_uport->rx.flush = FLUSH_SHUTDOWN;
956 if (flush >= FLUSH_DATA_INVALID)
957 goto out;
958
959 rx_count = msm_hs_read(uport, UARTDM_RX_TOTAL_SNAP_ADDR);
960
961 if (0 != (uport->read_status_mask & CREAD)) {
962 retval = tty_insert_flip_string(port, msm_uport->rx.buffer,
963 rx_count);
964 BUG_ON(retval != rx_count);
965 }
966
967 msm_hs_start_rx_locked(uport);
968
969out:
970 clk_disable(msm_uport->clk);
971
972 spin_unlock_irqrestore(&uport->lock, flags);
973
974 if (flush < FLUSH_DATA_INVALID)
975 queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
976}
977
978static void msm_hs_tty_flip_buffer_work(struct work_struct *work)
979{
980 struct msm_hs_port *msm_uport =
981 container_of(work, struct msm_hs_port, rx.tty_work);
982
983 tty_flip_buffer_push(&msm_uport->uport.state->port);
984}
985
986/*
987 * Standard API, Current states of modem control inputs
988 *
989 * Since CTS can be handled entirely by HARDWARE we always
990 * indicate clear to send and count on the TX FIFO to block when
991 * it fills up.
992 *
993 * - TIOCM_DCD
994 * - TIOCM_CTS
995 * - TIOCM_DSR
996 * - TIOCM_RI
997 * (Unsupported) DCD and DSR will return them high. RI will return low.
998 */
999static unsigned int msm_hs_get_mctrl_locked(struct uart_port *uport)
1000{
1001 return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
1002}
1003
1004/*
1005 * True enables UART auto RFR, which indicates we are ready for data if the RX
1006 * buffer is not full. False disables auto RFR, and deasserts RFR to indicate
1007 * we are not ready for data. Must be called with UART clock on.
1008 */
1009static void set_rfr_locked(struct uart_port *uport, int auto_rfr)
1010{
1011 unsigned int data;
1012
1013 data = msm_hs_read(uport, UARTDM_MR1_ADDR);
1014
1015 if (auto_rfr) {
1016 /* enable auto ready-for-receiving */
1017 data |= UARTDM_MR1_RX_RDY_CTL_BMSK;
1018 msm_hs_write(uport, UARTDM_MR1_ADDR, data);
1019 } else {
1020 /* disable auto ready-for-receiving */
1021 data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
1022 msm_hs_write(uport, UARTDM_MR1_ADDR, data);
1023 /* RFR is active low, set high */
1024 msm_hs_write(uport, UARTDM_CR_ADDR, RFR_HIGH);
1025 }
1026}
1027
1028/*
1029 * Standard API, used to set or clear RFR
1030 */
1031static void msm_hs_set_mctrl_locked(struct uart_port *uport,
1032 unsigned int mctrl)
1033{
1034 unsigned int auto_rfr;
1035 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1036
1037 clk_enable(msm_uport->clk);
1038
1039 auto_rfr = TIOCM_RTS & mctrl ? 1 : 0;
1040 set_rfr_locked(uport, auto_rfr);
1041
1042 clk_disable(msm_uport->clk);
1043}
1044
1045/* Standard API, Enable modem status (CTS) interrupt */
1046static void msm_hs_enable_ms_locked(struct uart_port *uport)
1047{
1048 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1049
1050 clk_enable(msm_uport->clk);
1051
1052 /* Enable DELTA_CTS Interrupt */
1053 msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK;
1054 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1055
1056 clk_disable(msm_uport->clk);
1057
1058}
1059
1060/*
1061 * Standard API, Break Signal
1062 *
1063 * Control the transmission of a break signal. ctl eq 0 => break
1064 * signal terminate ctl ne 0 => start break signal
1065 */
1066static void msm_hs_break_ctl(struct uart_port *uport, int ctl)
1067{
1068 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1069
1070 clk_enable(msm_uport->clk);
1071 msm_hs_write(uport, UARTDM_CR_ADDR, ctl ? START_BREAK : STOP_BREAK);
1072 clk_disable(msm_uport->clk);
1073}
1074
1075static void msm_hs_config_port(struct uart_port *uport, int cfg_flags)
1076{
1077 unsigned long flags;
1078
1079 spin_lock_irqsave(&uport->lock, flags);
1080 if (cfg_flags & UART_CONFIG_TYPE) {
1081 uport->type = PORT_MSM;
1082 msm_hs_request_port(uport);
1083 }
1084 spin_unlock_irqrestore(&uport->lock, flags);
1085}
1086
1087/* Handle CTS changes (Called from interrupt handler) */
1088static void msm_hs_handle_delta_cts_locked(struct uart_port *uport)
1089{
1090 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1091
1092 clk_enable(msm_uport->clk);
1093
1094 /* clear interrupt */
1095 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS);
1096 uport->icount.cts++;
1097
1098 clk_disable(msm_uport->clk);
1099
1100 /* clear the IOCTL TIOCMIWAIT if called */
1101 wake_up_interruptible(&uport->state->port.delta_msr_wait);
1102}
1103
1104/* check if the TX path is flushed, and if so clock off
1105 * returns 0 did not clock off, need to retry (still sending final byte)
1106 * -1 did not clock off, do not retry
1107 * 1 if we clocked off
1108 */
1109static int msm_hs_check_clock_off_locked(struct uart_port *uport)
1110{
1111 unsigned long sr_status;
1112 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1113 struct circ_buf *tx_buf = &uport->state->xmit;
1114
1115 /* Cancel if tx tty buffer is not empty, dma is in flight,
1116 * or tx fifo is not empty, or rx fifo is not empty */
1117 if (msm_uport->clk_state != MSM_HS_CLK_REQUEST_OFF ||
1118 !uart_circ_empty(tx_buf) || msm_uport->tx.dma_in_flight ||
1119 (msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) ||
1120 !(msm_uport->imr_reg & UARTDM_ISR_RXLEV_BMSK)) {
1121 return -1;
1122 }
1123
1124 /* Make sure the uart is finished with the last byte */
1125 sr_status = msm_hs_read(uport, UARTDM_SR_ADDR);
1126 if (!(sr_status & UARTDM_SR_TXEMT_BMSK))
1127 return 0; /* retry */
1128
1129 /* Make sure forced RXSTALE flush complete */
1130 switch (msm_uport->clk_req_off_state) {
1131 case CLK_REQ_OFF_START:
1132 msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_ISSUED;
1133 msm_hs_write(uport, UARTDM_CR_ADDR, FORCE_STALE_EVENT);
1134 return 0; /* RXSTALE flush not complete - retry */
1135 case CLK_REQ_OFF_RXSTALE_ISSUED:
1136 case CLK_REQ_OFF_FLUSH_ISSUED:
1137 return 0; /* RXSTALE flush not complete - retry */
1138 case CLK_REQ_OFF_RXSTALE_FLUSHED:
1139 break; /* continue */
1140 }
1141
1142 if (msm_uport->rx.flush != FLUSH_SHUTDOWN) {
1143 if (msm_uport->rx.flush == FLUSH_NONE)
1144 msm_hs_stop_rx_locked(uport);
1145 return 0; /* come back later to really clock off */
1146 }
1147
1148 /* we really want to clock off */
1149 clk_disable(msm_uport->clk);
1150 msm_uport->clk_state = MSM_HS_CLK_OFF;
1151
1152 if (use_low_power_rx_wakeup(msm_uport)) {
1153 msm_uport->rx_wakeup.ignore = 1;
1154 enable_irq(msm_uport->rx_wakeup.irq);
1155 }
1156 return 1;
1157}
1158
1159static enum hrtimer_restart msm_hs_clk_off_retry(struct hrtimer *timer)
1160{
1161 unsigned long flags;
1162 int ret = HRTIMER_NORESTART;
1163 struct msm_hs_port *msm_uport = container_of(timer, struct msm_hs_port,
1164 clk_off_timer);
1165 struct uart_port *uport = &msm_uport->uport;
1166
1167 spin_lock_irqsave(&uport->lock, flags);
1168
1169 if (!msm_hs_check_clock_off_locked(uport)) {
1170 hrtimer_forward_now(timer, msm_uport->clk_off_delay);
1171 ret = HRTIMER_RESTART;
1172 }
1173
1174 spin_unlock_irqrestore(&uport->lock, flags);
1175
1176 return ret;
1177}
1178
1179static irqreturn_t msm_hs_isr(int irq, void *dev)
1180{
1181 unsigned long flags;
1182 unsigned long isr_status;
1183 struct msm_hs_port *msm_uport = dev;
1184 struct uart_port *uport = &msm_uport->uport;
1185 struct circ_buf *tx_buf = &uport->state->xmit;
1186 struct msm_hs_tx *tx = &msm_uport->tx;
1187 struct msm_hs_rx *rx = &msm_uport->rx;
1188
1189 spin_lock_irqsave(&uport->lock, flags);
1190
1191 isr_status = msm_hs_read(uport, UARTDM_MISR_ADDR);
1192
1193 /* Uart RX starting */
1194 if (isr_status & UARTDM_ISR_RXLEV_BMSK) {
1195 msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK;
1196 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1197 }
1198 /* Stale rx interrupt */
1199 if (isr_status & UARTDM_ISR_RXSTALE_BMSK) {
1200 msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
1201 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
1202
1203 if (msm_uport->clk_req_off_state == CLK_REQ_OFF_RXSTALE_ISSUED)
1204 msm_uport->clk_req_off_state =
1205 CLK_REQ_OFF_FLUSH_ISSUED;
1206 if (rx->flush == FLUSH_NONE) {
1207 rx->flush = FLUSH_DATA_READY;
1208 msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
1209 }
1210 }
1211 /* tx ready interrupt */
1212 if (isr_status & UARTDM_ISR_TX_READY_BMSK) {
1213 /* Clear TX Ready */
1214 msm_hs_write(uport, UARTDM_CR_ADDR, CLEAR_TX_READY);
1215
1216 if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) {
1217 msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
1218 msm_hs_write(uport, UARTDM_IMR_ADDR,
1219 msm_uport->imr_reg);
1220 }
1221
1222 /* Complete DMA TX transactions and submit new transactions */
1223 tx_buf->tail = (tx_buf->tail + tx->tx_count) & ~UART_XMIT_SIZE;
1224
1225 tx->dma_in_flight = 0;
1226
1227 uport->icount.tx += tx->tx_count;
1228 if (tx->tx_ready_int_en)
1229 msm_hs_submit_tx_locked(uport);
1230
1231 if (uart_circ_chars_pending(tx_buf) < WAKEUP_CHARS)
1232 uart_write_wakeup(uport);
1233 }
1234 if (isr_status & UARTDM_ISR_TXLEV_BMSK) {
1235 /* TX FIFO is empty */
1236 msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK;
1237 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1238 if (!msm_hs_check_clock_off_locked(uport))
1239 hrtimer_start(&msm_uport->clk_off_timer,
1240 msm_uport->clk_off_delay,
1241 HRTIMER_MODE_REL);
1242 }
1243
1244 /* Change in CTS interrupt */
1245 if (isr_status & UARTDM_ISR_DELTA_CTS_BMSK)
1246 msm_hs_handle_delta_cts_locked(uport);
1247
1248 spin_unlock_irqrestore(&uport->lock, flags);
1249
1250 return IRQ_HANDLED;
1251}
1252
1253void msm_hs_request_clock_off_locked(struct uart_port *uport)
1254{
1255 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1256
1257 if (msm_uport->clk_state == MSM_HS_CLK_ON) {
1258 msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF;
1259 msm_uport->clk_req_off_state = CLK_REQ_OFF_START;
1260 if (!use_low_power_rx_wakeup(msm_uport))
1261 set_rfr_locked(uport, 0);
1262 msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
1263 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1264 }
1265}
1266
1267/**
1268 * msm_hs_request_clock_off - request to (i.e. asynchronously) turn off uart
1269 * clock once pending TX is flushed and Rx DMA command is terminated.
1270 * @uport: uart_port structure for the device instance.
1271 *
1272 * This functions puts the device into a partially active low power mode. It
1273 * waits to complete all pending tx transactions, flushes ongoing Rx DMA
1274 * command and terminates UART side Rx transaction, puts UART HW in non DMA
1275 * mode and then clocks off the device. A client calls this when no UART
1276 * data is expected. msm_request_clock_on() must be called before any further
1277 * UART can be sent or received.
1278 */
1279void msm_hs_request_clock_off(struct uart_port *uport)
1280{
1281 unsigned long flags;
1282
1283 spin_lock_irqsave(&uport->lock, flags);
1284 msm_hs_request_clock_off_locked(uport);
1285 spin_unlock_irqrestore(&uport->lock, flags);
1286}
1287
1288void msm_hs_request_clock_on_locked(struct uart_port *uport)
1289{
1290 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1291 unsigned int data;
1292
1293 switch (msm_uport->clk_state) {
1294 case MSM_HS_CLK_OFF:
1295 clk_enable(msm_uport->clk);
1296 disable_irq_nosync(msm_uport->rx_wakeup.irq);
1297 /* fall-through */
1298 case MSM_HS_CLK_REQUEST_OFF:
1299 if (msm_uport->rx.flush == FLUSH_STOP ||
1300 msm_uport->rx.flush == FLUSH_SHUTDOWN) {
1301 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
1302 data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
1303 data |= UARTDM_RX_DM_EN_BMSK;
1304 msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
1305 }
1306 hrtimer_try_to_cancel(&msm_uport->clk_off_timer);
1307 if (msm_uport->rx.flush == FLUSH_SHUTDOWN)
1308 msm_hs_start_rx_locked(uport);
1309 if (!use_low_power_rx_wakeup(msm_uport))
1310 set_rfr_locked(uport, 1);
1311 if (msm_uport->rx.flush == FLUSH_STOP)
1312 msm_uport->rx.flush = FLUSH_IGNORE;
1313 msm_uport->clk_state = MSM_HS_CLK_ON;
1314 break;
1315 case MSM_HS_CLK_ON:
1316 break;
1317 case MSM_HS_CLK_PORT_OFF:
1318 break;
1319 }
1320}
1321
1322/**
1323 * msm_hs_request_clock_on - Switch the device from partially active low
1324 * power mode to fully active (i.e. clock on) mode.
1325 * @uport: uart_port structure for the device.
1326 *
1327 * This function switches on the input clock, puts UART HW into DMA mode
1328 * and enqueues an Rx DMA command if the device was in partially active
1329 * mode. It has no effect if called with the device in inactive state.
1330 */
1331void msm_hs_request_clock_on(struct uart_port *uport)
1332{
1333 unsigned long flags;
1334
1335 spin_lock_irqsave(&uport->lock, flags);
1336 msm_hs_request_clock_on_locked(uport);
1337 spin_unlock_irqrestore(&uport->lock, flags);
1338}
1339
1340static irqreturn_t msm_hs_rx_wakeup_isr(int irq, void *dev)
1341{
1342 unsigned int wakeup = 0;
1343 unsigned long flags;
1344 struct msm_hs_port *msm_uport = dev;
1345 struct uart_port *uport = &msm_uport->uport;
1346
1347 spin_lock_irqsave(&uport->lock, flags);
1348 if (msm_uport->clk_state == MSM_HS_CLK_OFF) {
1349 /* ignore the first irq - it is a pending irq that occurred
1350 * before enable_irq() */
1351 if (msm_uport->rx_wakeup.ignore)
1352 msm_uport->rx_wakeup.ignore = 0;
1353 else
1354 wakeup = 1;
1355 }
1356
1357 if (wakeup) {
1358 /* the uart was clocked off during an rx, wake up and
1359 * optionally inject char into tty rx */
1360 msm_hs_request_clock_on_locked(uport);
1361 if (msm_uport->rx_wakeup.inject_rx) {
1362 tty_insert_flip_char(&uport->state->port,
1363 msm_uport->rx_wakeup.rx_to_inject,
1364 TTY_NORMAL);
1365 queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
1366 }
1367 }
1368
1369 spin_unlock_irqrestore(&uport->lock, flags);
1370
1371 return IRQ_HANDLED;
1372}
1373
1374static const char *msm_hs_type(struct uart_port *port)
1375{
1376 return (port->type == PORT_MSM) ? "MSM_HS_UART" : NULL;
1377}
1378
1379/* Called when port is opened */
1380static int msm_hs_startup(struct uart_port *uport)
1381{
1382 int ret;
1383 int rfr_level;
1384 unsigned long flags;
1385 unsigned int data;
1386 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1387 struct circ_buf *tx_buf = &uport->state->xmit;
1388 struct msm_hs_tx *tx = &msm_uport->tx;
1389 struct msm_hs_rx *rx = &msm_uport->rx;
1390
1391 rfr_level = uport->fifosize;
1392 if (rfr_level > 16)
1393 rfr_level -= 16;
1394
1395 tx->dma_base = dma_map_single(uport->dev, tx_buf->buf, UART_XMIT_SIZE,
1396 DMA_TO_DEVICE);
1397
1398 /* do not let tty layer execute RX in global workqueue, use a
1399 * dedicated workqueue managed by this driver */
1400 uport->state->port.low_latency = 1;
1401
1402 /* turn on uart clk */
1403 ret = msm_hs_init_clk_locked(uport);
1404 if (unlikely(ret)) {
1405 printk(KERN_ERR "Turning uartclk failed!\n");
1406 goto err_msm_hs_init_clk;
1407 }
1408
1409 /* Set auto RFR Level */
1410 data = msm_hs_read(uport, UARTDM_MR1_ADDR);
1411 data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
1412 data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
1413 data |= (UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2));
1414 data |= (UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level);
1415 msm_hs_write(uport, UARTDM_MR1_ADDR, data);
1416
1417 /* Make sure RXSTALE count is non-zero */
1418 data = msm_hs_read(uport, UARTDM_IPR_ADDR);
1419 if (!data) {
1420 data |= 0x1f & UARTDM_IPR_STALE_LSB_BMSK;
1421 msm_hs_write(uport, UARTDM_IPR_ADDR, data);
1422 }
1423
1424 /* Enable Data Mover Mode */
1425 data = UARTDM_TX_DM_EN_BMSK | UARTDM_RX_DM_EN_BMSK;
1426 msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
1427
1428 /* Reset TX */
1429 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
1430 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX);
1431 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
1432 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_BREAK_INT);
1433 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
1434 msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS);
1435 msm_hs_write(uport, UARTDM_CR_ADDR, RFR_LOW);
1436 /* Turn on Uart Receiver */
1437 msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_EN_BMSK);
1438
1439 /* Turn on Uart Transmitter */
1440 msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_EN_BMSK);
1441
1442 /* Initialize the tx */
1443 tx->tx_ready_int_en = 0;
1444 tx->dma_in_flight = 0;
1445
1446 tx->xfer.complete_func = msm_hs_dmov_tx_callback;
1447 tx->xfer.execute_func = NULL;
1448
1449 tx->command_ptr->cmd = CMD_LC |
1450 CMD_DST_CRCI(msm_uport->dma_tx_crci) | CMD_MODE_BOX;
1451
1452 tx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
1453 | (MSM_UARTDM_BURST_SIZE);
1454
1455 tx->command_ptr->row_offset = (MSM_UARTDM_BURST_SIZE << 16);
1456
1457 tx->command_ptr->dst_row_addr =
1458 msm_uport->uport.mapbase + UARTDM_TF_ADDR;
1459
1460
1461 /* Turn on Uart Receive */
1462 rx->xfer.complete_func = msm_hs_dmov_rx_callback;
1463 rx->xfer.execute_func = NULL;
1464
1465 rx->command_ptr->cmd = CMD_LC |
1466 CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX;
1467
1468 rx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
1469 | (MSM_UARTDM_BURST_SIZE);
1470 rx->command_ptr->row_offset = MSM_UARTDM_BURST_SIZE;
1471 rx->command_ptr->src_row_addr = uport->mapbase + UARTDM_RF_ADDR;
1472
1473
1474 msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK;
1475 /* Enable reading the current CTS, no harm even if CTS is ignored */
1476 msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK;
1477
1478 msm_hs_write(uport, UARTDM_TFWR_ADDR, 0); /* TXLEV on empty TX fifo */
1479
1480
1481 ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH,
1482 "msm_hs_uart", msm_uport);
1483 if (unlikely(ret)) {
1484 printk(KERN_ERR "Request msm_hs_uart IRQ failed!\n");
1485 goto err_request_irq;
1486 }
1487 if (use_low_power_rx_wakeup(msm_uport)) {
1488 ret = request_irq(msm_uport->rx_wakeup.irq,
1489 msm_hs_rx_wakeup_isr,
1490 IRQF_TRIGGER_FALLING,
1491 "msm_hs_rx_wakeup", msm_uport);
1492 if (unlikely(ret)) {
1493 printk(KERN_ERR "Request msm_hs_rx_wakeup IRQ failed!\n");
1494 free_irq(uport->irq, msm_uport);
1495 goto err_request_irq;
1496 }
1497 disable_irq(msm_uport->rx_wakeup.irq);
1498 }
1499
1500 spin_lock_irqsave(&uport->lock, flags);
1501
1502 msm_hs_write(uport, UARTDM_RFWR_ADDR, 0);
1503 msm_hs_start_rx_locked(uport);
1504
1505 spin_unlock_irqrestore(&uport->lock, flags);
1506 ret = pm_runtime_set_active(uport->dev);
1507 if (ret)
1508 dev_err(uport->dev, "set active error:%d\n", ret);
1509 pm_runtime_enable(uport->dev);
1510
1511 return 0;
1512
1513err_request_irq:
1514err_msm_hs_init_clk:
1515 dma_unmap_single(uport->dev, tx->dma_base,
1516 UART_XMIT_SIZE, DMA_TO_DEVICE);
1517 return ret;
1518}
1519
1520/* Initialize tx and rx data structures */
1521static int uartdm_init_port(struct uart_port *uport)
1522{
1523 int ret = 0;
1524 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1525 struct msm_hs_tx *tx = &msm_uport->tx;
1526 struct msm_hs_rx *rx = &msm_uport->rx;
1527
1528 /* Allocate the command pointer. Needs to be 64 bit aligned */
1529 tx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
1530 if (!tx->command_ptr)
1531 return -ENOMEM;
1532
1533 tx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA);
1534 if (!tx->command_ptr_ptr) {
1535 ret = -ENOMEM;
1536 goto err_tx_command_ptr_ptr;
1537 }
1538
1539 tx->mapped_cmd_ptr = dma_map_single(uport->dev, tx->command_ptr,
1540 sizeof(dmov_box), DMA_TO_DEVICE);
1541 tx->mapped_cmd_ptr_ptr = dma_map_single(uport->dev,
1542 tx->command_ptr_ptr,
1543 sizeof(u32), DMA_TO_DEVICE);
1544 tx->xfer.cmdptr = DMOV_CMD_ADDR(tx->mapped_cmd_ptr_ptr);
1545
1546 init_waitqueue_head(&rx->wait);
1547
1548 rx->pool = dma_pool_create("rx_buffer_pool", uport->dev,
1549 UARTDM_RX_BUF_SIZE, 16, 0);
1550 if (!rx->pool) {
1551 pr_err("%s(): cannot allocate rx_buffer_pool", __func__);
1552 ret = -ENOMEM;
1553 goto err_dma_pool_create;
1554 }
1555
1556 rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer);
1557 if (!rx->buffer) {
1558 pr_err("%s(): cannot allocate rx->buffer", __func__);
1559 ret = -ENOMEM;
1560 goto err_dma_pool_alloc;
1561 }
1562
1563 /* Allocate the command pointer. Needs to be 64 bit aligned */
1564 rx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
1565 if (!rx->command_ptr) {
1566 pr_err("%s(): cannot allocate rx->command_ptr", __func__);
1567 ret = -ENOMEM;
1568 goto err_rx_command_ptr;
1569 }
1570
1571 rx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA);
1572 if (!rx->command_ptr_ptr) {
1573 pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__);
1574 ret = -ENOMEM;
1575 goto err_rx_command_ptr_ptr;
1576 }
1577
1578 rx->command_ptr->num_rows = ((UARTDM_RX_BUF_SIZE >> 4) << 16) |
1579 (UARTDM_RX_BUF_SIZE >> 4);
1580
1581 rx->command_ptr->dst_row_addr = rx->rbuffer;
1582
1583 rx->mapped_cmd_ptr = dma_map_single(uport->dev, rx->command_ptr,
1584 sizeof(dmov_box), DMA_TO_DEVICE);
1585
1586 *rx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(rx->mapped_cmd_ptr);
1587
1588 rx->cmdptr_dmaaddr = dma_map_single(uport->dev, rx->command_ptr_ptr,
1589 sizeof(u32), DMA_TO_DEVICE);
1590 rx->xfer.cmdptr = DMOV_CMD_ADDR(rx->cmdptr_dmaaddr);
1591
1592 INIT_WORK(&rx->tty_work, msm_hs_tty_flip_buffer_work);
1593
1594 return ret;
1595
1596err_rx_command_ptr_ptr:
1597 kfree(rx->command_ptr);
1598err_rx_command_ptr:
1599 dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
1600 msm_uport->rx.rbuffer);
1601err_dma_pool_alloc:
1602 dma_pool_destroy(msm_uport->rx.pool);
1603err_dma_pool_create:
1604 dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr_ptr,
1605 sizeof(u32), DMA_TO_DEVICE);
1606 dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr,
1607 sizeof(dmov_box), DMA_TO_DEVICE);
1608 kfree(msm_uport->tx.command_ptr_ptr);
1609err_tx_command_ptr_ptr:
1610 kfree(msm_uport->tx.command_ptr);
1611 return ret;
1612}
1613
1614static int msm_hs_probe(struct platform_device *pdev)
1615{
1616 int ret;
1617 struct uart_port *uport;
1618 struct msm_hs_port *msm_uport;
1619 struct resource *resource;
1620 const struct msm_serial_hs_platform_data *pdata =
1621 dev_get_platdata(&pdev->dev);
1622
1623 if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
1624 printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
1625 return -EINVAL;
1626 }
1627
1628 msm_uport = &q_uart_port[pdev->id];
1629 uport = &msm_uport->uport;
1630
1631 uport->dev = &pdev->dev;
1632
1633 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1634 if (unlikely(!resource))
1635 return -ENXIO;
1636
1637 uport->mapbase = resource->start;
1638 uport->irq = platform_get_irq(pdev, 0);
1639 if (unlikely(uport->irq < 0))
1640 return -ENXIO;
1641
1642 if (unlikely(irq_set_irq_wake(uport->irq, 1)))
1643 return -ENXIO;
1644
1645 if (pdata == NULL || pdata->rx_wakeup_irq < 0)
1646 msm_uport->rx_wakeup.irq = -1;
1647 else {
1648 msm_uport->rx_wakeup.irq = pdata->rx_wakeup_irq;
1649 msm_uport->rx_wakeup.ignore = 1;
1650 msm_uport->rx_wakeup.inject_rx = pdata->inject_rx_on_wakeup;
1651 msm_uport->rx_wakeup.rx_to_inject = pdata->rx_to_inject;
1652
1653 if (unlikely(msm_uport->rx_wakeup.irq < 0))
1654 return -ENXIO;
1655
1656 if (unlikely(irq_set_irq_wake(msm_uport->rx_wakeup.irq, 1)))
1657 return -ENXIO;
1658 }
1659
1660 if (pdata == NULL)
1661 msm_uport->exit_lpm_cb = NULL;
1662 else
1663 msm_uport->exit_lpm_cb = pdata->exit_lpm_cb;
1664
1665 resource = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1666 "uartdm_channels");
1667 if (unlikely(!resource))
1668 return -ENXIO;
1669
1670 msm_uport->dma_tx_channel = resource->start;
1671 msm_uport->dma_rx_channel = resource->end;
1672
1673 resource = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1674 "uartdm_crci");
1675 if (unlikely(!resource))
1676 return -ENXIO;
1677
1678 msm_uport->dma_tx_crci = resource->start;
1679 msm_uport->dma_rx_crci = resource->end;
1680
1681 uport->iotype = UPIO_MEM;
1682 uport->fifosize = UART_FIFOSIZE;
1683 uport->ops = &msm_hs_ops;
1684 uport->flags = UPF_BOOT_AUTOCONF;
1685 uport->uartclk = UARTCLK;
1686 msm_uport->imr_reg = 0x0;
1687 msm_uport->clk = clk_get(&pdev->dev, "uartdm_clk");
1688 if (IS_ERR(msm_uport->clk))
1689 return PTR_ERR(msm_uport->clk);
1690
1691 ret = uartdm_init_port(uport);
1692 if (unlikely(ret))
1693 return ret;
1694
1695 msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
1696 hrtimer_init(&msm_uport->clk_off_timer, CLOCK_MONOTONIC,
1697 HRTIMER_MODE_REL);
1698 msm_uport->clk_off_timer.function = msm_hs_clk_off_retry;
1699 msm_uport->clk_off_delay = ktime_set(0, 1000000); /* 1ms */
1700
1701 uport->line = pdev->id;
1702 return uart_add_one_port(&msm_hs_driver, uport);
1703}
1704
1705static int __init msm_serial_hs_init(void)
1706{
1707 int ret, i;
1708
1709 /* Init all UARTS as non-configured */
1710 for (i = 0; i < UARTDM_NR; i++)
1711 q_uart_port[i].uport.type = PORT_UNKNOWN;
1712
1713 msm_hs_workqueue = create_singlethread_workqueue("msm_serial_hs");
1714 if (unlikely(!msm_hs_workqueue))
1715 return -ENOMEM;
1716
1717 ret = uart_register_driver(&msm_hs_driver);
1718 if (unlikely(ret)) {
1719 printk(KERN_ERR "%s failed to load\n", __func__);
1720 goto err_uart_register_driver;
1721 }
1722
1723 ret = platform_driver_register(&msm_serial_hs_platform_driver);
1724 if (ret) {
1725 printk(KERN_ERR "%s failed to load\n", __func__);
1726 goto err_platform_driver_register;
1727 }
1728
1729 return ret;
1730
1731err_platform_driver_register:
1732 uart_unregister_driver(&msm_hs_driver);
1733err_uart_register_driver:
1734 destroy_workqueue(msm_hs_workqueue);
1735 return ret;
1736}
1737module_init(msm_serial_hs_init);
1738
1739/*
1740 * Called by the upper layer when port is closed.
1741 * - Disables the port
1742 * - Unhook the ISR
1743 */
1744static void msm_hs_shutdown(struct uart_port *uport)
1745{
1746 unsigned long flags;
1747 struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
1748
1749 BUG_ON(msm_uport->rx.flush < FLUSH_STOP);
1750
1751 spin_lock_irqsave(&uport->lock, flags);
1752 clk_enable(msm_uport->clk);
1753
1754 /* Disable the transmitter */
1755 msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_DISABLE_BMSK);
1756 /* Disable the receiver */
1757 msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_DISABLE_BMSK);
1758
1759 pm_runtime_disable(uport->dev);
1760 pm_runtime_set_suspended(uport->dev);
1761
1762 /* Free the interrupt */
1763 free_irq(uport->irq, msm_uport);
1764 if (use_low_power_rx_wakeup(msm_uport))
1765 free_irq(msm_uport->rx_wakeup.irq, msm_uport);
1766
1767 msm_uport->imr_reg = 0;
1768 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
1769
1770 wait_event(msm_uport->rx.wait, msm_uport->rx.flush == FLUSH_SHUTDOWN);
1771
1772 clk_disable(msm_uport->clk); /* to balance local clk_enable() */
1773 if (msm_uport->clk_state != MSM_HS_CLK_OFF)
1774 clk_disable(msm_uport->clk); /* to balance clk_state */
1775 msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
1776
1777 dma_unmap_single(uport->dev, msm_uport->tx.dma_base,
1778 UART_XMIT_SIZE, DMA_TO_DEVICE);
1779
1780 spin_unlock_irqrestore(&uport->lock, flags);
1781
1782 if (cancel_work_sync(&msm_uport->rx.tty_work))
1783 msm_hs_tty_flip_buffer_work(&msm_uport->rx.tty_work);
1784}
1785
1786static void __exit msm_serial_hs_exit(void)
1787{
1788 flush_workqueue(msm_hs_workqueue);
1789 destroy_workqueue(msm_hs_workqueue);
1790 platform_driver_unregister(&msm_serial_hs_platform_driver);
1791 uart_unregister_driver(&msm_hs_driver);
1792}
1793module_exit(msm_serial_hs_exit);
1794
1795#ifdef CONFIG_PM_RUNTIME
1796static int msm_hs_runtime_idle(struct device *dev)
1797{
1798 /*
1799 * returning success from idle results in runtime suspend to be
1800 * called
1801 */
1802 return 0;
1803}
1804
1805static int msm_hs_runtime_resume(struct device *dev)
1806{
1807 struct platform_device *pdev = container_of(dev, struct
1808 platform_device, dev);
1809 struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
1810
1811 msm_hs_request_clock_on(&msm_uport->uport);
1812 return 0;
1813}
1814
1815static int msm_hs_runtime_suspend(struct device *dev)
1816{
1817 struct platform_device *pdev = container_of(dev, struct
1818 platform_device, dev);
1819 struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
1820
1821 msm_hs_request_clock_off(&msm_uport->uport);
1822 return 0;
1823}
1824#else
1825#define msm_hs_runtime_idle NULL
1826#define msm_hs_runtime_resume NULL
1827#define msm_hs_runtime_suspend NULL
1828#endif
1829
1830static const struct dev_pm_ops msm_hs_dev_pm_ops = {
1831 .runtime_suspend = msm_hs_runtime_suspend,
1832 .runtime_resume = msm_hs_runtime_resume,
1833 .runtime_idle = msm_hs_runtime_idle,
1834};
1835
1836static struct platform_driver msm_serial_hs_platform_driver = {
1837 .probe = msm_hs_probe,
1838 .remove = msm_hs_remove,
1839 .driver = {
1840 .name = "msm_serial_hs",
1841 .owner = THIS_MODULE,
1842 .pm = &msm_hs_dev_pm_ops,
1843 },
1844};
1845
1846static struct uart_driver msm_hs_driver = {
1847 .owner = THIS_MODULE,
1848 .driver_name = "msm_serial_hs",
1849 .dev_name = "ttyHS",
1850 .nr = UARTDM_NR,
1851 .cons = 0,
1852};
1853
1854static struct uart_ops msm_hs_ops = {
1855 .tx_empty = msm_hs_tx_empty,
1856 .set_mctrl = msm_hs_set_mctrl_locked,
1857 .get_mctrl = msm_hs_get_mctrl_locked,
1858 .stop_tx = msm_hs_stop_tx_locked,
1859 .start_tx = msm_hs_start_tx_locked,
1860 .stop_rx = msm_hs_stop_rx_locked,
1861 .enable_ms = msm_hs_enable_ms_locked,
1862 .break_ctl = msm_hs_break_ctl,
1863 .startup = msm_hs_startup,
1864 .shutdown = msm_hs_shutdown,
1865 .set_termios = msm_hs_set_termios,
1866 .pm = msm_hs_pm,
1867 .type = msm_hs_type,
1868 .config_port = msm_hs_config_port,
1869 .release_port = msm_hs_release_port,
1870 .request_port = msm_hs_request_port,
1871};
1872
1873MODULE_DESCRIPTION("High Speed UART Driver for the MSM chipset");
1874MODULE_VERSION("1.2");
1875MODULE_LICENSE("GPL v2");