Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/debugfs.h>
8#include <linux/delay.h>
9#include <linux/host1x.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/regulator/consumer.h>
16#include <linux/reset.h>
17
18#include <video/mipi_display.h>
19
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_debugfs.h>
22#include <drm/drm_file.h>
23#include <drm/drm_mipi_dsi.h>
24#include <drm/drm_panel.h>
25
26#include "dc.h"
27#include "drm.h"
28#include "dsi.h"
29#include "mipi-phy.h"
30#include "trace.h"
31
32struct tegra_dsi_state {
33 struct drm_connector_state base;
34
35 struct mipi_dphy_timing timing;
36 unsigned long period;
37
38 unsigned int vrefresh;
39 unsigned int lanes;
40 unsigned long pclk;
41 unsigned long bclk;
42
43 enum tegra_dsi_format format;
44 unsigned int mul;
45 unsigned int div;
46};
47
48static inline struct tegra_dsi_state *
49to_dsi_state(struct drm_connector_state *state)
50{
51 return container_of(state, struct tegra_dsi_state, base);
52}
53
54struct tegra_dsi {
55 struct host1x_client client;
56 struct tegra_output output;
57 struct device *dev;
58
59 void __iomem *regs;
60
61 struct reset_control *rst;
62 struct clk *clk_parent;
63 struct clk *clk_lp;
64 struct clk *clk;
65
66 struct drm_info_list *debugfs_files;
67
68 unsigned long flags;
69 enum mipi_dsi_pixel_format format;
70 unsigned int lanes;
71
72 struct tegra_mipi_device *mipi;
73 struct mipi_dsi_host host;
74
75 struct regulator *vdd;
76
77 unsigned int video_fifo_depth;
78 unsigned int host_fifo_depth;
79
80 /* for ganged-mode support */
81 struct tegra_dsi *master;
82 struct tegra_dsi *slave;
83};
84
85static inline struct tegra_dsi *
86host1x_client_to_dsi(struct host1x_client *client)
87{
88 return container_of(client, struct tegra_dsi, client);
89}
90
91static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
92{
93 return container_of(host, struct tegra_dsi, host);
94}
95
96static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
97{
98 return container_of(output, struct tegra_dsi, output);
99}
100
101static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
102{
103 return to_dsi_state(dsi->output.connector.state);
104}
105
106static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
107{
108 u32 value = readl(dsi->regs + (offset << 2));
109
110 trace_dsi_readl(dsi->dev, offset, value);
111
112 return value;
113}
114
115static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
116 unsigned int offset)
117{
118 trace_dsi_writel(dsi->dev, offset, value);
119 writel(value, dsi->regs + (offset << 2));
120}
121
122#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
123
124static const struct debugfs_reg32 tegra_dsi_regs[] = {
125 DEBUGFS_REG32(DSI_INCR_SYNCPT),
126 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
127 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
128 DEBUGFS_REG32(DSI_CTXSW),
129 DEBUGFS_REG32(DSI_RD_DATA),
130 DEBUGFS_REG32(DSI_WR_DATA),
131 DEBUGFS_REG32(DSI_POWER_CONTROL),
132 DEBUGFS_REG32(DSI_INT_ENABLE),
133 DEBUGFS_REG32(DSI_INT_STATUS),
134 DEBUGFS_REG32(DSI_INT_MASK),
135 DEBUGFS_REG32(DSI_HOST_CONTROL),
136 DEBUGFS_REG32(DSI_CONTROL),
137 DEBUGFS_REG32(DSI_SOL_DELAY),
138 DEBUGFS_REG32(DSI_MAX_THRESHOLD),
139 DEBUGFS_REG32(DSI_TRIGGER),
140 DEBUGFS_REG32(DSI_TX_CRC),
141 DEBUGFS_REG32(DSI_STATUS),
142 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
143 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
144 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
151 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
152 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
153 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
154 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
155 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
156 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
157 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
158 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
159 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
160 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
161 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
162 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
163 DEBUGFS_REG32(DSI_DCS_CMDS),
164 DEBUGFS_REG32(DSI_PKT_LEN_0_1),
165 DEBUGFS_REG32(DSI_PKT_LEN_2_3),
166 DEBUGFS_REG32(DSI_PKT_LEN_4_5),
167 DEBUGFS_REG32(DSI_PKT_LEN_6_7),
168 DEBUGFS_REG32(DSI_PHY_TIMING_0),
169 DEBUGFS_REG32(DSI_PHY_TIMING_1),
170 DEBUGFS_REG32(DSI_PHY_TIMING_2),
171 DEBUGFS_REG32(DSI_BTA_TIMING),
172 DEBUGFS_REG32(DSI_TIMEOUT_0),
173 DEBUGFS_REG32(DSI_TIMEOUT_1),
174 DEBUGFS_REG32(DSI_TO_TALLY),
175 DEBUGFS_REG32(DSI_PAD_CONTROL_0),
176 DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
177 DEBUGFS_REG32(DSI_PAD_CD_STATUS),
178 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
179 DEBUGFS_REG32(DSI_PAD_CONTROL_1),
180 DEBUGFS_REG32(DSI_PAD_CONTROL_2),
181 DEBUGFS_REG32(DSI_PAD_CONTROL_3),
182 DEBUGFS_REG32(DSI_PAD_CONTROL_4),
183 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
184 DEBUGFS_REG32(DSI_GANGED_MODE_START),
185 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
186 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
187 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
188 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
189 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
196};
197
198static int tegra_dsi_show_regs(struct seq_file *s, void *data)
199{
200 struct drm_info_node *node = s->private;
201 struct tegra_dsi *dsi = node->info_ent->data;
202 struct drm_crtc *crtc = dsi->output.encoder.crtc;
203 struct drm_device *drm = node->minor->dev;
204 unsigned int i;
205 int err = 0;
206
207 drm_modeset_lock_all(drm);
208
209 if (!crtc || !crtc->state->active) {
210 err = -EBUSY;
211 goto unlock;
212 }
213
214 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
215 unsigned int offset = tegra_dsi_regs[i].offset;
216
217 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
218 offset, tegra_dsi_readl(dsi, offset));
219 }
220
221unlock:
222 drm_modeset_unlock_all(drm);
223 return err;
224}
225
226static struct drm_info_list debugfs_files[] = {
227 { "regs", tegra_dsi_show_regs, 0, NULL },
228};
229
230static int tegra_dsi_late_register(struct drm_connector *connector)
231{
232 struct tegra_output *output = connector_to_output(connector);
233 unsigned int i, count = ARRAY_SIZE(debugfs_files);
234 struct drm_minor *minor = connector->dev->primary;
235 struct dentry *root = connector->debugfs_entry;
236 struct tegra_dsi *dsi = to_dsi(output);
237 int err;
238
239 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
240 GFP_KERNEL);
241 if (!dsi->debugfs_files)
242 return -ENOMEM;
243
244 for (i = 0; i < count; i++)
245 dsi->debugfs_files[i].data = dsi;
246
247 err = drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
248 if (err < 0)
249 goto free;
250
251 return 0;
252
253free:
254 kfree(dsi->debugfs_files);
255 dsi->debugfs_files = NULL;
256
257 return err;
258}
259
260static void tegra_dsi_early_unregister(struct drm_connector *connector)
261{
262 struct tegra_output *output = connector_to_output(connector);
263 unsigned int count = ARRAY_SIZE(debugfs_files);
264 struct tegra_dsi *dsi = to_dsi(output);
265
266 drm_debugfs_remove_files(dsi->debugfs_files, count,
267 connector->dev->primary);
268 kfree(dsi->debugfs_files);
269 dsi->debugfs_files = NULL;
270}
271
272#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
273#define PKT_LEN0(len) (((len) & 0x07) << 0)
274#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
275#define PKT_LEN1(len) (((len) & 0x07) << 10)
276#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
277#define PKT_LEN2(len) (((len) & 0x07) << 20)
278
279#define PKT_LP (1 << 30)
280#define NUM_PKT_SEQ 12
281
282/*
283 * non-burst mode with sync pulses
284 */
285static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
286 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
287 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
288 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
289 PKT_LP,
290 [ 1] = 0,
291 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
292 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
293 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
294 PKT_LP,
295 [ 3] = 0,
296 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
297 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
298 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
299 PKT_LP,
300 [ 5] = 0,
301 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
302 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
303 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
304 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
305 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
306 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
307 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
309 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
310 PKT_LP,
311 [ 9] = 0,
312 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
313 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
314 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
315 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
316 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
317 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
318};
319
320/*
321 * non-burst mode with sync events
322 */
323static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
324 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
325 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
326 PKT_LP,
327 [ 1] = 0,
328 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
329 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
330 PKT_LP,
331 [ 3] = 0,
332 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
333 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
334 PKT_LP,
335 [ 5] = 0,
336 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
337 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
338 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
339 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
340 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
341 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
342 PKT_LP,
343 [ 9] = 0,
344 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
345 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
346 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
347 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
348};
349
350static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
351 [ 0] = 0,
352 [ 1] = 0,
353 [ 2] = 0,
354 [ 3] = 0,
355 [ 4] = 0,
356 [ 5] = 0,
357 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
358 [ 7] = 0,
359 [ 8] = 0,
360 [ 9] = 0,
361 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
362 [11] = 0,
363};
364
365static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
366 unsigned long period,
367 const struct mipi_dphy_timing *timing)
368{
369 u32 value;
370
371 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
372 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
373 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
374 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
375 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
376
377 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
378 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
379 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
380 DSI_TIMING_FIELD(timing->lpx, period, 1);
381 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
382
383 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
384 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
385 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
386 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
387
388 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
389 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
390 DSI_TIMING_FIELD(timing->tago, period, 1);
391 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
392
393 if (dsi->slave)
394 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
395}
396
397static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
398 unsigned int *mulp, unsigned int *divp)
399{
400 switch (format) {
401 case MIPI_DSI_FMT_RGB666_PACKED:
402 case MIPI_DSI_FMT_RGB888:
403 *mulp = 3;
404 *divp = 1;
405 break;
406
407 case MIPI_DSI_FMT_RGB565:
408 *mulp = 2;
409 *divp = 1;
410 break;
411
412 case MIPI_DSI_FMT_RGB666:
413 *mulp = 9;
414 *divp = 4;
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 return 0;
422}
423
424static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
425 enum tegra_dsi_format *fmt)
426{
427 switch (format) {
428 case MIPI_DSI_FMT_RGB888:
429 *fmt = TEGRA_DSI_FORMAT_24P;
430 break;
431
432 case MIPI_DSI_FMT_RGB666:
433 *fmt = TEGRA_DSI_FORMAT_18NP;
434 break;
435
436 case MIPI_DSI_FMT_RGB666_PACKED:
437 *fmt = TEGRA_DSI_FORMAT_18P;
438 break;
439
440 case MIPI_DSI_FMT_RGB565:
441 *fmt = TEGRA_DSI_FORMAT_16P;
442 break;
443
444 default:
445 return -EINVAL;
446 }
447
448 return 0;
449}
450
451static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
452 unsigned int size)
453{
454 u32 value;
455
456 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
457 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
458
459 value = DSI_GANGED_MODE_CONTROL_ENABLE;
460 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
461}
462
463static void tegra_dsi_enable(struct tegra_dsi *dsi)
464{
465 u32 value;
466
467 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
468 value |= DSI_POWER_CONTROL_ENABLE;
469 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
470
471 if (dsi->slave)
472 tegra_dsi_enable(dsi->slave);
473}
474
475static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
476{
477 if (dsi->master)
478 return dsi->master->lanes + dsi->lanes;
479
480 if (dsi->slave)
481 return dsi->lanes + dsi->slave->lanes;
482
483 return dsi->lanes;
484}
485
486static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
487 const struct drm_display_mode *mode)
488{
489 unsigned int hact, hsw, hbp, hfp, i, mul, div;
490 struct tegra_dsi_state *state;
491 const u32 *pkt_seq;
492 u32 value;
493
494 /* XXX: pass in state into this function? */
495 if (dsi->master)
496 state = tegra_dsi_get_state(dsi->master);
497 else
498 state = tegra_dsi_get_state(dsi);
499
500 mul = state->mul;
501 div = state->div;
502
503 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
504 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
505 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
506 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
507 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
508 pkt_seq = pkt_seq_video_non_burst_sync_events;
509 } else {
510 DRM_DEBUG_KMS("Command mode\n");
511 pkt_seq = pkt_seq_command_mode;
512 }
513
514 value = DSI_CONTROL_CHANNEL(0) |
515 DSI_CONTROL_FORMAT(state->format) |
516 DSI_CONTROL_LANES(dsi->lanes - 1) |
517 DSI_CONTROL_SOURCE(pipe);
518 tegra_dsi_writel(dsi, value, DSI_CONTROL);
519
520 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
521
522 value = DSI_HOST_CONTROL_HS;
523 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
524
525 value = tegra_dsi_readl(dsi, DSI_CONTROL);
526
527 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
528 value |= DSI_CONTROL_HS_CLK_CTRL;
529
530 value &= ~DSI_CONTROL_TX_TRIG(3);
531
532 /* enable DCS commands for command mode */
533 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
534 value &= ~DSI_CONTROL_DCS_ENABLE;
535 else
536 value |= DSI_CONTROL_DCS_ENABLE;
537
538 value |= DSI_CONTROL_VIDEO_ENABLE;
539 value &= ~DSI_CONTROL_HOST_ENABLE;
540 tegra_dsi_writel(dsi, value, DSI_CONTROL);
541
542 for (i = 0; i < NUM_PKT_SEQ; i++)
543 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
544
545 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
546 /* horizontal active pixels */
547 hact = mode->hdisplay * mul / div;
548
549 /* horizontal sync width */
550 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
551
552 /* horizontal back porch */
553 hbp = (mode->htotal - mode->hsync_end) * mul / div;
554
555 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
556 hbp += hsw;
557
558 /* horizontal front porch */
559 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
560
561 /* subtract packet overhead */
562 hsw -= 10;
563 hbp -= 14;
564 hfp -= 8;
565
566 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
567 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
568 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
569 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
570
571 /* set SOL delay (for non-burst mode only) */
572 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
573
574 /* TODO: implement ganged mode */
575 } else {
576 u16 bytes;
577
578 if (dsi->master || dsi->slave) {
579 /*
580 * For ganged mode, assume symmetric left-right mode.
581 */
582 bytes = 1 + (mode->hdisplay / 2) * mul / div;
583 } else {
584 /* 1 byte (DCS command) + pixel data */
585 bytes = 1 + mode->hdisplay * mul / div;
586 }
587
588 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
589 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
590 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
591 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
592
593 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
594 MIPI_DCS_WRITE_MEMORY_CONTINUE;
595 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
596
597 /* set SOL delay */
598 if (dsi->master || dsi->slave) {
599 unsigned long delay, bclk, bclk_ganged;
600 unsigned int lanes = state->lanes;
601
602 /* SOL to valid, valid to FIFO and FIFO write delay */
603 delay = 4 + 4 + 2;
604 delay = DIV_ROUND_UP(delay * mul, div * lanes);
605 /* FIFO read delay */
606 delay = delay + 6;
607
608 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
609 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
610 value = bclk - bclk_ganged + delay + 20;
611 } else {
612 /* TODO: revisit for non-ganged mode */
613 value = 8 * mul / div;
614 }
615
616 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
617 }
618
619 if (dsi->slave) {
620 tegra_dsi_configure(dsi->slave, pipe, mode);
621
622 /*
623 * TODO: Support modes other than symmetrical left-right
624 * split.
625 */
626 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
627 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
628 mode->hdisplay / 2);
629 }
630}
631
632static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
633{
634 u32 value;
635
636 timeout = jiffies + msecs_to_jiffies(timeout);
637
638 while (time_before(jiffies, timeout)) {
639 value = tegra_dsi_readl(dsi, DSI_STATUS);
640 if (value & DSI_STATUS_IDLE)
641 return 0;
642
643 usleep_range(1000, 2000);
644 }
645
646 return -ETIMEDOUT;
647}
648
649static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
650{
651 u32 value;
652
653 value = tegra_dsi_readl(dsi, DSI_CONTROL);
654 value &= ~DSI_CONTROL_VIDEO_ENABLE;
655 tegra_dsi_writel(dsi, value, DSI_CONTROL);
656
657 if (dsi->slave)
658 tegra_dsi_video_disable(dsi->slave);
659}
660
661static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
662{
663 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
664 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
665 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
666}
667
668static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
669{
670 u32 value;
671
672 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
673 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
674
675 return 0;
676}
677
678static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
679{
680 u32 value;
681
682 /*
683 * XXX Is this still needed? The module reset is deasserted right
684 * before this function is called.
685 */
686 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
687 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
688 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
689 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
690 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
691
692 /* start calibration */
693 tegra_dsi_pad_enable(dsi);
694
695 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
696 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
697 DSI_PAD_OUT_CLK(0x0);
698 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
699
700 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
701 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
702 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
703
704 return tegra_mipi_calibrate(dsi->mipi);
705}
706
707static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
708 unsigned int vrefresh)
709{
710 unsigned int timeout;
711 u32 value;
712
713 /* one frame high-speed transmission timeout */
714 timeout = (bclk / vrefresh) / 512;
715 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
716 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
717
718 /* 2 ms peripheral timeout for panel */
719 timeout = 2 * bclk / 512 * 1000;
720 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
721 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
722
723 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
724 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
725
726 if (dsi->slave)
727 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
728}
729
730static void tegra_dsi_disable(struct tegra_dsi *dsi)
731{
732 u32 value;
733
734 if (dsi->slave) {
735 tegra_dsi_ganged_disable(dsi->slave);
736 tegra_dsi_ganged_disable(dsi);
737 }
738
739 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
740 value &= ~DSI_POWER_CONTROL_ENABLE;
741 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
742
743 if (dsi->slave)
744 tegra_dsi_disable(dsi->slave);
745
746 usleep_range(5000, 10000);
747}
748
749static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
750{
751 u32 value;
752
753 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
754 value &= ~DSI_POWER_CONTROL_ENABLE;
755 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
756
757 usleep_range(300, 1000);
758
759 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
760 value |= DSI_POWER_CONTROL_ENABLE;
761 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
762
763 usleep_range(300, 1000);
764
765 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
766 if (value)
767 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
768
769 if (dsi->slave)
770 tegra_dsi_soft_reset(dsi->slave);
771}
772
773static void tegra_dsi_connector_reset(struct drm_connector *connector)
774{
775 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
776
777 if (!state)
778 return;
779
780 if (connector->state) {
781 __drm_atomic_helper_connector_destroy_state(connector->state);
782 kfree(connector->state);
783 }
784
785 __drm_atomic_helper_connector_reset(connector, &state->base);
786}
787
788static struct drm_connector_state *
789tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
790{
791 struct tegra_dsi_state *state = to_dsi_state(connector->state);
792 struct tegra_dsi_state *copy;
793
794 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
795 if (!copy)
796 return NULL;
797
798 __drm_atomic_helper_connector_duplicate_state(connector,
799 ©->base);
800
801 return ©->base;
802}
803
804static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
805 .reset = tegra_dsi_connector_reset,
806 .detect = tegra_output_connector_detect,
807 .fill_modes = drm_helper_probe_single_connector_modes,
808 .destroy = tegra_output_connector_destroy,
809 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
810 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
811 .late_register = tegra_dsi_late_register,
812 .early_unregister = tegra_dsi_early_unregister,
813};
814
815static enum drm_mode_status
816tegra_dsi_connector_mode_valid(struct drm_connector *connector,
817 struct drm_display_mode *mode)
818{
819 return MODE_OK;
820}
821
822static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
823 .get_modes = tegra_output_connector_get_modes,
824 .mode_valid = tegra_dsi_connector_mode_valid,
825};
826
827static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
828 .destroy = tegra_output_encoder_destroy,
829};
830
831static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
832{
833 int err;
834
835 if (dsi->slave)
836 tegra_dsi_unprepare(dsi->slave);
837
838 err = tegra_mipi_disable(dsi->mipi);
839 if (err < 0)
840 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
841 err);
842
843 pm_runtime_put(dsi->dev);
844}
845
846static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
847{
848 struct tegra_output *output = encoder_to_output(encoder);
849 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
850 struct tegra_dsi *dsi = to_dsi(output);
851 u32 value;
852 int err;
853
854 if (output->panel)
855 drm_panel_disable(output->panel);
856
857 tegra_dsi_video_disable(dsi);
858
859 /*
860 * The following accesses registers of the display controller, so make
861 * sure it's only executed when the output is attached to one.
862 */
863 if (dc) {
864 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
865 value &= ~DSI_ENABLE;
866 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
867
868 tegra_dc_commit(dc);
869 }
870
871 err = tegra_dsi_wait_idle(dsi, 100);
872 if (err < 0)
873 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
874
875 tegra_dsi_soft_reset(dsi);
876
877 if (output->panel)
878 drm_panel_unprepare(output->panel);
879
880 tegra_dsi_disable(dsi);
881
882 tegra_dsi_unprepare(dsi);
883}
884
885static void tegra_dsi_prepare(struct tegra_dsi *dsi)
886{
887 int err;
888
889 pm_runtime_get_sync(dsi->dev);
890
891 err = tegra_mipi_enable(dsi->mipi);
892 if (err < 0)
893 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
894 err);
895
896 err = tegra_dsi_pad_calibrate(dsi);
897 if (err < 0)
898 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
899
900 if (dsi->slave)
901 tegra_dsi_prepare(dsi->slave);
902}
903
904static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
905{
906 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
907 struct tegra_output *output = encoder_to_output(encoder);
908 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
909 struct tegra_dsi *dsi = to_dsi(output);
910 struct tegra_dsi_state *state;
911 u32 value;
912
913 tegra_dsi_prepare(dsi);
914
915 state = tegra_dsi_get_state(dsi);
916
917 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
918
919 /*
920 * The D-PHY timing fields are expressed in byte-clock cycles, so
921 * multiply the period by 8.
922 */
923 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
924
925 if (output->panel)
926 drm_panel_prepare(output->panel);
927
928 tegra_dsi_configure(dsi, dc->pipe, mode);
929
930 /* enable display controller */
931 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
932 value |= DSI_ENABLE;
933 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
934
935 tegra_dc_commit(dc);
936
937 /* enable DSI controller */
938 tegra_dsi_enable(dsi);
939
940 if (output->panel)
941 drm_panel_enable(output->panel);
942}
943
944static int
945tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
946 struct drm_crtc_state *crtc_state,
947 struct drm_connector_state *conn_state)
948{
949 struct tegra_output *output = encoder_to_output(encoder);
950 struct tegra_dsi_state *state = to_dsi_state(conn_state);
951 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
952 struct tegra_dsi *dsi = to_dsi(output);
953 unsigned int scdiv;
954 unsigned long plld;
955 int err;
956
957 state->pclk = crtc_state->mode.clock * 1000;
958
959 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
960 if (err < 0)
961 return err;
962
963 state->lanes = tegra_dsi_get_lanes(dsi);
964
965 err = tegra_dsi_get_format(dsi->format, &state->format);
966 if (err < 0)
967 return err;
968
969 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
970
971 /* compute byte clock */
972 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
973
974 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
975 state->lanes);
976 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
977 state->vrefresh);
978 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
979
980 /*
981 * Compute bit clock and round up to the next MHz.
982 */
983 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
984 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
985
986 err = mipi_dphy_timing_get_default(&state->timing, state->period);
987 if (err < 0)
988 return err;
989
990 err = mipi_dphy_timing_validate(&state->timing, state->period);
991 if (err < 0) {
992 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
993 return err;
994 }
995
996 /*
997 * We divide the frequency by two here, but we make up for that by
998 * setting the shift clock divider (further below) to half of the
999 * correct value.
1000 */
1001 plld /= 2;
1002
1003 /*
1004 * Derive pixel clock from bit clock using the shift clock divider.
1005 * Note that this is only half of what we would expect, but we need
1006 * that to make up for the fact that we divided the bit clock by a
1007 * factor of two above.
1008 *
1009 * It's not clear exactly why this is necessary, but the display is
1010 * not working properly otherwise. Perhaps the PLLs cannot generate
1011 * frequencies sufficiently high.
1012 */
1013 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1014
1015 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
1016 plld, scdiv);
1017 if (err < 0) {
1018 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1019 return err;
1020 }
1021
1022 return err;
1023}
1024
1025static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1026 .disable = tegra_dsi_encoder_disable,
1027 .enable = tegra_dsi_encoder_enable,
1028 .atomic_check = tegra_dsi_encoder_atomic_check,
1029};
1030
1031static int tegra_dsi_init(struct host1x_client *client)
1032{
1033 struct drm_device *drm = dev_get_drvdata(client->parent);
1034 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1035 int err;
1036
1037 /* Gangsters must not register their own outputs. */
1038 if (!dsi->master) {
1039 dsi->output.dev = client->dev;
1040
1041 drm_connector_init(drm, &dsi->output.connector,
1042 &tegra_dsi_connector_funcs,
1043 DRM_MODE_CONNECTOR_DSI);
1044 drm_connector_helper_add(&dsi->output.connector,
1045 &tegra_dsi_connector_helper_funcs);
1046 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1047
1048 drm_encoder_init(drm, &dsi->output.encoder,
1049 &tegra_dsi_encoder_funcs,
1050 DRM_MODE_ENCODER_DSI, NULL);
1051 drm_encoder_helper_add(&dsi->output.encoder,
1052 &tegra_dsi_encoder_helper_funcs);
1053
1054 drm_connector_attach_encoder(&dsi->output.connector,
1055 &dsi->output.encoder);
1056 drm_connector_register(&dsi->output.connector);
1057
1058 err = tegra_output_init(drm, &dsi->output);
1059 if (err < 0)
1060 dev_err(dsi->dev, "failed to initialize output: %d\n",
1061 err);
1062
1063 dsi->output.encoder.possible_crtcs = 0x3;
1064 }
1065
1066 return 0;
1067}
1068
1069static int tegra_dsi_exit(struct host1x_client *client)
1070{
1071 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1072
1073 tegra_output_exit(&dsi->output);
1074
1075 return 0;
1076}
1077
1078static const struct host1x_client_ops dsi_client_ops = {
1079 .init = tegra_dsi_init,
1080 .exit = tegra_dsi_exit,
1081};
1082
1083static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1084{
1085 struct clk *parent;
1086 int err;
1087
1088 parent = clk_get_parent(dsi->clk);
1089 if (!parent)
1090 return -EINVAL;
1091
1092 err = clk_set_parent(parent, dsi->clk_parent);
1093 if (err < 0)
1094 return err;
1095
1096 return 0;
1097}
1098
1099static const char * const error_report[16] = {
1100 "SoT Error",
1101 "SoT Sync Error",
1102 "EoT Sync Error",
1103 "Escape Mode Entry Command Error",
1104 "Low-Power Transmit Sync Error",
1105 "Peripheral Timeout Error",
1106 "False Control Error",
1107 "Contention Detected",
1108 "ECC Error, single-bit",
1109 "ECC Error, multi-bit",
1110 "Checksum Error",
1111 "DSI Data Type Not Recognized",
1112 "DSI VC ID Invalid",
1113 "Invalid Transmission Length",
1114 "Reserved",
1115 "DSI Protocol Violation",
1116};
1117
1118static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1119 const struct mipi_dsi_msg *msg,
1120 size_t count)
1121{
1122 u8 *rx = msg->rx_buf;
1123 unsigned int i, j, k;
1124 size_t size = 0;
1125 u16 errors;
1126 u32 value;
1127
1128 /* read and parse packet header */
1129 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1130
1131 switch (value & 0x3f) {
1132 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1133 errors = (value >> 8) & 0xffff;
1134 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1135 errors);
1136 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1137 if (errors & BIT(i))
1138 dev_dbg(dsi->dev, " %2u: %s\n", i,
1139 error_report[i]);
1140 break;
1141
1142 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1143 rx[0] = (value >> 8) & 0xff;
1144 size = 1;
1145 break;
1146
1147 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1148 rx[0] = (value >> 8) & 0xff;
1149 rx[1] = (value >> 16) & 0xff;
1150 size = 2;
1151 break;
1152
1153 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1154 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1155 break;
1156
1157 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1158 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1159 break;
1160
1161 default:
1162 dev_err(dsi->dev, "unhandled response type: %02x\n",
1163 value & 0x3f);
1164 return -EPROTO;
1165 }
1166
1167 size = min(size, msg->rx_len);
1168
1169 if (msg->rx_buf && size > 0) {
1170 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1171 u8 *rx = msg->rx_buf + j;
1172
1173 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1174
1175 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1176 rx[j + k] = (value >> (k << 3)) & 0xff;
1177 }
1178 }
1179
1180 return size;
1181}
1182
1183static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1184{
1185 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1186
1187 timeout = jiffies + msecs_to_jiffies(timeout);
1188
1189 while (time_before(jiffies, timeout)) {
1190 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1191 if ((value & DSI_TRIGGER_HOST) == 0)
1192 return 0;
1193
1194 usleep_range(1000, 2000);
1195 }
1196
1197 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1198 return -ETIMEDOUT;
1199}
1200
1201static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1202 unsigned long timeout)
1203{
1204 timeout = jiffies + msecs_to_jiffies(250);
1205
1206 while (time_before(jiffies, timeout)) {
1207 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1208 u8 count = value & 0x1f;
1209
1210 if (count > 0)
1211 return count;
1212
1213 usleep_range(1000, 2000);
1214 }
1215
1216 DRM_DEBUG_KMS("peripheral returned no data\n");
1217 return -ETIMEDOUT;
1218}
1219
1220static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1221 const void *buffer, size_t size)
1222{
1223 const u8 *buf = buffer;
1224 size_t i, j;
1225 u32 value;
1226
1227 for (j = 0; j < size; j += 4) {
1228 value = 0;
1229
1230 for (i = 0; i < 4 && j + i < size; i++)
1231 value |= buf[j + i] << (i << 3);
1232
1233 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1234 }
1235}
1236
1237static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1238 const struct mipi_dsi_msg *msg)
1239{
1240 struct tegra_dsi *dsi = host_to_tegra(host);
1241 struct mipi_dsi_packet packet;
1242 const u8 *header;
1243 size_t count;
1244 ssize_t err;
1245 u32 value;
1246
1247 err = mipi_dsi_create_packet(&packet, msg);
1248 if (err < 0)
1249 return err;
1250
1251 header = packet.header;
1252
1253 /* maximum FIFO depth is 1920 words */
1254 if (packet.size > dsi->video_fifo_depth * 4)
1255 return -ENOSPC;
1256
1257 /* reset underflow/overflow flags */
1258 value = tegra_dsi_readl(dsi, DSI_STATUS);
1259 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1260 value = DSI_HOST_CONTROL_FIFO_RESET;
1261 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1262 usleep_range(10, 20);
1263 }
1264
1265 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1266 value |= DSI_POWER_CONTROL_ENABLE;
1267 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1268
1269 usleep_range(5000, 10000);
1270
1271 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1272 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1273
1274 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1275 value |= DSI_HOST_CONTROL_HS;
1276
1277 /*
1278 * The host FIFO has a maximum of 64 words, so larger transmissions
1279 * need to use the video FIFO.
1280 */
1281 if (packet.size > dsi->host_fifo_depth * 4)
1282 value |= DSI_HOST_CONTROL_FIFO_SEL;
1283
1284 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1285
1286 /*
1287 * For reads and messages with explicitly requested ACK, generate a
1288 * BTA sequence after the transmission of the packet.
1289 */
1290 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1291 (msg->rx_buf && msg->rx_len > 0)) {
1292 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1293 value |= DSI_HOST_CONTROL_PKT_BTA;
1294 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1295 }
1296
1297 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1298 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1299
1300 /* write packet header, ECC is generated by hardware */
1301 value = header[2] << 16 | header[1] << 8 | header[0];
1302 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1303
1304 /* write payload (if any) */
1305 if (packet.payload_length > 0)
1306 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1307 packet.payload_length);
1308
1309 err = tegra_dsi_transmit(dsi, 250);
1310 if (err < 0)
1311 return err;
1312
1313 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1314 (msg->rx_buf && msg->rx_len > 0)) {
1315 err = tegra_dsi_wait_for_response(dsi, 250);
1316 if (err < 0)
1317 return err;
1318
1319 count = err;
1320
1321 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1322 switch (value) {
1323 case 0x84:
1324 /*
1325 dev_dbg(dsi->dev, "ACK\n");
1326 */
1327 break;
1328
1329 case 0x87:
1330 /*
1331 dev_dbg(dsi->dev, "ESCAPE\n");
1332 */
1333 break;
1334
1335 default:
1336 dev_err(dsi->dev, "unknown status: %08x\n", value);
1337 break;
1338 }
1339
1340 if (count > 1) {
1341 err = tegra_dsi_read_response(dsi, msg, count);
1342 if (err < 0)
1343 dev_err(dsi->dev,
1344 "failed to parse response: %zd\n",
1345 err);
1346 else {
1347 /*
1348 * For read commands, return the number of
1349 * bytes returned by the peripheral.
1350 */
1351 count = err;
1352 }
1353 }
1354 } else {
1355 /*
1356 * For write commands, we have transmitted the 4-byte header
1357 * plus the variable-length payload.
1358 */
1359 count = 4 + packet.payload_length;
1360 }
1361
1362 return count;
1363}
1364
1365static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1366{
1367 struct clk *parent;
1368 int err;
1369
1370 /* make sure both DSI controllers share the same PLL */
1371 parent = clk_get_parent(dsi->slave->clk);
1372 if (!parent)
1373 return -EINVAL;
1374
1375 err = clk_set_parent(parent, dsi->clk_parent);
1376 if (err < 0)
1377 return err;
1378
1379 return 0;
1380}
1381
1382static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1383 struct mipi_dsi_device *device)
1384{
1385 struct tegra_dsi *dsi = host_to_tegra(host);
1386
1387 dsi->flags = device->mode_flags;
1388 dsi->format = device->format;
1389 dsi->lanes = device->lanes;
1390
1391 if (dsi->slave) {
1392 int err;
1393
1394 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1395 dev_name(&device->dev));
1396
1397 err = tegra_dsi_ganged_setup(dsi);
1398 if (err < 0) {
1399 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1400 err);
1401 return err;
1402 }
1403 }
1404
1405 /*
1406 * Slaves don't have a panel associated with them, so they provide
1407 * merely the second channel.
1408 */
1409 if (!dsi->master) {
1410 struct tegra_output *output = &dsi->output;
1411
1412 output->panel = of_drm_find_panel(device->dev.of_node);
1413 if (IS_ERR(output->panel))
1414 output->panel = NULL;
1415
1416 if (output->panel && output->connector.dev) {
1417 drm_panel_attach(output->panel, &output->connector);
1418 drm_helper_hpd_irq_event(output->connector.dev);
1419 }
1420 }
1421
1422 return 0;
1423}
1424
1425static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1426 struct mipi_dsi_device *device)
1427{
1428 struct tegra_dsi *dsi = host_to_tegra(host);
1429 struct tegra_output *output = &dsi->output;
1430
1431 if (output->panel && &device->dev == output->panel->dev) {
1432 output->panel = NULL;
1433
1434 if (output->connector.dev)
1435 drm_helper_hpd_irq_event(output->connector.dev);
1436 }
1437
1438 return 0;
1439}
1440
1441static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1442 .attach = tegra_dsi_host_attach,
1443 .detach = tegra_dsi_host_detach,
1444 .transfer = tegra_dsi_host_transfer,
1445};
1446
1447static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1448{
1449 struct device_node *np;
1450
1451 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1452 if (np) {
1453 struct platform_device *gangster = of_find_device_by_node(np);
1454
1455 dsi->slave = platform_get_drvdata(gangster);
1456 of_node_put(np);
1457
1458 if (!dsi->slave)
1459 return -EPROBE_DEFER;
1460
1461 dsi->slave->master = dsi;
1462 }
1463
1464 return 0;
1465}
1466
1467static int tegra_dsi_probe(struct platform_device *pdev)
1468{
1469 struct tegra_dsi *dsi;
1470 struct resource *regs;
1471 int err;
1472
1473 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1474 if (!dsi)
1475 return -ENOMEM;
1476
1477 dsi->output.dev = dsi->dev = &pdev->dev;
1478 dsi->video_fifo_depth = 1920;
1479 dsi->host_fifo_depth = 64;
1480
1481 err = tegra_dsi_ganged_probe(dsi);
1482 if (err < 0)
1483 return err;
1484
1485 err = tegra_output_probe(&dsi->output);
1486 if (err < 0)
1487 return err;
1488
1489 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1490
1491 /*
1492 * Assume these values by default. When a DSI peripheral driver
1493 * attaches to the DSI host, the parameters will be taken from
1494 * the attached device.
1495 */
1496 dsi->flags = MIPI_DSI_MODE_VIDEO;
1497 dsi->format = MIPI_DSI_FMT_RGB888;
1498 dsi->lanes = 4;
1499
1500 if (!pdev->dev.pm_domain) {
1501 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1502 if (IS_ERR(dsi->rst))
1503 return PTR_ERR(dsi->rst);
1504 }
1505
1506 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1507 if (IS_ERR(dsi->clk)) {
1508 dev_err(&pdev->dev, "cannot get DSI clock\n");
1509 return PTR_ERR(dsi->clk);
1510 }
1511
1512 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1513 if (IS_ERR(dsi->clk_lp)) {
1514 dev_err(&pdev->dev, "cannot get low-power clock\n");
1515 return PTR_ERR(dsi->clk_lp);
1516 }
1517
1518 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1519 if (IS_ERR(dsi->clk_parent)) {
1520 dev_err(&pdev->dev, "cannot get parent clock\n");
1521 return PTR_ERR(dsi->clk_parent);
1522 }
1523
1524 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1525 if (IS_ERR(dsi->vdd)) {
1526 dev_err(&pdev->dev, "cannot get VDD supply\n");
1527 return PTR_ERR(dsi->vdd);
1528 }
1529
1530 err = tegra_dsi_setup_clocks(dsi);
1531 if (err < 0) {
1532 dev_err(&pdev->dev, "cannot setup clocks\n");
1533 return err;
1534 }
1535
1536 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1538 if (IS_ERR(dsi->regs))
1539 return PTR_ERR(dsi->regs);
1540
1541 dsi->mipi = tegra_mipi_request(&pdev->dev);
1542 if (IS_ERR(dsi->mipi))
1543 return PTR_ERR(dsi->mipi);
1544
1545 dsi->host.ops = &tegra_dsi_host_ops;
1546 dsi->host.dev = &pdev->dev;
1547
1548 err = mipi_dsi_host_register(&dsi->host);
1549 if (err < 0) {
1550 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1551 goto mipi_free;
1552 }
1553
1554 platform_set_drvdata(pdev, dsi);
1555 pm_runtime_enable(&pdev->dev);
1556
1557 INIT_LIST_HEAD(&dsi->client.list);
1558 dsi->client.ops = &dsi_client_ops;
1559 dsi->client.dev = &pdev->dev;
1560
1561 err = host1x_client_register(&dsi->client);
1562 if (err < 0) {
1563 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1564 err);
1565 goto unregister;
1566 }
1567
1568 return 0;
1569
1570unregister:
1571 mipi_dsi_host_unregister(&dsi->host);
1572mipi_free:
1573 tegra_mipi_free(dsi->mipi);
1574 return err;
1575}
1576
1577static int tegra_dsi_remove(struct platform_device *pdev)
1578{
1579 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1580 int err;
1581
1582 pm_runtime_disable(&pdev->dev);
1583
1584 err = host1x_client_unregister(&dsi->client);
1585 if (err < 0) {
1586 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1587 err);
1588 return err;
1589 }
1590
1591 tegra_output_remove(&dsi->output);
1592
1593 mipi_dsi_host_unregister(&dsi->host);
1594 tegra_mipi_free(dsi->mipi);
1595
1596 return 0;
1597}
1598
1599#ifdef CONFIG_PM
1600static int tegra_dsi_suspend(struct device *dev)
1601{
1602 struct tegra_dsi *dsi = dev_get_drvdata(dev);
1603 int err;
1604
1605 if (dsi->rst) {
1606 err = reset_control_assert(dsi->rst);
1607 if (err < 0) {
1608 dev_err(dev, "failed to assert reset: %d\n", err);
1609 return err;
1610 }
1611 }
1612
1613 usleep_range(1000, 2000);
1614
1615 clk_disable_unprepare(dsi->clk_lp);
1616 clk_disable_unprepare(dsi->clk);
1617
1618 regulator_disable(dsi->vdd);
1619
1620 return 0;
1621}
1622
1623static int tegra_dsi_resume(struct device *dev)
1624{
1625 struct tegra_dsi *dsi = dev_get_drvdata(dev);
1626 int err;
1627
1628 err = regulator_enable(dsi->vdd);
1629 if (err < 0) {
1630 dev_err(dsi->dev, "failed to enable VDD supply: %d\n", err);
1631 return err;
1632 }
1633
1634 err = clk_prepare_enable(dsi->clk);
1635 if (err < 0) {
1636 dev_err(dev, "cannot enable DSI clock: %d\n", err);
1637 goto disable_vdd;
1638 }
1639
1640 err = clk_prepare_enable(dsi->clk_lp);
1641 if (err < 0) {
1642 dev_err(dev, "cannot enable low-power clock: %d\n", err);
1643 goto disable_clk;
1644 }
1645
1646 usleep_range(1000, 2000);
1647
1648 if (dsi->rst) {
1649 err = reset_control_deassert(dsi->rst);
1650 if (err < 0) {
1651 dev_err(dev, "cannot assert reset: %d\n", err);
1652 goto disable_clk_lp;
1653 }
1654 }
1655
1656 return 0;
1657
1658disable_clk_lp:
1659 clk_disable_unprepare(dsi->clk_lp);
1660disable_clk:
1661 clk_disable_unprepare(dsi->clk);
1662disable_vdd:
1663 regulator_disable(dsi->vdd);
1664 return err;
1665}
1666#endif
1667
1668static const struct dev_pm_ops tegra_dsi_pm_ops = {
1669 SET_RUNTIME_PM_OPS(tegra_dsi_suspend, tegra_dsi_resume, NULL)
1670};
1671
1672static const struct of_device_id tegra_dsi_of_match[] = {
1673 { .compatible = "nvidia,tegra210-dsi", },
1674 { .compatible = "nvidia,tegra132-dsi", },
1675 { .compatible = "nvidia,tegra124-dsi", },
1676 { .compatible = "nvidia,tegra114-dsi", },
1677 { },
1678};
1679MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1680
1681struct platform_driver tegra_dsi_driver = {
1682 .driver = {
1683 .name = "tegra-dsi",
1684 .of_match_table = tegra_dsi_of_match,
1685 .pm = &tegra_dsi_pm_ops,
1686 },
1687 .probe = tegra_dsi_probe,
1688 .remove = tegra_dsi_remove,
1689};
1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
10#include <linux/debugfs.h>
11#include <linux/host1x.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/reset.h>
16
17#include <drm/drm_mipi_dsi.h>
18#include <drm/drm_panel.h>
19
20#include <video/mipi_display.h>
21
22#include "dc.h"
23#include "drm.h"
24#include "dsi.h"
25#include "mipi-phy.h"
26
27#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
28#define DSI_HOST_FIFO_DEPTH 64
29
30struct tegra_dsi {
31 struct host1x_client client;
32 struct tegra_output output;
33 struct device *dev;
34
35 void __iomem *regs;
36
37 struct reset_control *rst;
38 struct clk *clk_parent;
39 struct clk *clk_lp;
40 struct clk *clk;
41
42 struct drm_info_list *debugfs_files;
43 struct drm_minor *minor;
44 struct dentry *debugfs;
45
46 enum mipi_dsi_pixel_format format;
47 unsigned int lanes;
48
49 struct tegra_mipi_device *mipi;
50 struct mipi_dsi_host host;
51};
52
53static inline struct tegra_dsi *
54host1x_client_to_dsi(struct host1x_client *client)
55{
56 return container_of(client, struct tegra_dsi, client);
57}
58
59static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
60{
61 return container_of(host, struct tegra_dsi, host);
62}
63
64static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
65{
66 return container_of(output, struct tegra_dsi, output);
67}
68
69static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
70 unsigned long reg)
71{
72 return readl(dsi->regs + (reg << 2));
73}
74
75static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
76 unsigned long reg)
77{
78 writel(value, dsi->regs + (reg << 2));
79}
80
81static int tegra_dsi_show_regs(struct seq_file *s, void *data)
82{
83 struct drm_info_node *node = s->private;
84 struct tegra_dsi *dsi = node->info_ent->data;
85
86#define DUMP_REG(name) \
87 seq_printf(s, "%-32s %#05x %08lx\n", #name, name, \
88 tegra_dsi_readl(dsi, name))
89
90 DUMP_REG(DSI_INCR_SYNCPT);
91 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
92 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
93 DUMP_REG(DSI_CTXSW);
94 DUMP_REG(DSI_RD_DATA);
95 DUMP_REG(DSI_WR_DATA);
96 DUMP_REG(DSI_POWER_CONTROL);
97 DUMP_REG(DSI_INT_ENABLE);
98 DUMP_REG(DSI_INT_STATUS);
99 DUMP_REG(DSI_INT_MASK);
100 DUMP_REG(DSI_HOST_CONTROL);
101 DUMP_REG(DSI_CONTROL);
102 DUMP_REG(DSI_SOL_DELAY);
103 DUMP_REG(DSI_MAX_THRESHOLD);
104 DUMP_REG(DSI_TRIGGER);
105 DUMP_REG(DSI_TX_CRC);
106 DUMP_REG(DSI_STATUS);
107
108 DUMP_REG(DSI_INIT_SEQ_CONTROL);
109 DUMP_REG(DSI_INIT_SEQ_DATA_0);
110 DUMP_REG(DSI_INIT_SEQ_DATA_1);
111 DUMP_REG(DSI_INIT_SEQ_DATA_2);
112 DUMP_REG(DSI_INIT_SEQ_DATA_3);
113 DUMP_REG(DSI_INIT_SEQ_DATA_4);
114 DUMP_REG(DSI_INIT_SEQ_DATA_5);
115 DUMP_REG(DSI_INIT_SEQ_DATA_6);
116 DUMP_REG(DSI_INIT_SEQ_DATA_7);
117
118 DUMP_REG(DSI_PKT_SEQ_0_LO);
119 DUMP_REG(DSI_PKT_SEQ_0_HI);
120 DUMP_REG(DSI_PKT_SEQ_1_LO);
121 DUMP_REG(DSI_PKT_SEQ_1_HI);
122 DUMP_REG(DSI_PKT_SEQ_2_LO);
123 DUMP_REG(DSI_PKT_SEQ_2_HI);
124 DUMP_REG(DSI_PKT_SEQ_3_LO);
125 DUMP_REG(DSI_PKT_SEQ_3_HI);
126 DUMP_REG(DSI_PKT_SEQ_4_LO);
127 DUMP_REG(DSI_PKT_SEQ_4_HI);
128 DUMP_REG(DSI_PKT_SEQ_5_LO);
129 DUMP_REG(DSI_PKT_SEQ_5_HI);
130
131 DUMP_REG(DSI_DCS_CMDS);
132
133 DUMP_REG(DSI_PKT_LEN_0_1);
134 DUMP_REG(DSI_PKT_LEN_2_3);
135 DUMP_REG(DSI_PKT_LEN_4_5);
136 DUMP_REG(DSI_PKT_LEN_6_7);
137
138 DUMP_REG(DSI_PHY_TIMING_0);
139 DUMP_REG(DSI_PHY_TIMING_1);
140 DUMP_REG(DSI_PHY_TIMING_2);
141 DUMP_REG(DSI_BTA_TIMING);
142
143 DUMP_REG(DSI_TIMEOUT_0);
144 DUMP_REG(DSI_TIMEOUT_1);
145 DUMP_REG(DSI_TO_TALLY);
146
147 DUMP_REG(DSI_PAD_CONTROL_0);
148 DUMP_REG(DSI_PAD_CONTROL_CD);
149 DUMP_REG(DSI_PAD_CD_STATUS);
150 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
151 DUMP_REG(DSI_PAD_CONTROL_1);
152 DUMP_REG(DSI_PAD_CONTROL_2);
153 DUMP_REG(DSI_PAD_CONTROL_3);
154 DUMP_REG(DSI_PAD_CONTROL_4);
155
156 DUMP_REG(DSI_GANGED_MODE_CONTROL);
157 DUMP_REG(DSI_GANGED_MODE_START);
158 DUMP_REG(DSI_GANGED_MODE_SIZE);
159
160 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
161 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
162
163 DUMP_REG(DSI_INIT_SEQ_DATA_8);
164 DUMP_REG(DSI_INIT_SEQ_DATA_9);
165 DUMP_REG(DSI_INIT_SEQ_DATA_10);
166 DUMP_REG(DSI_INIT_SEQ_DATA_11);
167 DUMP_REG(DSI_INIT_SEQ_DATA_12);
168 DUMP_REG(DSI_INIT_SEQ_DATA_13);
169 DUMP_REG(DSI_INIT_SEQ_DATA_14);
170 DUMP_REG(DSI_INIT_SEQ_DATA_15);
171
172#undef DUMP_REG
173
174 return 0;
175}
176
177static struct drm_info_list debugfs_files[] = {
178 { "regs", tegra_dsi_show_regs, 0, NULL },
179};
180
181static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
182 struct drm_minor *minor)
183{
184 const char *name = dev_name(dsi->dev);
185 unsigned int i;
186 int err;
187
188 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
189 if (!dsi->debugfs)
190 return -ENOMEM;
191
192 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
193 GFP_KERNEL);
194 if (!dsi->debugfs_files) {
195 err = -ENOMEM;
196 goto remove;
197 }
198
199 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
200 dsi->debugfs_files[i].data = dsi;
201
202 err = drm_debugfs_create_files(dsi->debugfs_files,
203 ARRAY_SIZE(debugfs_files),
204 dsi->debugfs, minor);
205 if (err < 0)
206 goto free;
207
208 dsi->minor = minor;
209
210 return 0;
211
212free:
213 kfree(dsi->debugfs_files);
214 dsi->debugfs_files = NULL;
215remove:
216 debugfs_remove(dsi->debugfs);
217 dsi->debugfs = NULL;
218
219 return err;
220}
221
222static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
223{
224 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
225 dsi->minor);
226 dsi->minor = NULL;
227
228 kfree(dsi->debugfs_files);
229 dsi->debugfs_files = NULL;
230
231 debugfs_remove(dsi->debugfs);
232 dsi->debugfs = NULL;
233
234 return 0;
235}
236
237#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
238#define PKT_LEN0(len) (((len) & 0x07) << 0)
239#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
240#define PKT_LEN1(len) (((len) & 0x07) << 10)
241#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
242#define PKT_LEN2(len) (((len) & 0x07) << 20)
243
244#define PKT_LP (1 << 30)
245#define NUM_PKT_SEQ 12
246
247/* non-burst mode with sync-end */
248static const u32 pkt_seq_vnb_syne[NUM_PKT_SEQ] = {
249 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
250 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
251 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
252 PKT_LP,
253 [ 1] = 0,
254 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
255 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
256 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
257 PKT_LP,
258 [ 3] = 0,
259 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
260 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
261 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
262 PKT_LP,
263 [ 5] = 0,
264 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
265 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
266 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
267 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
268 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
269 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
270 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
271 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
272 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
273 PKT_LP,
274 [ 9] = 0,
275 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
276 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
277 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
278 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
279 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
280 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
281};
282
283static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
284{
285 struct mipi_dphy_timing timing;
286 unsigned long value, period;
287 long rate;
288 int err;
289
290 rate = clk_get_rate(dsi->clk);
291 if (rate < 0)
292 return rate;
293
294 period = DIV_ROUND_CLOSEST(1000000000UL, rate * 2);
295
296 err = mipi_dphy_timing_get_default(&timing, period);
297 if (err < 0)
298 return err;
299
300 err = mipi_dphy_timing_validate(&timing, period);
301 if (err < 0) {
302 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
303 return err;
304 }
305
306 /*
307 * The D-PHY timing fields below are expressed in byte-clock cycles,
308 * so multiply the period by 8.
309 */
310 period *= 8;
311
312 value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
313 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
314 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
315 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
316 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
317
318 value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
319 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
320 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
321 DSI_TIMING_FIELD(timing.lpx, period, 1);
322 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
323
324 value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
325 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
326 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
327 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
328
329 value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
330 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
331 DSI_TIMING_FIELD(timing.tago, period, 1);
332 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
333
334 return 0;
335}
336
337static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
338 unsigned int *mulp, unsigned int *divp)
339{
340 switch (format) {
341 case MIPI_DSI_FMT_RGB666_PACKED:
342 case MIPI_DSI_FMT_RGB888:
343 *mulp = 3;
344 *divp = 1;
345 break;
346
347 case MIPI_DSI_FMT_RGB565:
348 *mulp = 2;
349 *divp = 1;
350 break;
351
352 case MIPI_DSI_FMT_RGB666:
353 *mulp = 9;
354 *divp = 4;
355 break;
356
357 default:
358 return -EINVAL;
359 }
360
361 return 0;
362}
363
364static int tegra_output_dsi_enable(struct tegra_output *output)
365{
366 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
367 struct drm_display_mode *mode = &dc->base.mode;
368 unsigned int hact, hsw, hbp, hfp, i, mul, div;
369 struct tegra_dsi *dsi = to_dsi(output);
370 /* FIXME: don't hardcode this */
371 const u32 *pkt_seq = pkt_seq_vnb_syne;
372 unsigned long value;
373 int err;
374
375 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
376 if (err < 0)
377 return err;
378
379 err = clk_enable(dsi->clk);
380 if (err < 0)
381 return err;
382
383 reset_control_deassert(dsi->rst);
384
385 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(dsi->format) |
386 DSI_CONTROL_LANES(dsi->lanes - 1) |
387 DSI_CONTROL_SOURCE(dc->pipe);
388 tegra_dsi_writel(dsi, value, DSI_CONTROL);
389
390 tegra_dsi_writel(dsi, DSI_VIDEO_FIFO_DEPTH, DSI_MAX_THRESHOLD);
391
392 value = DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS |
393 DSI_HOST_CONTROL_ECC;
394 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
395
396 value = tegra_dsi_readl(dsi, DSI_CONTROL);
397 value |= DSI_CONTROL_HS_CLK_CTRL;
398 value &= ~DSI_CONTROL_TX_TRIG(3);
399 value &= ~DSI_CONTROL_DCS_ENABLE;
400 value |= DSI_CONTROL_VIDEO_ENABLE;
401 value &= ~DSI_CONTROL_HOST_ENABLE;
402 tegra_dsi_writel(dsi, value, DSI_CONTROL);
403
404 err = tegra_dsi_set_phy_timing(dsi);
405 if (err < 0)
406 return err;
407
408 for (i = 0; i < NUM_PKT_SEQ; i++)
409 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
410
411 /* horizontal active pixels */
412 hact = mode->hdisplay * mul / div;
413
414 /* horizontal sync width */
415 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
416 hsw -= 10;
417
418 /* horizontal back porch */
419 hbp = (mode->htotal - mode->hsync_end) * mul / div;
420 hbp -= 14;
421
422 /* horizontal front porch */
423 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
424 hfp -= 8;
425
426 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
427 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
428 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
429 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
430
431 /* set SOL delay */
432 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
433
434 /* enable display controller */
435 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
436 value |= DSI_ENABLE;
437 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
438
439 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
440 value &= ~DISP_CTRL_MODE_MASK;
441 value |= DISP_CTRL_MODE_C_DISPLAY;
442 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
443
444 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
445 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
446 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
447 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
448
449 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
450 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
451
452 /* enable DSI controller */
453 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
454 value |= DSI_POWER_CONTROL_ENABLE;
455 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
456
457 return 0;
458}
459
460static int tegra_output_dsi_disable(struct tegra_output *output)
461{
462 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
463 struct tegra_dsi *dsi = to_dsi(output);
464 unsigned long value;
465
466 /* disable DSI controller */
467 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
468 value &= DSI_POWER_CONTROL_ENABLE;
469 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
470
471 /*
472 * The following accesses registers of the display controller, so make
473 * sure it's only executed when the output is attached to one.
474 */
475 if (dc) {
476 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
477 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
478 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
479 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
480
481 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
482 value &= ~DISP_CTRL_MODE_MASK;
483 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
484
485 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
486 value &= ~DSI_ENABLE;
487 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
488
489 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
490 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
491 }
492
493 clk_disable(dsi->clk);
494
495 return 0;
496}
497
498static int tegra_output_dsi_setup_clock(struct tegra_output *output,
499 struct clk *clk, unsigned long pclk)
500{
501 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
502 struct drm_display_mode *mode = &dc->base.mode;
503 unsigned int timeout, mul, div, vrefresh;
504 struct tegra_dsi *dsi = to_dsi(output);
505 unsigned long bclk, plld, value;
506 struct clk *base;
507 int err;
508
509 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
510 if (err < 0)
511 return err;
512
513 vrefresh = drm_mode_vrefresh(mode);
514
515 pclk = mode->htotal * mode->vtotal * vrefresh;
516 bclk = (pclk * mul) / (div * dsi->lanes);
517 plld = DIV_ROUND_UP(bclk * 8, 1000000);
518 pclk = (plld * 1000000) / 2;
519
520 err = clk_set_parent(clk, dsi->clk_parent);
521 if (err < 0) {
522 dev_err(dsi->dev, "failed to set parent clock: %d\n", err);
523 return err;
524 }
525
526 base = clk_get_parent(dsi->clk_parent);
527
528 /*
529 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
530 * respectively, each of which divides the base pll_d by 2.
531 */
532 err = clk_set_rate(base, pclk * 2);
533 if (err < 0) {
534 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
535 pclk * 2);
536 return err;
537 }
538
539 /*
540 * XXX: Move the below somewhere else so that we don't need to have
541 * access to the vrefresh in this function?
542 */
543
544 /* one frame high-speed transmission timeout */
545 timeout = (bclk / vrefresh) / 512;
546 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
547 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
548
549 /* 2 ms peripheral timeout for panel */
550 timeout = 2 * bclk / 512 * 1000;
551 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
552 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
553
554 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
555 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
556
557 return 0;
558}
559
560static int tegra_output_dsi_check_mode(struct tegra_output *output,
561 struct drm_display_mode *mode,
562 enum drm_mode_status *status)
563{
564 /*
565 * FIXME: For now, always assume that the mode is okay.
566 */
567
568 *status = MODE_OK;
569
570 return 0;
571}
572
573static const struct tegra_output_ops dsi_ops = {
574 .enable = tegra_output_dsi_enable,
575 .disable = tegra_output_dsi_disable,
576 .setup_clock = tegra_output_dsi_setup_clock,
577 .check_mode = tegra_output_dsi_check_mode,
578};
579
580static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
581{
582 unsigned long value;
583
584 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
585 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
586
587 return 0;
588}
589
590static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
591{
592 unsigned long value;
593
594 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
595 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
596 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
597 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
598 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
599
600 /* start calibration */
601 tegra_dsi_pad_enable(dsi);
602
603 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
604 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
605 DSI_PAD_OUT_CLK(0x0);
606 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
607
608 return tegra_mipi_calibrate(dsi->mipi);
609}
610
611static int tegra_dsi_init(struct host1x_client *client)
612{
613 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
614 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
615 unsigned long value, i;
616 int err;
617
618 dsi->output.type = TEGRA_OUTPUT_DSI;
619 dsi->output.dev = client->dev;
620 dsi->output.ops = &dsi_ops;
621
622 err = tegra_output_init(tegra->drm, &dsi->output);
623 if (err < 0) {
624 dev_err(client->dev, "output setup failed: %d\n", err);
625 return err;
626 }
627
628 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
629 err = tegra_dsi_debugfs_init(dsi, tegra->drm->primary);
630 if (err < 0)
631 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
632 }
633
634 /*
635 * enable high-speed mode, checksum generation, ECC generation and
636 * disable raw mode
637 */
638 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
639 value |= DSI_HOST_CONTROL_ECC | DSI_HOST_CONTROL_CS |
640 DSI_HOST_CONTROL_HS;
641 value &= ~DSI_HOST_CONTROL_RAW;
642 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
643
644 tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
645 tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
646
647 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
648
649 for (i = 0; i < 8; i++) {
650 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
651 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
652 }
653
654 for (i = 0; i < 12; i++)
655 tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
656
657 tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
658
659 err = tegra_dsi_pad_calibrate(dsi);
660 if (err < 0) {
661 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
662 return err;
663 }
664
665 tegra_dsi_writel(dsi, DSI_POWER_CONTROL_ENABLE, DSI_POWER_CONTROL);
666 usleep_range(300, 1000);
667
668 return 0;
669}
670
671static int tegra_dsi_exit(struct host1x_client *client)
672{
673 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
674 int err;
675
676 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
677 err = tegra_dsi_debugfs_exit(dsi);
678 if (err < 0)
679 dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
680 }
681
682 err = tegra_output_disable(&dsi->output);
683 if (err < 0) {
684 dev_err(client->dev, "output failed to disable: %d\n", err);
685 return err;
686 }
687
688 err = tegra_output_exit(&dsi->output);
689 if (err < 0) {
690 dev_err(client->dev, "output cleanup failed: %d\n", err);
691 return err;
692 }
693
694 return 0;
695}
696
697static const struct host1x_client_ops dsi_client_ops = {
698 .init = tegra_dsi_init,
699 .exit = tegra_dsi_exit,
700};
701
702static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
703{
704 struct clk *parent;
705 int err;
706
707 parent = clk_get_parent(dsi->clk);
708 if (!parent)
709 return -EINVAL;
710
711 err = clk_set_parent(parent, dsi->clk_parent);
712 if (err < 0)
713 return err;
714
715 return 0;
716}
717
718static void tegra_dsi_initialize(struct tegra_dsi *dsi)
719{
720 unsigned int i;
721
722 tegra_dsi_writel(dsi, 0, DSI_POWER_CONTROL);
723
724 tegra_dsi_writel(dsi, 0, DSI_INT_ENABLE);
725 tegra_dsi_writel(dsi, 0, DSI_INT_STATUS);
726 tegra_dsi_writel(dsi, 0, DSI_INT_MASK);
727
728 tegra_dsi_writel(dsi, 0, DSI_HOST_CONTROL);
729 tegra_dsi_writel(dsi, 0, DSI_CONTROL);
730
731 tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
732 tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
733
734 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
735
736 for (i = 0; i < 8; i++) {
737 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
738 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
739 }
740
741 for (i = 0; i < 12; i++)
742 tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
743
744 tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
745
746 for (i = 0; i < 4; i++)
747 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1 + i);
748
749 tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_0);
750 tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_1);
751 tegra_dsi_writel(dsi, 0x000000ff, DSI_PHY_TIMING_2);
752 tegra_dsi_writel(dsi, 0x00000000, DSI_BTA_TIMING);
753
754 tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_0);
755 tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_1);
756 tegra_dsi_writel(dsi, 0, DSI_TO_TALLY);
757
758 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
759 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_CD);
760 tegra_dsi_writel(dsi, 0, DSI_PAD_CD_STATUS);
761 tegra_dsi_writel(dsi, 0, DSI_VIDEO_MODE_CONTROL);
762 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
763 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
764 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
765 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
766
767 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
768 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
769 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
770}
771
772static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
773 struct mipi_dsi_device *device)
774{
775 struct tegra_dsi *dsi = host_to_tegra(host);
776 struct tegra_output *output = &dsi->output;
777
778 dsi->format = device->format;
779 dsi->lanes = device->lanes;
780
781 output->panel = of_drm_find_panel(device->dev.of_node);
782 if (output->panel) {
783 if (output->connector.dev)
784 drm_helper_hpd_irq_event(output->connector.dev);
785 }
786
787 return 0;
788}
789
790static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
791 struct mipi_dsi_device *device)
792{
793 struct tegra_dsi *dsi = host_to_tegra(host);
794 struct tegra_output *output = &dsi->output;
795
796 if (output->panel && &device->dev == output->panel->dev) {
797 if (output->connector.dev)
798 drm_helper_hpd_irq_event(output->connector.dev);
799
800 output->panel = NULL;
801 }
802
803 return 0;
804}
805
806static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
807 .attach = tegra_dsi_host_attach,
808 .detach = tegra_dsi_host_detach,
809};
810
811static int tegra_dsi_probe(struct platform_device *pdev)
812{
813 struct tegra_dsi *dsi;
814 struct resource *regs;
815 int err;
816
817 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
818 if (!dsi)
819 return -ENOMEM;
820
821 dsi->output.dev = dsi->dev = &pdev->dev;
822
823 err = tegra_output_probe(&dsi->output);
824 if (err < 0)
825 return err;
826
827 /*
828 * Assume these values by default. When a DSI peripheral driver
829 * attaches to the DSI host, the parameters will be taken from
830 * the attached device.
831 */
832 dsi->format = MIPI_DSI_FMT_RGB888;
833 dsi->lanes = 4;
834
835 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
836 if (IS_ERR(dsi->rst))
837 return PTR_ERR(dsi->rst);
838
839 dsi->clk = devm_clk_get(&pdev->dev, NULL);
840 if (IS_ERR(dsi->clk)) {
841 dev_err(&pdev->dev, "cannot get DSI clock\n");
842 return PTR_ERR(dsi->clk);
843 }
844
845 err = clk_prepare_enable(dsi->clk);
846 if (err < 0) {
847 dev_err(&pdev->dev, "cannot enable DSI clock\n");
848 return err;
849 }
850
851 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
852 if (IS_ERR(dsi->clk_lp)) {
853 dev_err(&pdev->dev, "cannot get low-power clock\n");
854 return PTR_ERR(dsi->clk_lp);
855 }
856
857 err = clk_prepare_enable(dsi->clk_lp);
858 if (err < 0) {
859 dev_err(&pdev->dev, "cannot enable low-power clock\n");
860 return err;
861 }
862
863 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
864 if (IS_ERR(dsi->clk_parent)) {
865 dev_err(&pdev->dev, "cannot get parent clock\n");
866 return PTR_ERR(dsi->clk_parent);
867 }
868
869 err = clk_prepare_enable(dsi->clk_parent);
870 if (err < 0) {
871 dev_err(&pdev->dev, "cannot enable parent clock\n");
872 return err;
873 }
874
875 err = tegra_dsi_setup_clocks(dsi);
876 if (err < 0) {
877 dev_err(&pdev->dev, "cannot setup clocks\n");
878 return err;
879 }
880
881 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
882 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
883 if (IS_ERR(dsi->regs))
884 return PTR_ERR(dsi->regs);
885
886 tegra_dsi_initialize(dsi);
887
888 dsi->mipi = tegra_mipi_request(&pdev->dev);
889 if (IS_ERR(dsi->mipi))
890 return PTR_ERR(dsi->mipi);
891
892 dsi->host.ops = &tegra_dsi_host_ops;
893 dsi->host.dev = &pdev->dev;
894
895 err = mipi_dsi_host_register(&dsi->host);
896 if (err < 0) {
897 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
898 return err;
899 }
900
901 INIT_LIST_HEAD(&dsi->client.list);
902 dsi->client.ops = &dsi_client_ops;
903 dsi->client.dev = &pdev->dev;
904
905 err = host1x_client_register(&dsi->client);
906 if (err < 0) {
907 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
908 err);
909 return err;
910 }
911
912 platform_set_drvdata(pdev, dsi);
913
914 return 0;
915}
916
917static int tegra_dsi_remove(struct platform_device *pdev)
918{
919 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
920 int err;
921
922 err = host1x_client_unregister(&dsi->client);
923 if (err < 0) {
924 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
925 err);
926 return err;
927 }
928
929 mipi_dsi_host_unregister(&dsi->host);
930 tegra_mipi_free(dsi->mipi);
931
932 clk_disable_unprepare(dsi->clk_parent);
933 clk_disable_unprepare(dsi->clk_lp);
934 clk_disable_unprepare(dsi->clk);
935
936 err = tegra_output_remove(&dsi->output);
937 if (err < 0) {
938 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
939 return err;
940 }
941
942 return 0;
943}
944
945static const struct of_device_id tegra_dsi_of_match[] = {
946 { .compatible = "nvidia,tegra114-dsi", },
947 { },
948};
949
950struct platform_driver tegra_dsi_driver = {
951 .driver = {
952 .name = "tegra-dsi",
953 .of_match_table = tegra_dsi_of_match,
954 },
955 .probe = tegra_dsi_probe,
956 .remove = tegra_dsi_remove,
957};