1/*
  2 * Performance events - AMD IBS
  3 *
  4 *  Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
  5 *
  6 *  For licencing details see kernel-base/COPYING
  7 */
  8
  9#include <linux/perf_event.h>
 10#include <linux/module.h>
 11#include <linux/pci.h>
 12#include <linux/ptrace.h>
 13#include <linux/syscore_ops.h>
 14
 15#include <asm/apic.h>
 16
 17#include "perf_event.h"
 18
 19static u32 ibs_caps;
 20
 21#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
 22
 23#include <linux/kprobes.h>
 24#include <linux/hardirq.h>
 25
 26#include <asm/nmi.h>
 27
 28#define IBS_FETCH_CONFIG_MASK	(IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
 29#define IBS_OP_CONFIG_MASK	IBS_OP_MAX_CNT
 30
 31enum ibs_states {
 32	IBS_ENABLED	= 0,
 33	IBS_STARTED	= 1,
 34	IBS_STOPPING	= 2,
 35
 36	IBS_MAX_STATES,
 37};
 38
 39struct cpu_perf_ibs {
 40	struct perf_event	*event;
 41	unsigned long		state[BITS_TO_LONGS(IBS_MAX_STATES)];
 42};
 43
 44struct perf_ibs {
 45	struct pmu			pmu;
 46	unsigned int			msr;
 47	u64				config_mask;
 48	u64				cnt_mask;
 49	u64				enable_mask;
 50	u64				valid_mask;
 51	u64				max_period;
 52	unsigned long			offset_mask[1];
 53	int				offset_max;
 54	struct cpu_perf_ibs __percpu	*pcpu;
 55
 56	struct attribute		**format_attrs;
 57	struct attribute_group		format_group;
 58	const struct attribute_group	*attr_groups[2];
 59
 60	u64				(*get_count)(u64 config);
 61};
 62
 63struct perf_ibs_data {
 64	u32		size;
 65	union {
 66		u32	data[0];	/* data buffer starts here */
 67		u32	caps;
 68	};
 69	u64		regs[MSR_AMD64_IBS_REG_COUNT_MAX];
 70};
 71
 72static int
 73perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
 74{
 75	s64 left = local64_read(&hwc->period_left);
 76	s64 period = hwc->sample_period;
 77	int overflow = 0;
 78
 79	/*
 80	 * If we are way outside a reasonable range then just skip forward:
 81	 */
 82	if (unlikely(left <= -period)) {
 83		left = period;
 84		local64_set(&hwc->period_left, left);
 85		hwc->last_period = period;
 86		overflow = 1;
 87	}
 88
 89	if (unlikely(left < (s64)min)) {
 90		left += period;
 91		local64_set(&hwc->period_left, left);
 92		hwc->last_period = period;
 93		overflow = 1;
 94	}
 95
 96	/*
 97	 * If the hw period that triggers the sw overflow is too short
 98	 * we might hit the irq handler. This biases the results.
 99	 * Thus we shorten the next-to-last period and set the last
100	 * period to the max period.
101	 */
102	if (left > max) {
103		left -= max;
104		if (left > max)
105			left = max;
106		else if (left < min)
107			left = min;
108	}
109
110	*hw_period = (u64)left;
111
112	return overflow;
113}
114
115static  int
116perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
117{
118	struct hw_perf_event *hwc = &event->hw;
119	int shift = 64 - width;
120	u64 prev_raw_count;
121	u64 delta;
122
123	/*
124	 * Careful: an NMI might modify the previous event value.
125	 *
126	 * Our tactic to handle this is to first atomically read and
127	 * exchange a new raw count - then add that new-prev delta
128	 * count to the generic event atomically:
129	 */
130	prev_raw_count = local64_read(&hwc->prev_count);
131	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
132					new_raw_count) != prev_raw_count)
133		return 0;
134
135	/*
136	 * Now we have the new raw value and have updated the prev
137	 * timestamp already. We can now calculate the elapsed delta
138	 * (event-)time and add that to the generic event.
139	 *
140	 * Careful, not all hw sign-extends above the physical width
141	 * of the count.
142	 */
143	delta = (new_raw_count << shift) - (prev_raw_count << shift);
144	delta >>= shift;
145
146	local64_add(delta, &event->count);
147	local64_sub(delta, &hwc->period_left);
148
149	return 1;
150}
151
152static struct perf_ibs perf_ibs_fetch;
153static struct perf_ibs perf_ibs_op;
154
155static struct perf_ibs *get_ibs_pmu(int type)
156{
157	if (perf_ibs_fetch.pmu.type == type)
158		return &perf_ibs_fetch;
159	if (perf_ibs_op.pmu.type == type)
160		return &perf_ibs_op;
161	return NULL;
162}
163
164/*
165 * Use IBS for precise event sampling:
166 *
167 *  perf record -a -e cpu-cycles:p ...    # use ibs op counting cycle count
168 *  perf record -a -e r076:p ...          # same as -e cpu-cycles:p
169 *  perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
170 *
171 * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
172 * MSRC001_1033) is used to select either cycle or micro-ops counting
173 * mode.
174 *
175 * The rip of IBS samples has skid 0. Thus, IBS supports precise
176 * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
177 * rip is invalid when IBS was not able to record the rip correctly.
178 * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
179 *
180 */
181static int perf_ibs_precise_event(struct perf_event *event, u64 *config)
182{
183	switch (event->attr.precise_ip) {
184	case 0:
185		return -ENOENT;
186	case 1:
187	case 2:
188		break;
189	default:
190		return -EOPNOTSUPP;
191	}
192
193	switch (event->attr.type) {
194	case PERF_TYPE_HARDWARE:
195		switch (event->attr.config) {
196		case PERF_COUNT_HW_CPU_CYCLES:
197			*config = 0;
198			return 0;
199		}
200		break;
201	case PERF_TYPE_RAW:
202		switch (event->attr.config) {
203		case 0x0076:
204			*config = 0;
205			return 0;
206		case 0x00C1:
207			*config = IBS_OP_CNT_CTL;
208			return 0;
209		}
210		break;
211	default:
212		return -ENOENT;
213	}
214
215	return -EOPNOTSUPP;
216}
217
218static const struct perf_event_attr ibs_notsupp = {
219	.exclude_user	= 1,
220	.exclude_kernel	= 1,
221	.exclude_hv	= 1,
222	.exclude_idle	= 1,
223	.exclude_host	= 1,
224	.exclude_guest	= 1,
225};
226
227static int perf_ibs_init(struct perf_event *event)
228{
229	struct hw_perf_event *hwc = &event->hw;
230	struct perf_ibs *perf_ibs;
231	u64 max_cnt, config;
232	int ret;
233
234	perf_ibs = get_ibs_pmu(event->attr.type);
235	if (perf_ibs) {
236		config = event->attr.config;
237	} else {
238		perf_ibs = &perf_ibs_op;
239		ret = perf_ibs_precise_event(event, &config);
240		if (ret)
241			return ret;
242	}
243
244	if (event->pmu != &perf_ibs->pmu)
245		return -ENOENT;
246
247	if (perf_flags(&event->attr) & perf_flags(&ibs_notsupp))
248		return -EINVAL;
249
250	if (config & ~perf_ibs->config_mask)
251		return -EINVAL;
252
253	if (hwc->sample_period) {
254		if (config & perf_ibs->cnt_mask)
255			/* raw max_cnt may not be set */
256			return -EINVAL;
257		if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
258			/*
259			 * lower 4 bits can not be set in ibs max cnt,
260			 * but allowing it in case we adjust the
261			 * sample period to set a frequency.
262			 */
263			return -EINVAL;
264		hwc->sample_period &= ~0x0FULL;
265		if (!hwc->sample_period)
266			hwc->sample_period = 0x10;
267	} else {
268		max_cnt = config & perf_ibs->cnt_mask;
269		config &= ~perf_ibs->cnt_mask;
270		event->attr.sample_period = max_cnt << 4;
271		hwc->sample_period = event->attr.sample_period;
272	}
273
274	if (!hwc->sample_period)
275		return -EINVAL;
276
277	/*
278	 * If we modify hwc->sample_period, we also need to update
279	 * hwc->last_period and hwc->period_left.
280	 */
281	hwc->last_period = hwc->sample_period;
282	local64_set(&hwc->period_left, hwc->sample_period);
283
284	hwc->config_base = perf_ibs->msr;
285	hwc->config = config;
286
287	return 0;
288}
289
290static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
291			       struct hw_perf_event *hwc, u64 *period)
292{
293	int overflow;
294
295	/* ignore lower 4 bits in min count: */
296	overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
297	local64_set(&hwc->prev_count, 0);
298
299	return overflow;
300}
301
302static u64 get_ibs_fetch_count(u64 config)
303{
304	return (config & IBS_FETCH_CNT) >> 12;
305}
306
307static u64 get_ibs_op_count(u64 config)
308{
309	u64 count = 0;
310
311	if (config & IBS_OP_VAL)
312		count += (config & IBS_OP_MAX_CNT) << 4; /* cnt rolled over */
313
314	if (ibs_caps & IBS_CAPS_RDWROPCNT)
315		count += (config & IBS_OP_CUR_CNT) >> 32;
316
317	return count;
318}
319
320static void
321perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
322		      u64 *config)
323{
324	u64 count = perf_ibs->get_count(*config);
325
326	/*
327	 * Set width to 64 since we do not overflow on max width but
328	 * instead on max count. In perf_ibs_set_period() we clear
329	 * prev count manually on overflow.
330	 */
331	while (!perf_event_try_update(event, count, 64)) {
332		rdmsrl(event->hw.config_base, *config);
333		count = perf_ibs->get_count(*config);
334	}
335}
336
337static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
338					 struct hw_perf_event *hwc, u64 config)
339{
340	wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask);
341}
342
343/*
344 * Erratum #420 Instruction-Based Sampling Engine May Generate
345 * Interrupt that Cannot Be Cleared:
346 *
347 * Must clear counter mask first, then clear the enable bit. See
348 * Revision Guide for AMD Family 10h Processors, Publication #41322.
349 */
350static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
351					  struct hw_perf_event *hwc, u64 config)
352{
353	config &= ~perf_ibs->cnt_mask;
354	wrmsrl(hwc->config_base, config);
355	config &= ~perf_ibs->enable_mask;
356	wrmsrl(hwc->config_base, config);
357}
358
359/*
360 * We cannot restore the ibs pmu state, so we always needs to update
361 * the event while stopping it and then reset the state when starting
362 * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
363 * perf_ibs_start()/perf_ibs_stop() and instead always do it.
364 */
365static void perf_ibs_start(struct perf_event *event, int flags)
366{
367	struct hw_perf_event *hwc = &event->hw;
368	struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
369	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
370	u64 period;
371
372	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
373		return;
374
375	WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
376	hwc->state = 0;
377
378	perf_ibs_set_period(perf_ibs, hwc, &period);
379	set_bit(IBS_STARTED, pcpu->state);
380	perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
381
382	perf_event_update_userpage(event);
383}
384
385static void perf_ibs_stop(struct perf_event *event, int flags)
386{
387	struct hw_perf_event *hwc = &event->hw;
388	struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
389	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
390	u64 config;
391	int stopping;
392
393	stopping = test_and_clear_bit(IBS_STARTED, pcpu->state);
394
395	if (!stopping && (hwc->state & PERF_HES_UPTODATE))
396		return;
397
398	rdmsrl(hwc->config_base, config);
399
400	if (stopping) {
401		set_bit(IBS_STOPPING, pcpu->state);
402		perf_ibs_disable_event(perf_ibs, hwc, config);
403		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
404		hwc->state |= PERF_HES_STOPPED;
405	}
406
407	if (hwc->state & PERF_HES_UPTODATE)
408		return;
409
410	/*
411	 * Clear valid bit to not count rollovers on update, rollovers
412	 * are only updated in the irq handler.
413	 */
414	config &= ~perf_ibs->valid_mask;
415
416	perf_ibs_event_update(perf_ibs, event, &config);
417	hwc->state |= PERF_HES_UPTODATE;
418}
419
420static int perf_ibs_add(struct perf_event *event, int flags)
421{
422	struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
423	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
424
425	if (test_and_set_bit(IBS_ENABLED, pcpu->state))
426		return -ENOSPC;
427
428	event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
429
430	pcpu->event = event;
431
432	if (flags & PERF_EF_START)
433		perf_ibs_start(event, PERF_EF_RELOAD);
434
435	return 0;
436}
437
438static void perf_ibs_del(struct perf_event *event, int flags)
439{
440	struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
441	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
442
443	if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
444		return;
445
446	perf_ibs_stop(event, PERF_EF_UPDATE);
447
448	pcpu->event = NULL;
449
450	perf_event_update_userpage(event);
451}
452
453static void perf_ibs_read(struct perf_event *event) { }
454
455PMU_FORMAT_ATTR(rand_en,	"config:57");
456PMU_FORMAT_ATTR(cnt_ctl,	"config:19");
457
458static struct attribute *ibs_fetch_format_attrs[] = {
459	&format_attr_rand_en.attr,
460	NULL,
461};
462
463static struct attribute *ibs_op_format_attrs[] = {
464	NULL,	/* &format_attr_cnt_ctl.attr if IBS_CAPS_OPCNT */
465	NULL,
466};
467
468static struct perf_ibs perf_ibs_fetch = {
469	.pmu = {
470		.task_ctx_nr	= perf_invalid_context,
471
472		.event_init	= perf_ibs_init,
473		.add		= perf_ibs_add,
474		.del		= perf_ibs_del,
475		.start		= perf_ibs_start,
476		.stop		= perf_ibs_stop,
477		.read		= perf_ibs_read,
478	},
479	.msr			= MSR_AMD64_IBSFETCHCTL,
480	.config_mask		= IBS_FETCH_CONFIG_MASK,
481	.cnt_mask		= IBS_FETCH_MAX_CNT,
482	.enable_mask		= IBS_FETCH_ENABLE,
483	.valid_mask		= IBS_FETCH_VAL,
484	.max_period		= IBS_FETCH_MAX_CNT << 4,
485	.offset_mask		= { MSR_AMD64_IBSFETCH_REG_MASK },
486	.offset_max		= MSR_AMD64_IBSFETCH_REG_COUNT,
487	.format_attrs		= ibs_fetch_format_attrs,
488
489	.get_count		= get_ibs_fetch_count,
490};
491
492static struct perf_ibs perf_ibs_op = {
493	.pmu = {
494		.task_ctx_nr	= perf_invalid_context,
495
496		.event_init	= perf_ibs_init,
497		.add		= perf_ibs_add,
498		.del		= perf_ibs_del,
499		.start		= perf_ibs_start,
500		.stop		= perf_ibs_stop,
501		.read		= perf_ibs_read,
502	},
503	.msr			= MSR_AMD64_IBSOPCTL,
504	.config_mask		= IBS_OP_CONFIG_MASK,
505	.cnt_mask		= IBS_OP_MAX_CNT,
506	.enable_mask		= IBS_OP_ENABLE,
507	.valid_mask		= IBS_OP_VAL,
508	.max_period		= IBS_OP_MAX_CNT << 4,
509	.offset_mask		= { MSR_AMD64_IBSOP_REG_MASK },
510	.offset_max		= MSR_AMD64_IBSOP_REG_COUNT,
511	.format_attrs		= ibs_op_format_attrs,
512
513	.get_count		= get_ibs_op_count,
514};
515
516static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
517{
518	struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
519	struct perf_event *event = pcpu->event;
520	struct hw_perf_event *hwc = &event->hw;
521	struct perf_sample_data data;
522	struct perf_raw_record raw;
523	struct pt_regs regs;
524	struct perf_ibs_data ibs_data;
525	int offset, size, check_rip, offset_max, throttle = 0;
526	unsigned int msr;
527	u64 *buf, *config, period;
528
529	if (!test_bit(IBS_STARTED, pcpu->state)) {
530		/*
531		 * Catch spurious interrupts after stopping IBS: After
532		 * disabling IBS there could be still incoming NMIs
533		 * with samples that even have the valid bit cleared.
534		 * Mark all this NMIs as handled.
535		 */
536		return test_and_clear_bit(IBS_STOPPING, pcpu->state) ? 1 : 0;
537	}
538
539	msr = hwc->config_base;
540	buf = ibs_data.regs;
541	rdmsrl(msr, *buf);
542	if (!(*buf++ & perf_ibs->valid_mask))
543		return 0;
544
545	config = &ibs_data.regs[0];
546	perf_ibs_event_update(perf_ibs, event, config);
547	perf_sample_data_init(&data, 0, hwc->last_period);
548	if (!perf_ibs_set_period(perf_ibs, hwc, &period))
549		goto out;	/* no sw counter overflow */
550
551	ibs_data.caps = ibs_caps;
552	size = 1;
553	offset = 1;
554	check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
555	if (event->attr.sample_type & PERF_SAMPLE_RAW)
556		offset_max = perf_ibs->offset_max;
557	else if (check_rip)
558		offset_max = 2;
559	else
560		offset_max = 1;
561	do {
562		rdmsrl(msr + offset, *buf++);
563		size++;
564		offset = find_next_bit(perf_ibs->offset_mask,
565				       perf_ibs->offset_max,
566				       offset + 1);
567	} while (offset < offset_max);
568	ibs_data.size = sizeof(u64) * size;
569
570	regs = *iregs;
571	if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
572		regs.flags &= ~PERF_EFLAGS_EXACT;
573	} else {
574		set_linear_ip(&regs, ibs_data.regs[1]);
575		regs.flags |= PERF_EFLAGS_EXACT;
576	}
577
578	if (event->attr.sample_type & PERF_SAMPLE_RAW) {
579		raw.size = sizeof(u32) + ibs_data.size;
580		raw.data = ibs_data.data;
581		data.raw = &raw;
582	}
583
584	throttle = perf_event_overflow(event, &data, &regs);
585out:
586	if (throttle)
587		perf_ibs_disable_event(perf_ibs, hwc, *config);
588	else
589		perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
590
591	perf_event_update_userpage(event);
592
593	return 1;
594}
595
596static int __kprobes
597perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
598{
599	int handled = 0;
600
601	handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
602	handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
603
604	if (handled)
605		inc_irq_stat(apic_perf_irqs);
606
607	return handled;
608}
609
610static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
611{
612	struct cpu_perf_ibs __percpu *pcpu;
613	int ret;
614
615	pcpu = alloc_percpu(struct cpu_perf_ibs);
616	if (!pcpu)
617		return -ENOMEM;
618
619	perf_ibs->pcpu = pcpu;
620
621	/* register attributes */
622	if (perf_ibs->format_attrs[0]) {
623		memset(&perf_ibs->format_group, 0, sizeof(perf_ibs->format_group));
624		perf_ibs->format_group.name	= "format";
625		perf_ibs->format_group.attrs	= perf_ibs->format_attrs;
626
627		memset(&perf_ibs->attr_groups, 0, sizeof(perf_ibs->attr_groups));
628		perf_ibs->attr_groups[0]	= &perf_ibs->format_group;
629		perf_ibs->pmu.attr_groups	= perf_ibs->attr_groups;
630	}
631
632	ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
633	if (ret) {
634		perf_ibs->pcpu = NULL;
635		free_percpu(pcpu);
636	}
637
638	return ret;
639}
640
641static __init int perf_event_ibs_init(void)
642{
643	struct attribute **attr = ibs_op_format_attrs;
644
645	if (!ibs_caps)
646		return -ENODEV;	/* ibs not supported by the cpu */
647
648	perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
649
650	if (ibs_caps & IBS_CAPS_OPCNT) {
651		perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
652		*attr++ = &format_attr_cnt_ctl.attr;
653	}
654	perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
655
656	register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
657	printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
658
659	return 0;
660}
661
662#else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
663
664static __init int perf_event_ibs_init(void) { return 0; }
665
666#endif
667
668/* IBS - apic initialization, for perf and oprofile */
669
670static __init u32 __get_ibs_caps(void)
671{
672	u32 caps;
673	unsigned int max_level;
674
675	if (!boot_cpu_has(X86_FEATURE_IBS))
676		return 0;
677
678	/* check IBS cpuid feature flags */
679	max_level = cpuid_eax(0x80000000);
680	if (max_level < IBS_CPUID_FEATURES)
681		return IBS_CAPS_DEFAULT;
682
683	caps = cpuid_eax(IBS_CPUID_FEATURES);
684	if (!(caps & IBS_CAPS_AVAIL))
685		/* cpuid flags not valid */
686		return IBS_CAPS_DEFAULT;
687
688	return caps;
689}
690
691u32 get_ibs_caps(void)
692{
693	return ibs_caps;
694}
695
696EXPORT_SYMBOL(get_ibs_caps);
697
698static inline int get_eilvt(int offset)
699{
700	return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
701}
702
703static inline int put_eilvt(int offset)
704{
705	return !setup_APIC_eilvt(offset, 0, 0, 1);
706}
707
708/*
709 * Check and reserve APIC extended interrupt LVT offset for IBS if available.
710 */
711static inline int ibs_eilvt_valid(void)
712{
713	int offset;
714	u64 val;
715	int valid = 0;
716
717	preempt_disable();
718
719	rdmsrl(MSR_AMD64_IBSCTL, val);
720	offset = val & IBSCTL_LVT_OFFSET_MASK;
721
722	if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
723		pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
724		       smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
725		goto out;
726	}
727
728	if (!get_eilvt(offset)) {
729		pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
730		       smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
731		goto out;
732	}
733
734	valid = 1;
735out:
736	preempt_enable();
737
738	return valid;
739}
740
741static int setup_ibs_ctl(int ibs_eilvt_off)
742{
743	struct pci_dev *cpu_cfg;
744	int nodes;
745	u32 value = 0;
746
747	nodes = 0;
748	cpu_cfg = NULL;
749	do {
750		cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
751					 PCI_DEVICE_ID_AMD_10H_NB_MISC,
752					 cpu_cfg);
753		if (!cpu_cfg)
754			break;
755		++nodes;
756		pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
757				       | IBSCTL_LVT_OFFSET_VALID);
758		pci_read_config_dword(cpu_cfg, IBSCTL, &value);
759		if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
760			pci_dev_put(cpu_cfg);
761			printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
762			       "IBSCTL = 0x%08x\n", value);
763			return -EINVAL;
764		}
765	} while (1);
766
767	if (!nodes) {
768		printk(KERN_DEBUG "No CPU node configured for IBS\n");
769		return -ENODEV;
770	}
771
772	return 0;
773}
774
775/*
776 * This runs only on the current cpu. We try to find an LVT offset and
777 * setup the local APIC. For this we must disable preemption. On
778 * success we initialize all nodes with this offset. This updates then
779 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
780 * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
781 * is using the new offset.
782 */
783static int force_ibs_eilvt_setup(void)
784{
785	int offset;
786	int ret;
787
788	preempt_disable();
789	/* find the next free available EILVT entry, skip offset 0 */
790	for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
791		if (get_eilvt(offset))
792			break;
793	}
794	preempt_enable();
795
796	if (offset == APIC_EILVT_NR_MAX) {
797		printk(KERN_DEBUG "No EILVT entry available\n");
798		return -EBUSY;
799	}
800
801	ret = setup_ibs_ctl(offset);
802	if (ret)
803		goto out;
804
805	if (!ibs_eilvt_valid()) {
806		ret = -EFAULT;
807		goto out;
808	}
809
810	pr_info("IBS: LVT offset %d assigned\n", offset);
811
812	return 0;
813out:
814	preempt_disable();
815	put_eilvt(offset);
816	preempt_enable();
817	return ret;
818}
819
820static void ibs_eilvt_setup(void)
821{
822	/*
823	 * Force LVT offset assignment for family 10h: The offsets are
824	 * not assigned by the BIOS for this family, so the OS is
825	 * responsible for doing it. If the OS assignment fails, fall
826	 * back to BIOS settings and try to setup this.
827	 */
828	if (boot_cpu_data.x86 == 0x10)
829		force_ibs_eilvt_setup();
830}
831
832static inline int get_ibs_lvt_offset(void)
833{
834	u64 val;
835
836	rdmsrl(MSR_AMD64_IBSCTL, val);
837	if (!(val & IBSCTL_LVT_OFFSET_VALID))
838		return -EINVAL;
839
840	return val & IBSCTL_LVT_OFFSET_MASK;
841}
842
843static void setup_APIC_ibs(void *dummy)
844{
845	int offset;
846
847	offset = get_ibs_lvt_offset();
848	if (offset < 0)
849		goto failed;
850
851	if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
852		return;
853failed:
854	pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
855		smp_processor_id());
856}
857
858static void clear_APIC_ibs(void *dummy)
859{
860	int offset;
861
862	offset = get_ibs_lvt_offset();
863	if (offset >= 0)
864		setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
865}
866
867#ifdef CONFIG_PM
868
869static int perf_ibs_suspend(void)
870{
871	clear_APIC_ibs(NULL);
872	return 0;
873}
874
875static void perf_ibs_resume(void)
876{
877	ibs_eilvt_setup();
878	setup_APIC_ibs(NULL);
879}
880
881static struct syscore_ops perf_ibs_syscore_ops = {
882	.resume		= perf_ibs_resume,
883	.suspend	= perf_ibs_suspend,
884};
885
886static void perf_ibs_pm_init(void)
887{
888	register_syscore_ops(&perf_ibs_syscore_ops);
889}
890
891#else
892
893static inline void perf_ibs_pm_init(void) { }
894
895#endif
896
897static int
898perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
899{
900	switch (action & ~CPU_TASKS_FROZEN) {
901	case CPU_STARTING:
902		setup_APIC_ibs(NULL);
903		break;
904	case CPU_DYING:
905		clear_APIC_ibs(NULL);
906		break;
907	default:
908		break;
909	}
910
911	return NOTIFY_OK;
912}
913
914static __init int amd_ibs_init(void)
915{
916	u32 caps;
917	int ret = -EINVAL;
918
919	caps = __get_ibs_caps();
920	if (!caps)
921		return -ENODEV;	/* ibs not supported by the cpu */
922
923	ibs_eilvt_setup();
924
925	if (!ibs_eilvt_valid())
926		goto out;
927
928	perf_ibs_pm_init();
929	cpu_notifier_register_begin();
930	ibs_caps = caps;
931	/* make ibs_caps visible to other cpus: */
932	smp_mb();
933	smp_call_function(setup_APIC_ibs, NULL, 1);
934	__perf_cpu_notifier(perf_ibs_cpu_notifier);
935	cpu_notifier_register_done();
936
937	ret = perf_event_ibs_init();
938out:
939	if (ret)
940		pr_err("Failed to setup IBS, %d\n", ret);
941	return ret;
942}
943
944/* Since we need the pci subsystem to init ibs we can't do this earlier: */
945device_initcall(amd_ibs_init);