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1/*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15#include <linux/perf_event.h>
16
17#if 0
18#undef wrmsrl
19#define wrmsrl(msr, val) \
20do { \
21 unsigned int _msr = (msr); \
22 u64 _val = (val); \
23 trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \
24 (unsigned long long)(_val)); \
25 native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \
26} while (0)
27#endif
28
29/*
30 * | NHM/WSM | SNB |
31 * register -------------------------------
32 * | HT | no HT | HT | no HT |
33 *-----------------------------------------
34 * offcore | core | core | cpu | core |
35 * lbr_sel | core | core | cpu | core |
36 * ld_lat | cpu | core | cpu | core |
37 *-----------------------------------------
38 *
39 * Given that there is a small number of shared regs,
40 * we can pre-allocate their slot in the per-cpu
41 * per-core reg tables.
42 */
43enum extra_reg_type {
44 EXTRA_REG_NONE = -1, /* not used */
45
46 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
47 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
48 EXTRA_REG_LBR = 2, /* lbr_select */
49 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
50
51 EXTRA_REG_MAX /* number of entries needed */
52};
53
54struct event_constraint {
55 union {
56 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
57 u64 idxmsk64;
58 };
59 u64 code;
60 u64 cmask;
61 int weight;
62 int overlap;
63 int flags;
64};
65/*
66 * struct hw_perf_event.flags flags
67 */
68#define PERF_X86_EVENT_PEBS_LDLAT 0x1 /* ld+ldlat data address sampling */
69#define PERF_X86_EVENT_PEBS_ST 0x2 /* st data address sampling */
70#define PERF_X86_EVENT_PEBS_ST_HSW 0x4 /* haswell style st data sampling */
71#define PERF_X86_EVENT_COMMITTED 0x8 /* event passed commit_txn */
72
73struct amd_nb {
74 int nb_id; /* NorthBridge id */
75 int refcnt; /* reference count */
76 struct perf_event *owners[X86_PMC_IDX_MAX];
77 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
78};
79
80/* The maximal number of PEBS events: */
81#define MAX_PEBS_EVENTS 8
82
83/*
84 * A debug store configuration.
85 *
86 * We only support architectures that use 64bit fields.
87 */
88struct debug_store {
89 u64 bts_buffer_base;
90 u64 bts_index;
91 u64 bts_absolute_maximum;
92 u64 bts_interrupt_threshold;
93 u64 pebs_buffer_base;
94 u64 pebs_index;
95 u64 pebs_absolute_maximum;
96 u64 pebs_interrupt_threshold;
97 u64 pebs_event_reset[MAX_PEBS_EVENTS];
98};
99
100/*
101 * Per register state.
102 */
103struct er_account {
104 raw_spinlock_t lock; /* per-core: protect structure */
105 u64 config; /* extra MSR config */
106 u64 reg; /* extra MSR number */
107 atomic_t ref; /* reference count */
108};
109
110/*
111 * Per core/cpu state
112 *
113 * Used to coordinate shared registers between HT threads or
114 * among events on a single PMU.
115 */
116struct intel_shared_regs {
117 struct er_account regs[EXTRA_REG_MAX];
118 int refcnt; /* per-core: #HT threads */
119 unsigned core_id; /* per-core: core id */
120};
121
122#define MAX_LBR_ENTRIES 16
123
124struct cpu_hw_events {
125 /*
126 * Generic x86 PMC bits
127 */
128 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
129 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
130 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
131 int enabled;
132
133 int n_events; /* the # of events in the below arrays */
134 int n_added; /* the # last events in the below arrays;
135 they've never been enabled yet */
136 int n_txn; /* the # last events in the below arrays;
137 added in the current transaction */
138 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
139 u64 tags[X86_PMC_IDX_MAX];
140 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
141
142 unsigned int group_flag;
143 int is_fake;
144
145 /*
146 * Intel DebugStore bits
147 */
148 struct debug_store *ds;
149 u64 pebs_enabled;
150
151 /*
152 * Intel LBR bits
153 */
154 int lbr_users;
155 void *lbr_context;
156 struct perf_branch_stack lbr_stack;
157 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
158 struct er_account *lbr_sel;
159 u64 br_sel;
160
161 /*
162 * Intel host/guest exclude bits
163 */
164 u64 intel_ctrl_guest_mask;
165 u64 intel_ctrl_host_mask;
166 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
167
168 /*
169 * Intel checkpoint mask
170 */
171 u64 intel_cp_status;
172
173 /*
174 * manage shared (per-core, per-cpu) registers
175 * used on Intel NHM/WSM/SNB
176 */
177 struct intel_shared_regs *shared_regs;
178
179 /*
180 * AMD specific bits
181 */
182 struct amd_nb *amd_nb;
183 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
184 u64 perf_ctr_virt_mask;
185
186 void *kfree_on_online;
187};
188
189#define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
190 { .idxmsk64 = (n) }, \
191 .code = (c), \
192 .cmask = (m), \
193 .weight = (w), \
194 .overlap = (o), \
195 .flags = f, \
196}
197
198#define EVENT_CONSTRAINT(c, n, m) \
199 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
200
201/*
202 * The overlap flag marks event constraints with overlapping counter
203 * masks. This is the case if the counter mask of such an event is not
204 * a subset of any other counter mask of a constraint with an equal or
205 * higher weight, e.g.:
206 *
207 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
208 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
209 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
210 *
211 * The event scheduler may not select the correct counter in the first
212 * cycle because it needs to know which subsequent events will be
213 * scheduled. It may fail to schedule the events then. So we set the
214 * overlap flag for such constraints to give the scheduler a hint which
215 * events to select for counter rescheduling.
216 *
217 * Care must be taken as the rescheduling algorithm is O(n!) which
218 * will increase scheduling cycles for an over-commited system
219 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
220 * and its counter masks must be kept at a minimum.
221 */
222#define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
223 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
224
225/*
226 * Constraint on the Event code.
227 */
228#define INTEL_EVENT_CONSTRAINT(c, n) \
229 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
230
231/*
232 * Constraint on the Event code + UMask + fixed-mask
233 *
234 * filter mask to validate fixed counter events.
235 * the following filters disqualify for fixed counters:
236 * - inv
237 * - edge
238 * - cnt-mask
239 * - in_tx
240 * - in_tx_checkpointed
241 * The other filters are supported by fixed counters.
242 * The any-thread option is supported starting with v3.
243 */
244#define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
245#define FIXED_EVENT_CONSTRAINT(c, n) \
246 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
247
248/*
249 * Constraint on the Event code + UMask
250 */
251#define INTEL_UEVENT_CONSTRAINT(c, n) \
252 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
253
254#define INTEL_PLD_CONSTRAINT(c, n) \
255 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
256 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
257
258#define INTEL_PST_CONSTRAINT(c, n) \
259 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
260 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
261
262/* DataLA version of store sampling without extra enable bit. */
263#define INTEL_PST_HSW_CONSTRAINT(c, n) \
264 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
265 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
266
267/*
268 * We define the end marker as having a weight of -1
269 * to enable blacklisting of events using a counter bitmask
270 * of zero and thus a weight of zero.
271 * The end marker has a weight that cannot possibly be
272 * obtained from counting the bits in the bitmask.
273 */
274#define EVENT_CONSTRAINT_END { .weight = -1 }
275
276/*
277 * Check for end marker with weight == -1
278 */
279#define for_each_event_constraint(e, c) \
280 for ((e) = (c); (e)->weight != -1; (e)++)
281
282/*
283 * Extra registers for specific events.
284 *
285 * Some events need large masks and require external MSRs.
286 * Those extra MSRs end up being shared for all events on
287 * a PMU and sometimes between PMU of sibling HT threads.
288 * In either case, the kernel needs to handle conflicting
289 * accesses to those extra, shared, regs. The data structure
290 * to manage those registers is stored in cpu_hw_event.
291 */
292struct extra_reg {
293 unsigned int event;
294 unsigned int msr;
295 u64 config_mask;
296 u64 valid_mask;
297 int idx; /* per_xxx->regs[] reg index */
298};
299
300#define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
301 .event = (e), \
302 .msr = (ms), \
303 .config_mask = (m), \
304 .valid_mask = (vm), \
305 .idx = EXTRA_REG_##i, \
306 }
307
308#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
309 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
310
311#define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
312 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
313 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
314
315#define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
316 INTEL_UEVENT_EXTRA_REG(c, \
317 MSR_PEBS_LD_LAT_THRESHOLD, \
318 0xffff, \
319 LDLAT)
320
321#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
322
323union perf_capabilities {
324 struct {
325 u64 lbr_format:6;
326 u64 pebs_trap:1;
327 u64 pebs_arch_reg:1;
328 u64 pebs_format:4;
329 u64 smm_freeze:1;
330 /*
331 * PMU supports separate counter range for writing
332 * values > 32bit.
333 */
334 u64 full_width_write:1;
335 };
336 u64 capabilities;
337};
338
339struct x86_pmu_quirk {
340 struct x86_pmu_quirk *next;
341 void (*func)(void);
342};
343
344union x86_pmu_config {
345 struct {
346 u64 event:8,
347 umask:8,
348 usr:1,
349 os:1,
350 edge:1,
351 pc:1,
352 interrupt:1,
353 __reserved1:1,
354 en:1,
355 inv:1,
356 cmask:8,
357 event2:4,
358 __reserved2:4,
359 go:1,
360 ho:1;
361 } bits;
362 u64 value;
363};
364
365#define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
366
367/*
368 * struct x86_pmu - generic x86 pmu
369 */
370struct x86_pmu {
371 /*
372 * Generic x86 PMC bits
373 */
374 const char *name;
375 int version;
376 int (*handle_irq)(struct pt_regs *);
377 void (*disable_all)(void);
378 void (*enable_all)(int added);
379 void (*enable)(struct perf_event *);
380 void (*disable)(struct perf_event *);
381 int (*hw_config)(struct perf_event *event);
382 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
383 unsigned eventsel;
384 unsigned perfctr;
385 int (*addr_offset)(int index, bool eventsel);
386 int (*rdpmc_index)(int index);
387 u64 (*event_map)(int);
388 int max_events;
389 int num_counters;
390 int num_counters_fixed;
391 int cntval_bits;
392 u64 cntval_mask;
393 union {
394 unsigned long events_maskl;
395 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
396 };
397 int events_mask_len;
398 int apic;
399 u64 max_period;
400 struct event_constraint *
401 (*get_event_constraints)(struct cpu_hw_events *cpuc,
402 struct perf_event *event);
403
404 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
405 struct perf_event *event);
406 struct event_constraint *event_constraints;
407 struct x86_pmu_quirk *quirks;
408 int perfctr_second_write;
409 bool late_ack;
410
411 /*
412 * sysfs attrs
413 */
414 int attr_rdpmc_broken;
415 int attr_rdpmc;
416 struct attribute **format_attrs;
417 struct attribute **event_attrs;
418
419 ssize_t (*events_sysfs_show)(char *page, u64 config);
420 struct attribute **cpu_events;
421
422 /*
423 * CPU Hotplug hooks
424 */
425 int (*cpu_prepare)(int cpu);
426 void (*cpu_starting)(int cpu);
427 void (*cpu_dying)(int cpu);
428 void (*cpu_dead)(int cpu);
429
430 void (*check_microcode)(void);
431 void (*flush_branch_stack)(void);
432
433 /*
434 * Intel Arch Perfmon v2+
435 */
436 u64 intel_ctrl;
437 union perf_capabilities intel_cap;
438
439 /*
440 * Intel DebugStore bits
441 */
442 unsigned int bts :1,
443 bts_active :1,
444 pebs :1,
445 pebs_active :1,
446 pebs_broken :1;
447 int pebs_record_size;
448 void (*drain_pebs)(struct pt_regs *regs);
449 struct event_constraint *pebs_constraints;
450 void (*pebs_aliases)(struct perf_event *event);
451 int max_pebs_events;
452
453 /*
454 * Intel LBR
455 */
456 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
457 int lbr_nr; /* hardware stack size */
458 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
459 const int *lbr_sel_map; /* lbr_select mappings */
460 bool lbr_double_abort; /* duplicated lbr aborts */
461
462 /*
463 * Extra registers for events
464 */
465 struct extra_reg *extra_regs;
466 unsigned int er_flags;
467
468 /*
469 * Intel host/guest support (KVM)
470 */
471 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
472};
473
474#define x86_add_quirk(func_) \
475do { \
476 static struct x86_pmu_quirk __quirk __initdata = { \
477 .func = func_, \
478 }; \
479 __quirk.next = x86_pmu.quirks; \
480 x86_pmu.quirks = &__quirk; \
481} while (0)
482
483#define ERF_NO_HT_SHARING 1
484#define ERF_HAS_RSP_1 2
485
486#define EVENT_VAR(_id) event_attr_##_id
487#define EVENT_PTR(_id) &event_attr_##_id.attr.attr
488
489#define EVENT_ATTR(_name, _id) \
490static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
491 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
492 .id = PERF_COUNT_HW_##_id, \
493 .event_str = NULL, \
494};
495
496#define EVENT_ATTR_STR(_name, v, str) \
497static struct perf_pmu_events_attr event_attr_##v = { \
498 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
499 .id = 0, \
500 .event_str = str, \
501};
502
503extern struct x86_pmu x86_pmu __read_mostly;
504
505DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
506
507int x86_perf_event_set_period(struct perf_event *event);
508
509/*
510 * Generalized hw caching related hw_event table, filled
511 * in on a per model basis. A value of 0 means
512 * 'not supported', -1 means 'hw_event makes no sense on
513 * this CPU', any other value means the raw hw_event
514 * ID.
515 */
516
517#define C(x) PERF_COUNT_HW_CACHE_##x
518
519extern u64 __read_mostly hw_cache_event_ids
520 [PERF_COUNT_HW_CACHE_MAX]
521 [PERF_COUNT_HW_CACHE_OP_MAX]
522 [PERF_COUNT_HW_CACHE_RESULT_MAX];
523extern u64 __read_mostly hw_cache_extra_regs
524 [PERF_COUNT_HW_CACHE_MAX]
525 [PERF_COUNT_HW_CACHE_OP_MAX]
526 [PERF_COUNT_HW_CACHE_RESULT_MAX];
527
528u64 x86_perf_event_update(struct perf_event *event);
529
530static inline unsigned int x86_pmu_config_addr(int index)
531{
532 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
533 x86_pmu.addr_offset(index, true) : index);
534}
535
536static inline unsigned int x86_pmu_event_addr(int index)
537{
538 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
539 x86_pmu.addr_offset(index, false) : index);
540}
541
542static inline int x86_pmu_rdpmc_index(int index)
543{
544 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
545}
546
547int x86_setup_perfctr(struct perf_event *event);
548
549int x86_pmu_hw_config(struct perf_event *event);
550
551void x86_pmu_disable_all(void);
552
553static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
554 u64 enable_mask)
555{
556 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
557
558 if (hwc->extra_reg.reg)
559 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
560 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
561}
562
563void x86_pmu_enable_all(int added);
564
565int perf_assign_events(struct perf_event **events, int n,
566 int wmin, int wmax, int *assign);
567int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
568
569void x86_pmu_stop(struct perf_event *event, int flags);
570
571static inline void x86_pmu_disable_event(struct perf_event *event)
572{
573 struct hw_perf_event *hwc = &event->hw;
574
575 wrmsrl(hwc->config_base, hwc->config);
576}
577
578void x86_pmu_enable_event(struct perf_event *event);
579
580int x86_pmu_handle_irq(struct pt_regs *regs);
581
582extern struct event_constraint emptyconstraint;
583
584extern struct event_constraint unconstrained;
585
586static inline bool kernel_ip(unsigned long ip)
587{
588#ifdef CONFIG_X86_32
589 return ip > PAGE_OFFSET;
590#else
591 return (long)ip < 0;
592#endif
593}
594
595/*
596 * Not all PMUs provide the right context information to place the reported IP
597 * into full context. Specifically segment registers are typically not
598 * supplied.
599 *
600 * Assuming the address is a linear address (it is for IBS), we fake the CS and
601 * vm86 mode using the known zero-based code segment and 'fix up' the registers
602 * to reflect this.
603 *
604 * Intel PEBS/LBR appear to typically provide the effective address, nothing
605 * much we can do about that but pray and treat it like a linear address.
606 */
607static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
608{
609 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
610 if (regs->flags & X86_VM_MASK)
611 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
612 regs->ip = ip;
613}
614
615ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
616ssize_t intel_event_sysfs_show(char *page, u64 config);
617
618#ifdef CONFIG_CPU_SUP_AMD
619
620int amd_pmu_init(void);
621
622#else /* CONFIG_CPU_SUP_AMD */
623
624static inline int amd_pmu_init(void)
625{
626 return 0;
627}
628
629#endif /* CONFIG_CPU_SUP_AMD */
630
631#ifdef CONFIG_CPU_SUP_INTEL
632
633int intel_pmu_save_and_restart(struct perf_event *event);
634
635struct event_constraint *
636x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
637
638struct intel_shared_regs *allocate_shared_regs(int cpu);
639
640int intel_pmu_init(void);
641
642void init_debug_store_on_cpu(int cpu);
643
644void fini_debug_store_on_cpu(int cpu);
645
646void release_ds_buffers(void);
647
648void reserve_ds_buffers(void);
649
650extern struct event_constraint bts_constraint;
651
652void intel_pmu_enable_bts(u64 config);
653
654void intel_pmu_disable_bts(void);
655
656int intel_pmu_drain_bts_buffer(void);
657
658extern struct event_constraint intel_core2_pebs_event_constraints[];
659
660extern struct event_constraint intel_atom_pebs_event_constraints[];
661
662extern struct event_constraint intel_slm_pebs_event_constraints[];
663
664extern struct event_constraint intel_nehalem_pebs_event_constraints[];
665
666extern struct event_constraint intel_westmere_pebs_event_constraints[];
667
668extern struct event_constraint intel_snb_pebs_event_constraints[];
669
670extern struct event_constraint intel_ivb_pebs_event_constraints[];
671
672extern struct event_constraint intel_hsw_pebs_event_constraints[];
673
674struct event_constraint *intel_pebs_constraints(struct perf_event *event);
675
676void intel_pmu_pebs_enable(struct perf_event *event);
677
678void intel_pmu_pebs_disable(struct perf_event *event);
679
680void intel_pmu_pebs_enable_all(void);
681
682void intel_pmu_pebs_disable_all(void);
683
684void intel_ds_init(void);
685
686void intel_pmu_lbr_reset(void);
687
688void intel_pmu_lbr_enable(struct perf_event *event);
689
690void intel_pmu_lbr_disable(struct perf_event *event);
691
692void intel_pmu_lbr_enable_all(void);
693
694void intel_pmu_lbr_disable_all(void);
695
696void intel_pmu_lbr_read(void);
697
698void intel_pmu_lbr_init_core(void);
699
700void intel_pmu_lbr_init_nhm(void);
701
702void intel_pmu_lbr_init_atom(void);
703
704void intel_pmu_lbr_init_snb(void);
705
706int intel_pmu_setup_lbr_filter(struct perf_event *event);
707
708int p4_pmu_init(void);
709
710int p6_pmu_init(void);
711
712int knc_pmu_init(void);
713
714ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
715 char *page);
716
717#else /* CONFIG_CPU_SUP_INTEL */
718
719static inline void reserve_ds_buffers(void)
720{
721}
722
723static inline void release_ds_buffers(void)
724{
725}
726
727static inline int intel_pmu_init(void)
728{
729 return 0;
730}
731
732static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
733{
734 return NULL;
735}
736
737#endif /* CONFIG_CPU_SUP_INTEL */