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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * iommu.c: IOMMU specific routines for memory management.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
7 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/slab.h>
15#include <linux/highmem.h> /* pte_offset_map => kmap_atomic */
16#include <linux/dma-mapping.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19
20#include <asm/pgalloc.h>
21#include <asm/pgtable.h>
22#include <asm/io.h>
23#include <asm/mxcc.h>
24#include <asm/mbus.h>
25#include <asm/cacheflush.h>
26#include <asm/tlbflush.h>
27#include <asm/bitext.h>
28#include <asm/iommu.h>
29#include <asm/dma.h>
30
31#include "mm_32.h"
32
33/*
34 * This can be sized dynamically, but we will do this
35 * only when we have a guidance about actual I/O pressures.
36 */
37#define IOMMU_RNGE IOMMU_RNGE_256MB
38#define IOMMU_START 0xF0000000
39#define IOMMU_WINSIZE (256*1024*1024U)
40#define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
41#define IOMMU_ORDER 6 /* 4096 * (1<<6) */
42
43static int viking_flush;
44/* viking.S */
45extern void viking_flush_page(unsigned long page);
46extern void viking_mxcc_flush_page(unsigned long page);
47
48/*
49 * Values precomputed according to CPU type.
50 */
51static unsigned int ioperm_noc; /* Consistent mapping iopte flags */
52static pgprot_t dvma_prot; /* Consistent mapping pte flags */
53
54#define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
55#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
56
57static void __init sbus_iommu_init(struct platform_device *op)
58{
59 struct iommu_struct *iommu;
60 unsigned int impl, vers;
61 unsigned long *bitmap;
62 unsigned long control;
63 unsigned long base;
64 unsigned long tmp;
65
66 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
67 if (!iommu) {
68 prom_printf("Unable to allocate iommu structure\n");
69 prom_halt();
70 }
71
72 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
73 "iommu_regs");
74 if (!iommu->regs) {
75 prom_printf("Cannot map IOMMU registers\n");
76 prom_halt();
77 }
78
79 control = sbus_readl(&iommu->regs->control);
80 impl = (control & IOMMU_CTRL_IMPL) >> 28;
81 vers = (control & IOMMU_CTRL_VERS) >> 24;
82 control &= ~(IOMMU_CTRL_RNGE);
83 control |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
84 sbus_writel(control, &iommu->regs->control);
85
86 iommu_invalidate(iommu->regs);
87 iommu->start = IOMMU_START;
88 iommu->end = 0xffffffff;
89
90 /* Allocate IOMMU page table */
91 /* Stupid alignment constraints give me a headache.
92 We need 256K or 512K or 1M or 2M area aligned to
93 its size and current gfp will fortunately give
94 it to us. */
95 tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
96 if (!tmp) {
97 prom_printf("Unable to allocate iommu table [0x%lx]\n",
98 IOMMU_NPTES * sizeof(iopte_t));
99 prom_halt();
100 }
101 iommu->page_table = (iopte_t *)tmp;
102
103 /* Initialize new table. */
104 memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
105 flush_cache_all();
106 flush_tlb_all();
107
108 base = __pa((unsigned long)iommu->page_table) >> 4;
109 sbus_writel(base, &iommu->regs->base);
110 iommu_invalidate(iommu->regs);
111
112 bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
113 if (!bitmap) {
114 prom_printf("Unable to allocate iommu bitmap [%d]\n",
115 (int)(IOMMU_NPTES>>3));
116 prom_halt();
117 }
118 bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
119 /* To be coherent on HyperSparc, the page color of DVMA
120 * and physical addresses must match.
121 */
122 if (srmmu_modtype == HyperSparc)
123 iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
124 else
125 iommu->usemap.num_colors = 1;
126
127 printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
128 impl, vers, iommu->page_table,
129 (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
130
131 op->dev.archdata.iommu = iommu;
132}
133
134static int __init iommu_init(void)
135{
136 struct device_node *dp;
137
138 for_each_node_by_name(dp, "iommu") {
139 struct platform_device *op = of_find_device_by_node(dp);
140
141 sbus_iommu_init(op);
142 of_propagate_archdata(op);
143 }
144
145 return 0;
146}
147
148subsys_initcall(iommu_init);
149
150/* Flush the iotlb entries to ram. */
151/* This could be better if we didn't have to flush whole pages. */
152static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
153{
154 unsigned long start;
155 unsigned long end;
156
157 start = (unsigned long)iopte;
158 end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
159 start &= PAGE_MASK;
160 if (viking_mxcc_present) {
161 while(start < end) {
162 viking_mxcc_flush_page(start);
163 start += PAGE_SIZE;
164 }
165 } else if (viking_flush) {
166 while(start < end) {
167 viking_flush_page(start);
168 start += PAGE_SIZE;
169 }
170 } else {
171 while(start < end) {
172 __flush_page_to_ram(start);
173 start += PAGE_SIZE;
174 }
175 }
176}
177
178static dma_addr_t __sbus_iommu_map_page(struct device *dev, struct page *page,
179 unsigned long offset, size_t len, bool per_page_flush)
180{
181 struct iommu_struct *iommu = dev->archdata.iommu;
182 phys_addr_t paddr = page_to_phys(page) + offset;
183 unsigned long off = paddr & ~PAGE_MASK;
184 unsigned long npages = (off + len + PAGE_SIZE - 1) >> PAGE_SHIFT;
185 unsigned long pfn = __phys_to_pfn(paddr);
186 unsigned int busa, busa0;
187 iopte_t *iopte, *iopte0;
188 int ioptex, i;
189
190 /* XXX So what is maxphys for us and how do drivers know it? */
191 if (!len || len > 256 * 1024)
192 return DMA_MAPPING_ERROR;
193
194 /*
195 * We expect unmapped highmem pages to be not in the cache.
196 * XXX Is this a good assumption?
197 * XXX What if someone else unmaps it here and races us?
198 */
199 if (per_page_flush && !PageHighMem(page)) {
200 unsigned long vaddr, p;
201
202 vaddr = (unsigned long)page_address(page) + offset;
203 for (p = vaddr & PAGE_MASK; p < vaddr + len; p += PAGE_SIZE)
204 flush_page_for_dma(p);
205 }
206
207 /* page color = pfn of page */
208 ioptex = bit_map_string_get(&iommu->usemap, npages, pfn);
209 if (ioptex < 0)
210 panic("iommu out");
211 busa0 = iommu->start + (ioptex << PAGE_SHIFT);
212 iopte0 = &iommu->page_table[ioptex];
213
214 busa = busa0;
215 iopte = iopte0;
216 for (i = 0; i < npages; i++) {
217 iopte_val(*iopte) = MKIOPTE(pfn, IOPERM);
218 iommu_invalidate_page(iommu->regs, busa);
219 busa += PAGE_SIZE;
220 iopte++;
221 pfn++;
222 }
223
224 iommu_flush_iotlb(iopte0, npages);
225 return busa0 + off;
226}
227
228static dma_addr_t sbus_iommu_map_page_gflush(struct device *dev,
229 struct page *page, unsigned long offset, size_t len,
230 enum dma_data_direction dir, unsigned long attrs)
231{
232 flush_page_for_dma(0);
233 return __sbus_iommu_map_page(dev, page, offset, len, false);
234}
235
236static dma_addr_t sbus_iommu_map_page_pflush(struct device *dev,
237 struct page *page, unsigned long offset, size_t len,
238 enum dma_data_direction dir, unsigned long attrs)
239{
240 return __sbus_iommu_map_page(dev, page, offset, len, true);
241}
242
243static int __sbus_iommu_map_sg(struct device *dev, struct scatterlist *sgl,
244 int nents, enum dma_data_direction dir, unsigned long attrs,
245 bool per_page_flush)
246{
247 struct scatterlist *sg;
248 int j;
249
250 for_each_sg(sgl, sg, nents, j) {
251 sg->dma_address =__sbus_iommu_map_page(dev, sg_page(sg),
252 sg->offset, sg->length, per_page_flush);
253 if (sg->dma_address == DMA_MAPPING_ERROR)
254 return 0;
255 sg->dma_length = sg->length;
256 }
257
258 return nents;
259}
260
261static int sbus_iommu_map_sg_gflush(struct device *dev, struct scatterlist *sgl,
262 int nents, enum dma_data_direction dir, unsigned long attrs)
263{
264 flush_page_for_dma(0);
265 return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, false);
266}
267
268static int sbus_iommu_map_sg_pflush(struct device *dev, struct scatterlist *sgl,
269 int nents, enum dma_data_direction dir, unsigned long attrs)
270{
271 return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, true);
272}
273
274static void sbus_iommu_unmap_page(struct device *dev, dma_addr_t dma_addr,
275 size_t len, enum dma_data_direction dir, unsigned long attrs)
276{
277 struct iommu_struct *iommu = dev->archdata.iommu;
278 unsigned int busa = dma_addr & PAGE_MASK;
279 unsigned long off = dma_addr & ~PAGE_MASK;
280 unsigned int npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
281 unsigned int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
282 unsigned int i;
283
284 BUG_ON(busa < iommu->start);
285 for (i = 0; i < npages; i++) {
286 iopte_val(iommu->page_table[ioptex + i]) = 0;
287 iommu_invalidate_page(iommu->regs, busa);
288 busa += PAGE_SIZE;
289 }
290 bit_map_clear(&iommu->usemap, ioptex, npages);
291}
292
293static void sbus_iommu_unmap_sg(struct device *dev, struct scatterlist *sgl,
294 int nents, enum dma_data_direction dir, unsigned long attrs)
295{
296 struct scatterlist *sg;
297 int i;
298
299 for_each_sg(sgl, sg, nents, i) {
300 sbus_iommu_unmap_page(dev, sg->dma_address, sg->length, dir,
301 attrs);
302 sg->dma_address = 0x21212121;
303 }
304}
305
306#ifdef CONFIG_SBUS
307static void *sbus_iommu_alloc(struct device *dev, size_t len,
308 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
309{
310 struct iommu_struct *iommu = dev->archdata.iommu;
311 unsigned long va, addr, page, end, ret;
312 iopte_t *iopte = iommu->page_table;
313 iopte_t *first;
314 int ioptex;
315
316 /* XXX So what is maxphys for us and how do drivers know it? */
317 if (!len || len > 256 * 1024)
318 return NULL;
319
320 len = PAGE_ALIGN(len);
321 va = __get_free_pages(gfp | __GFP_ZERO, get_order(len));
322 if (va == 0)
323 return NULL;
324
325 addr = ret = sparc_dma_alloc_resource(dev, len);
326 if (!addr)
327 goto out_free_pages;
328
329 BUG_ON((va & ~PAGE_MASK) != 0);
330 BUG_ON((addr & ~PAGE_MASK) != 0);
331 BUG_ON((len & ~PAGE_MASK) != 0);
332
333 /* page color = physical address */
334 ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
335 addr >> PAGE_SHIFT);
336 if (ioptex < 0)
337 panic("iommu out");
338
339 iopte += ioptex;
340 first = iopte;
341 end = addr + len;
342 while(addr < end) {
343 page = va;
344 {
345 pgd_t *pgdp;
346 pmd_t *pmdp;
347 pte_t *ptep;
348
349 if (viking_mxcc_present)
350 viking_mxcc_flush_page(page);
351 else if (viking_flush)
352 viking_flush_page(page);
353 else
354 __flush_page_to_ram(page);
355
356 pgdp = pgd_offset(&init_mm, addr);
357 pmdp = pmd_offset(pgdp, addr);
358 ptep = pte_offset_map(pmdp, addr);
359
360 set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
361 }
362 iopte_val(*iopte++) =
363 MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
364 addr += PAGE_SIZE;
365 va += PAGE_SIZE;
366 }
367 /* P3: why do we need this?
368 *
369 * DAVEM: Because there are several aspects, none of which
370 * are handled by a single interface. Some cpus are
371 * completely not I/O DMA coherent, and some have
372 * virtually indexed caches. The driver DMA flushing
373 * methods handle the former case, but here during
374 * IOMMU page table modifications, and usage of non-cacheable
375 * cpu mappings of pages potentially in the cpu caches, we have
376 * to handle the latter case as well.
377 */
378 flush_cache_all();
379 iommu_flush_iotlb(first, len >> PAGE_SHIFT);
380 flush_tlb_all();
381 iommu_invalidate(iommu->regs);
382
383 *dma_handle = iommu->start + (ioptex << PAGE_SHIFT);
384 return (void *)ret;
385
386out_free_pages:
387 free_pages(va, get_order(len));
388 return NULL;
389}
390
391static void sbus_iommu_free(struct device *dev, size_t len, void *cpu_addr,
392 dma_addr_t busa, unsigned long attrs)
393{
394 struct iommu_struct *iommu = dev->archdata.iommu;
395 iopte_t *iopte = iommu->page_table;
396 struct page *page = virt_to_page(cpu_addr);
397 int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
398 unsigned long end;
399
400 if (!sparc_dma_free_resource(cpu_addr, len))
401 return;
402
403 BUG_ON((busa & ~PAGE_MASK) != 0);
404 BUG_ON((len & ~PAGE_MASK) != 0);
405
406 iopte += ioptex;
407 end = busa + len;
408 while (busa < end) {
409 iopte_val(*iopte++) = 0;
410 busa += PAGE_SIZE;
411 }
412 flush_tlb_all();
413 iommu_invalidate(iommu->regs);
414 bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
415
416 __free_pages(page, get_order(len));
417}
418#endif
419
420static const struct dma_map_ops sbus_iommu_dma_gflush_ops = {
421#ifdef CONFIG_SBUS
422 .alloc = sbus_iommu_alloc,
423 .free = sbus_iommu_free,
424#endif
425 .map_page = sbus_iommu_map_page_gflush,
426 .unmap_page = sbus_iommu_unmap_page,
427 .map_sg = sbus_iommu_map_sg_gflush,
428 .unmap_sg = sbus_iommu_unmap_sg,
429};
430
431static const struct dma_map_ops sbus_iommu_dma_pflush_ops = {
432#ifdef CONFIG_SBUS
433 .alloc = sbus_iommu_alloc,
434 .free = sbus_iommu_free,
435#endif
436 .map_page = sbus_iommu_map_page_pflush,
437 .unmap_page = sbus_iommu_unmap_page,
438 .map_sg = sbus_iommu_map_sg_pflush,
439 .unmap_sg = sbus_iommu_unmap_sg,
440};
441
442void __init ld_mmu_iommu(void)
443{
444 if (flush_page_for_dma_global) {
445 /* flush_page_for_dma flushes everything, no matter of what page is it */
446 dma_ops = &sbus_iommu_dma_gflush_ops;
447 } else {
448 dma_ops = &sbus_iommu_dma_pflush_ops;
449 }
450
451 if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
452 dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
453 ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
454 } else {
455 dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
456 ioperm_noc = IOPTE_WRITE | IOPTE_VALID;
457 }
458}
1/*
2 * iommu.c: IOMMU specific routines for memory management.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/mm.h>
13#include <linux/slab.h>
14#include <linux/highmem.h> /* pte_offset_map => kmap_atomic */
15#include <linux/scatterlist.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18
19#include <asm/pgalloc.h>
20#include <asm/pgtable.h>
21#include <asm/io.h>
22#include <asm/mxcc.h>
23#include <asm/mbus.h>
24#include <asm/cacheflush.h>
25#include <asm/tlbflush.h>
26#include <asm/bitext.h>
27#include <asm/iommu.h>
28#include <asm/dma.h>
29
30/*
31 * This can be sized dynamically, but we will do this
32 * only when we have a guidance about actual I/O pressures.
33 */
34#define IOMMU_RNGE IOMMU_RNGE_256MB
35#define IOMMU_START 0xF0000000
36#define IOMMU_WINSIZE (256*1024*1024U)
37#define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
38#define IOMMU_ORDER 6 /* 4096 * (1<<6) */
39
40/* srmmu.c */
41extern int viking_mxcc_present;
42extern int flush_page_for_dma_global;
43static int viking_flush;
44/* viking.S */
45extern void viking_flush_page(unsigned long page);
46extern void viking_mxcc_flush_page(unsigned long page);
47
48/*
49 * Values precomputed according to CPU type.
50 */
51static unsigned int ioperm_noc; /* Consistent mapping iopte flags */
52static pgprot_t dvma_prot; /* Consistent mapping pte flags */
53
54#define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
55#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
56
57static void __init sbus_iommu_init(struct platform_device *op)
58{
59 struct iommu_struct *iommu;
60 unsigned int impl, vers;
61 unsigned long *bitmap;
62 unsigned long tmp;
63
64 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
65 if (!iommu) {
66 prom_printf("Unable to allocate iommu structure\n");
67 prom_halt();
68 }
69
70 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
71 "iommu_regs");
72 if (!iommu->regs) {
73 prom_printf("Cannot map IOMMU registers\n");
74 prom_halt();
75 }
76 impl = (iommu->regs->control & IOMMU_CTRL_IMPL) >> 28;
77 vers = (iommu->regs->control & IOMMU_CTRL_VERS) >> 24;
78 tmp = iommu->regs->control;
79 tmp &= ~(IOMMU_CTRL_RNGE);
80 tmp |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
81 iommu->regs->control = tmp;
82 iommu_invalidate(iommu->regs);
83 iommu->start = IOMMU_START;
84 iommu->end = 0xffffffff;
85
86 /* Allocate IOMMU page table */
87 /* Stupid alignment constraints give me a headache.
88 We need 256K or 512K or 1M or 2M area aligned to
89 its size and current gfp will fortunately give
90 it to us. */
91 tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
92 if (!tmp) {
93 prom_printf("Unable to allocate iommu table [0x%lx]\n",
94 IOMMU_NPTES * sizeof(iopte_t));
95 prom_halt();
96 }
97 iommu->page_table = (iopte_t *)tmp;
98
99 /* Initialize new table. */
100 memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
101 flush_cache_all();
102 flush_tlb_all();
103 iommu->regs->base = __pa((unsigned long) iommu->page_table) >> 4;
104 iommu_invalidate(iommu->regs);
105
106 bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
107 if (!bitmap) {
108 prom_printf("Unable to allocate iommu bitmap [%d]\n",
109 (int)(IOMMU_NPTES>>3));
110 prom_halt();
111 }
112 bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
113 /* To be coherent on HyperSparc, the page color of DVMA
114 * and physical addresses must match.
115 */
116 if (srmmu_modtype == HyperSparc)
117 iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
118 else
119 iommu->usemap.num_colors = 1;
120
121 printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
122 impl, vers, iommu->page_table,
123 (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
124
125 op->dev.archdata.iommu = iommu;
126}
127
128static int __init iommu_init(void)
129{
130 struct device_node *dp;
131
132 for_each_node_by_name(dp, "iommu") {
133 struct platform_device *op = of_find_device_by_node(dp);
134
135 sbus_iommu_init(op);
136 of_propagate_archdata(op);
137 }
138
139 return 0;
140}
141
142subsys_initcall(iommu_init);
143
144/* Flush the iotlb entries to ram. */
145/* This could be better if we didn't have to flush whole pages. */
146static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
147{
148 unsigned long start;
149 unsigned long end;
150
151 start = (unsigned long)iopte;
152 end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
153 start &= PAGE_MASK;
154 if (viking_mxcc_present) {
155 while(start < end) {
156 viking_mxcc_flush_page(start);
157 start += PAGE_SIZE;
158 }
159 } else if (viking_flush) {
160 while(start < end) {
161 viking_flush_page(start);
162 start += PAGE_SIZE;
163 }
164 } else {
165 while(start < end) {
166 __flush_page_to_ram(start);
167 start += PAGE_SIZE;
168 }
169 }
170}
171
172static u32 iommu_get_one(struct device *dev, struct page *page, int npages)
173{
174 struct iommu_struct *iommu = dev->archdata.iommu;
175 int ioptex;
176 iopte_t *iopte, *iopte0;
177 unsigned int busa, busa0;
178 int i;
179
180 /* page color = pfn of page */
181 ioptex = bit_map_string_get(&iommu->usemap, npages, page_to_pfn(page));
182 if (ioptex < 0)
183 panic("iommu out");
184 busa0 = iommu->start + (ioptex << PAGE_SHIFT);
185 iopte0 = &iommu->page_table[ioptex];
186
187 busa = busa0;
188 iopte = iopte0;
189 for (i = 0; i < npages; i++) {
190 iopte_val(*iopte) = MKIOPTE(page_to_pfn(page), IOPERM);
191 iommu_invalidate_page(iommu->regs, busa);
192 busa += PAGE_SIZE;
193 iopte++;
194 page++;
195 }
196
197 iommu_flush_iotlb(iopte0, npages);
198
199 return busa0;
200}
201
202static u32 iommu_get_scsi_one(struct device *dev, char *vaddr, unsigned int len)
203{
204 unsigned long off;
205 int npages;
206 struct page *page;
207 u32 busa;
208
209 off = (unsigned long)vaddr & ~PAGE_MASK;
210 npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
211 page = virt_to_page((unsigned long)vaddr & PAGE_MASK);
212 busa = iommu_get_one(dev, page, npages);
213 return busa + off;
214}
215
216static __u32 iommu_get_scsi_one_gflush(struct device *dev, char *vaddr, unsigned long len)
217{
218 flush_page_for_dma(0);
219 return iommu_get_scsi_one(dev, vaddr, len);
220}
221
222static __u32 iommu_get_scsi_one_pflush(struct device *dev, char *vaddr, unsigned long len)
223{
224 unsigned long page = ((unsigned long) vaddr) & PAGE_MASK;
225
226 while(page < ((unsigned long)(vaddr + len))) {
227 flush_page_for_dma(page);
228 page += PAGE_SIZE;
229 }
230 return iommu_get_scsi_one(dev, vaddr, len);
231}
232
233static void iommu_get_scsi_sgl_gflush(struct device *dev, struct scatterlist *sg, int sz)
234{
235 int n;
236
237 flush_page_for_dma(0);
238 while (sz != 0) {
239 --sz;
240 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
241 sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
242 sg->dma_length = sg->length;
243 sg = sg_next(sg);
244 }
245}
246
247static void iommu_get_scsi_sgl_pflush(struct device *dev, struct scatterlist *sg, int sz)
248{
249 unsigned long page, oldpage = 0;
250 int n, i;
251
252 while(sz != 0) {
253 --sz;
254
255 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
256
257 /*
258 * We expect unmapped highmem pages to be not in the cache.
259 * XXX Is this a good assumption?
260 * XXX What if someone else unmaps it here and races us?
261 */
262 if ((page = (unsigned long) page_address(sg_page(sg))) != 0) {
263 for (i = 0; i < n; i++) {
264 if (page != oldpage) { /* Already flushed? */
265 flush_page_for_dma(page);
266 oldpage = page;
267 }
268 page += PAGE_SIZE;
269 }
270 }
271
272 sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
273 sg->dma_length = sg->length;
274 sg = sg_next(sg);
275 }
276}
277
278static void iommu_release_one(struct device *dev, u32 busa, int npages)
279{
280 struct iommu_struct *iommu = dev->archdata.iommu;
281 int ioptex;
282 int i;
283
284 BUG_ON(busa < iommu->start);
285 ioptex = (busa - iommu->start) >> PAGE_SHIFT;
286 for (i = 0; i < npages; i++) {
287 iopte_val(iommu->page_table[ioptex + i]) = 0;
288 iommu_invalidate_page(iommu->regs, busa);
289 busa += PAGE_SIZE;
290 }
291 bit_map_clear(&iommu->usemap, ioptex, npages);
292}
293
294static void iommu_release_scsi_one(struct device *dev, __u32 vaddr, unsigned long len)
295{
296 unsigned long off;
297 int npages;
298
299 off = vaddr & ~PAGE_MASK;
300 npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
301 iommu_release_one(dev, vaddr & PAGE_MASK, npages);
302}
303
304static void iommu_release_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
305{
306 int n;
307
308 while(sz != 0) {
309 --sz;
310
311 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
312 iommu_release_one(dev, sg->dma_address & PAGE_MASK, n);
313 sg->dma_address = 0x21212121;
314 sg = sg_next(sg);
315 }
316}
317
318#ifdef CONFIG_SBUS
319static int iommu_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va,
320 unsigned long addr, int len)
321{
322 struct iommu_struct *iommu = dev->archdata.iommu;
323 unsigned long page, end;
324 iopte_t *iopte = iommu->page_table;
325 iopte_t *first;
326 int ioptex;
327
328 BUG_ON((va & ~PAGE_MASK) != 0);
329 BUG_ON((addr & ~PAGE_MASK) != 0);
330 BUG_ON((len & ~PAGE_MASK) != 0);
331
332 /* page color = physical address */
333 ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
334 addr >> PAGE_SHIFT);
335 if (ioptex < 0)
336 panic("iommu out");
337
338 iopte += ioptex;
339 first = iopte;
340 end = addr + len;
341 while(addr < end) {
342 page = va;
343 {
344 pgd_t *pgdp;
345 pmd_t *pmdp;
346 pte_t *ptep;
347
348 if (viking_mxcc_present)
349 viking_mxcc_flush_page(page);
350 else if (viking_flush)
351 viking_flush_page(page);
352 else
353 __flush_page_to_ram(page);
354
355 pgdp = pgd_offset(&init_mm, addr);
356 pmdp = pmd_offset(pgdp, addr);
357 ptep = pte_offset_map(pmdp, addr);
358
359 set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
360 }
361 iopte_val(*iopte++) =
362 MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
363 addr += PAGE_SIZE;
364 va += PAGE_SIZE;
365 }
366 /* P3: why do we need this?
367 *
368 * DAVEM: Because there are several aspects, none of which
369 * are handled by a single interface. Some cpus are
370 * completely not I/O DMA coherent, and some have
371 * virtually indexed caches. The driver DMA flushing
372 * methods handle the former case, but here during
373 * IOMMU page table modifications, and usage of non-cacheable
374 * cpu mappings of pages potentially in the cpu caches, we have
375 * to handle the latter case as well.
376 */
377 flush_cache_all();
378 iommu_flush_iotlb(first, len >> PAGE_SHIFT);
379 flush_tlb_all();
380 iommu_invalidate(iommu->regs);
381
382 *pba = iommu->start + (ioptex << PAGE_SHIFT);
383 return 0;
384}
385
386static void iommu_unmap_dma_area(struct device *dev, unsigned long busa, int len)
387{
388 struct iommu_struct *iommu = dev->archdata.iommu;
389 iopte_t *iopte = iommu->page_table;
390 unsigned long end;
391 int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
392
393 BUG_ON((busa & ~PAGE_MASK) != 0);
394 BUG_ON((len & ~PAGE_MASK) != 0);
395
396 iopte += ioptex;
397 end = busa + len;
398 while (busa < end) {
399 iopte_val(*iopte++) = 0;
400 busa += PAGE_SIZE;
401 }
402 flush_tlb_all();
403 iommu_invalidate(iommu->regs);
404 bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
405}
406#endif
407
408static const struct sparc32_dma_ops iommu_dma_gflush_ops = {
409 .get_scsi_one = iommu_get_scsi_one_gflush,
410 .get_scsi_sgl = iommu_get_scsi_sgl_gflush,
411 .release_scsi_one = iommu_release_scsi_one,
412 .release_scsi_sgl = iommu_release_scsi_sgl,
413#ifdef CONFIG_SBUS
414 .map_dma_area = iommu_map_dma_area,
415 .unmap_dma_area = iommu_unmap_dma_area,
416#endif
417};
418
419static const struct sparc32_dma_ops iommu_dma_pflush_ops = {
420 .get_scsi_one = iommu_get_scsi_one_pflush,
421 .get_scsi_sgl = iommu_get_scsi_sgl_pflush,
422 .release_scsi_one = iommu_release_scsi_one,
423 .release_scsi_sgl = iommu_release_scsi_sgl,
424#ifdef CONFIG_SBUS
425 .map_dma_area = iommu_map_dma_area,
426 .unmap_dma_area = iommu_unmap_dma_area,
427#endif
428};
429
430void __init ld_mmu_iommu(void)
431{
432 if (flush_page_for_dma_global) {
433 /* flush_page_for_dma flushes everything, no matter of what page is it */
434 sparc32_dma_ops = &iommu_dma_gflush_ops;
435 } else {
436 sparc32_dma_ops = &iommu_dma_pflush_ops;
437 }
438
439 if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
440 dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
441 ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
442 } else {
443 dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
444 ioperm_noc = IOPTE_WRITE | IOPTE_VALID;
445 }
446}