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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Perf PMU sysfs events attributes for available CPU-measurement counters
4 *
5 */
6
7#include <linux/slab.h>
8#include <linux/perf_event.h>
9#include <asm/cpu_mf.h>
10
11
12/* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
13
14CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
15CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
16CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
17CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
18CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
19CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
20CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
21CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
22CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
23CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
24CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004);
25CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005);
26CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000);
27CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001);
28CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002);
29CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003);
30CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020);
31CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
32CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
33CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
34CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_FUNCTIONS, 0x0040);
35CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_CYCLES, 0x0041);
36CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS, 0x0042);
37CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_CYCLES, 0x0043);
38CPUMF_EVENT_ATTR(cf_svn_12345, SHA_FUNCTIONS, 0x0044);
39CPUMF_EVENT_ATTR(cf_svn_12345, SHA_CYCLES, 0x0045);
40CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS, 0x0046);
41CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_CYCLES, 0x0047);
42CPUMF_EVENT_ATTR(cf_svn_12345, DEA_FUNCTIONS, 0x0048);
43CPUMF_EVENT_ATTR(cf_svn_12345, DEA_CYCLES, 0x0049);
44CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS, 0x004a);
45CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_CYCLES, 0x004b);
46CPUMF_EVENT_ATTR(cf_svn_12345, AES_FUNCTIONS, 0x004c);
47CPUMF_EVENT_ATTR(cf_svn_12345, AES_CYCLES, 0x004d);
48CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS, 0x004e);
49CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_CYCLES, 0x004f);
50CPUMF_EVENT_ATTR(cf_svn_6, ECC_FUNCTION_COUNT, 0x0050);
51CPUMF_EVENT_ATTR(cf_svn_6, ECC_CYCLES_COUNT, 0x0051);
52CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT, 0x0052);
53CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT, 0x0053);
54CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
55CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
56CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
57CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
58CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
59CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
60CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
61CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
62CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
63CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
64CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
65CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
66CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
67CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
68CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
69CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
70CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
71CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
72CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
73CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
74CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
75CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
76CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
77CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
78CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
79CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
80CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
81CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
82CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
83CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
84CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
85CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
86CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
87CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
88CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
89CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
90CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
91CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
92CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
93CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
94CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
95CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
96CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
97CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
98CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
99CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
100CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
101CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
102CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
103CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
104CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
105CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
106CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
107CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
108CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
109CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
110CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
111CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
112CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
113CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
114CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
115CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
116CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
117CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
118CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
119CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
120CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
121CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
122CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
123CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
124CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
125CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
126CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
127CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
128CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
129CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
130CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
131CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080);
132CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081);
133CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082);
134CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083);
135CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084);
136CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085);
137CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086);
138CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087);
139CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088);
140CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089);
141CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a);
142CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b);
143CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c);
144CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d);
145CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f);
146CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
147CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091);
148CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092);
149CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093);
150CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094);
151CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095);
152CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096);
153CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097);
154CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098);
155CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099);
156CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a);
157CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b);
158CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c);
159CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d);
160CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e);
161CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f);
162CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0);
163CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1);
164CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
165CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3);
166CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4);
167CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5);
168CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6);
169CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7);
170CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8);
171CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9);
172CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa);
173CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab);
174CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac);
175CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad);
176CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae);
177CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af);
178CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0);
179CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1);
180CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2);
181CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3);
182CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da);
183CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
184CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
185CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
186CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
187CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080);
188CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081);
189CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082);
190CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083);
191CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084);
192CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085);
193CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086);
194CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087);
195CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088);
196CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089);
197CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a);
198CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b);
199CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c);
200CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d);
201CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f);
202CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
203CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
204CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
205CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
206CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
207CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
208CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
209CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
210CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
211CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
212CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
213CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
214CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
215CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
216CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
217CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
218CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
219CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
220CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
221CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
222CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
223CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
224CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
225CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
226CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
227CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
228CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
229CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
230CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
231CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
232CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1);
233CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2);
234CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8);
235CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3);
236CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
237CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
238CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
239CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
240
241static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
242 CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
243 CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
244 CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES),
245 CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES),
246 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES),
247 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS),
248 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES),
249 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES),
250 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES),
251 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES),
252 CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES),
253 CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES),
254 NULL,
255};
256
257static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = {
258 CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES),
259 CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS),
260 CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES),
261 CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES),
262 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES),
263 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS),
264 CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES),
265 CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES),
266 NULL,
267};
268
269static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
270 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
271 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
272 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
273 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
274 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
275 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
276 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
277 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
278 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
279 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
280 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
281 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
282 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
283 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
284 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
285 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
286 NULL,
287};
288
289static struct attribute *cpumcf_svn_6_pmu_event_attr[] __initdata = {
290 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
291 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
292 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
293 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
294 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
295 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
296 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
297 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
298 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
299 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
300 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
301 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
302 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
303 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
304 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
305 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
306 CPUMF_EVENT_PTR(cf_svn_6, ECC_FUNCTION_COUNT),
307 CPUMF_EVENT_PTR(cf_svn_6, ECC_CYCLES_COUNT),
308 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT),
309 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT),
310 NULL,
311};
312
313static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
314 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
315 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
316 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
317 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
318 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
319 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
320 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
321 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
322 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
323 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
324 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
325 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
326 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
327 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
328 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
329 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
330 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
331 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
332 NULL,
333};
334
335static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
336 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
337 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
338 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
339 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
340 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
341 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
342 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
343 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
344 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
345 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
346 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
347 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
348 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
349 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
350 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
351 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
352 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
353 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
354 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
355 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
356 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
357 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
358 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
359 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
360 NULL,
361};
362
363static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
364 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
365 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
366 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
367 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
368 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
369 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
370 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
371 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
372 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
373 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
374 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
375 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
376 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
377 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
378 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
379 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
380 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
381 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
382 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
383 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
384 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
385 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
386 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
387 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
388 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
389 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
390 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
391 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
392 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
393 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
394 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
395 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
396 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
397 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
398 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
399 NULL,
400};
401
402static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
403 CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES),
404 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES),
405 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES),
406 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES),
407 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES),
408 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES),
409 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES),
410 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES),
411 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES),
412 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES),
413 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES),
414 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES),
415 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND),
416 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND),
417 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES),
418 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES),
419 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
420 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES),
421 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV),
422 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES),
423 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES),
424 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV),
425 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES),
426 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
427 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
428 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
429 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
430 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
431 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
432 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES),
433 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES),
434 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES),
435 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES),
436 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES),
437 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
438 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES),
439 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV),
440 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES),
441 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES),
442 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV),
443 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES),
444 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
445 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
446 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
447 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
448 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
449 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
450 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES),
451 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES),
452 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES),
453 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES),
454 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT),
455 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL),
456 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL),
457 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
458 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
459 NULL,
460};
461
462static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
463 CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES),
464 CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES),
465 CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES),
466 CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES),
467 CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES),
468 CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES),
469 CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES),
470 CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES),
471 CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES),
472 CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES),
473 CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES),
474 CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY),
475 CPUMF_EVENT_PTR(cf_z14, TX_C_TEND),
476 CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND),
477 CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES),
478 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES),
479 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
480 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
481 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES),
482 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
483 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
484 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
485 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
486 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
487 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES),
488 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
489 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
490 CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES),
491 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES),
492 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
493 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES),
494 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
495 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
496 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES),
497 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
498 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
499 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
500 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
501 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
502 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES),
503 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
504 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
505 CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES),
506 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES),
507 CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS),
508 CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS),
509 CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS),
510 CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS),
511 CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT),
512 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL),
513 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL),
514 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
515 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
516 NULL,
517};
518
519/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
520
521static struct attribute_group cpumcf_pmu_events_group = {
522 .name = "events",
523};
524
525PMU_FORMAT_ATTR(event, "config:0-63");
526
527static struct attribute *cpumcf_pmu_format_attr[] = {
528 &format_attr_event.attr,
529 NULL,
530};
531
532static struct attribute_group cpumcf_pmu_format_group = {
533 .name = "format",
534 .attrs = cpumcf_pmu_format_attr,
535};
536
537static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
538 &cpumcf_pmu_events_group,
539 &cpumcf_pmu_format_group,
540 NULL,
541};
542
543
544static __init struct attribute **merge_attr(struct attribute **a,
545 struct attribute **b,
546 struct attribute **c)
547{
548 struct attribute **new;
549 int j, i;
550
551 for (j = 0; a[j]; j++)
552 ;
553 for (i = 0; b[i]; i++)
554 j++;
555 for (i = 0; c[i]; i++)
556 j++;
557 j++;
558
559 new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL);
560 if (!new)
561 return NULL;
562 j = 0;
563 for (i = 0; a[i]; i++)
564 new[j++] = a[i];
565 for (i = 0; b[i]; i++)
566 new[j++] = b[i];
567 for (i = 0; c[i]; i++)
568 new[j++] = c[i];
569 new[j] = NULL;
570
571 return new;
572}
573
574__init const struct attribute_group **cpumf_cf_event_group(void)
575{
576 struct attribute **combined, **model, **cfvn, **csvn;
577 struct attribute *none[] = { NULL };
578 struct cpumf_ctr_info ci;
579 struct cpuid cpu_id;
580
581 /* Determine generic counters set(s) */
582 qctri(&ci);
583 switch (ci.cfvn) {
584 case 1:
585 cfvn = cpumcf_fvn1_pmu_event_attr;
586 break;
587 case 3:
588 cfvn = cpumcf_fvn3_pmu_event_attr;
589 break;
590 default:
591 cfvn = none;
592 }
593
594 /* Determine version specific crypto set */
595 switch (ci.csvn) {
596 case 1 ... 5:
597 csvn = cpumcf_svn_12345_pmu_event_attr;
598 break;
599 case 6:
600 csvn = cpumcf_svn_6_pmu_event_attr;
601 break;
602 default:
603 csvn = none;
604 }
605
606 /* Determine model-specific counter set(s) */
607 get_cpu_id(&cpu_id);
608 switch (cpu_id.machine) {
609 case 0x2097:
610 case 0x2098:
611 model = cpumcf_z10_pmu_event_attr;
612 break;
613 case 0x2817:
614 case 0x2818:
615 model = cpumcf_z196_pmu_event_attr;
616 break;
617 case 0x2827:
618 case 0x2828:
619 model = cpumcf_zec12_pmu_event_attr;
620 break;
621 case 0x2964:
622 case 0x2965:
623 model = cpumcf_z13_pmu_event_attr;
624 break;
625 case 0x3906:
626 case 0x3907:
627 case 0x8561:
628 case 0x8562:
629 model = cpumcf_z14_pmu_event_attr;
630 break;
631 default:
632 model = none;
633 break;
634 }
635
636 combined = merge_attr(cfvn, csvn, model);
637 if (combined)
638 cpumcf_pmu_events_group.attrs = combined;
639 return cpumcf_pmu_attr_groups;
640}
1/*
2 * Perf PMU sysfs events attributes for available CPU-measurement counters
3 *
4 */
5
6#include <linux/slab.h>
7#include <linux/perf_event.h>
8
9
10/* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
11
12CPUMF_EVENT_ATTR(cf, CPU_CYCLES, 0x0000);
13CPUMF_EVENT_ATTR(cf, INSTRUCTIONS, 0x0001);
14CPUMF_EVENT_ATTR(cf, L1I_DIR_WRITES, 0x0002);
15CPUMF_EVENT_ATTR(cf, L1I_PENALTY_CYCLES, 0x0003);
16CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_CPU_CYCLES, 0x0020);
17CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
18CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
19CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
20CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
21CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
22CPUMF_EVENT_ATTR(cf, L1D_DIR_WRITES, 0x0004);
23CPUMF_EVENT_ATTR(cf, L1D_PENALTY_CYCLES, 0x0005);
24CPUMF_EVENT_ATTR(cf, PRNG_FUNCTIONS, 0x0040);
25CPUMF_EVENT_ATTR(cf, PRNG_CYCLES, 0x0041);
26CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_FUNCTIONS, 0x0042);
27CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_CYCLES, 0x0043);
28CPUMF_EVENT_ATTR(cf, SHA_FUNCTIONS, 0x0044);
29CPUMF_EVENT_ATTR(cf, SHA_CYCLES, 0x0045);
30CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_FUNCTIONS, 0x0046);
31CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_CYCLES, 0x0047);
32CPUMF_EVENT_ATTR(cf, DEA_FUNCTIONS, 0x0048);
33CPUMF_EVENT_ATTR(cf, DEA_CYCLES, 0x0049);
34CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_FUNCTIONS, 0x004a);
35CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_CYCLES, 0x004b);
36CPUMF_EVENT_ATTR(cf, AES_FUNCTIONS, 0x004c);
37CPUMF_EVENT_ATTR(cf, AES_CYCLES, 0x004d);
38CPUMF_EVENT_ATTR(cf, AES_BLOCKED_FUNCTIONS, 0x004e);
39CPUMF_EVENT_ATTR(cf, AES_BLOCKED_CYCLES, 0x004f);
40CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
41CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
42CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
43CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
44CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
45CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
46CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
47CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
48CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
49CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
50CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
51CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
52CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
53CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
54CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
55CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
56CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
57CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
58CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
59CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
60CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
61CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
62CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
63CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
64CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
65CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
66CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
67CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
68CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
69CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
70CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
71CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
72CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
73CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
74CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
75CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
76CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
77CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
78CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
79CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
80CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
81CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
82CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
83CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
84CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
85CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
86CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
87CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
88CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
89CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
90CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
91CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
92CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
93CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
94CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
95CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
96CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
97CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
98CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
99CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
100CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
101CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
102CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
103CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
104CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
105CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
106CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
107CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
108CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
109CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
110CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
111CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
112CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
113CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
114CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
115CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
116CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
117
118static struct attribute *cpumcf_pmu_event_attr[] = {
119 CPUMF_EVENT_PTR(cf, CPU_CYCLES),
120 CPUMF_EVENT_PTR(cf, INSTRUCTIONS),
121 CPUMF_EVENT_PTR(cf, L1I_DIR_WRITES),
122 CPUMF_EVENT_PTR(cf, L1I_PENALTY_CYCLES),
123 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_CPU_CYCLES),
124 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_INSTRUCTIONS),
125 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_DIR_WRITES),
126 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES),
127 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_DIR_WRITES),
128 CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES),
129 CPUMF_EVENT_PTR(cf, L1D_DIR_WRITES),
130 CPUMF_EVENT_PTR(cf, L1D_PENALTY_CYCLES),
131 CPUMF_EVENT_PTR(cf, PRNG_FUNCTIONS),
132 CPUMF_EVENT_PTR(cf, PRNG_CYCLES),
133 CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_FUNCTIONS),
134 CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_CYCLES),
135 CPUMF_EVENT_PTR(cf, SHA_FUNCTIONS),
136 CPUMF_EVENT_PTR(cf, SHA_CYCLES),
137 CPUMF_EVENT_PTR(cf, SHA_BLOCKED_FUNCTIONS),
138 CPUMF_EVENT_PTR(cf, SHA_BLOCKED_CYCLES),
139 CPUMF_EVENT_PTR(cf, DEA_FUNCTIONS),
140 CPUMF_EVENT_PTR(cf, DEA_CYCLES),
141 CPUMF_EVENT_PTR(cf, DEA_BLOCKED_FUNCTIONS),
142 CPUMF_EVENT_PTR(cf, DEA_BLOCKED_CYCLES),
143 CPUMF_EVENT_PTR(cf, AES_FUNCTIONS),
144 CPUMF_EVENT_PTR(cf, AES_CYCLES),
145 CPUMF_EVENT_PTR(cf, AES_BLOCKED_FUNCTIONS),
146 CPUMF_EVENT_PTR(cf, AES_BLOCKED_CYCLES),
147 NULL,
148};
149
150static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
151 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
152 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
153 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
154 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
155 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
156 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
157 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
158 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
159 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
160 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
161 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
162 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
163 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
164 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
165 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
166 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
167 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
168 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
169 NULL,
170};
171
172static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
173 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
174 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
175 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
176 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
177 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
178 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
179 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
180 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
181 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
182 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
183 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
184 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
185 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
186 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
187 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
188 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
189 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
190 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
191 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
192 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
193 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
194 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
195 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
196 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
197 NULL,
198};
199
200static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
201 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
202 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
203 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
204 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
205 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
206 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
207 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
208 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
209 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
210 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
211 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
212 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
213 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
214 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
215 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
216 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
217 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
218 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
219 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
220 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
221 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
222 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
223 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
224 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
225 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
226 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
227 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
228 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
229 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
230 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
231 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
232 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
233 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
234 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
235 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
236 NULL,
237};
238
239/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
240
241static struct attribute_group cpumsf_pmu_events_group = {
242 .name = "events",
243 .attrs = cpumcf_pmu_event_attr,
244};
245
246PMU_FORMAT_ATTR(event, "config:0-63");
247
248static struct attribute *cpumsf_pmu_format_attr[] = {
249 &format_attr_event.attr,
250 NULL,
251};
252
253static struct attribute_group cpumsf_pmu_format_group = {
254 .name = "format",
255 .attrs = cpumsf_pmu_format_attr,
256};
257
258static const struct attribute_group *cpumsf_pmu_attr_groups[] = {
259 &cpumsf_pmu_events_group,
260 &cpumsf_pmu_format_group,
261 NULL,
262};
263
264
265static __init struct attribute **merge_attr(struct attribute **a,
266 struct attribute **b)
267{
268 struct attribute **new;
269 int j, i;
270
271 for (j = 0; a[j]; j++)
272 ;
273 for (i = 0; b[i]; i++)
274 j++;
275 j++;
276
277 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
278 if (!new)
279 return NULL;
280 j = 0;
281 for (i = 0; a[i]; i++)
282 new[j++] = a[i];
283 for (i = 0; b[i]; i++)
284 new[j++] = b[i];
285 new[j] = NULL;
286
287 return new;
288}
289
290__init const struct attribute_group **cpumf_cf_event_group(void)
291{
292 struct attribute **combined, **model;
293 struct cpuid cpu_id;
294
295 get_cpu_id(&cpu_id);
296 switch (cpu_id.machine) {
297 case 0x2097:
298 case 0x2098:
299 model = cpumcf_z10_pmu_event_attr;
300 break;
301 case 0x2817:
302 case 0x2818:
303 model = cpumcf_z196_pmu_event_attr;
304 break;
305 case 0x2827:
306 case 0x2828:
307 model = cpumcf_zec12_pmu_event_attr;
308 break;
309 default:
310 model = NULL;
311 break;
312 };
313
314 if (!model)
315 goto out;
316
317 combined = merge_attr(cpumcf_pmu_event_attr, model);
318 if (combined)
319 cpumsf_pmu_events_group.attrs = combined;
320out:
321 return cpumsf_pmu_attr_groups;
322}