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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIXX_DEFS_H__
29#define __CVMX_MIXX_DEFS_H__
30
31#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
32#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
33#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
34#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
35#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
36#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
37#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
38#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
39#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
40#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
41#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
42#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
43#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
44#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
45#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
46
47union cvmx_mixx_bist {
48 uint64_t u64;
49 struct cvmx_mixx_bist_s {
50#ifdef __BIG_ENDIAN_BITFIELD
51 uint64_t reserved_6_63:58;
52 uint64_t opfdat:1;
53 uint64_t mrgdat:1;
54 uint64_t mrqdat:1;
55 uint64_t ipfdat:1;
56 uint64_t irfdat:1;
57 uint64_t orfdat:1;
58#else
59 uint64_t orfdat:1;
60 uint64_t irfdat:1;
61 uint64_t ipfdat:1;
62 uint64_t mrqdat:1;
63 uint64_t mrgdat:1;
64 uint64_t opfdat:1;
65 uint64_t reserved_6_63:58;
66#endif
67 } s;
68 struct cvmx_mixx_bist_cn52xx {
69#ifdef __BIG_ENDIAN_BITFIELD
70 uint64_t reserved_4_63:60;
71 uint64_t mrqdat:1;
72 uint64_t ipfdat:1;
73 uint64_t irfdat:1;
74 uint64_t orfdat:1;
75#else
76 uint64_t orfdat:1;
77 uint64_t irfdat:1;
78 uint64_t ipfdat:1;
79 uint64_t mrqdat:1;
80 uint64_t reserved_4_63:60;
81#endif
82 } cn52xx;
83};
84
85union cvmx_mixx_ctl {
86 uint64_t u64;
87 struct cvmx_mixx_ctl_s {
88#ifdef __BIG_ENDIAN_BITFIELD
89 uint64_t reserved_12_63:52;
90 uint64_t ts_thresh:4;
91 uint64_t crc_strip:1;
92 uint64_t busy:1;
93 uint64_t en:1;
94 uint64_t reset:1;
95 uint64_t lendian:1;
96 uint64_t nbtarb:1;
97 uint64_t mrq_hwm:2;
98#else
99 uint64_t mrq_hwm:2;
100 uint64_t nbtarb:1;
101 uint64_t lendian:1;
102 uint64_t reset:1;
103 uint64_t en:1;
104 uint64_t busy:1;
105 uint64_t crc_strip:1;
106 uint64_t ts_thresh:4;
107 uint64_t reserved_12_63:52;
108#endif
109 } s;
110 struct cvmx_mixx_ctl_cn52xx {
111#ifdef __BIG_ENDIAN_BITFIELD
112 uint64_t reserved_8_63:56;
113 uint64_t crc_strip:1;
114 uint64_t busy:1;
115 uint64_t en:1;
116 uint64_t reset:1;
117 uint64_t lendian:1;
118 uint64_t nbtarb:1;
119 uint64_t mrq_hwm:2;
120#else
121 uint64_t mrq_hwm:2;
122 uint64_t nbtarb:1;
123 uint64_t lendian:1;
124 uint64_t reset:1;
125 uint64_t en:1;
126 uint64_t busy:1;
127 uint64_t crc_strip:1;
128 uint64_t reserved_8_63:56;
129#endif
130 } cn52xx;
131};
132
133union cvmx_mixx_intena {
134 uint64_t u64;
135 struct cvmx_mixx_intena_s {
136#ifdef __BIG_ENDIAN_BITFIELD
137 uint64_t reserved_8_63:56;
138 uint64_t tsena:1;
139 uint64_t orunena:1;
140 uint64_t irunena:1;
141 uint64_t data_drpena:1;
142 uint64_t ithena:1;
143 uint64_t othena:1;
144 uint64_t ivfena:1;
145 uint64_t ovfena:1;
146#else
147 uint64_t ovfena:1;
148 uint64_t ivfena:1;
149 uint64_t othena:1;
150 uint64_t ithena:1;
151 uint64_t data_drpena:1;
152 uint64_t irunena:1;
153 uint64_t orunena:1;
154 uint64_t tsena:1;
155 uint64_t reserved_8_63:56;
156#endif
157 } s;
158 struct cvmx_mixx_intena_cn52xx {
159#ifdef __BIG_ENDIAN_BITFIELD
160 uint64_t reserved_7_63:57;
161 uint64_t orunena:1;
162 uint64_t irunena:1;
163 uint64_t data_drpena:1;
164 uint64_t ithena:1;
165 uint64_t othena:1;
166 uint64_t ivfena:1;
167 uint64_t ovfena:1;
168#else
169 uint64_t ovfena:1;
170 uint64_t ivfena:1;
171 uint64_t othena:1;
172 uint64_t ithena:1;
173 uint64_t data_drpena:1;
174 uint64_t irunena:1;
175 uint64_t orunena:1;
176 uint64_t reserved_7_63:57;
177#endif
178 } cn52xx;
179};
180
181union cvmx_mixx_ircnt {
182 uint64_t u64;
183 struct cvmx_mixx_ircnt_s {
184#ifdef __BIG_ENDIAN_BITFIELD
185 uint64_t reserved_20_63:44;
186 uint64_t ircnt:20;
187#else
188 uint64_t ircnt:20;
189 uint64_t reserved_20_63:44;
190#endif
191 } s;
192};
193
194union cvmx_mixx_irhwm {
195 uint64_t u64;
196 struct cvmx_mixx_irhwm_s {
197#ifdef __BIG_ENDIAN_BITFIELD
198 uint64_t reserved_40_63:24;
199 uint64_t ibplwm:20;
200 uint64_t irhwm:20;
201#else
202 uint64_t irhwm:20;
203 uint64_t ibplwm:20;
204 uint64_t reserved_40_63:24;
205#endif
206 } s;
207};
208
209union cvmx_mixx_iring1 {
210 uint64_t u64;
211 struct cvmx_mixx_iring1_s {
212#ifdef __BIG_ENDIAN_BITFIELD
213 uint64_t reserved_60_63:4;
214 uint64_t isize:20;
215 uint64_t ibase:37;
216 uint64_t reserved_0_2:3;
217#else
218 uint64_t reserved_0_2:3;
219 uint64_t ibase:37;
220 uint64_t isize:20;
221 uint64_t reserved_60_63:4;
222#endif
223 } s;
224 struct cvmx_mixx_iring1_cn52xx {
225#ifdef __BIG_ENDIAN_BITFIELD
226 uint64_t reserved_60_63:4;
227 uint64_t isize:20;
228 uint64_t reserved_36_39:4;
229 uint64_t ibase:33;
230 uint64_t reserved_0_2:3;
231#else
232 uint64_t reserved_0_2:3;
233 uint64_t ibase:33;
234 uint64_t reserved_36_39:4;
235 uint64_t isize:20;
236 uint64_t reserved_60_63:4;
237#endif
238 } cn52xx;
239};
240
241union cvmx_mixx_iring2 {
242 uint64_t u64;
243 struct cvmx_mixx_iring2_s {
244#ifdef __BIG_ENDIAN_BITFIELD
245 uint64_t reserved_52_63:12;
246 uint64_t itlptr:20;
247 uint64_t reserved_20_31:12;
248 uint64_t idbell:20;
249#else
250 uint64_t idbell:20;
251 uint64_t reserved_20_31:12;
252 uint64_t itlptr:20;
253 uint64_t reserved_52_63:12;
254#endif
255 } s;
256};
257
258union cvmx_mixx_isr {
259 uint64_t u64;
260 struct cvmx_mixx_isr_s {
261#ifdef __BIG_ENDIAN_BITFIELD
262 uint64_t reserved_8_63:56;
263 uint64_t ts:1;
264 uint64_t orun:1;
265 uint64_t irun:1;
266 uint64_t data_drp:1;
267 uint64_t irthresh:1;
268 uint64_t orthresh:1;
269 uint64_t idblovf:1;
270 uint64_t odblovf:1;
271#else
272 uint64_t odblovf:1;
273 uint64_t idblovf:1;
274 uint64_t orthresh:1;
275 uint64_t irthresh:1;
276 uint64_t data_drp:1;
277 uint64_t irun:1;
278 uint64_t orun:1;
279 uint64_t ts:1;
280 uint64_t reserved_8_63:56;
281#endif
282 } s;
283 struct cvmx_mixx_isr_cn52xx {
284#ifdef __BIG_ENDIAN_BITFIELD
285 uint64_t reserved_7_63:57;
286 uint64_t orun:1;
287 uint64_t irun:1;
288 uint64_t data_drp:1;
289 uint64_t irthresh:1;
290 uint64_t orthresh:1;
291 uint64_t idblovf:1;
292 uint64_t odblovf:1;
293#else
294 uint64_t odblovf:1;
295 uint64_t idblovf:1;
296 uint64_t orthresh:1;
297 uint64_t irthresh:1;
298 uint64_t data_drp:1;
299 uint64_t irun:1;
300 uint64_t orun:1;
301 uint64_t reserved_7_63:57;
302#endif
303 } cn52xx;
304};
305
306union cvmx_mixx_orcnt {
307 uint64_t u64;
308 struct cvmx_mixx_orcnt_s {
309#ifdef __BIG_ENDIAN_BITFIELD
310 uint64_t reserved_20_63:44;
311 uint64_t orcnt:20;
312#else
313 uint64_t orcnt:20;
314 uint64_t reserved_20_63:44;
315#endif
316 } s;
317};
318
319union cvmx_mixx_orhwm {
320 uint64_t u64;
321 struct cvmx_mixx_orhwm_s {
322#ifdef __BIG_ENDIAN_BITFIELD
323 uint64_t reserved_20_63:44;
324 uint64_t orhwm:20;
325#else
326 uint64_t orhwm:20;
327 uint64_t reserved_20_63:44;
328#endif
329 } s;
330};
331
332union cvmx_mixx_oring1 {
333 uint64_t u64;
334 struct cvmx_mixx_oring1_s {
335#ifdef __BIG_ENDIAN_BITFIELD
336 uint64_t reserved_60_63:4;
337 uint64_t osize:20;
338 uint64_t obase:37;
339 uint64_t reserved_0_2:3;
340#else
341 uint64_t reserved_0_2:3;
342 uint64_t obase:37;
343 uint64_t osize:20;
344 uint64_t reserved_60_63:4;
345#endif
346 } s;
347 struct cvmx_mixx_oring1_cn52xx {
348#ifdef __BIG_ENDIAN_BITFIELD
349 uint64_t reserved_60_63:4;
350 uint64_t osize:20;
351 uint64_t reserved_36_39:4;
352 uint64_t obase:33;
353 uint64_t reserved_0_2:3;
354#else
355 uint64_t reserved_0_2:3;
356 uint64_t obase:33;
357 uint64_t reserved_36_39:4;
358 uint64_t osize:20;
359 uint64_t reserved_60_63:4;
360#endif
361 } cn52xx;
362};
363
364union cvmx_mixx_oring2 {
365 uint64_t u64;
366 struct cvmx_mixx_oring2_s {
367#ifdef __BIG_ENDIAN_BITFIELD
368 uint64_t reserved_52_63:12;
369 uint64_t otlptr:20;
370 uint64_t reserved_20_31:12;
371 uint64_t odbell:20;
372#else
373 uint64_t odbell:20;
374 uint64_t reserved_20_31:12;
375 uint64_t otlptr:20;
376 uint64_t reserved_52_63:12;
377#endif
378 } s;
379};
380
381union cvmx_mixx_remcnt {
382 uint64_t u64;
383 struct cvmx_mixx_remcnt_s {
384#ifdef __BIG_ENDIAN_BITFIELD
385 uint64_t reserved_52_63:12;
386 uint64_t iremcnt:20;
387 uint64_t reserved_20_31:12;
388 uint64_t oremcnt:20;
389#else
390 uint64_t oremcnt:20;
391 uint64_t reserved_20_31:12;
392 uint64_t iremcnt:20;
393 uint64_t reserved_52_63:12;
394#endif
395 } s;
396};
397
398union cvmx_mixx_tsctl {
399 uint64_t u64;
400 struct cvmx_mixx_tsctl_s {
401#ifdef __BIG_ENDIAN_BITFIELD
402 uint64_t reserved_21_63:43;
403 uint64_t tsavl:5;
404 uint64_t reserved_13_15:3;
405 uint64_t tstot:5;
406 uint64_t reserved_5_7:3;
407 uint64_t tscnt:5;
408#else
409 uint64_t tscnt:5;
410 uint64_t reserved_5_7:3;
411 uint64_t tstot:5;
412 uint64_t reserved_13_15:3;
413 uint64_t tsavl:5;
414 uint64_t reserved_21_63:43;
415#endif
416 } s;
417};
418
419union cvmx_mixx_tstamp {
420 uint64_t u64;
421 struct cvmx_mixx_tstamp_s {
422#ifdef __BIG_ENDIAN_BITFIELD
423 uint64_t tstamp:64;
424#else
425 uint64_t tstamp:64;
426#endif
427 } s;
428};
429
430#endif
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIXX_DEFS_H__
29#define __CVMX_MIXX_DEFS_H__
30
31#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
32#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
33#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
34#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
35#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
36#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
37#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
38#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
39#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
40#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
41#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
42#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
43#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
44#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
45#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
46
47union cvmx_mixx_bist {
48 uint64_t u64;
49 struct cvmx_mixx_bist_s {
50#ifdef __BIG_ENDIAN_BITFIELD
51 uint64_t reserved_6_63:58;
52 uint64_t opfdat:1;
53 uint64_t mrgdat:1;
54 uint64_t mrqdat:1;
55 uint64_t ipfdat:1;
56 uint64_t irfdat:1;
57 uint64_t orfdat:1;
58#else
59 uint64_t orfdat:1;
60 uint64_t irfdat:1;
61 uint64_t ipfdat:1;
62 uint64_t mrqdat:1;
63 uint64_t mrgdat:1;
64 uint64_t opfdat:1;
65 uint64_t reserved_6_63:58;
66#endif
67 } s;
68 struct cvmx_mixx_bist_cn52xx {
69#ifdef __BIG_ENDIAN_BITFIELD
70 uint64_t reserved_4_63:60;
71 uint64_t mrqdat:1;
72 uint64_t ipfdat:1;
73 uint64_t irfdat:1;
74 uint64_t orfdat:1;
75#else
76 uint64_t orfdat:1;
77 uint64_t irfdat:1;
78 uint64_t ipfdat:1;
79 uint64_t mrqdat:1;
80 uint64_t reserved_4_63:60;
81#endif
82 } cn52xx;
83 struct cvmx_mixx_bist_cn52xx cn52xxp1;
84 struct cvmx_mixx_bist_cn52xx cn56xx;
85 struct cvmx_mixx_bist_cn52xx cn56xxp1;
86 struct cvmx_mixx_bist_s cn61xx;
87 struct cvmx_mixx_bist_s cn63xx;
88 struct cvmx_mixx_bist_s cn63xxp1;
89 struct cvmx_mixx_bist_s cn66xx;
90 struct cvmx_mixx_bist_s cn68xx;
91 struct cvmx_mixx_bist_s cn68xxp1;
92};
93
94union cvmx_mixx_ctl {
95 uint64_t u64;
96 struct cvmx_mixx_ctl_s {
97#ifdef __BIG_ENDIAN_BITFIELD
98 uint64_t reserved_12_63:52;
99 uint64_t ts_thresh:4;
100 uint64_t crc_strip:1;
101 uint64_t busy:1;
102 uint64_t en:1;
103 uint64_t reset:1;
104 uint64_t lendian:1;
105 uint64_t nbtarb:1;
106 uint64_t mrq_hwm:2;
107#else
108 uint64_t mrq_hwm:2;
109 uint64_t nbtarb:1;
110 uint64_t lendian:1;
111 uint64_t reset:1;
112 uint64_t en:1;
113 uint64_t busy:1;
114 uint64_t crc_strip:1;
115 uint64_t ts_thresh:4;
116 uint64_t reserved_12_63:52;
117#endif
118 } s;
119 struct cvmx_mixx_ctl_cn52xx {
120#ifdef __BIG_ENDIAN_BITFIELD
121 uint64_t reserved_8_63:56;
122 uint64_t crc_strip:1;
123 uint64_t busy:1;
124 uint64_t en:1;
125 uint64_t reset:1;
126 uint64_t lendian:1;
127 uint64_t nbtarb:1;
128 uint64_t mrq_hwm:2;
129#else
130 uint64_t mrq_hwm:2;
131 uint64_t nbtarb:1;
132 uint64_t lendian:1;
133 uint64_t reset:1;
134 uint64_t en:1;
135 uint64_t busy:1;
136 uint64_t crc_strip:1;
137 uint64_t reserved_8_63:56;
138#endif
139 } cn52xx;
140 struct cvmx_mixx_ctl_cn52xx cn52xxp1;
141 struct cvmx_mixx_ctl_cn52xx cn56xx;
142 struct cvmx_mixx_ctl_cn52xx cn56xxp1;
143 struct cvmx_mixx_ctl_s cn61xx;
144 struct cvmx_mixx_ctl_s cn63xx;
145 struct cvmx_mixx_ctl_s cn63xxp1;
146 struct cvmx_mixx_ctl_s cn66xx;
147 struct cvmx_mixx_ctl_s cn68xx;
148 struct cvmx_mixx_ctl_s cn68xxp1;
149};
150
151union cvmx_mixx_intena {
152 uint64_t u64;
153 struct cvmx_mixx_intena_s {
154#ifdef __BIG_ENDIAN_BITFIELD
155 uint64_t reserved_8_63:56;
156 uint64_t tsena:1;
157 uint64_t orunena:1;
158 uint64_t irunena:1;
159 uint64_t data_drpena:1;
160 uint64_t ithena:1;
161 uint64_t othena:1;
162 uint64_t ivfena:1;
163 uint64_t ovfena:1;
164#else
165 uint64_t ovfena:1;
166 uint64_t ivfena:1;
167 uint64_t othena:1;
168 uint64_t ithena:1;
169 uint64_t data_drpena:1;
170 uint64_t irunena:1;
171 uint64_t orunena:1;
172 uint64_t tsena:1;
173 uint64_t reserved_8_63:56;
174#endif
175 } s;
176 struct cvmx_mixx_intena_cn52xx {
177#ifdef __BIG_ENDIAN_BITFIELD
178 uint64_t reserved_7_63:57;
179 uint64_t orunena:1;
180 uint64_t irunena:1;
181 uint64_t data_drpena:1;
182 uint64_t ithena:1;
183 uint64_t othena:1;
184 uint64_t ivfena:1;
185 uint64_t ovfena:1;
186#else
187 uint64_t ovfena:1;
188 uint64_t ivfena:1;
189 uint64_t othena:1;
190 uint64_t ithena:1;
191 uint64_t data_drpena:1;
192 uint64_t irunena:1;
193 uint64_t orunena:1;
194 uint64_t reserved_7_63:57;
195#endif
196 } cn52xx;
197 struct cvmx_mixx_intena_cn52xx cn52xxp1;
198 struct cvmx_mixx_intena_cn52xx cn56xx;
199 struct cvmx_mixx_intena_cn52xx cn56xxp1;
200 struct cvmx_mixx_intena_s cn61xx;
201 struct cvmx_mixx_intena_s cn63xx;
202 struct cvmx_mixx_intena_s cn63xxp1;
203 struct cvmx_mixx_intena_s cn66xx;
204 struct cvmx_mixx_intena_s cn68xx;
205 struct cvmx_mixx_intena_s cn68xxp1;
206};
207
208union cvmx_mixx_ircnt {
209 uint64_t u64;
210 struct cvmx_mixx_ircnt_s {
211#ifdef __BIG_ENDIAN_BITFIELD
212 uint64_t reserved_20_63:44;
213 uint64_t ircnt:20;
214#else
215 uint64_t ircnt:20;
216 uint64_t reserved_20_63:44;
217#endif
218 } s;
219 struct cvmx_mixx_ircnt_s cn52xx;
220 struct cvmx_mixx_ircnt_s cn52xxp1;
221 struct cvmx_mixx_ircnt_s cn56xx;
222 struct cvmx_mixx_ircnt_s cn56xxp1;
223 struct cvmx_mixx_ircnt_s cn61xx;
224 struct cvmx_mixx_ircnt_s cn63xx;
225 struct cvmx_mixx_ircnt_s cn63xxp1;
226 struct cvmx_mixx_ircnt_s cn66xx;
227 struct cvmx_mixx_ircnt_s cn68xx;
228 struct cvmx_mixx_ircnt_s cn68xxp1;
229};
230
231union cvmx_mixx_irhwm {
232 uint64_t u64;
233 struct cvmx_mixx_irhwm_s {
234#ifdef __BIG_ENDIAN_BITFIELD
235 uint64_t reserved_40_63:24;
236 uint64_t ibplwm:20;
237 uint64_t irhwm:20;
238#else
239 uint64_t irhwm:20;
240 uint64_t ibplwm:20;
241 uint64_t reserved_40_63:24;
242#endif
243 } s;
244 struct cvmx_mixx_irhwm_s cn52xx;
245 struct cvmx_mixx_irhwm_s cn52xxp1;
246 struct cvmx_mixx_irhwm_s cn56xx;
247 struct cvmx_mixx_irhwm_s cn56xxp1;
248 struct cvmx_mixx_irhwm_s cn61xx;
249 struct cvmx_mixx_irhwm_s cn63xx;
250 struct cvmx_mixx_irhwm_s cn63xxp1;
251 struct cvmx_mixx_irhwm_s cn66xx;
252 struct cvmx_mixx_irhwm_s cn68xx;
253 struct cvmx_mixx_irhwm_s cn68xxp1;
254};
255
256union cvmx_mixx_iring1 {
257 uint64_t u64;
258 struct cvmx_mixx_iring1_s {
259#ifdef __BIG_ENDIAN_BITFIELD
260 uint64_t reserved_60_63:4;
261 uint64_t isize:20;
262 uint64_t ibase:37;
263 uint64_t reserved_0_2:3;
264#else
265 uint64_t reserved_0_2:3;
266 uint64_t ibase:37;
267 uint64_t isize:20;
268 uint64_t reserved_60_63:4;
269#endif
270 } s;
271 struct cvmx_mixx_iring1_cn52xx {
272#ifdef __BIG_ENDIAN_BITFIELD
273 uint64_t reserved_60_63:4;
274 uint64_t isize:20;
275 uint64_t reserved_36_39:4;
276 uint64_t ibase:33;
277 uint64_t reserved_0_2:3;
278#else
279 uint64_t reserved_0_2:3;
280 uint64_t ibase:33;
281 uint64_t reserved_36_39:4;
282 uint64_t isize:20;
283 uint64_t reserved_60_63:4;
284#endif
285 } cn52xx;
286 struct cvmx_mixx_iring1_cn52xx cn52xxp1;
287 struct cvmx_mixx_iring1_cn52xx cn56xx;
288 struct cvmx_mixx_iring1_cn52xx cn56xxp1;
289 struct cvmx_mixx_iring1_s cn61xx;
290 struct cvmx_mixx_iring1_s cn63xx;
291 struct cvmx_mixx_iring1_s cn63xxp1;
292 struct cvmx_mixx_iring1_s cn66xx;
293 struct cvmx_mixx_iring1_s cn68xx;
294 struct cvmx_mixx_iring1_s cn68xxp1;
295};
296
297union cvmx_mixx_iring2 {
298 uint64_t u64;
299 struct cvmx_mixx_iring2_s {
300#ifdef __BIG_ENDIAN_BITFIELD
301 uint64_t reserved_52_63:12;
302 uint64_t itlptr:20;
303 uint64_t reserved_20_31:12;
304 uint64_t idbell:20;
305#else
306 uint64_t idbell:20;
307 uint64_t reserved_20_31:12;
308 uint64_t itlptr:20;
309 uint64_t reserved_52_63:12;
310#endif
311 } s;
312 struct cvmx_mixx_iring2_s cn52xx;
313 struct cvmx_mixx_iring2_s cn52xxp1;
314 struct cvmx_mixx_iring2_s cn56xx;
315 struct cvmx_mixx_iring2_s cn56xxp1;
316 struct cvmx_mixx_iring2_s cn61xx;
317 struct cvmx_mixx_iring2_s cn63xx;
318 struct cvmx_mixx_iring2_s cn63xxp1;
319 struct cvmx_mixx_iring2_s cn66xx;
320 struct cvmx_mixx_iring2_s cn68xx;
321 struct cvmx_mixx_iring2_s cn68xxp1;
322};
323
324union cvmx_mixx_isr {
325 uint64_t u64;
326 struct cvmx_mixx_isr_s {
327#ifdef __BIG_ENDIAN_BITFIELD
328 uint64_t reserved_8_63:56;
329 uint64_t ts:1;
330 uint64_t orun:1;
331 uint64_t irun:1;
332 uint64_t data_drp:1;
333 uint64_t irthresh:1;
334 uint64_t orthresh:1;
335 uint64_t idblovf:1;
336 uint64_t odblovf:1;
337#else
338 uint64_t odblovf:1;
339 uint64_t idblovf:1;
340 uint64_t orthresh:1;
341 uint64_t irthresh:1;
342 uint64_t data_drp:1;
343 uint64_t irun:1;
344 uint64_t orun:1;
345 uint64_t ts:1;
346 uint64_t reserved_8_63:56;
347#endif
348 } s;
349 struct cvmx_mixx_isr_cn52xx {
350#ifdef __BIG_ENDIAN_BITFIELD
351 uint64_t reserved_7_63:57;
352 uint64_t orun:1;
353 uint64_t irun:1;
354 uint64_t data_drp:1;
355 uint64_t irthresh:1;
356 uint64_t orthresh:1;
357 uint64_t idblovf:1;
358 uint64_t odblovf:1;
359#else
360 uint64_t odblovf:1;
361 uint64_t idblovf:1;
362 uint64_t orthresh:1;
363 uint64_t irthresh:1;
364 uint64_t data_drp:1;
365 uint64_t irun:1;
366 uint64_t orun:1;
367 uint64_t reserved_7_63:57;
368#endif
369 } cn52xx;
370 struct cvmx_mixx_isr_cn52xx cn52xxp1;
371 struct cvmx_mixx_isr_cn52xx cn56xx;
372 struct cvmx_mixx_isr_cn52xx cn56xxp1;
373 struct cvmx_mixx_isr_s cn61xx;
374 struct cvmx_mixx_isr_s cn63xx;
375 struct cvmx_mixx_isr_s cn63xxp1;
376 struct cvmx_mixx_isr_s cn66xx;
377 struct cvmx_mixx_isr_s cn68xx;
378 struct cvmx_mixx_isr_s cn68xxp1;
379};
380
381union cvmx_mixx_orcnt {
382 uint64_t u64;
383 struct cvmx_mixx_orcnt_s {
384#ifdef __BIG_ENDIAN_BITFIELD
385 uint64_t reserved_20_63:44;
386 uint64_t orcnt:20;
387#else
388 uint64_t orcnt:20;
389 uint64_t reserved_20_63:44;
390#endif
391 } s;
392 struct cvmx_mixx_orcnt_s cn52xx;
393 struct cvmx_mixx_orcnt_s cn52xxp1;
394 struct cvmx_mixx_orcnt_s cn56xx;
395 struct cvmx_mixx_orcnt_s cn56xxp1;
396 struct cvmx_mixx_orcnt_s cn61xx;
397 struct cvmx_mixx_orcnt_s cn63xx;
398 struct cvmx_mixx_orcnt_s cn63xxp1;
399 struct cvmx_mixx_orcnt_s cn66xx;
400 struct cvmx_mixx_orcnt_s cn68xx;
401 struct cvmx_mixx_orcnt_s cn68xxp1;
402};
403
404union cvmx_mixx_orhwm {
405 uint64_t u64;
406 struct cvmx_mixx_orhwm_s {
407#ifdef __BIG_ENDIAN_BITFIELD
408 uint64_t reserved_20_63:44;
409 uint64_t orhwm:20;
410#else
411 uint64_t orhwm:20;
412 uint64_t reserved_20_63:44;
413#endif
414 } s;
415 struct cvmx_mixx_orhwm_s cn52xx;
416 struct cvmx_mixx_orhwm_s cn52xxp1;
417 struct cvmx_mixx_orhwm_s cn56xx;
418 struct cvmx_mixx_orhwm_s cn56xxp1;
419 struct cvmx_mixx_orhwm_s cn61xx;
420 struct cvmx_mixx_orhwm_s cn63xx;
421 struct cvmx_mixx_orhwm_s cn63xxp1;
422 struct cvmx_mixx_orhwm_s cn66xx;
423 struct cvmx_mixx_orhwm_s cn68xx;
424 struct cvmx_mixx_orhwm_s cn68xxp1;
425};
426
427union cvmx_mixx_oring1 {
428 uint64_t u64;
429 struct cvmx_mixx_oring1_s {
430#ifdef __BIG_ENDIAN_BITFIELD
431 uint64_t reserved_60_63:4;
432 uint64_t osize:20;
433 uint64_t obase:37;
434 uint64_t reserved_0_2:3;
435#else
436 uint64_t reserved_0_2:3;
437 uint64_t obase:37;
438 uint64_t osize:20;
439 uint64_t reserved_60_63:4;
440#endif
441 } s;
442 struct cvmx_mixx_oring1_cn52xx {
443#ifdef __BIG_ENDIAN_BITFIELD
444 uint64_t reserved_60_63:4;
445 uint64_t osize:20;
446 uint64_t reserved_36_39:4;
447 uint64_t obase:33;
448 uint64_t reserved_0_2:3;
449#else
450 uint64_t reserved_0_2:3;
451 uint64_t obase:33;
452 uint64_t reserved_36_39:4;
453 uint64_t osize:20;
454 uint64_t reserved_60_63:4;
455#endif
456 } cn52xx;
457 struct cvmx_mixx_oring1_cn52xx cn52xxp1;
458 struct cvmx_mixx_oring1_cn52xx cn56xx;
459 struct cvmx_mixx_oring1_cn52xx cn56xxp1;
460 struct cvmx_mixx_oring1_s cn61xx;
461 struct cvmx_mixx_oring1_s cn63xx;
462 struct cvmx_mixx_oring1_s cn63xxp1;
463 struct cvmx_mixx_oring1_s cn66xx;
464 struct cvmx_mixx_oring1_s cn68xx;
465 struct cvmx_mixx_oring1_s cn68xxp1;
466};
467
468union cvmx_mixx_oring2 {
469 uint64_t u64;
470 struct cvmx_mixx_oring2_s {
471#ifdef __BIG_ENDIAN_BITFIELD
472 uint64_t reserved_52_63:12;
473 uint64_t otlptr:20;
474 uint64_t reserved_20_31:12;
475 uint64_t odbell:20;
476#else
477 uint64_t odbell:20;
478 uint64_t reserved_20_31:12;
479 uint64_t otlptr:20;
480 uint64_t reserved_52_63:12;
481#endif
482 } s;
483 struct cvmx_mixx_oring2_s cn52xx;
484 struct cvmx_mixx_oring2_s cn52xxp1;
485 struct cvmx_mixx_oring2_s cn56xx;
486 struct cvmx_mixx_oring2_s cn56xxp1;
487 struct cvmx_mixx_oring2_s cn61xx;
488 struct cvmx_mixx_oring2_s cn63xx;
489 struct cvmx_mixx_oring2_s cn63xxp1;
490 struct cvmx_mixx_oring2_s cn66xx;
491 struct cvmx_mixx_oring2_s cn68xx;
492 struct cvmx_mixx_oring2_s cn68xxp1;
493};
494
495union cvmx_mixx_remcnt {
496 uint64_t u64;
497 struct cvmx_mixx_remcnt_s {
498#ifdef __BIG_ENDIAN_BITFIELD
499 uint64_t reserved_52_63:12;
500 uint64_t iremcnt:20;
501 uint64_t reserved_20_31:12;
502 uint64_t oremcnt:20;
503#else
504 uint64_t oremcnt:20;
505 uint64_t reserved_20_31:12;
506 uint64_t iremcnt:20;
507 uint64_t reserved_52_63:12;
508#endif
509 } s;
510 struct cvmx_mixx_remcnt_s cn52xx;
511 struct cvmx_mixx_remcnt_s cn52xxp1;
512 struct cvmx_mixx_remcnt_s cn56xx;
513 struct cvmx_mixx_remcnt_s cn56xxp1;
514 struct cvmx_mixx_remcnt_s cn61xx;
515 struct cvmx_mixx_remcnt_s cn63xx;
516 struct cvmx_mixx_remcnt_s cn63xxp1;
517 struct cvmx_mixx_remcnt_s cn66xx;
518 struct cvmx_mixx_remcnt_s cn68xx;
519 struct cvmx_mixx_remcnt_s cn68xxp1;
520};
521
522union cvmx_mixx_tsctl {
523 uint64_t u64;
524 struct cvmx_mixx_tsctl_s {
525#ifdef __BIG_ENDIAN_BITFIELD
526 uint64_t reserved_21_63:43;
527 uint64_t tsavl:5;
528 uint64_t reserved_13_15:3;
529 uint64_t tstot:5;
530 uint64_t reserved_5_7:3;
531 uint64_t tscnt:5;
532#else
533 uint64_t tscnt:5;
534 uint64_t reserved_5_7:3;
535 uint64_t tstot:5;
536 uint64_t reserved_13_15:3;
537 uint64_t tsavl:5;
538 uint64_t reserved_21_63:43;
539#endif
540 } s;
541 struct cvmx_mixx_tsctl_s cn61xx;
542 struct cvmx_mixx_tsctl_s cn63xx;
543 struct cvmx_mixx_tsctl_s cn63xxp1;
544 struct cvmx_mixx_tsctl_s cn66xx;
545 struct cvmx_mixx_tsctl_s cn68xx;
546 struct cvmx_mixx_tsctl_s cn68xxp1;
547};
548
549union cvmx_mixx_tstamp {
550 uint64_t u64;
551 struct cvmx_mixx_tstamp_s {
552#ifdef __BIG_ENDIAN_BITFIELD
553 uint64_t tstamp:64;
554#else
555 uint64_t tstamp:64;
556#endif
557 } s;
558 struct cvmx_mixx_tstamp_s cn61xx;
559 struct cvmx_mixx_tstamp_s cn63xx;
560 struct cvmx_mixx_tstamp_s cn63xxp1;
561 struct cvmx_mixx_tstamp_s cn66xx;
562 struct cvmx_mixx_tstamp_s cn68xx;
563 struct cvmx_mixx_tstamp_s cn68xxp1;
564};
565
566#endif