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1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "sun5i.dtsi"
46
47#include <dt-bindings/thermal/thermal.h>
48
49/ {
50 thermal-zones {
51 cpu_thermal {
52 /* milliseconds */
53 polling-delay-passive = <250>;
54 polling-delay = <1000>;
55 thermal-sensors = <&rtp>;
56
57 cooling-maps {
58 map0 {
59 trip = <&cpu_alert0>;
60 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
61 };
62 };
63
64 trips {
65 cpu_alert0: cpu_alert0 {
66 /* milliCelsius */
67 temperature = <85000>;
68 hysteresis = <2000>;
69 type = "passive";
70 };
71
72 cpu_crit: cpu_crit {
73 /* milliCelsius */
74 temperature = <100000>;
75 hysteresis = <2000>;
76 type = "critical";
77 };
78 };
79 };
80 };
81
82 display-engine {
83 compatible = "allwinner,sun5i-a13-display-engine";
84 allwinner,pipelines = <&fe0>;
85 };
86
87 soc {
88 pwm: pwm@1c20e00 {
89 compatible = "allwinner,sun5i-a13-pwm";
90 reg = <0x01c20e00 0xc>;
91 clocks = <&ccu CLK_HOSC>;
92 #pwm-cells = <3>;
93 status = "disabled";
94 };
95
96 };
97};
98
99&ccu {
100 compatible = "allwinner,sun5i-a13-ccu";
101};
102
103&cpu0 {
104 clock-latency = <244144>; /* 8 32k periods */
105 operating-points = <
106 /* kHz uV */
107 1008000 1400000
108 912000 1350000
109 864000 1300000
110 624000 1200000
111 576000 1200000
112 432000 1200000
113 >;
114 #cooling-cells = <2>;
115};
116
117&pio {
118 compatible = "allwinner,sun5i-a13-pinctrl";
119};
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&intc>;
18
19 aliases {
20 serial0 = &uart1;
21 serial1 = &uart3;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a8";
30 reg = <0x0>;
31 };
32 };
33
34 memory {
35 reg = <0x40000000 0x20000000>;
36 };
37
38 clocks {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges;
42
43 /*
44 * This is a dummy clock, to be used as placeholder on
45 * other mux clocks when a specific parent clock is not
46 * yet implemented. It should be dropped when the driver
47 * is complete.
48 */
49 dummy: dummy {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <0>;
53 };
54
55 osc24M: clk@01c20050 {
56 #clock-cells = <0>;
57 compatible = "allwinner,sun4i-a10-osc-clk";
58 reg = <0x01c20050 0x4>;
59 clock-frequency = <24000000>;
60 clock-output-names = "osc24M";
61 };
62
63 osc32k: clk@0 {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 clock-output-names = "osc32k";
68 };
69
70 pll1: clk@01c20000 {
71 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20000 0x4>;
74 clocks = <&osc24M>;
75 clock-output-names = "pll1";
76 };
77
78 pll4: clk@01c20018 {
79 #clock-cells = <0>;
80 compatible = "allwinner,sun4i-a10-pll1-clk";
81 reg = <0x01c20018 0x4>;
82 clocks = <&osc24M>;
83 clock-output-names = "pll4";
84 };
85
86 pll5: clk@01c20020 {
87 #clock-cells = <1>;
88 compatible = "allwinner,sun4i-a10-pll5-clk";
89 reg = <0x01c20020 0x4>;
90 clocks = <&osc24M>;
91 clock-output-names = "pll5_ddr", "pll5_other";
92 };
93
94 pll6: clk@01c20028 {
95 #clock-cells = <1>;
96 compatible = "allwinner,sun4i-a10-pll6-clk";
97 reg = <0x01c20028 0x4>;
98 clocks = <&osc24M>;
99 clock-output-names = "pll6_sata", "pll6_other", "pll6";
100 };
101
102 /* dummy is 200M */
103 cpu: cpu@01c20054 {
104 #clock-cells = <0>;
105 compatible = "allwinner,sun4i-a10-cpu-clk";
106 reg = <0x01c20054 0x4>;
107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
108 clock-output-names = "cpu";
109 };
110
111 axi: axi@01c20054 {
112 #clock-cells = <0>;
113 compatible = "allwinner,sun4i-a10-axi-clk";
114 reg = <0x01c20054 0x4>;
115 clocks = <&cpu>;
116 clock-output-names = "axi";
117 };
118
119 axi_gates: clk@01c2005c {
120 #clock-cells = <1>;
121 compatible = "allwinner,sun4i-a10-axi-gates-clk";
122 reg = <0x01c2005c 0x4>;
123 clocks = <&axi>;
124 clock-output-names = "axi_dram";
125 };
126
127 ahb: ahb@01c20054 {
128 #clock-cells = <0>;
129 compatible = "allwinner,sun4i-a10-ahb-clk";
130 reg = <0x01c20054 0x4>;
131 clocks = <&axi>;
132 clock-output-names = "ahb";
133 };
134
135 ahb_gates: clk@01c20060 {
136 #clock-cells = <1>;
137 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
138 reg = <0x01c20060 0x8>;
139 clocks = <&ahb>;
140 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
141 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
142 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
143 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
144 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
145 "ahb_de_fe", "ahb_iep", "ahb_mali400";
146 };
147
148 apb0: apb0@01c20054 {
149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-a10-apb0-clk";
151 reg = <0x01c20054 0x4>;
152 clocks = <&ahb>;
153 clock-output-names = "apb0";
154 };
155
156 apb0_gates: clk@01c20068 {
157 #clock-cells = <1>;
158 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
159 reg = <0x01c20068 0x4>;
160 clocks = <&apb0>;
161 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
162 };
163
164 apb1_mux: apb1_mux@01c20058 {
165 #clock-cells = <0>;
166 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
167 reg = <0x01c20058 0x4>;
168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169 clock-output-names = "apb1_mux";
170 };
171
172 apb1: apb1@01c20058 {
173 #clock-cells = <0>;
174 compatible = "allwinner,sun4i-a10-apb1-clk";
175 reg = <0x01c20058 0x4>;
176 clocks = <&apb1_mux>;
177 clock-output-names = "apb1";
178 };
179
180 apb1_gates: clk@01c2006c {
181 #clock-cells = <1>;
182 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
183 reg = <0x01c2006c 0x4>;
184 clocks = <&apb1>;
185 clock-output-names = "apb1_i2c0", "apb1_i2c1",
186 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
187 };
188
189 nand_clk: clk@01c20080 {
190 #clock-cells = <0>;
191 compatible = "allwinner,sun4i-a10-mod0-clk";
192 reg = <0x01c20080 0x4>;
193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
194 clock-output-names = "nand";
195 };
196
197 ms_clk: clk@01c20084 {
198 #clock-cells = <0>;
199 compatible = "allwinner,sun4i-a10-mod0-clk";
200 reg = <0x01c20084 0x4>;
201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
202 clock-output-names = "ms";
203 };
204
205 mmc0_clk: clk@01c20088 {
206 #clock-cells = <0>;
207 compatible = "allwinner,sun4i-a10-mod0-clk";
208 reg = <0x01c20088 0x4>;
209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
210 clock-output-names = "mmc0";
211 };
212
213 mmc1_clk: clk@01c2008c {
214 #clock-cells = <0>;
215 compatible = "allwinner,sun4i-a10-mod0-clk";
216 reg = <0x01c2008c 0x4>;
217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
218 clock-output-names = "mmc1";
219 };
220
221 mmc2_clk: clk@01c20090 {
222 #clock-cells = <0>;
223 compatible = "allwinner,sun4i-a10-mod0-clk";
224 reg = <0x01c20090 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "mmc2";
227 };
228
229 ts_clk: clk@01c20098 {
230 #clock-cells = <0>;
231 compatible = "allwinner,sun4i-a10-mod0-clk";
232 reg = <0x01c20098 0x4>;
233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
234 clock-output-names = "ts";
235 };
236
237 ss_clk: clk@01c2009c {
238 #clock-cells = <0>;
239 compatible = "allwinner,sun4i-a10-mod0-clk";
240 reg = <0x01c2009c 0x4>;
241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
242 clock-output-names = "ss";
243 };
244
245 spi0_clk: clk@01c200a0 {
246 #clock-cells = <0>;
247 compatible = "allwinner,sun4i-a10-mod0-clk";
248 reg = <0x01c200a0 0x4>;
249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clock-output-names = "spi0";
251 };
252
253 spi1_clk: clk@01c200a4 {
254 #clock-cells = <0>;
255 compatible = "allwinner,sun4i-a10-mod0-clk";
256 reg = <0x01c200a4 0x4>;
257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clock-output-names = "spi1";
259 };
260
261 spi2_clk: clk@01c200a8 {
262 #clock-cells = <0>;
263 compatible = "allwinner,sun4i-a10-mod0-clk";
264 reg = <0x01c200a8 0x4>;
265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
266 clock-output-names = "spi2";
267 };
268
269 ir0_clk: clk@01c200b0 {
270 #clock-cells = <0>;
271 compatible = "allwinner,sun4i-a10-mod0-clk";
272 reg = <0x01c200b0 0x4>;
273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
274 clock-output-names = "ir0";
275 };
276
277 usb_clk: clk@01c200cc {
278 #clock-cells = <1>;
279 #reset-cells = <1>;
280 compatible = "allwinner,sun5i-a13-usb-clk";
281 reg = <0x01c200cc 0x4>;
282 clocks = <&pll6 1>;
283 clock-output-names = "usb_ohci0", "usb_phy";
284 };
285
286 mbus_clk: clk@01c2015c {
287 #clock-cells = <0>;
288 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c2015c 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "mbus";
292 };
293 };
294
295 soc@01c00000 {
296 compatible = "simple-bus";
297 #address-cells = <1>;
298 #size-cells = <1>;
299 ranges;
300
301 spi0: spi@01c05000 {
302 compatible = "allwinner,sun4i-a10-spi";
303 reg = <0x01c05000 0x1000>;
304 interrupts = <10>;
305 clocks = <&ahb_gates 20>, <&spi0_clk>;
306 clock-names = "ahb", "mod";
307 status = "disabled";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 };
311
312 spi1: spi@01c06000 {
313 compatible = "allwinner,sun4i-a10-spi";
314 reg = <0x01c06000 0x1000>;
315 interrupts = <11>;
316 clocks = <&ahb_gates 21>, <&spi1_clk>;
317 clock-names = "ahb", "mod";
318 status = "disabled";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 };
322
323 usbphy: phy@01c13400 {
324 #phy-cells = <1>;
325 compatible = "allwinner,sun5i-a13-usb-phy";
326 reg = <0x01c13400 0x10 0x01c14800 0x4>;
327 reg-names = "phy_ctrl", "pmu1";
328 clocks = <&usb_clk 8>;
329 clock-names = "usb_phy";
330 resets = <&usb_clk 1>;
331 reset-names = "usb1_reset";
332 status = "disabled";
333 };
334
335 ehci0: usb@01c14000 {
336 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
337 reg = <0x01c14000 0x100>;
338 interrupts = <39>;
339 clocks = <&ahb_gates 1>;
340 phys = <&usbphy 1>;
341 phy-names = "usb";
342 status = "disabled";
343 };
344
345 ohci0: usb@01c14400 {
346 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
347 reg = <0x01c14400 0x100>;
348 interrupts = <40>;
349 clocks = <&usb_clk 6>, <&ahb_gates 2>;
350 phys = <&usbphy 1>;
351 phy-names = "usb";
352 status = "disabled";
353 };
354
355 spi2: spi@01c17000 {
356 compatible = "allwinner,sun4i-a10-spi";
357 reg = <0x01c17000 0x1000>;
358 interrupts = <12>;
359 clocks = <&ahb_gates 22>, <&spi2_clk>;
360 clock-names = "ahb", "mod";
361 status = "disabled";
362 #address-cells = <1>;
363 #size-cells = <0>;
364 };
365
366 intc: interrupt-controller@01c20400 {
367 compatible = "allwinner,sun4i-a10-ic";
368 reg = <0x01c20400 0x400>;
369 interrupt-controller;
370 #interrupt-cells = <1>;
371 };
372
373 pio: pinctrl@01c20800 {
374 compatible = "allwinner,sun5i-a13-pinctrl";
375 reg = <0x01c20800 0x400>;
376 interrupts = <28>;
377 clocks = <&apb0_gates 5>;
378 gpio-controller;
379 interrupt-controller;
380 #address-cells = <1>;
381 #size-cells = <0>;
382 #gpio-cells = <3>;
383
384 uart1_pins_a: uart1@0 {
385 allwinner,pins = "PE10", "PE11";
386 allwinner,function = "uart1";
387 allwinner,drive = <0>;
388 allwinner,pull = <0>;
389 };
390
391 uart1_pins_b: uart1@1 {
392 allwinner,pins = "PG3", "PG4";
393 allwinner,function = "uart1";
394 allwinner,drive = <0>;
395 allwinner,pull = <0>;
396 };
397
398 i2c0_pins_a: i2c0@0 {
399 allwinner,pins = "PB0", "PB1";
400 allwinner,function = "i2c0";
401 allwinner,drive = <0>;
402 allwinner,pull = <0>;
403 };
404
405 i2c1_pins_a: i2c1@0 {
406 allwinner,pins = "PB15", "PB16";
407 allwinner,function = "i2c1";
408 allwinner,drive = <0>;
409 allwinner,pull = <0>;
410 };
411
412 i2c2_pins_a: i2c2@0 {
413 allwinner,pins = "PB17", "PB18";
414 allwinner,function = "i2c2";
415 allwinner,drive = <0>;
416 allwinner,pull = <0>;
417 };
418 };
419
420 timer@01c20c00 {
421 compatible = "allwinner,sun4i-a10-timer";
422 reg = <0x01c20c00 0x90>;
423 interrupts = <22>;
424 clocks = <&osc24M>;
425 };
426
427 wdt: watchdog@01c20c90 {
428 compatible = "allwinner,sun4i-a10-wdt";
429 reg = <0x01c20c90 0x10>;
430 };
431
432 sid: eeprom@01c23800 {
433 compatible = "allwinner,sun4i-a10-sid";
434 reg = <0x01c23800 0x10>;
435 };
436
437 rtp: rtp@01c25000 {
438 compatible = "allwinner,sun4i-a10-ts";
439 reg = <0x01c25000 0x100>;
440 interrupts = <29>;
441 };
442
443 uart1: serial@01c28400 {
444 compatible = "snps,dw-apb-uart";
445 reg = <0x01c28400 0x400>;
446 interrupts = <2>;
447 reg-shift = <2>;
448 reg-io-width = <4>;
449 clocks = <&apb1_gates 17>;
450 status = "disabled";
451 };
452
453 uart3: serial@01c28c00 {
454 compatible = "snps,dw-apb-uart";
455 reg = <0x01c28c00 0x400>;
456 interrupts = <4>;
457 reg-shift = <2>;
458 reg-io-width = <4>;
459 clocks = <&apb1_gates 19>;
460 status = "disabled";
461 };
462
463 i2c0: i2c@01c2ac00 {
464 compatible = "allwinner,sun4i-i2c";
465 reg = <0x01c2ac00 0x400>;
466 interrupts = <7>;
467 clocks = <&apb1_gates 0>;
468 clock-frequency = <100000>;
469 status = "disabled";
470 };
471
472 i2c1: i2c@01c2b000 {
473 compatible = "allwinner,sun4i-i2c";
474 reg = <0x01c2b000 0x400>;
475 interrupts = <8>;
476 clocks = <&apb1_gates 1>;
477 clock-frequency = <100000>;
478 status = "disabled";
479 };
480
481 i2c2: i2c@01c2b400 {
482 compatible = "allwinner,sun4i-i2c";
483 reg = <0x01c2b400 0x400>;
484 interrupts = <9>;
485 clocks = <&apb1_gates 2>;
486 clock-frequency = <100000>;
487 status = "disabled";
488 };
489
490 timer@01c60000 {
491 compatible = "allwinner,sun5i-a13-hstimer";
492 reg = <0x01c60000 0x1000>;
493 interrupts = <82>, <83>;
494 clocks = <&ahb_gates 28>;
495 };
496 };
497};