1// SPDX-License-Identifier: GPL-2.0+
 2/*
 3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 
 
 
 
 
 
 
 
 
 
 
 
 
 4 */
 5
 6/dts-v1/;
 7/* First 4KB has trampoline code for secondary cores. */
 8/memreserve/ 0x00000000 0x0001000;
 9#include "socfpga.dtsi"
10
11/ {
12	soc {
13		clkmgr@ffd04000 {
14			clocks {
15				osc1 {
16					clock-frequency = <25000000>;
17				};
18			};
19		};
20
21		mmc0: dwmmc0@ff704000 {
 
 
22			broken-cd;
23			bus-width = <4>;
24			cap-mmc-highspeed;
25			cap-sd-highspeed;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
26		};
27
28		sysmgr@ffd08000 {
29			cpu1-start-addr = <0xffd080c4>;
30		};
31	};
32};
33
34&watchdog0 {
35	status = "okay";
36};

 
 1/*
 2 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License as published by
 6 * the Free Software Foundation; either version 2 of the License, or
 7 * (at your option) any later version.
 8 *
 9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/dts-v1/;
19/include/ "socfpga.dtsi"
 
 
20
21/ {
22	soc {
23		clkmgr@ffd04000 {
24			clocks {
25				osc1 {
26					clock-frequency = <25000000>;
27				};
28			};
29		};
30
31		dwmmc0@ff704000 {
32			num-slots = <1>;
33			supports-highspeed;
34			broken-cd;
35
36			slot@0 {
37				reg = <0>;
38				bus-width = <4>;
39			};
40		};
41
42		ethernet@ff702000 {
43			phy-mode = "rgmii";
44			phy-addr = <0xffffffff>; /* probe for phy addr */
45			status = "okay";
46		};
47
48		timer0@ffc08000 {
49			clock-frequency = <100000000>;
50		};
51
52		timer1@ffc09000 {
53			clock-frequency = <100000000>;
54		};
55
56		timer2@ffd00000 {
57			clock-frequency = <25000000>;
58		};
59
60		timer3@ffd01000 {
61			clock-frequency = <25000000>;
62		};
63
64		serial0@ffc02000 {
65			clock-frequency = <100000000>;
66		};
67
68		serial1@ffc03000 {
69			clock-frequency = <100000000>;
70		};
71
72		sysmgr@ffd08000 {
73			cpu1-start-addr = <0xffd080c4>;
74		};
75	};
 
 
 
 
76};