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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
4 */
5
6#include "imx6q.dtsi"
7#include "imx6qdl-phytec-pfla02.dtsi"
8
9/ {
10 model = "Phytec phyFLEX-i.MX6 Quad";
11 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
12
13 memory@10000000 {
14 device_type = "memory";
15 reg = <0x10000000 0x80000000>;
16 };
17};
1/*
2 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "imx6q.dtsi"
13
14/ {
15 model = "Phytec phyFLEX-i.MX6 Ouad";
16 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
17
18 memory {
19 reg = <0x10000000 0x80000000>;
20 };
21
22 regulators {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 reg_usb_otg_vbus: regulator@0 {
28 compatible = "regulator-fixed";
29 reg = <0>;
30 regulator-name = "usb_otg_vbus";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
33 gpio = <&gpio4 15 0>;
34 };
35
36 reg_usb_h1_vbus: regulator@1 {
37 compatible = "regulator-fixed";
38 reg = <1>;
39 regulator-name = "usb_h1_vbus";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
42 gpio = <&gpio1 0 0>;
43 };
44 };
45};
46
47&ecspi3 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_ecspi3>;
50 status = "okay";
51 fsl,spi-num-chipselects = <1>;
52 cs-gpios = <&gpio4 24 0>;
53
54 flash@0 {
55 compatible = "m25p80";
56 spi-max-frequency = <20000000>;
57 reg = <0>;
58 };
59};
60
61&i2c1 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_i2c1>;
64 status = "okay";
65
66 eeprom@50 {
67 compatible = "atmel,24c32";
68 reg = <0x50>;
69 };
70
71 pmic@58 {
72 compatible = "dialog,da9063";
73 reg = <0x58>;
74 interrupt-parent = <&gpio4>;
75 interrupts = <17 0x8>; /* active-low GPIO4_17 */
76
77 regulators {
78 vddcore_reg: bcore1 {
79 regulator-min-microvolt = <730000>;
80 regulator-max-microvolt = <1380000>;
81 regulator-always-on;
82 };
83
84 vddsoc_reg: bcore2 {
85 regulator-min-microvolt = <730000>;
86 regulator-max-microvolt = <1380000>;
87 regulator-always-on;
88 };
89
90 vdd_ddr3_reg: bpro {
91 regulator-min-microvolt = <1500000>;
92 regulator-max-microvolt = <1500000>;
93 regulator-always-on;
94 };
95
96 vdd_3v3_reg: bperi {
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
99 regulator-always-on;
100 };
101
102 vdd_buckmem_reg: bmem {
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-always-on;
106 };
107
108 vdd_eth_reg: bio {
109 regulator-min-microvolt = <1200000>;
110 regulator-max-microvolt = <1200000>;
111 regulator-always-on;
112 };
113
114 vdd_eth_io_reg: ldo4 {
115 regulator-min-microvolt = <2500000>;
116 regulator-max-microvolt = <2500000>;
117 regulator-always-on;
118 };
119
120 vdd_mx6_snvs_reg: ldo5 {
121 regulator-min-microvolt = <3000000>;
122 regulator-max-microvolt = <3000000>;
123 regulator-always-on;
124 };
125
126 vdd_3v3_pmic_io_reg: ldo6 {
127 regulator-min-microvolt = <3300000>;
128 regulator-max-microvolt = <3300000>;
129 regulator-always-on;
130 };
131
132 vdd_sd0_reg: ldo9 {
133 regulator-min-microvolt = <3300000>;
134 regulator-max-microvolt = <3300000>;
135 };
136
137 vdd_sd1_reg: ldo10 {
138 regulator-min-microvolt = <3300000>;
139 regulator-max-microvolt = <3300000>;
140 };
141
142 vdd_mx6_high_reg: ldo11 {
143 regulator-min-microvolt = <3000000>;
144 regulator-max-microvolt = <3000000>;
145 regulator-always-on;
146 };
147 };
148 };
149};
150
151&iomuxc {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_hog>;
154
155 imx6q-phytec-pfla02 {
156 pinctrl_hog: hoggrp {
157 fsl,pins = <
158 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
159 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
160 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
161 >;
162 };
163
164 pinctrl_ecspi3: ecspi3grp {
165 fsl,pins = <
166 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
167 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
168 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
169 >;
170 };
171
172 pinctrl_enet: enetgrp {
173 fsl,pins = <
174 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
175 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
176 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
177 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
178 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
179 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
180 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
181 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
182 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
183 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
184 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
185 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
186 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
187 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
188 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
189 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
190 >;
191 };
192
193 pinctrl_gpmi_nand: gpminandgrp {
194 fsl,pins = <
195 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
196 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
197 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
198 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
199 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
200 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
201 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
202 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
203 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
204 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
205 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
206 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
207 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
208 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
209 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
210 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
211 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
212 >;
213 };
214
215 pinctrl_i2c1: i2c1grp {
216 fsl,pins = <
217 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
218 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
219 >;
220 };
221
222 pinctrl_uart4: uart4grp {
223 fsl,pins = <
224 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
225 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
226 >;
227 };
228
229 pinctrl_usbh1: usbh1grp {
230 fsl,pins = <
231 MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
232 >;
233 };
234
235 pinctrl_usbotg: usbotggrp {
236 fsl,pins = <
237 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
238 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
239 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
240 >;
241 };
242
243 pinctrl_usdhc2: usdhc2grp {
244 fsl,pins = <
245 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
246 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
247 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
248 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
249 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
250 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
251 >;
252 };
253
254 pinctrl_usdhc3: usdhc3grp {
255 fsl,pins = <
256 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
257 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
258 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
259 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
260 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
261 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
262 >;
263 };
264
265 pinctrl_usdhc3_cdwp: usdhc3cdwp {
266 fsl,pins = <
267 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
268 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
269 >;
270 };
271 };
272};
273
274&fec {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_enet>;
277 phy-mode = "rgmii";
278 phy-reset-gpios = <&gpio3 23 0>;
279 status = "disabled";
280};
281
282&gpmi {
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_gpmi_nand>;
285 nand-on-flash-bbt;
286 status = "disabled";
287};
288
289&uart4 {
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_uart4>;
292 status = "disabled";
293};
294
295&usbh1 {
296 vbus-supply = <®_usb_h1_vbus>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_usbh1>;
299 status = "disabled";
300};
301
302&usbotg {
303 vbus-supply = <®_usb_otg_vbus>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_usbotg>;
306 disable-over-current;
307 status = "disabled";
308};
309
310&usdhc2 {
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_usdhc2>;
313 cd-gpios = <&gpio1 4 0>;
314 wp-gpios = <&gpio1 2 0>;
315 status = "disabled";
316};
317
318&usdhc3 {
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_usdhc3
321 &pinctrl_usdhc3_cdwp>;
322 cd-gpios = <&gpio1 27 0>;
323 wp-gpios = <&gpio1 29 0>;
324 status = "disabled";
325};