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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MPS2 UART driver
4 *
5 * Copyright (C) 2015 ARM Limited
6 *
7 * Author: Vladimir Murzin <vladimir.murzin@arm.com>
8 *
9 * TODO: support for SysRq
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/console.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/of_device.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/serial_core.h>
23#include <linux/tty_flip.h>
24#include <linux/types.h>
25#include <linux/idr.h>
26
27#define SERIAL_NAME "ttyMPS"
28#define DRIVER_NAME "mps2-uart"
29#define MAKE_NAME(x) (DRIVER_NAME # x)
30
31#define UARTn_DATA 0x00
32
33#define UARTn_STATE 0x04
34#define UARTn_STATE_TX_FULL BIT(0)
35#define UARTn_STATE_RX_FULL BIT(1)
36#define UARTn_STATE_TX_OVERRUN BIT(2)
37#define UARTn_STATE_RX_OVERRUN BIT(3)
38
39#define UARTn_CTRL 0x08
40#define UARTn_CTRL_TX_ENABLE BIT(0)
41#define UARTn_CTRL_RX_ENABLE BIT(1)
42#define UARTn_CTRL_TX_INT_ENABLE BIT(2)
43#define UARTn_CTRL_RX_INT_ENABLE BIT(3)
44#define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4)
45#define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5)
46
47#define UARTn_INT 0x0c
48#define UARTn_INT_TX BIT(0)
49#define UARTn_INT_RX BIT(1)
50#define UARTn_INT_TX_OVERRUN BIT(2)
51#define UARTn_INT_RX_OVERRUN BIT(3)
52
53#define UARTn_BAUDDIV 0x10
54#define UARTn_BAUDDIV_MASK GENMASK(20, 0)
55
56/*
57 * Helpers to make typical enable/disable operations more readable.
58 */
59#define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\
60 UARTn_CTRL_TX_INT_ENABLE |\
61 UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
62
63#define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\
64 UARTn_CTRL_RX_INT_ENABLE |\
65 UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
66
67#define MPS2_MAX_PORTS 3
68
69#define UART_PORT_COMBINED_IRQ BIT(0)
70
71struct mps2_uart_port {
72 struct uart_port port;
73 struct clk *clk;
74 unsigned int tx_irq;
75 unsigned int rx_irq;
76 unsigned int flags;
77};
78
79static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
80{
81 return container_of(port, struct mps2_uart_port, port);
82}
83
84static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off)
85{
86 struct mps2_uart_port *mps_port = to_mps2_port(port);
87
88 writeb(val, mps_port->port.membase + off);
89}
90
91static u8 mps2_uart_read8(struct uart_port *port, unsigned int off)
92{
93 struct mps2_uart_port *mps_port = to_mps2_port(port);
94
95 return readb(mps_port->port.membase + off);
96}
97
98static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off)
99{
100 struct mps2_uart_port *mps_port = to_mps2_port(port);
101
102 writel_relaxed(val, mps_port->port.membase + off);
103}
104
105static unsigned int mps2_uart_tx_empty(struct uart_port *port)
106{
107 u8 status = mps2_uart_read8(port, UARTn_STATE);
108
109 return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
110}
111
112static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
113{
114}
115
116static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
117{
118 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
119}
120
121static void mps2_uart_stop_tx(struct uart_port *port)
122{
123 u8 control = mps2_uart_read8(port, UARTn_CTRL);
124
125 control &= ~UARTn_CTRL_TX_INT_ENABLE;
126
127 mps2_uart_write8(port, control, UARTn_CTRL);
128}
129
130static void mps2_uart_tx_chars(struct uart_port *port)
131{
132 struct circ_buf *xmit = &port->state->xmit;
133
134 while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) {
135 if (port->x_char) {
136 mps2_uart_write8(port, port->x_char, UARTn_DATA);
137 port->x_char = 0;
138 port->icount.tx++;
139 continue;
140 }
141
142 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
143 break;
144
145 mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA);
146 xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
147 port->icount.tx++;
148 }
149
150 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
151 uart_write_wakeup(port);
152
153 if (uart_circ_empty(xmit))
154 mps2_uart_stop_tx(port);
155}
156
157static void mps2_uart_start_tx(struct uart_port *port)
158{
159 u8 control = mps2_uart_read8(port, UARTn_CTRL);
160
161 control |= UARTn_CTRL_TX_INT_ENABLE;
162
163 mps2_uart_write8(port, control, UARTn_CTRL);
164
165 /*
166 * We've just unmasked the TX IRQ and now slow-starting via
167 * polling; if there is enough data to fill up the internal
168 * write buffer in one go, the TX IRQ should assert, at which
169 * point we switch to fully interrupt-driven TX.
170 */
171
172 mps2_uart_tx_chars(port);
173}
174
175static void mps2_uart_stop_rx(struct uart_port *port)
176{
177 u8 control = mps2_uart_read8(port, UARTn_CTRL);
178
179 control &= ~UARTn_CTRL_RX_GRP;
180
181 mps2_uart_write8(port, control, UARTn_CTRL);
182}
183
184static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
185{
186}
187
188static void mps2_uart_rx_chars(struct uart_port *port)
189{
190 struct tty_port *tport = &port->state->port;
191
192 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
193 u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
194
195 port->icount.rx++;
196 tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
197 }
198
199 tty_flip_buffer_push(tport);
200}
201
202static irqreturn_t mps2_uart_rxirq(int irq, void *data)
203{
204 struct uart_port *port = data;
205 u8 irqflag = mps2_uart_read8(port, UARTn_INT);
206
207 if (unlikely(!(irqflag & UARTn_INT_RX)))
208 return IRQ_NONE;
209
210 spin_lock(&port->lock);
211
212 mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
213 mps2_uart_rx_chars(port);
214
215 spin_unlock(&port->lock);
216
217 return IRQ_HANDLED;
218}
219
220static irqreturn_t mps2_uart_txirq(int irq, void *data)
221{
222 struct uart_port *port = data;
223 u8 irqflag = mps2_uart_read8(port, UARTn_INT);
224
225 if (unlikely(!(irqflag & UARTn_INT_TX)))
226 return IRQ_NONE;
227
228 spin_lock(&port->lock);
229
230 mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
231 mps2_uart_tx_chars(port);
232
233 spin_unlock(&port->lock);
234
235 return IRQ_HANDLED;
236}
237
238static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
239{
240 irqreturn_t handled = IRQ_NONE;
241 struct uart_port *port = data;
242 u8 irqflag = mps2_uart_read8(port, UARTn_INT);
243
244 spin_lock(&port->lock);
245
246 if (irqflag & UARTn_INT_RX_OVERRUN) {
247 struct tty_port *tport = &port->state->port;
248
249 mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
250 port->icount.overrun++;
251 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
252 tty_flip_buffer_push(tport);
253 handled = IRQ_HANDLED;
254 }
255
256 /*
257 * It's never been seen in practice and it never *should* happen since
258 * we check if there is enough room in TX buffer before sending data.
259 * So we keep this check in case something suspicious has happened.
260 */
261 if (irqflag & UARTn_INT_TX_OVERRUN) {
262 mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
263 handled = IRQ_HANDLED;
264 }
265
266 spin_unlock(&port->lock);
267
268 return handled;
269}
270
271static irqreturn_t mps2_uart_combinedirq(int irq, void *data)
272{
273 if (mps2_uart_rxirq(irq, data) == IRQ_HANDLED)
274 return IRQ_HANDLED;
275
276 if (mps2_uart_txirq(irq, data) == IRQ_HANDLED)
277 return IRQ_HANDLED;
278
279 if (mps2_uart_oerrirq(irq, data) == IRQ_HANDLED)
280 return IRQ_HANDLED;
281
282 return IRQ_NONE;
283}
284
285static int mps2_uart_startup(struct uart_port *port)
286{
287 struct mps2_uart_port *mps_port = to_mps2_port(port);
288 u8 control = mps2_uart_read8(port, UARTn_CTRL);
289 int ret;
290
291 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
292
293 mps2_uart_write8(port, control, UARTn_CTRL);
294
295 if (mps_port->flags & UART_PORT_COMBINED_IRQ) {
296 ret = request_irq(port->irq, mps2_uart_combinedirq, 0,
297 MAKE_NAME(-combined), mps_port);
298
299 if (ret) {
300 dev_err(port->dev, "failed to register combinedirq (%d)\n", ret);
301 return ret;
302 }
303 } else {
304 ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED,
305 MAKE_NAME(-overrun), mps_port);
306
307 if (ret) {
308 dev_err(port->dev, "failed to register oerrirq (%d)\n", ret);
309 return ret;
310 }
311
312 ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0,
313 MAKE_NAME(-rx), mps_port);
314 if (ret) {
315 dev_err(port->dev, "failed to register rxirq (%d)\n", ret);
316 goto err_free_oerrirq;
317 }
318
319 ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0,
320 MAKE_NAME(-tx), mps_port);
321 if (ret) {
322 dev_err(port->dev, "failed to register txirq (%d)\n", ret);
323 goto err_free_rxirq;
324 }
325
326 }
327
328 control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP;
329
330 mps2_uart_write8(port, control, UARTn_CTRL);
331
332 return 0;
333
334err_free_rxirq:
335 free_irq(mps_port->rx_irq, mps_port);
336err_free_oerrirq:
337 free_irq(port->irq, mps_port);
338
339 return ret;
340}
341
342static void mps2_uart_shutdown(struct uart_port *port)
343{
344 struct mps2_uart_port *mps_port = to_mps2_port(port);
345 u8 control = mps2_uart_read8(port, UARTn_CTRL);
346
347 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
348
349 mps2_uart_write8(port, control, UARTn_CTRL);
350
351 if (!(mps_port->flags & UART_PORT_COMBINED_IRQ)) {
352 free_irq(mps_port->rx_irq, mps_port);
353 free_irq(mps_port->tx_irq, mps_port);
354 }
355
356 free_irq(port->irq, mps_port);
357}
358
359static void
360mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios,
361 struct ktermios *old)
362{
363 unsigned long flags;
364 unsigned int baud, bauddiv;
365
366 termios->c_cflag &= ~(CRTSCTS | CMSPAR);
367 termios->c_cflag &= ~CSIZE;
368 termios->c_cflag |= CS8;
369 termios->c_cflag &= ~PARENB;
370 termios->c_cflag &= ~CSTOPB;
371
372 baud = uart_get_baud_rate(port, termios, old,
373 DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK),
374 DIV_ROUND_CLOSEST(port->uartclk, 16));
375
376 bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
377
378 spin_lock_irqsave(&port->lock, flags);
379
380 uart_update_timeout(port, termios->c_cflag, baud);
381 mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV);
382
383 spin_unlock_irqrestore(&port->lock, flags);
384
385 if (tty_termios_baud_rate(termios))
386 tty_termios_encode_baud_rate(termios, baud, baud);
387}
388
389static const char *mps2_uart_type(struct uart_port *port)
390{
391 return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL;
392}
393
394static void mps2_uart_release_port(struct uart_port *port)
395{
396}
397
398static int mps2_uart_request_port(struct uart_port *port)
399{
400 return 0;
401}
402
403static void mps2_uart_config_port(struct uart_port *port, int type)
404{
405 if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port))
406 port->type = PORT_MPS2UART;
407}
408
409static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo)
410{
411 return -EINVAL;
412}
413
414static const struct uart_ops mps2_uart_pops = {
415 .tx_empty = mps2_uart_tx_empty,
416 .set_mctrl = mps2_uart_set_mctrl,
417 .get_mctrl = mps2_uart_get_mctrl,
418 .stop_tx = mps2_uart_stop_tx,
419 .start_tx = mps2_uart_start_tx,
420 .stop_rx = mps2_uart_stop_rx,
421 .break_ctl = mps2_uart_break_ctl,
422 .startup = mps2_uart_startup,
423 .shutdown = mps2_uart_shutdown,
424 .set_termios = mps2_uart_set_termios,
425 .type = mps2_uart_type,
426 .release_port = mps2_uart_release_port,
427 .request_port = mps2_uart_request_port,
428 .config_port = mps2_uart_config_port,
429 .verify_port = mps2_uart_verify_port,
430};
431
432static DEFINE_IDR(ports_idr);
433
434#ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE
435static void mps2_uart_console_putchar(struct uart_port *port, int ch)
436{
437 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)
438 cpu_relax();
439
440 mps2_uart_write8(port, ch, UARTn_DATA);
441}
442
443static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt)
444{
445 struct mps2_uart_port *mps_port = idr_find(&ports_idr, co->index);
446 struct uart_port *port = &mps_port->port;
447
448 uart_console_write(port, s, cnt, mps2_uart_console_putchar);
449}
450
451static int mps2_uart_console_setup(struct console *co, char *options)
452{
453 struct mps2_uart_port *mps_port;
454 int baud = 9600;
455 int bits = 8;
456 int parity = 'n';
457 int flow = 'n';
458
459 if (co->index < 0 || co->index >= MPS2_MAX_PORTS)
460 return -ENODEV;
461
462 mps_port = idr_find(&ports_idr, co->index);
463
464 if (!mps_port)
465 return -ENODEV;
466
467 if (options)
468 uart_parse_options(options, &baud, &parity, &bits, &flow);
469
470 return uart_set_options(&mps_port->port, co, baud, parity, bits, flow);
471}
472
473static struct uart_driver mps2_uart_driver;
474
475static struct console mps2_uart_console = {
476 .name = SERIAL_NAME,
477 .device = uart_console_device,
478 .write = mps2_uart_console_write,
479 .setup = mps2_uart_console_setup,
480 .flags = CON_PRINTBUFFER,
481 .index = -1,
482 .data = &mps2_uart_driver,
483};
484
485#define MPS2_SERIAL_CONSOLE (&mps2_uart_console)
486
487static void mps2_early_putchar(struct uart_port *port, int ch)
488{
489 while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL)
490 cpu_relax();
491
492 writeb((unsigned char)ch, port->membase + UARTn_DATA);
493}
494
495static void mps2_early_write(struct console *con, const char *s, unsigned int n)
496{
497 struct earlycon_device *dev = con->data;
498
499 uart_console_write(&dev->port, s, n, mps2_early_putchar);
500}
501
502static int __init mps2_early_console_setup(struct earlycon_device *device,
503 const char *opt)
504{
505 if (!device->port.membase)
506 return -ENODEV;
507
508 device->con->write = mps2_early_write;
509
510 return 0;
511}
512
513OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup);
514
515#else
516#define MPS2_SERIAL_CONSOLE NULL
517#endif
518
519static struct uart_driver mps2_uart_driver = {
520 .driver_name = DRIVER_NAME,
521 .dev_name = SERIAL_NAME,
522 .nr = MPS2_MAX_PORTS,
523 .cons = MPS2_SERIAL_CONSOLE,
524};
525
526static int mps2_of_get_port(struct platform_device *pdev,
527 struct mps2_uart_port *mps_port)
528{
529 struct device_node *np = pdev->dev.of_node;
530 int id;
531
532 if (!np)
533 return -ENODEV;
534
535 id = of_alias_get_id(np, "serial");
536
537 if (id < 0)
538 id = idr_alloc_cyclic(&ports_idr, (void *)mps_port, 0, MPS2_MAX_PORTS, GFP_KERNEL);
539 else
540 id = idr_alloc(&ports_idr, (void *)mps_port, id, MPS2_MAX_PORTS, GFP_KERNEL);
541
542 if (id < 0)
543 return id;
544
545 /* Only combined irq is presesnt */
546 if (platform_irq_count(pdev) == 1)
547 mps_port->flags |= UART_PORT_COMBINED_IRQ;
548
549 mps_port->port.line = id;
550
551 return 0;
552}
553
554static int mps2_init_port(struct platform_device *pdev,
555 struct mps2_uart_port *mps_port)
556{
557 struct resource *res;
558 int ret;
559
560 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
561 mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res);
562 if (IS_ERR(mps_port->port.membase))
563 return PTR_ERR(mps_port->port.membase);
564
565 mps_port->port.mapbase = res->start;
566 mps_port->port.mapsize = resource_size(res);
567 mps_port->port.iotype = UPIO_MEM;
568 mps_port->port.flags = UPF_BOOT_AUTOCONF;
569 mps_port->port.fifosize = 1;
570 mps_port->port.ops = &mps2_uart_pops;
571 mps_port->port.dev = &pdev->dev;
572
573 mps_port->clk = devm_clk_get(&pdev->dev, NULL);
574 if (IS_ERR(mps_port->clk))
575 return PTR_ERR(mps_port->clk);
576
577 ret = clk_prepare_enable(mps_port->clk);
578 if (ret)
579 return ret;
580
581 mps_port->port.uartclk = clk_get_rate(mps_port->clk);
582
583 clk_disable_unprepare(mps_port->clk);
584
585
586 if (mps_port->flags & UART_PORT_COMBINED_IRQ) {
587 mps_port->port.irq = platform_get_irq(pdev, 0);
588 } else {
589 mps_port->rx_irq = platform_get_irq(pdev, 0);
590 mps_port->tx_irq = platform_get_irq(pdev, 1);
591 mps_port->port.irq = platform_get_irq(pdev, 2);
592 }
593
594 return ret;
595}
596
597static int mps2_serial_probe(struct platform_device *pdev)
598{
599 struct mps2_uart_port *mps_port;
600 int ret;
601
602 mps_port = devm_kzalloc(&pdev->dev, sizeof(struct mps2_uart_port), GFP_KERNEL);
603
604 if (!mps_port)
605 return -ENOMEM;
606
607 ret = mps2_of_get_port(pdev, mps_port);
608 if (ret)
609 return ret;
610
611 ret = mps2_init_port(pdev, mps_port);
612 if (ret)
613 return ret;
614
615 ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port);
616 if (ret)
617 return ret;
618
619 platform_set_drvdata(pdev, mps_port);
620
621 return 0;
622}
623
624#ifdef CONFIG_OF
625static const struct of_device_id mps2_match[] = {
626 { .compatible = "arm,mps2-uart", },
627 {},
628};
629#endif
630
631static struct platform_driver mps2_serial_driver = {
632 .probe = mps2_serial_probe,
633
634 .driver = {
635 .name = DRIVER_NAME,
636 .of_match_table = of_match_ptr(mps2_match),
637 .suppress_bind_attrs = true,
638 },
639};
640
641static int __init mps2_uart_init(void)
642{
643 int ret;
644
645 ret = uart_register_driver(&mps2_uart_driver);
646 if (ret)
647 return ret;
648
649 ret = platform_driver_register(&mps2_serial_driver);
650 if (ret)
651 uart_unregister_driver(&mps2_uart_driver);
652
653 return ret;
654}
655arch_initcall(mps2_uart_init);