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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#include "i40e.h"
5#include <linux/ptp_classify.h>
6
7/* The XL710 timesync is very much like Intel's 82599 design when it comes to
8 * the fundamental clock design. However, the clock operations are much simpler
9 * in the XL710 because the device supports a full 64 bits of nanoseconds.
10 * Because the field is so wide, we can forgo the cycle counter and just
11 * operate with the nanosecond field directly without fear of overflow.
12 *
13 * Much like the 82599, the update period is dependent upon the link speed:
14 * At 40Gb link or no link, the period is 1.6ns.
15 * At 10Gb link, the period is multiplied by 2. (3.2ns)
16 * At 1Gb link, the period is multiplied by 20. (32ns)
17 * 1588 functionality is not supported at 100Mbps.
18 */
19#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
20#define I40E_PTP_10GB_INCVAL_MULT 2
21#define I40E_PTP_1GB_INCVAL_MULT 20
22
23#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
24#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \
25 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
26
27/**
28 * i40e_ptp_read - Read the PHC time from the device
29 * @pf: Board private structure
30 * @ts: timespec structure to hold the current time value
31 * @sts: structure to hold the system time before and after reading the PHC
32 *
33 * This function reads the PRTTSYN_TIME registers and stores them in a
34 * timespec. However, since the registers are 64 bits of nanoseconds, we must
35 * convert the result to a timespec before we can return.
36 **/
37static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts,
38 struct ptp_system_timestamp *sts)
39{
40 struct i40e_hw *hw = &pf->hw;
41 u32 hi, lo;
42 u64 ns;
43
44 /* The timer latches on the lowest register read. */
45 ptp_read_system_prets(sts);
46 lo = rd32(hw, I40E_PRTTSYN_TIME_L);
47 ptp_read_system_postts(sts);
48 hi = rd32(hw, I40E_PRTTSYN_TIME_H);
49
50 ns = (((u64)hi) << 32) | lo;
51
52 *ts = ns_to_timespec64(ns);
53}
54
55/**
56 * i40e_ptp_write - Write the PHC time to the device
57 * @pf: Board private structure
58 * @ts: timespec structure that holds the new time value
59 *
60 * This function writes the PRTTSYN_TIME registers with the user value. Since
61 * we receive a timespec from the stack, we must convert that timespec into
62 * nanoseconds before programming the registers.
63 **/
64static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts)
65{
66 struct i40e_hw *hw = &pf->hw;
67 u64 ns = timespec64_to_ns(ts);
68
69 /* The timer will not update until the high register is written, so
70 * write the low register first.
71 */
72 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
73 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
74}
75
76/**
77 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
78 * @hwtstamps: Timestamp structure to update
79 * @timestamp: Timestamp from the hardware
80 *
81 * We need to convert the NIC clock value into a hwtstamp which can be used by
82 * the upper level timestamping functions. Since the timestamp is simply a 64-
83 * bit nanosecond value, we can call ns_to_ktime directly to handle this.
84 **/
85static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
86 u64 timestamp)
87{
88 memset(hwtstamps, 0, sizeof(*hwtstamps));
89
90 hwtstamps->hwtstamp = ns_to_ktime(timestamp);
91}
92
93/**
94 * i40e_ptp_adjfreq - Adjust the PHC frequency
95 * @ptp: The PTP clock structure
96 * @ppb: Parts per billion adjustment from the base
97 *
98 * Adjust the frequency of the PHC by the indicated parts per billion from the
99 * base frequency.
100 **/
101static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
102{
103 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
104 struct i40e_hw *hw = &pf->hw;
105 u64 adj, freq, diff;
106 int neg_adj = 0;
107
108 if (ppb < 0) {
109 neg_adj = 1;
110 ppb = -ppb;
111 }
112
113 freq = I40E_PTP_40GB_INCVAL;
114 freq *= ppb;
115 diff = div_u64(freq, 1000000000ULL);
116
117 if (neg_adj)
118 adj = I40E_PTP_40GB_INCVAL - diff;
119 else
120 adj = I40E_PTP_40GB_INCVAL + diff;
121
122 /* At some link speeds, the base incval is so large that directly
123 * multiplying by ppb would result in arithmetic overflow even when
124 * using a u64. Avoid this by instead calculating the new incval
125 * always in terms of the 40GbE clock rate and then multiplying by the
126 * link speed factor afterwards. This does result in slightly lower
127 * precision at lower link speeds, but it is fairly minor.
128 */
129 smp_mb(); /* Force any pending update before accessing. */
130 adj *= READ_ONCE(pf->ptp_adj_mult);
131
132 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
133 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
134
135 return 0;
136}
137
138/**
139 * i40e_ptp_adjtime - Adjust the PHC time
140 * @ptp: The PTP clock structure
141 * @delta: Offset in nanoseconds to adjust the PHC time by
142 *
143 * Adjust the current clock time by a delta specified in nanoseconds.
144 **/
145static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
146{
147 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
148 struct timespec64 now, then;
149
150 then = ns_to_timespec64(delta);
151 mutex_lock(&pf->tmreg_lock);
152
153 i40e_ptp_read(pf, &now, NULL);
154 now = timespec64_add(now, then);
155 i40e_ptp_write(pf, (const struct timespec64 *)&now);
156
157 mutex_unlock(&pf->tmreg_lock);
158
159 return 0;
160}
161
162/**
163 * i40e_ptp_gettimex - Get the time of the PHC
164 * @ptp: The PTP clock structure
165 * @ts: timespec structure to hold the current time value
166 * @sts: structure to hold the system time before and after reading the PHC
167 *
168 * Read the device clock and return the correct value on ns, after converting it
169 * into a timespec struct.
170 **/
171static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
172 struct ptp_system_timestamp *sts)
173{
174 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
175
176 mutex_lock(&pf->tmreg_lock);
177 i40e_ptp_read(pf, ts, sts);
178 mutex_unlock(&pf->tmreg_lock);
179
180 return 0;
181}
182
183/**
184 * i40e_ptp_settime - Set the time of the PHC
185 * @ptp: The PTP clock structure
186 * @ts: timespec structure that holds the new time value
187 *
188 * Set the device clock to the user input value. The conversion from timespec
189 * to ns happens in the write function.
190 **/
191static int i40e_ptp_settime(struct ptp_clock_info *ptp,
192 const struct timespec64 *ts)
193{
194 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
195
196 mutex_lock(&pf->tmreg_lock);
197 i40e_ptp_write(pf, ts);
198 mutex_unlock(&pf->tmreg_lock);
199
200 return 0;
201}
202
203/**
204 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem
205 * @ptp: The PTP clock structure
206 * @rq: The requested feature to change
207 * @on: Enable/disable flag
208 *
209 * The XL710 does not support any of the ancillary features of the PHC
210 * subsystem, so this function may just return.
211 **/
212static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp,
213 struct ptp_clock_request *rq, int on)
214{
215 return -EOPNOTSUPP;
216}
217
218/**
219 * i40e_ptp_update_latch_events - Read I40E_PRTTSYN_STAT_1 and latch events
220 * @pf: the PF data structure
221 *
222 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers
223 * for noticed latch events. This allows the driver to keep track of the first
224 * time a latch event was noticed which will be used to help clear out Rx
225 * timestamps for packets that got dropped or lost.
226 *
227 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is
228 * expected to be called only while under the ptp_rx_lock.
229 **/
230static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf)
231{
232 struct i40e_hw *hw = &pf->hw;
233 u32 prttsyn_stat, new_latch_events;
234 int i;
235
236 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
237 new_latch_events = prttsyn_stat & ~pf->latch_event_flags;
238
239 /* Update the jiffies time for any newly latched timestamp. This
240 * ensures that we store the time that we first discovered a timestamp
241 * was latched by the hardware. The service task will later determine
242 * if we should free the latch and drop that timestamp should too much
243 * time pass. This flow ensures that we only update jiffies for new
244 * events latched since the last time we checked, and not all events
245 * currently latched, so that the service task accounting remains
246 * accurate.
247 */
248 for (i = 0; i < 4; i++) {
249 if (new_latch_events & BIT(i))
250 pf->latch_events[i] = jiffies;
251 }
252
253 /* Finally, we store the current status of the Rx timestamp latches */
254 pf->latch_event_flags = prttsyn_stat;
255
256 return prttsyn_stat;
257}
258
259/**
260 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
261 * @pf: The PF private data structure
262 * @vsi: The VSI with the rings relevant to 1588
263 *
264 * This watchdog task is scheduled to detect error case where hardware has
265 * dropped an Rx packet that was timestamped when the ring is full. The
266 * particular error is rare but leaves the device in a state unable to timestamp
267 * any future packets.
268 **/
269void i40e_ptp_rx_hang(struct i40e_pf *pf)
270{
271 struct i40e_hw *hw = &pf->hw;
272 unsigned int i, cleared = 0;
273
274 /* Since we cannot turn off the Rx timestamp logic if the device is
275 * configured for Tx timestamping, we check if Rx timestamping is
276 * configured. We don't want to spuriously warn about Rx timestamp
277 * hangs if we don't care about the timestamps.
278 */
279 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
280 return;
281
282 spin_lock_bh(&pf->ptp_rx_lock);
283
284 /* Update current latch times for Rx events */
285 i40e_ptp_get_rx_events(pf);
286
287 /* Check all the currently latched Rx events and see whether they have
288 * been latched for over a second. It is assumed that any timestamp
289 * should have been cleared within this time, or else it was captured
290 * for a dropped frame that the driver never received. Thus, we will
291 * clear any timestamp that has been latched for over 1 second.
292 */
293 for (i = 0; i < 4; i++) {
294 if ((pf->latch_event_flags & BIT(i)) &&
295 time_is_before_jiffies(pf->latch_events[i] + HZ)) {
296 rd32(hw, I40E_PRTTSYN_RXTIME_H(i));
297 pf->latch_event_flags &= ~BIT(i);
298 cleared++;
299 }
300 }
301
302 spin_unlock_bh(&pf->ptp_rx_lock);
303
304 /* Log a warning if more than 2 timestamps got dropped in the same
305 * check. We don't want to warn about all drops because it can occur
306 * in normal scenarios such as PTP frames on multicast addresses we
307 * aren't listening to. However, administrator should know if this is
308 * the reason packets aren't receiving timestamps.
309 */
310 if (cleared > 2)
311 dev_dbg(&pf->pdev->dev,
312 "Dropped %d missed RXTIME timestamp events\n",
313 cleared);
314
315 /* Finally, update the rx_hwtstamp_cleared counter */
316 pf->rx_hwtstamp_cleared += cleared;
317}
318
319/**
320 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung
321 * @pf: The PF private data structure
322 *
323 * This watchdog task is run periodically to make sure that we clear the Tx
324 * timestamp logic if we don't obtain a timestamp in a reasonable amount of
325 * time. It is unexpected in the normal case but if it occurs it results in
326 * permanently preventing timestamps of future packets.
327 **/
328void i40e_ptp_tx_hang(struct i40e_pf *pf)
329{
330 struct sk_buff *skb;
331
332 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
333 return;
334
335 /* Nothing to do if we're not already waiting for a timestamp */
336 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state))
337 return;
338
339 /* We already have a handler routine which is run when we are notified
340 * of a Tx timestamp in the hardware. If we don't get an interrupt
341 * within a second it is reasonable to assume that we never will.
342 */
343 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) {
344 skb = pf->ptp_tx_skb;
345 pf->ptp_tx_skb = NULL;
346 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
347
348 /* Free the skb after we clear the bitlock */
349 dev_kfree_skb_any(skb);
350 pf->tx_hwtstamp_timeouts++;
351 }
352}
353
354/**
355 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
356 * @pf: Board private structure
357 *
358 * Read the value of the Tx timestamp from the registers, convert it into a
359 * value consumable by the stack, and store that result into the shhwtstamps
360 * struct before returning it up the stack.
361 **/
362void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
363{
364 struct skb_shared_hwtstamps shhwtstamps;
365 struct sk_buff *skb = pf->ptp_tx_skb;
366 struct i40e_hw *hw = &pf->hw;
367 u32 hi, lo;
368 u64 ns;
369
370 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
371 return;
372
373 /* don't attempt to timestamp if we don't have an skb */
374 if (!pf->ptp_tx_skb)
375 return;
376
377 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
378 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
379
380 ns = (((u64)hi) << 32) | lo;
381 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
382
383 /* Clear the bit lock as soon as possible after reading the register,
384 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise
385 * applications might wake up and attempt to request another transmit
386 * timestamp prior to the bit lock being cleared.
387 */
388 pf->ptp_tx_skb = NULL;
389 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
390
391 /* Notify the stack and free the skb after we've unlocked */
392 skb_tstamp_tx(skb, &shhwtstamps);
393 dev_kfree_skb_any(skb);
394}
395
396/**
397 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
398 * @pf: Board private structure
399 * @skb: Particular skb to send timestamp with
400 * @index: Index into the receive timestamp registers for the timestamp
401 *
402 * The XL710 receives a notification in the receive descriptor with an offset
403 * into the set of RXTIME registers where the timestamp is for that skb. This
404 * function goes and fetches the receive timestamp from that offset, if a valid
405 * one exists. The RXTIME registers are in ns, so we must convert the result
406 * first.
407 **/
408void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
409{
410 u32 prttsyn_stat, hi, lo;
411 struct i40e_hw *hw;
412 u64 ns;
413
414 /* Since we cannot turn off the Rx timestamp logic if the device is
415 * doing Tx timestamping, check if Rx timestamping is configured.
416 */
417 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
418 return;
419
420 hw = &pf->hw;
421
422 spin_lock_bh(&pf->ptp_rx_lock);
423
424 /* Get current Rx events and update latch times */
425 prttsyn_stat = i40e_ptp_get_rx_events(pf);
426
427 /* TODO: Should we warn about missing Rx timestamp event? */
428 if (!(prttsyn_stat & BIT(index))) {
429 spin_unlock_bh(&pf->ptp_rx_lock);
430 return;
431 }
432
433 /* Clear the latched event since we're about to read its register */
434 pf->latch_event_flags &= ~BIT(index);
435
436 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
437 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
438
439 spin_unlock_bh(&pf->ptp_rx_lock);
440
441 ns = (((u64)hi) << 32) | lo;
442
443 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
444}
445
446/**
447 * i40e_ptp_set_increment - Utility function to update clock increment rate
448 * @pf: Board private structure
449 *
450 * During a link change, the DMA frequency that drives the 1588 logic will
451 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
452 * we must update the increment value per clock tick.
453 **/
454void i40e_ptp_set_increment(struct i40e_pf *pf)
455{
456 struct i40e_link_status *hw_link_info;
457 struct i40e_hw *hw = &pf->hw;
458 u64 incval;
459 u32 mult;
460
461 hw_link_info = &hw->phy.link_info;
462
463 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
464
465 switch (hw_link_info->link_speed) {
466 case I40E_LINK_SPEED_10GB:
467 mult = I40E_PTP_10GB_INCVAL_MULT;
468 break;
469 case I40E_LINK_SPEED_1GB:
470 mult = I40E_PTP_1GB_INCVAL_MULT;
471 break;
472 case I40E_LINK_SPEED_100MB:
473 {
474 static int warn_once;
475
476 if (!warn_once) {
477 dev_warn(&pf->pdev->dev,
478 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n");
479 warn_once++;
480 }
481 mult = 0;
482 break;
483 }
484 case I40E_LINK_SPEED_40GB:
485 default:
486 mult = 1;
487 break;
488 }
489
490 /* The increment value is calculated by taking the base 40GbE incvalue
491 * and multiplying it by a factor based on the link speed.
492 */
493 incval = I40E_PTP_40GB_INCVAL * mult;
494
495 /* Write the new increment value into the increment register. The
496 * hardware will not update the clock until both registers have been
497 * written.
498 */
499 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
500 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
501
502 /* Update the base adjustement value. */
503 WRITE_ONCE(pf->ptp_adj_mult, mult);
504 smp_mb(); /* Force the above update. */
505}
506
507/**
508 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
509 * @pf: Board private structure
510 * @ifr: ioctl data
511 *
512 * Obtain the current hardware timestamping settigs as requested. To do this,
513 * keep a shadow copy of the timestamp settings rather than attempting to
514 * deconstruct it from the registers.
515 **/
516int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
517{
518 struct hwtstamp_config *config = &pf->tstamp_config;
519
520 if (!(pf->flags & I40E_FLAG_PTP))
521 return -EOPNOTSUPP;
522
523 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
524 -EFAULT : 0;
525}
526
527/**
528 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode
529 * @pf: Board private structure
530 * @config: hwtstamp settings requested or saved
531 *
532 * Control hardware registers to enter the specific mode requested by the
533 * user. Also used during reset path to ensure that timestamp settings are
534 * maintained.
535 *
536 * Note: modifies config in place, and may update the requested mode to be
537 * more broad if the specific filter is not directly supported.
538 **/
539static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
540 struct hwtstamp_config *config)
541{
542 struct i40e_hw *hw = &pf->hw;
543 u32 tsyntype, regval;
544
545 /* Reserved for future extensions. */
546 if (config->flags)
547 return -EINVAL;
548
549 switch (config->tx_type) {
550 case HWTSTAMP_TX_OFF:
551 pf->ptp_tx = false;
552 break;
553 case HWTSTAMP_TX_ON:
554 pf->ptp_tx = true;
555 break;
556 default:
557 return -ERANGE;
558 }
559
560 switch (config->rx_filter) {
561 case HWTSTAMP_FILTER_NONE:
562 pf->ptp_rx = false;
563 /* We set the type to V1, but do not enable UDP packet
564 * recognition. In this way, we should be as close to
565 * disabling PTP Rx timestamps as possible since V1 packets
566 * are always UDP, since L2 packets are a V2 feature.
567 */
568 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1;
569 break;
570 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
571 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
572 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
573 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
574 return -ERANGE;
575 pf->ptp_rx = true;
576 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
577 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
578 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
579 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
580 break;
581 case HWTSTAMP_FILTER_PTP_V2_EVENT:
582 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
583 case HWTSTAMP_FILTER_PTP_V2_SYNC:
584 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
585 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
586 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
587 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
588 return -ERANGE;
589 /* fall through */
590 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
591 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
592 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
593 pf->ptp_rx = true;
594 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
595 I40E_PRTTSYN_CTL1_TSYNTYPE_V2;
596 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) {
597 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
598 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
599 } else {
600 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
601 }
602 break;
603 case HWTSTAMP_FILTER_NTP_ALL:
604 case HWTSTAMP_FILTER_ALL:
605 default:
606 return -ERANGE;
607 }
608
609 /* Clear out all 1588-related registers to clear and unlatch them. */
610 spin_lock_bh(&pf->ptp_rx_lock);
611 rd32(hw, I40E_PRTTSYN_STAT_0);
612 rd32(hw, I40E_PRTTSYN_TXTIME_H);
613 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
614 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
615 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
616 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
617 pf->latch_event_flags = 0;
618 spin_unlock_bh(&pf->ptp_rx_lock);
619
620 /* Enable/disable the Tx timestamp interrupt based on user input. */
621 regval = rd32(hw, I40E_PRTTSYN_CTL0);
622 if (pf->ptp_tx)
623 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
624 else
625 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
626 wr32(hw, I40E_PRTTSYN_CTL0, regval);
627
628 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
629 if (pf->ptp_tx)
630 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
631 else
632 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
633 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
634
635 /* Although there is no simple on/off switch for Rx, we "disable" Rx
636 * timestamps by setting to V1 only mode and clear the UDP
637 * recognition. This ought to disable all PTP Rx timestamps as V1
638 * packets are always over UDP. Note that software is configured to
639 * ignore Rx timestamps via the pf->ptp_rx flag.
640 */
641 regval = rd32(hw, I40E_PRTTSYN_CTL1);
642 /* clear everything but the enable bit */
643 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
644 /* now enable bits for desired Rx timestamps */
645 regval |= tsyntype;
646 wr32(hw, I40E_PRTTSYN_CTL1, regval);
647
648 return 0;
649}
650
651/**
652 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
653 * @pf: Board private structure
654 * @ifr: ioctl data
655 *
656 * Respond to the user filter requests and make the appropriate hardware
657 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
658 * logic, so keep track in software of whether to indicate these timestamps
659 * or not.
660 *
661 * It is permissible to "upgrade" the user request to a broader filter, as long
662 * as the user receives the timestamps they care about and the user is notified
663 * the filter has been broadened.
664 **/
665int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
666{
667 struct hwtstamp_config config;
668 int err;
669
670 if (!(pf->flags & I40E_FLAG_PTP))
671 return -EOPNOTSUPP;
672
673 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
674 return -EFAULT;
675
676 err = i40e_ptp_set_timestamp_mode(pf, &config);
677 if (err)
678 return err;
679
680 /* save these settings for future reference */
681 pf->tstamp_config = config;
682
683 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
684 -EFAULT : 0;
685}
686
687/**
688 * i40e_ptp_create_clock - Create PTP clock device for userspace
689 * @pf: Board private structure
690 *
691 * This function creates a new PTP clock device. It only creates one if we
692 * don't already have one, so it is safe to call. Will return error if it
693 * can't create one, but success if we already have a device. Should be used
694 * by i40e_ptp_init to create clock initially, and prevent global resets from
695 * creating new clock devices.
696 **/
697static long i40e_ptp_create_clock(struct i40e_pf *pf)
698{
699 /* no need to create a clock device if we already have one */
700 if (!IS_ERR_OR_NULL(pf->ptp_clock))
701 return 0;
702
703 strlcpy(pf->ptp_caps.name, i40e_driver_name,
704 sizeof(pf->ptp_caps.name) - 1);
705 pf->ptp_caps.owner = THIS_MODULE;
706 pf->ptp_caps.max_adj = 999999999;
707 pf->ptp_caps.n_ext_ts = 0;
708 pf->ptp_caps.pps = 0;
709 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
710 pf->ptp_caps.adjtime = i40e_ptp_adjtime;
711 pf->ptp_caps.gettimex64 = i40e_ptp_gettimex;
712 pf->ptp_caps.settime64 = i40e_ptp_settime;
713 pf->ptp_caps.enable = i40e_ptp_feature_enable;
714
715 /* Attempt to register the clock before enabling the hardware. */
716 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
717 if (IS_ERR(pf->ptp_clock))
718 return PTR_ERR(pf->ptp_clock);
719
720 /* clear the hwtstamp settings here during clock create, instead of
721 * during regular init, so that we can maintain settings across a
722 * reset or suspend.
723 */
724 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
725 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
726
727 /* Set the previous "reset" time to the current Kernel clock time */
728 ktime_get_real_ts64(&pf->ptp_prev_hw_time);
729 pf->ptp_reset_start = ktime_get();
730
731 return 0;
732}
733
734/**
735 * i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time
736 * @pf: Board private structure
737 *
738 * Read the current PTP time and save it into pf->ptp_prev_hw_time. This should
739 * be called at the end of preparing to reset, just before hardware reset
740 * occurs, in order to preserve the PTP time as close as possible across
741 * resets.
742 */
743void i40e_ptp_save_hw_time(struct i40e_pf *pf)
744{
745 /* don't try to access the PTP clock if it's not enabled */
746 if (!(pf->flags & I40E_FLAG_PTP))
747 return;
748
749 i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL);
750 /* Get a monotonic starting time for this reset */
751 pf->ptp_reset_start = ktime_get();
752}
753
754/**
755 * i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs
756 * @pf: Board private structure
757 *
758 * Restore the PTP hardware clock registers. We previously cached the PTP
759 * hardware time as pf->ptp_prev_hw_time. To be as accurate as possible,
760 * update this value based on the time delta since the time was saved, using
761 * CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference.
762 *
763 * This ensures that the hardware clock is restored to nearly what it should
764 * have been if a reset had not occurred.
765 */
766void i40e_ptp_restore_hw_time(struct i40e_pf *pf)
767{
768 ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start);
769
770 /* Update the previous HW time with the ktime delta */
771 timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta));
772
773 /* Restore the hardware clock registers */
774 i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time);
775}
776
777/**
778 * i40e_ptp_init - Initialize the 1588 support after device probe or reset
779 * @pf: Board private structure
780 *
781 * This function sets device up for 1588 support. The first time it is run, it
782 * will create a PHC clock device. It does not create a clock device if one
783 * already exists. It also reconfigures the device after a reset.
784 *
785 * The first time a clock is created, i40e_ptp_create_clock will set
786 * pf->ptp_prev_hw_time to the current system time. During resets, it is
787 * expected that this timespec will be set to the last known PTP clock time,
788 * in order to preserve the clock time as close as possible across a reset.
789 **/
790void i40e_ptp_init(struct i40e_pf *pf)
791{
792 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
793 struct i40e_hw *hw = &pf->hw;
794 u32 pf_id;
795 long err;
796
797 /* Only one PF is assigned to control 1588 logic per port. Do not
798 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID
799 */
800 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
801 I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
802 if (hw->pf_id != pf_id) {
803 pf->flags &= ~I40E_FLAG_PTP;
804 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",
805 __func__,
806 netdev->name);
807 return;
808 }
809
810 mutex_init(&pf->tmreg_lock);
811 spin_lock_init(&pf->ptp_rx_lock);
812
813 /* ensure we have a clock device */
814 err = i40e_ptp_create_clock(pf);
815 if (err) {
816 pf->ptp_clock = NULL;
817 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
818 __func__);
819 } else if (pf->ptp_clock) {
820 u32 regval;
821
822 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
823 dev_info(&pf->pdev->dev, "PHC enabled\n");
824 pf->flags |= I40E_FLAG_PTP;
825
826 /* Ensure the clocks are running. */
827 regval = rd32(hw, I40E_PRTTSYN_CTL0);
828 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
829 wr32(hw, I40E_PRTTSYN_CTL0, regval);
830 regval = rd32(hw, I40E_PRTTSYN_CTL1);
831 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
832 wr32(hw, I40E_PRTTSYN_CTL1, regval);
833
834 /* Set the increment value per clock tick. */
835 i40e_ptp_set_increment(pf);
836
837 /* reset timestamping mode */
838 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config);
839
840 /* Restore the clock time based on last known value */
841 i40e_ptp_restore_hw_time(pf);
842 }
843}
844
845/**
846 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
847 * @pf: Board private structure
848 *
849 * This function handles the cleanup work required from the initialization by
850 * clearing out the important information and unregistering the PHC.
851 **/
852void i40e_ptp_stop(struct i40e_pf *pf)
853{
854 pf->flags &= ~I40E_FLAG_PTP;
855 pf->ptp_tx = false;
856 pf->ptp_rx = false;
857
858 if (pf->ptp_tx_skb) {
859 struct sk_buff *skb = pf->ptp_tx_skb;
860
861 pf->ptp_tx_skb = NULL;
862 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
863 dev_kfree_skb_any(skb);
864 }
865
866 if (pf->ptp_clock) {
867 ptp_clock_unregister(pf->ptp_clock);
868 pf->ptp_clock = NULL;
869 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
870 pf->vsi[pf->lan_vsi]->netdev->name);
871 }
872}
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e.h"
28#include <linux/export.h>
29#include <linux/ptp_classify.h>
30
31/* The XL710 timesync is very much like Intel's 82599 design when it comes to
32 * the fundamental clock design. However, the clock operations are much simpler
33 * in the XL710 because the device supports a full 64 bits of nanoseconds.
34 * Because the field is so wide, we can forgo the cycle counter and just
35 * operate with the nanosecond field directly without fear of overflow.
36 *
37 * Much like the 82599, the update period is dependent upon the link speed:
38 * At 40Gb link or no link, the period is 1.6ns.
39 * At 10Gb link, the period is multiplied by 2. (3.2ns)
40 * At 1Gb link, the period is multiplied by 20. (32ns)
41 * 1588 functionality is not supported at 100Mbps.
42 */
43#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
44#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
45#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
46
47#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 (0x1 << \
48 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
49#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (0x2 << \
50 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
51#define I40E_PTP_TX_TIMEOUT (HZ * 15)
52
53/**
54 * i40e_ptp_read - Read the PHC time from the device
55 * @pf: Board private structure
56 * @ts: timespec structure to hold the current time value
57 *
58 * This function reads the PRTTSYN_TIME registers and stores them in a
59 * timespec. However, since the registers are 64 bits of nanoseconds, we must
60 * convert the result to a timespec before we can return.
61 **/
62static void i40e_ptp_read(struct i40e_pf *pf, struct timespec *ts)
63{
64 struct i40e_hw *hw = &pf->hw;
65 u32 hi, lo;
66 u64 ns;
67
68 /* The timer latches on the lowest register read. */
69 lo = rd32(hw, I40E_PRTTSYN_TIME_L);
70 hi = rd32(hw, I40E_PRTTSYN_TIME_H);
71
72 ns = (((u64)hi) << 32) | lo;
73
74 *ts = ns_to_timespec(ns);
75}
76
77/**
78 * i40e_ptp_write - Write the PHC time to the device
79 * @pf: Board private structure
80 * @ts: timespec structure that holds the new time value
81 *
82 * This function writes the PRTTSYN_TIME registers with the user value. Since
83 * we receive a timespec from the stack, we must convert that timespec into
84 * nanoseconds before programming the registers.
85 **/
86static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec *ts)
87{
88 struct i40e_hw *hw = &pf->hw;
89 u64 ns = timespec_to_ns(ts);
90
91 /* The timer will not update until the high register is written, so
92 * write the low register first.
93 */
94 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
95 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
96}
97
98/**
99 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
100 * @hwtstamps: Timestamp structure to update
101 * @timestamp: Timestamp from the hardware
102 *
103 * We need to convert the NIC clock value into a hwtstamp which can be used by
104 * the upper level timestamping functions. Since the timestamp is simply a 64-
105 * bit nanosecond value, we can call ns_to_ktime directly to handle this.
106 **/
107static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
108 u64 timestamp)
109{
110 memset(hwtstamps, 0, sizeof(*hwtstamps));
111
112 hwtstamps->hwtstamp = ns_to_ktime(timestamp);
113}
114
115/**
116 * i40e_ptp_adjfreq - Adjust the PHC frequency
117 * @ptp: The PTP clock structure
118 * @ppb: Parts per billion adjustment from the base
119 *
120 * Adjust the frequency of the PHC by the indicated parts per billion from the
121 * base frequency.
122 **/
123static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
124{
125 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
126 struct i40e_hw *hw = &pf->hw;
127 u64 adj, freq, diff;
128 int neg_adj = 0;
129
130 if (ppb < 0) {
131 neg_adj = 1;
132 ppb = -ppb;
133 }
134
135 smp_mb(); /* Force any pending update before accessing. */
136 adj = ACCESS_ONCE(pf->ptp_base_adj);
137
138 freq = adj;
139 freq *= ppb;
140 diff = div_u64(freq, 1000000000ULL);
141
142 if (neg_adj)
143 adj -= diff;
144 else
145 adj += diff;
146
147 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
148 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
149
150 return 0;
151}
152
153/**
154 * i40e_ptp_adjtime - Adjust the PHC time
155 * @ptp: The PTP clock structure
156 * @delta: Offset in nanoseconds to adjust the PHC time by
157 *
158 * Adjust the frequency of the PHC by the indicated parts per billion from the
159 * base frequency.
160 **/
161static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
162{
163 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
164 struct timespec now, then = ns_to_timespec(delta);
165 unsigned long flags;
166
167 spin_lock_irqsave(&pf->tmreg_lock, flags);
168
169 i40e_ptp_read(pf, &now);
170 now = timespec_add(now, then);
171 i40e_ptp_write(pf, (const struct timespec *)&now);
172
173 spin_unlock_irqrestore(&pf->tmreg_lock, flags);
174
175 return 0;
176}
177
178/**
179 * i40e_ptp_gettime - Get the time of the PHC
180 * @ptp: The PTP clock structure
181 * @ts: timespec structure to hold the current time value
182 *
183 * Read the device clock and return the correct value on ns, after converting it
184 * into a timespec struct.
185 **/
186static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
187{
188 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
189 unsigned long flags;
190
191 spin_lock_irqsave(&pf->tmreg_lock, flags);
192 i40e_ptp_read(pf, ts);
193 spin_unlock_irqrestore(&pf->tmreg_lock, flags);
194
195 return 0;
196}
197
198/**
199 * i40e_ptp_settime - Set the time of the PHC
200 * @ptp: The PTP clock structure
201 * @ts: timespec structure that holds the new time value
202 *
203 * Set the device clock to the user input value. The conversion from timespec
204 * to ns happens in the write function.
205 **/
206static int i40e_ptp_settime(struct ptp_clock_info *ptp,
207 const struct timespec *ts)
208{
209 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
210 unsigned long flags;
211
212 spin_lock_irqsave(&pf->tmreg_lock, flags);
213 i40e_ptp_write(pf, ts);
214 spin_unlock_irqrestore(&pf->tmreg_lock, flags);
215
216 return 0;
217}
218
219/**
220 * i40e_ptp_tx_work
221 * @work: pointer to work struct
222 *
223 * This work function polls the PRTTSYN_STAT_0.TXTIME bit to determine when a
224 * Tx timestamp event has occurred, in order to pass the Tx timestamp value up
225 * the stack in the skb.
226 */
227static void i40e_ptp_tx_work(struct work_struct *work)
228{
229 struct i40e_pf *pf = container_of(work, struct i40e_pf,
230 ptp_tx_work);
231 struct i40e_hw *hw = &pf->hw;
232 u32 prttsyn_stat_0;
233
234 if (!pf->ptp_tx_skb)
235 return;
236
237 if (time_is_before_jiffies(pf->ptp_tx_start +
238 I40E_PTP_TX_TIMEOUT)) {
239 dev_kfree_skb_any(pf->ptp_tx_skb);
240 pf->ptp_tx_skb = NULL;
241 pf->tx_hwtstamp_timeouts++;
242 dev_warn(&pf->pdev->dev, "clearing Tx timestamp hang\n");
243 return;
244 }
245
246 prttsyn_stat_0 = rd32(hw, I40E_PRTTSYN_STAT_0);
247 if (prttsyn_stat_0 & I40E_PRTTSYN_STAT_0_TXTIME_MASK)
248 i40e_ptp_tx_hwtstamp(pf);
249 else
250 schedule_work(&pf->ptp_tx_work);
251}
252
253/**
254 * i40e_ptp_enable - Enable/disable ancillary features of the PHC subsystem
255 * @ptp: The PTP clock structure
256 * @rq: The requested feature to change
257 * @on: Enable/disable flag
258 *
259 * The XL710 does not support any of the ancillary features of the PHC
260 * subsystem, so this function may just return.
261 **/
262static int i40e_ptp_enable(struct ptp_clock_info *ptp,
263 struct ptp_clock_request *rq, int on)
264{
265 return -EOPNOTSUPP;
266}
267
268/**
269 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
270 * @vsi: The VSI with the rings relevant to 1588
271 *
272 * This watchdog task is scheduled to detect error case where hardware has
273 * dropped an Rx packet that was timestamped when the ring is full. The
274 * particular error is rare but leaves the device in a state unable to timestamp
275 * any future packets.
276 **/
277void i40e_ptp_rx_hang(struct i40e_vsi *vsi)
278{
279 struct i40e_pf *pf = vsi->back;
280 struct i40e_hw *hw = &pf->hw;
281 struct i40e_ring *rx_ring;
282 unsigned long rx_event;
283 u32 prttsyn_stat;
284 int n;
285
286 if (pf->flags & I40E_FLAG_PTP)
287 return;
288
289 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
290
291 /* Unless all four receive timestamp registers are latched, we are not
292 * concerned about a possible PTP Rx hang, so just update the timeout
293 * counter and exit.
294 */
295 if (!(prttsyn_stat & ((I40E_PRTTSYN_STAT_1_RXT0_MASK <<
296 I40E_PRTTSYN_STAT_1_RXT0_SHIFT) |
297 (I40E_PRTTSYN_STAT_1_RXT1_MASK <<
298 I40E_PRTTSYN_STAT_1_RXT1_SHIFT) |
299 (I40E_PRTTSYN_STAT_1_RXT2_MASK <<
300 I40E_PRTTSYN_STAT_1_RXT2_SHIFT) |
301 (I40E_PRTTSYN_STAT_1_RXT3_MASK <<
302 I40E_PRTTSYN_STAT_1_RXT3_SHIFT)))) {
303 pf->last_rx_ptp_check = jiffies;
304 return;
305 }
306
307 /* Determine the most recent watchdog or rx_timestamp event. */
308 rx_event = pf->last_rx_ptp_check;
309 for (n = 0; n < vsi->num_queue_pairs; n++) {
310 rx_ring = vsi->rx_rings[n];
311 if (time_after(rx_ring->last_rx_timestamp, rx_event))
312 rx_event = rx_ring->last_rx_timestamp;
313 }
314
315 /* Only need to read the high RXSTMP register to clear the lock */
316 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
317 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
318 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
319 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
320 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
321 pf->last_rx_ptp_check = jiffies;
322 pf->rx_hwtstamp_cleared++;
323 dev_warn(&vsi->back->pdev->dev,
324 "%s: clearing Rx timestamp hang\n",
325 __func__);
326 }
327}
328
329/**
330 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
331 * @pf: Board private structure
332 *
333 * Read the value of the Tx timestamp from the registers, convert it into a
334 * value consumable by the stack, and store that result into the shhwtstamps
335 * struct before returning it up the stack.
336 **/
337void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
338{
339 struct skb_shared_hwtstamps shhwtstamps;
340 struct i40e_hw *hw = &pf->hw;
341 u32 hi, lo;
342 u64 ns;
343
344 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
345 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
346
347 ns = (((u64)hi) << 32) | lo;
348
349 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
350 skb_tstamp_tx(pf->ptp_tx_skb, &shhwtstamps);
351 dev_kfree_skb_any(pf->ptp_tx_skb);
352 pf->ptp_tx_skb = NULL;
353}
354
355/**
356 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
357 * @pf: Board private structure
358 * @skb: Particular skb to send timestamp with
359 * @index: Index into the receive timestamp registers for the timestamp
360 *
361 * The XL710 receives a notification in the receive descriptor with an offset
362 * into the set of RXTIME registers where the timestamp is for that skb. This
363 * function goes and fetches the receive timestamp from that offset, if a valid
364 * one exists. The RXTIME registers are in ns, so we must convert the result
365 * first.
366 **/
367void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
368{
369 u32 prttsyn_stat, hi, lo;
370 struct i40e_hw *hw;
371 u64 ns;
372
373 /* Since we cannot turn off the Rx timestamp logic if the device is
374 * doing Tx timestamping, check if Rx timestamping is configured.
375 */
376 if (!pf->ptp_rx)
377 return;
378
379 hw = &pf->hw;
380
381 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
382
383 if (!(prttsyn_stat & (1 << index)))
384 return;
385
386 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
387 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
388
389 ns = (((u64)hi) << 32) | lo;
390
391 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
392}
393
394/**
395 * i40e_ptp_set_increment - Utility function to update clock increment rate
396 * @pf: Board private structure
397 *
398 * During a link change, the DMA frequency that drives the 1588 logic will
399 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
400 * we must update the increment value per clock tick.
401 **/
402void i40e_ptp_set_increment(struct i40e_pf *pf)
403{
404 struct i40e_link_status *hw_link_info;
405 struct i40e_hw *hw = &pf->hw;
406 u64 incval;
407
408 hw_link_info = &hw->phy.link_info;
409
410 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
411
412 switch (hw_link_info->link_speed) {
413 case I40E_LINK_SPEED_10GB:
414 incval = I40E_PTP_10GB_INCVAL;
415 break;
416 case I40E_LINK_SPEED_1GB:
417 incval = I40E_PTP_1GB_INCVAL;
418 break;
419 case I40E_LINK_SPEED_100MB:
420 dev_warn(&pf->pdev->dev,
421 "%s: 1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n",
422 __func__);
423 incval = 0;
424 break;
425 case I40E_LINK_SPEED_40GB:
426 default:
427 incval = I40E_PTP_40GB_INCVAL;
428 break;
429 }
430
431 /* Write the new increment value into the increment register. The
432 * hardware will not update the clock until both registers have been
433 * written.
434 */
435 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
436 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
437
438 /* Update the base adjustement value. */
439 ACCESS_ONCE(pf->ptp_base_adj) = incval;
440 smp_mb(); /* Force the above update. */
441}
442
443/**
444 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
445 * @pf: Board private structure
446 * @ifreq: ioctl data
447 *
448 * Obtain the current hardware timestamping settigs as requested. To do this,
449 * keep a shadow copy of the timestamp settings rather than attempting to
450 * deconstruct it from the registers.
451 **/
452int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
453{
454 struct hwtstamp_config *config = &pf->tstamp_config;
455
456 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
457 -EFAULT : 0;
458}
459
460/**
461 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
462 * @pf: Board private structure
463 * @ifreq: ioctl data
464 *
465 * Respond to the user filter requests and make the appropriate hardware
466 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
467 * logic, so keep track in software of whether to indicate these timestamps
468 * or not.
469 *
470 * It is permissible to "upgrade" the user request to a broader filter, as long
471 * as the user receives the timestamps they care about and the user is notified
472 * the filter has been broadened.
473 **/
474int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
475{
476 struct i40e_hw *hw = &pf->hw;
477 struct hwtstamp_config *config = &pf->tstamp_config;
478 u32 pf_id, tsyntype, regval;
479
480 if (copy_from_user(config, ifr->ifr_data, sizeof(*config)))
481 return -EFAULT;
482
483 /* Reserved for future extensions. */
484 if (config->flags)
485 return -EINVAL;
486
487 /* Confirm that 1588 is supported on this PF. */
488 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
489 I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
490 if (hw->pf_id != pf_id)
491 return -EINVAL;
492
493 switch (config->tx_type) {
494 case HWTSTAMP_TX_OFF:
495 pf->ptp_tx = false;
496 break;
497 case HWTSTAMP_TX_ON:
498 pf->ptp_tx = true;
499 break;
500 default:
501 return -ERANGE;
502 }
503
504 switch (config->rx_filter) {
505 case HWTSTAMP_FILTER_NONE:
506 pf->ptp_rx = false;
507 tsyntype = 0;
508 break;
509 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
510 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
511 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
512 pf->ptp_rx = true;
513 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
514 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
515 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
516 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
517 break;
518 case HWTSTAMP_FILTER_PTP_V2_EVENT:
519 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
520 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
521 case HWTSTAMP_FILTER_PTP_V2_SYNC:
522 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
523 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
524 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
525 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
526 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
527 pf->ptp_rx = true;
528 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
529 I40E_PRTTSYN_CTL1_TSYNTYPE_V2 |
530 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
531 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
532 break;
533 case HWTSTAMP_FILTER_ALL:
534 default:
535 return -ERANGE;
536 }
537
538 /* Clear out all 1588-related registers to clear and unlatch them. */
539 rd32(hw, I40E_PRTTSYN_STAT_0);
540 rd32(hw, I40E_PRTTSYN_TXTIME_H);
541 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
542 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
543 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
544 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
545
546 /* Enable/disable the Tx timestamp interrupt based on user input. */
547 regval = rd32(hw, I40E_PRTTSYN_CTL0);
548 if (pf->ptp_tx)
549 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
550 else
551 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
552 wr32(hw, I40E_PRTTSYN_CTL0, regval);
553
554 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
555 if (pf->ptp_tx)
556 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
557 else
558 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
559 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
560
561 /* There is no simple on/off switch for Rx. To "disable" Rx support,
562 * ignore any received timestamps, rather than turn off the clock.
563 */
564 if (pf->ptp_rx) {
565 regval = rd32(hw, I40E_PRTTSYN_CTL1);
566 /* clear everything but the enable bit */
567 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
568 /* now enable bits for desired Rx timestamps */
569 regval |= tsyntype;
570 wr32(hw, I40E_PRTTSYN_CTL1, regval);
571 }
572
573 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
574 -EFAULT : 0;
575}
576
577/**
578 * i40e_ptp_init - Initialize the 1588 support and register the PHC
579 * @pf: Board private structure
580 *
581 * This function registers the device clock as a PHC. If it is successful, it
582 * starts the clock in the hardware.
583 **/
584void i40e_ptp_init(struct i40e_pf *pf)
585{
586 struct i40e_hw *hw = &pf->hw;
587 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
588
589 strncpy(pf->ptp_caps.name, "i40e", sizeof(pf->ptp_caps.name));
590 pf->ptp_caps.owner = THIS_MODULE;
591 pf->ptp_caps.max_adj = 999999999;
592 pf->ptp_caps.n_ext_ts = 0;
593 pf->ptp_caps.pps = 0;
594 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
595 pf->ptp_caps.adjtime = i40e_ptp_adjtime;
596 pf->ptp_caps.gettime = i40e_ptp_gettime;
597 pf->ptp_caps.settime = i40e_ptp_settime;
598 pf->ptp_caps.enable = i40e_ptp_enable;
599
600 /* Attempt to register the clock before enabling the hardware. */
601 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
602 if (IS_ERR(pf->ptp_clock)) {
603 pf->ptp_clock = NULL;
604 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
605 __func__);
606 } else {
607 struct timespec ts;
608 u32 regval;
609
610 spin_lock_init(&pf->tmreg_lock);
611 INIT_WORK(&pf->ptp_tx_work, i40e_ptp_tx_work);
612
613 dev_info(&pf->pdev->dev, "%s: added PHC on %s\n", __func__,
614 netdev->name);
615 pf->flags |= I40E_FLAG_PTP;
616
617 /* Ensure the clocks are running. */
618 regval = rd32(hw, I40E_PRTTSYN_CTL0);
619 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
620 wr32(hw, I40E_PRTTSYN_CTL0, regval);
621 regval = rd32(hw, I40E_PRTTSYN_CTL1);
622 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
623 wr32(hw, I40E_PRTTSYN_CTL1, regval);
624
625 /* Set the increment value per clock tick. */
626 i40e_ptp_set_increment(pf);
627
628 /* reset the tstamp_config */
629 memset(&pf->tstamp_config, 0, sizeof(pf->tstamp_config));
630
631 /* Set the clock value. */
632 ts = ktime_to_timespec(ktime_get_real());
633 i40e_ptp_settime(&pf->ptp_caps, &ts);
634 }
635}
636
637/**
638 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
639 * @pf: Board private structure
640 *
641 * This function handles the cleanup work required from the initialization by
642 * clearing out the important information and unregistering the PHC.
643 **/
644void i40e_ptp_stop(struct i40e_pf *pf)
645{
646 pf->flags &= ~I40E_FLAG_PTP;
647 pf->ptp_tx = false;
648 pf->ptp_rx = false;
649
650 cancel_work_sync(&pf->ptp_tx_work);
651 if (pf->ptp_tx_skb) {
652 dev_kfree_skb_any(pf->ptp_tx_skb);
653 pf->ptp_tx_skb = NULL;
654 }
655
656 if (pf->ptp_clock) {
657 ptp_clock_unregister(pf->ptp_clock);
658 pf->ptp_clock = NULL;
659 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
660 pf->vsi[pf->lan_vsi]->netdev->name);
661 }
662}