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1// SPDX-License-Identifier: GPL-2.0
2#include <linux/linkage.h>
3#include <linux/errno.h>
4#include <linux/signal.h>
5#include <linux/sched.h>
6#include <linux/ioport.h>
7#include <linux/interrupt.h>
8#include <linux/irq.h>
9#include <linux/timex.h>
10#include <linux/random.h>
11#include <linux/kprobes.h>
12#include <linux/init.h>
13#include <linux/kernel_stat.h>
14#include <linux/device.h>
15#include <linux/bitops.h>
16#include <linux/acpi.h>
17#include <linux/io.h>
18#include <linux/delay.h>
19
20#include <linux/atomic.h>
21#include <asm/timer.h>
22#include <asm/hw_irq.h>
23#include <asm/pgtable.h>
24#include <asm/desc.h>
25#include <asm/apic.h>
26#include <asm/setup.h>
27#include <asm/i8259.h>
28#include <asm/traps.h>
29#include <asm/prom.h>
30
31/*
32 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
33 * (these are usually mapped to vectors 0x30-0x3f)
34 */
35
36/*
37 * The IO-APIC gives us many more interrupt sources. Most of these
38 * are unused but an SMP system is supposed to have enough memory ...
39 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
40 * across the spectrum, so we really want to be prepared to get all
41 * of these. Plus, more powerful systems might have more than 64
42 * IO-APIC registers.
43 *
44 * (these are usually mapped into the 0x30-0xff vector range)
45 */
46
47/*
48 * IRQ2 is cascade interrupt to second interrupt controller
49 */
50static struct irqaction irq2 = {
51 .handler = no_action,
52 .name = "cascade",
53 .flags = IRQF_NO_THREAD,
54};
55
56DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
57 [0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
58};
59
60void __init init_ISA_irqs(void)
61{
62 struct irq_chip *chip = legacy_pic->chip;
63 int i;
64
65 /*
66 * Try to set up the through-local-APIC virtual wire mode earlier.
67 *
68 * On some 32-bit UP machines, whose APIC has been disabled by BIOS
69 * and then got re-enabled by "lapic", it hangs at boot time without this.
70 */
71 init_bsp_APIC();
72
73 legacy_pic->init(0);
74
75 for (i = 0; i < nr_legacy_irqs(); i++)
76 irq_set_chip_and_handler(i, chip, handle_level_irq);
77}
78
79void __init init_IRQ(void)
80{
81 int i;
82
83 /*
84 * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
85 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
86 * then this configuration will likely be static after the boot. If
87 * these IRQ's are handled by more mordern controllers like IO-APIC,
88 * then this vector space can be freed and re-used dynamically as the
89 * irq's migrate etc.
90 */
91 for (i = 0; i < nr_legacy_irqs(); i++)
92 per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
93
94 BUG_ON(irq_init_percpu_irqstack(smp_processor_id()));
95
96 x86_init.irqs.intr_init();
97}
98
99void __init native_init_IRQ(void)
100{
101 /* Execute any quirks before the call gates are initialised: */
102 x86_init.irqs.pre_vector_init();
103
104 idt_setup_apic_and_irq_gates();
105 lapic_assign_system_vectors();
106
107 if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
108 setup_irq(2, &irq2);
109}
1#include <linux/linkage.h>
2#include <linux/errno.h>
3#include <linux/signal.h>
4#include <linux/sched.h>
5#include <linux/ioport.h>
6#include <linux/interrupt.h>
7#include <linux/timex.h>
8#include <linux/random.h>
9#include <linux/kprobes.h>
10#include <linux/init.h>
11#include <linux/kernel_stat.h>
12#include <linux/device.h>
13#include <linux/bitops.h>
14#include <linux/acpi.h>
15#include <linux/io.h>
16#include <linux/delay.h>
17
18#include <linux/atomic.h>
19#include <asm/timer.h>
20#include <asm/hw_irq.h>
21#include <asm/pgtable.h>
22#include <asm/desc.h>
23#include <asm/apic.h>
24#include <asm/setup.h>
25#include <asm/i8259.h>
26#include <asm/traps.h>
27#include <asm/prom.h>
28
29/*
30 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
31 * (these are usually mapped to vectors 0x30-0x3f)
32 */
33
34/*
35 * The IO-APIC gives us many more interrupt sources. Most of these
36 * are unused but an SMP system is supposed to have enough memory ...
37 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
38 * across the spectrum, so we really want to be prepared to get all
39 * of these. Plus, more powerful systems might have more than 64
40 * IO-APIC registers.
41 *
42 * (these are usually mapped into the 0x30-0xff vector range)
43 */
44
45/*
46 * IRQ2 is cascade interrupt to second interrupt controller
47 */
48static struct irqaction irq2 = {
49 .handler = no_action,
50 .name = "cascade",
51 .flags = IRQF_NO_THREAD,
52};
53
54DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
55 [0 ... NR_VECTORS - 1] = VECTOR_UNDEFINED,
56};
57
58int vector_used_by_percpu_irq(unsigned int vector)
59{
60 int cpu;
61
62 for_each_online_cpu(cpu) {
63 if (per_cpu(vector_irq, cpu)[vector] > VECTOR_UNDEFINED)
64 return 1;
65 }
66
67 return 0;
68}
69
70void __init init_ISA_irqs(void)
71{
72 struct irq_chip *chip = legacy_pic->chip;
73 const char *name = chip->name;
74 int i;
75
76#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
77 init_bsp_APIC();
78#endif
79 legacy_pic->init(0);
80
81 for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
82 irq_set_chip_and_handler_name(i, chip, handle_level_irq, name);
83}
84
85void __init init_IRQ(void)
86{
87 int i;
88
89 /*
90 * We probably need a better place for this, but it works for
91 * now ...
92 */
93 x86_add_irq_domains();
94
95 /*
96 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
97 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
98 * then this configuration will likely be static after the boot. If
99 * these IRQ's are handled by more mordern controllers like IO-APIC,
100 * then this vector space can be freed and re-used dynamically as the
101 * irq's migrate etc.
102 */
103 for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
104 per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;
105
106 x86_init.irqs.intr_init();
107}
108
109/*
110 * Setup the vector to irq mappings.
111 */
112void setup_vector_irq(int cpu)
113{
114#ifndef CONFIG_X86_IO_APIC
115 int irq;
116
117 /*
118 * On most of the platforms, legacy PIC delivers the interrupts on the
119 * boot cpu. But there are certain platforms where PIC interrupts are
120 * delivered to multiple cpu's. If the legacy IRQ is handled by the
121 * legacy PIC, for the new cpu that is coming online, setup the static
122 * legacy vector to irq mapping:
123 */
124 for (irq = 0; irq < legacy_pic->nr_legacy_irqs; irq++)
125 per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
126#endif
127
128 __setup_vector_irq(cpu);
129}
130
131static void __init smp_intr_init(void)
132{
133#ifdef CONFIG_SMP
134#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
135 /*
136 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
137 * IPI, driven by wakeup.
138 */
139 alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
140
141 /* IPI for generic function call */
142 alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
143
144 /* IPI for generic single function call */
145 alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
146 call_function_single_interrupt);
147
148 /* Low priority IPI to cleanup after moving an irq */
149 set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
150 set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
151
152 /* IPI used for rebooting/stopping */
153 alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt);
154#endif
155#endif /* CONFIG_SMP */
156}
157
158static void __init apic_intr_init(void)
159{
160 smp_intr_init();
161
162#ifdef CONFIG_X86_THERMAL_VECTOR
163 alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
164#endif
165#ifdef CONFIG_X86_MCE_THRESHOLD
166 alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
167#endif
168
169#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
170 /* self generated IPI for local APIC timer */
171 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
172
173 /* IPI for X86 platform specific use */
174 alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);
175#ifdef CONFIG_HAVE_KVM
176 /* IPI for KVM to deliver posted interrupt */
177 alloc_intr_gate(POSTED_INTR_VECTOR, kvm_posted_intr_ipi);
178#endif
179
180 /* IPI vectors for APIC spurious and error interrupts */
181 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
182 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
183
184 /* IRQ work interrupts: */
185# ifdef CONFIG_IRQ_WORK
186 alloc_intr_gate(IRQ_WORK_VECTOR, irq_work_interrupt);
187# endif
188
189#endif
190}
191
192void __init native_init_IRQ(void)
193{
194 int i;
195
196 /* Execute any quirks before the call gates are initialised: */
197 x86_init.irqs.pre_vector_init();
198
199 apic_intr_init();
200
201 /*
202 * Cover the whole vector space, no vector can escape
203 * us. (some of these will be overridden and become
204 * 'special' SMP interrupts)
205 */
206 i = FIRST_EXTERNAL_VECTOR;
207 for_each_clear_bit_from(i, used_vectors, NR_VECTORS) {
208 /* IA32_SYSCALL_VECTOR could be used in trap_init already. */
209 set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]);
210 }
211
212 if (!acpi_ioapic && !of_ioapic)
213 setup_irq(2, &irq2);
214
215#ifdef CONFIG_X86_32
216 irq_ctx_init(smp_processor_id());
217#endif
218}